PATENT CLAIM ANALYSIS

Application Number: 16139415
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["327", "166000"]

Abstract:
A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.

Claim (Index 1):
A clock and data recovery circuit, comprising:\n a first phase detector, comparing a phase of a data signal with that of a first clock signal to output a first output signal, wherein the first output signal indicates whether the phase of data signal is ahead or behind that of the first clock signal; an auxiliary module, comprising: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of the first clock signal to output a second output signal, wherein the second output signal indicates whether the phase of the auxiliary clock signal is ahead or behind that of the first clock signal; and a multiplexing selecting unit, coupled to the first phase detector and the second phase detector, outputting a multiplexing output signal according to a selection signal; a first charge pump, coupled to the multiplexing selecting unit, outputting a control signal according to the multiplexing output signal; and a first voltage-controlled oscillator (VCO), coupled to the first charge pump, generating the first clock signal according to the control signal; wherein the second phase detector comprises: a first delay unit, receiving the auxiliary clock signal and the first clock signal to generate a first delayed signal; a second delay unit, coupled to the first delay unit, receiving the first delayed signal and the first clock signal to generate a second delayed signal; a first exclusive OR (XOR) gate, performing an XOR operation on the auxiliary clock signal and the first delayed signal to generate a first rising signal; and a second XOR gate, performing an XOR operation on the first delayed signal and the second delayed signal to generate a first falling signal; wherein, the first rising signal and the first falling signal form the second output signal.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.19565
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10038613', '11472815', '10947891', '11228990', '11789330']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7721675310545446
- 35 USC 102 Novelty (BERT): 0.4596969986882479
- Combined Prediction Score: 0.740920477817915
- Mean Citation Score: 194.63989
- Max Citation Score: 205.70082
- Similarity Product: 183.48272009882928

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test