PATENT CLAIM ANALYSIS

Application Number: 16291793
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-06
Patent Classification: ["716", "136000"]

Abstract:
An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

Claim (Index 17):
The method of  claim 16 , wherein:\n the gate of the second PMOS transistor is electrically connected to the gate of the second NMOS transistor, and the node serves as the input of the NAND gate; the gate of the third PMOS transistor is electrically connected to the gate of the third NMOS transistor; the source of the second PMOS transistor and the source of the third PMOS transistor are electrically connected to Vdd; the drain of the second PMOS transistor and the drain of the third PMOS transistor are electrically connected to the source of the third NMOS transistor; the drain of the third NMOS transistor is electrically connected to the source of the second NMOS transistor, and is further electrically connected to the drain of the first PMOS transistor and the source of the first NMOS transistor; the drain of the second NMOS transistor is electrically connected to ground; the source of the first PMOS transistor is a first monitor node, and the drain of the first NMOS transistor is a second monitor node; and the gate of the first PMOS is a first enable node, the gate of the first NMOS transistor is a second enable node, and the gates of third PMOS transistor and the third NMOS transistor are electrically connected together as a third enable node.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 99.0
- Lexical Diversity: 3.02439
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15170707', '13009649', '15635711', '13183521', '15040817']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3195791932266985
- 35 USC 102 Novelty (BERT): 0.5556131048000887
- Combined Prediction Score: 0.3431825843840375
- Mean Citation Score: 254.893488
- Max Citation Score: 452.67166
- Similarity Product: 380.129349972862

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test