PATENT CLAIM ANALYSIS

Application Number: 16105424
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["340", "012510"]

Abstract:
A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

Claim (Index 14):
The system of  claim 13 , wherein the first signal is based on bits of the first shift register.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.31111
- Patent Class: 340.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15607588', '15334070', '10966254', '11134923', '13742578']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6891261085675869
- 35 USC 102 Novelty (BERT): 0.5341956508762856
- Combined Prediction Score: 0.6736330627984568
- Mean Citation Score: 201.629236
- Max Citation Score: 324.0302700000001
- Similarity Product: 198.2991823222948

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test