PATENT CLAIM ANALYSIS

Application Number: 15914560
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "314000"]

Abstract:
A first alternating stack of first insulating layers and first spacer layers, an inter-tier dielectric layer, a sacrificial memory opening fill structure, and a second alternating stack of second insulating layers and second spacer layers are formed over a substrate. The spacer layers are formed as, or are subsequently replaced with, electrically conductive layers. A concave downward-facing surface of the inter-tier dielectric layer is formed on a convex upper surface of the sacrificial memory opening fill structure. An inter-tier memory opening is provided by forming second-tier memory opening and removing the sacrificial memory opening fill structure. A memory stack structure including a memory film is formed in the inter-tier memory opening. The memory film includes a rounded top surface at the joint between tiers to enhance its reliability.

Claim (Index 5):
The three-dimensional memory device of  claim 1 , wherein the inter-tier dielectric layer comprises two different dielectric material compositions with a horizontal interface or a vertical interface therebetween.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 2.24194
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15909073', '15632983', '15638672', '15269041', '15877219']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.94774258612942
- 35 USC 102 Novelty (BERT): 0.5512248229374478
- Combined Prediction Score: 0.9080908098102228
- Mean Citation Score: 417.486418
- Max Citation Score: 421.33356
- Similarity Product: 351.33708654250154

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test