PATENT CLAIM ANALYSIS

Application Number: 15863164
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "048000"]

Abstract:
An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

Claim (Index 20):
A structure for printing transferrable integrated circuit chiplets, comprising:\n a substrate; a patterned sacrificial layer on the substrate; and a plurality of integrated circuit chiplets disposed on the patterned sacrificial layer, wherein each of the plurality of integrated circuit chiplets comprises:\n a separate chiplet substrate detached from the substrate by a pattern of the sacrificial layer; \n active elements disposed on or in the chiplet substrate; \n a connection pad disposed on a surface of the chiplet substrate; \n chiplet wires disposed on or in the chiplet substrate electrically connecting the active elements and the connection pad; \n a conductor electrically separate from the connection pad on the surface of the chiplet substrate, the conductor electrically connected to at least one of a conductor chiplet wire and one of the active elements; and \n an insulating layer disposed on the chiplet substrate and the conductor, the insulating layer leaving at least a portion of the connection pad exposed.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.35938
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13302497', '12546118', '15596982', '12264457', '13029549']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9294094419701184
- 35 USC 102 Novelty (BERT): 0.5541094731448126
- Combined Prediction Score: 0.8918794450875879
- Mean Citation Score: 315.179724
- Max Citation Score: 418.92358
- Similarity Product: 324.7961567615938

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test