PATENT CLAIM ANALYSIS

Application Number: 15977910
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["341", "172000"]

Abstract:
A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

Claim (Index 12):
The device of  claim 10 , wherein the plurality of capacitors receive a control signal that includes a clock signal with a rising edge, wherein the rising edge triggers the sampling of the analog input signal.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 93.0
- Lexical Diversity: 1.91304
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12199803', '14576315', '14490831', '15261643', '15007368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6265012073322346
- 35 USC 102 Novelty (BERT): 0.5201701435228566
- Combined Prediction Score: 0.6158681009512968
- Mean Citation Score: 249.634278
- Max Citation Score: 258.5641
- Similarity Product: 152.93101340637804

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test