PATENT CLAIM ANALYSIS

Application Number: 15902325
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185290"]

Abstract:
An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.

Claim (Index 13):
The flash memory according to  claim 8 , wherein when the sector enable signal is initially de-asserted, if the memory block corresponding to the address has the under-erased transistor memory cell, the transistor memory cells of the memory block are injected with an erasing shot at least one time by the memory management apparatus until the memory block is verified to have the over-erased transistor memory cell.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.36735
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11497597', '11297085', '10636551', '10159780', '12833305']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7928537933583153
- 35 USC 102 Novelty (BERT): 0.4937456124536378
- Combined Prediction Score: 0.7629429752678476
- Mean Citation Score: 237.274182
- Max Citation Score: 241.13254
- Similarity Product: 183.04735219290973

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test