PATENT CLAIM ANALYSIS

Application Number: 16120823
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-08
Patent Classification: ["257", "072000"]

Abstract:
An array substrate and a method for manufacturing the same, a display panel and a display device are provided. The array substrate includes a gate layer, a gate insulation layer, a source-drain layer, a first passivation layer and an ITO layer successively formed on a base substrate, a first through hole in the first passivation layer and a second through hole in the gate insulation layer, and a second passivation layer; and a part of the second passivation layer is arranged in the first and second through holes to cover a part of the ITO layer in the first through hole and the second through hole.

Claim (Index 9):
A method for manufacturing an array substrate, the array substrate being divided into a through-hole region, a peripheral wiring region and an effective display region, and the method comprising steps of forming a gate layer, a gate insulation layer, a source-drain layer, a first passivation layer and an ITO layer successively on a base substrate such that the ITO layer is provided in a first through hole in the first passivation layer and a second through hole in the gate insulation layer,\n the method further comprises steps of: forming a second passivation layer on the ITO layer after forming the ITO layer and before further performing a patterning process on the ITO layer, forming a photoresist layer on the second passivation layer, and performing an exposure and development process on the photoresist layer using a halftone mask such that a part of the photoresist layer, corresponding to the first and second through holes at the through-hole region, is completely retained, a part of the photoresist layer, corresponding to a part of the ITO layer at the effective display region which will be etched out, is completely removed, and a part of the photoresist layer, corresponding to a part of the ITO layer which will not be etched out at the effective display region, and a part of the ITO layer at the through-hole region except the first and second through holes, is thinned; performing a first etching on the second passivation layer to expose the part of the ITO layer at the effective display area which will be etched out; performing an ashing process on the photoresist layer to remove the photoresist layer at the effective display region and the photoresist layer at the through-hole region except the first and second through holes, and then performing an etching process on an exposed part of the ITO layer to form a pattern of the ITO layer; performing a second etching on the second passivation layer to completely remove the part of the second passivation layer at the through-hole region except the first and second through holes and at the effective display region at which the part of the ITO layer will not be etched out; and peeling off the photoresist layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.67442
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14408717', '15544562', '14897525', '13458478', '11354789']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9176620980750874
- 35 USC 102 Novelty (BERT): 0.4904362482348898
- Combined Prediction Score: 0.8749395130910677
- Mean Citation Score: 227.520654
- Max Citation Score: 236.28479
- Similarity Product: 179.92157258749603

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test