PATENT CLAIM ANALYSIS

Application Number: 15941194
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-01
Patent Classification: ["365", "189150"]

Abstract:
An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

Claim (Index 16):
An integrated circuit, comprising:\n an amplifier circuit that includes a first NMOS transistor for pulling down a first output node in response to a voltage level of a first line, a second NMOS transistor for pulling down a second output node in response to a voltage level of a second line, a first PMOS transistor for pulling up the first output node in response to a voltage level of the second output node, and a second PMOS transistor for pulling up the second output node in response to a voltage level of the first output node, wherein the first output node and the second line are electrically connected to each other, and the second output node and the first line are electrically connected to each other during an amplification operation, and wherein the first output node and the first line are electrically connected to each other, and the second output node and the second line are electrically connected to each other during an offset cancellation operation; a replica amplifier circuit that includes a first replica NMOS transistor for pulling down a first replica output node in response to a voltage level of a first replica line, a second replica NMOS transistor for pulling down a second replica output node in response to a voltage level of a second replica line, a first replica PMOS transistor for pulling up the first replica output node in response to a voltage level of the second replica output node, and a second replica PMOS transistor for pulling up the second replica output node in response to a voltage level of the first replica output node, wherein the first replica output node and the first replica line are electrically connected to each other, and the second replica output node and the second replica line are electrically connected to each other; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 3.04
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14658353', '15941173', '12157243', '13972974', '15589056']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7716062099540372
- 35 USC 102 Novelty (BERT): 0.487345129082411
- Combined Prediction Score: 0.7431801018668747
- Mean Citation Score: 234.939274
- Max Citation Score: 243.68147
- Similarity Product: 197.1885678824877

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test