PATENT CLAIM ANALYSIS

Application Number: 15742809
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "417000"]

Abstract:
A semiconductor device includes a metal body; a bonding layer placed on the metal body; and a semiconductor chip placed on the bonding layer. The bonding layer includes a filler-containing first layer formed between the metal body and the semiconductor chip and a second layer bonded to the first layer and the semiconductor chip. The second layer has a thermal expansion coefficient higher than that of the first layer.

Claim (Index 10):
A method for fabricating a semiconductor device comprising:\n forming a filler-containing first bonding layer on a metal body; forming a second bonding layer on the first bonding layer, the second layer having a thermal expansion coefficient higher than that of the first bonding layer; and bonding a semiconductor chip to the second bonding layer.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.3125
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15023716', '15739283', '09587768', '13571580', '13384479']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8917134578723042
- 35 USC 102 Novelty (BERT): 0.4579403471296904
- Combined Prediction Score: 0.8483361467980428
- Mean Citation Score: 152.032758
- Max Citation Score: 156.39093
- Similarity Product: 133.3069303707075

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test