PATENT CLAIM ANALYSIS

Application Number: 16014774
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "225000"]

Abstract:
An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

Claim (Index 24):
A method for manufacturing an image capturing device having a photoelectric conversion region, a transfer transistor and a first peripheral transistor, comprising the steps of:\n (a) defining a pixel region and a peripheral region by forming an element isolation insulating film in a semiconductor substrate; (b) forming a transfer gate electrode of the transfer transistor in the pixel region and forming a first peripheral gate electrode of the first peripheral transistor in the peripheral region; (c) forming the photoelectric conversion region in a portion of the pixel region on one side of the transfer gate electrode; (d) forming a first insulating film so as to cover the pixel region and the peripheral region; (e) forming a first resist pattern over the first insulating film so as to cover the pixel region; (f) performing anisotropic etching of the first insulating film to form respective offset spacers on opposite side surfaces of the first peripheral gate electrode; (g) removing the first resist pattern; (h) forming respective first extension diffusion regions in the peripheral region on the opposite side surface sides of the first peripheral gate electrode by implanting an impurity of a predetermined conductivity type using the first peripheral gate electrode and the offset spacers as an implantation mask; (i) removing the first insulating film on the photoelectric conversion region while protecting the peripheral region to leave the offset spacers by performing a wet etching process; (j) forming a second insulating film so as to cover the pixel region and the peripheral region; (k) forming a second resist pattern over the second insulating film so as to cover the photoelectric conversion region; (l) performing anisotropic etching of the second insulating film to form respective sidewall spacers interposing the offset spacers on the opposite side surfaces of the first peripheral gate electrode; (m) removing the second resist pattern; (n) after the step (m), forming source-drain regions in the peripheral region on the opposite side surface sides of the first peripheral gate electrode by implanting an impurity of a predetermined conductivity type using the first peripheral gate electrode, the offset spacers and the sidewall spacers as an implantation mask.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15788695', '15404320', '14437910', '14894298', '14024117']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9493866897791248
- 35 USC 102 Novelty (BERT): 0.6779797419959464
- Combined Prediction Score: 0.922245995000807
- Mean Citation Score: 589.64782
- Max Citation Score: 751.5104
- Similarity Product: 651.5071857959747

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test