PATENT CLAIM ANALYSIS

Application Number: 15895837
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["375", "362000"]

Abstract:
A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

Claim (Index 3):
The serializer of  claim 1 , wherein the plurality of pre-clock signals include first to fourth pre-clock signals sequentially having phase difference of 90 degrees with each other,\n wherein the plurality of main clock signals include first to fourth main clock signals sequentially having phase difference of 90 degrees with each other, and wherein the first to fourth pre-clock signals have leading phases of 90 degrees to the first to fourth main clock signals, respectively.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 88.0
- Lexical Diversity: 2.51351
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15855567', '11850754', '12165171', '14882942', '15366345']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5006938011909647
- 35 USC 102 Novelty (BERT): 0.5041609318489363
- Combined Prediction Score: 0.5010405142567619
- Mean Citation Score: 196.609306
- Max Citation Score: 216.4241
- Similarity Product: 132.9251142766893

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test