PATENT CLAIM ANALYSIS

Application Number: 15887629
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["710", "105000"]

Abstract:
A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Claim (Index 28):
The clock gating circuit of  claim 21 , wherein each of the first counter and the second counter receives a clock.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 1.63158
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13556545', '11124271', '13176160', '11741156', '11741328']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6687286609221389
- 35 USC 102 Novelty (BERT): 0.5482872104116492
- Combined Prediction Score: 0.6566845158710899
- Mean Citation Score: 260.848288
- Max Citation Score: 419.9261
- Similarity Product: 262.221588372004

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test