PATENT CLAIM ANALYSIS

Application Number: 16234065
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["365", "203000"]

Abstract:
Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

Claim (Index 35):
The computing system of  claim 34 , wherein the first clipper circuitry and the second clipper circuitry are to alternately couple the read port node of the first bitcell array and the read port node of the second bitcell array to the LBL node based on at least one control signal.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 98.0
- Lexical Diversity: 2.42857
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15485059', '15072278', '15604519', '15176069', '14283209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8239161981752592
- 35 USC 102 Novelty (BERT): 0.536611745728342
- Combined Prediction Score: 0.7951857529305675
- Mean Citation Score: 259.085932
- Max Citation Score: 396.76147
- Similarity Product: 269.54847286028144

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test