PATENT CLAIM ANALYSIS

Application Number: 16114327
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["338", "309000"]

Abstract:
Shown herein is a method of forming an electrical resistor comprising the steps of: forming an electrically resistive layer on a substrate; measuring an electrical resistance-related parameter of the electrically resistive layer and determining a target length of the electrically resistive layer corresponding to a target electrical resistance; and forming first and second electrically conductive terminals contacting the electrically resistive layer, said first and second electrically conductive terminals being separated by a distance corresponding to the target length.

Claim (Index 32):
Arrangement for forming an electrical resistor having a target electrical resistance by additive manufacturing, wherein the arrangement comprises:\n a first deposition device configured for depositing an electrically resistive material for forming an electrically resistive layer; a processing unit configured for measuring an electrical resistance-related parameter of an electrically resistive layer formed by the first deposition device and determining from the electrical resistance-related parameter a target length of the electrically resistive layer corresponding to the target electrical resistance; a second deposition device configured for depositing an electrically conductive material for forming electrically conductive terminals; and a third deposition device configured for depositing an electrically isolating material for forming an electrically isolating layer; wherein the processing unit is further configured for controlling the third deposition device to form the electrically isolating layer on an electrically resistive layer formed by the first deposition device, such that the electrically isolating layer extends from a first end to a second end, wherein the electrically isolating layer covers the electrically resistive layer in an overlap region extending between said first end and said second end, such that a length of the electrically resistive layer covered by the electrically isolating layer corresponds to the target length; and wherein the processing unit is further configured for controlling the second deposition device to form a first electrically conductive terminal on the electrically resistive layer directly adjacent to the first end of the electrically isolating layer and to form a second electrically conductive terminal on the electrically resistive layer directly adjacent to the second end of the electrically isolating layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 96.0
- Lexical Diversity: 1.97619
- Patent Class: 338.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13340255', '13060872', '13339968', '12007820', '10883913']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.69749983194908
- 35 USC 102 Novelty (BERT): 0.4684447376972442
- Combined Prediction Score: 0.6745943225238965
- Mean Citation Score: 160.73258
- Max Citation Score: 166.32591000000005
- Similarity Product: 115.82946065713944

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test