PATENT CLAIM ANALYSIS

Application Number: 16000582
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "175000"]

Abstract:
In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.

Claim (Index 7):
A duty cycle controller comprising:\n a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal for a time less than the predetermined delay time and configured to delay the feedback clock signal for the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.7
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12400495', '13563863', '13420459', '13098154', '14810900']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7873913161523692
- 35 USC 102 Novelty (BERT): 0.4925766448143792
- Combined Prediction Score: 0.7579098490185703
- Mean Citation Score: 262.21605200000005
- Max Citation Score: 270.6687
- Similarity Product: 218.9604959074616

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test