PATENT CLAIM ANALYSIS

Application Number: 15933021
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["327", "199000"]

Abstract:
A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

Claim (Index 8):
The circuit of  claim 7 , further comprising:\n a first register to store an output bit from each of the second plurality of logic gates; and a second register coupled to a receive a programmed value; a control signal derived from the second register's programmed value to control the multiplexer to select a signal on one of the multiplexer's inputs as an output of the multiplexer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.93939
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12738931', '13690205', '11098130', '15786976', '11194610']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7875096528019213
- 35 USC 102 Novelty (BERT): 0.4979269376690169
- Combined Prediction Score: 0.7585513812886309
- Mean Citation Score: 259.228592
- Max Citation Score: 267.7731
- Similarity Product: 199.8255252076864

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test