PATENT CLAIM ANALYSIS

Application Number: 15862857
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["713", "400000"]

Abstract:
A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.

Claim (Index 5):
The CDR circuit of  claim 3 , wherein the first counter increments the frequency control code by the predefined value when the clock count value is less than the target count value for matching the frequency of the VCO clock signal to the target frequency.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.37736
- Patent Class: 713.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13306326', '12434051', '14560820', '13005271', '13235628']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.42525578174327
- 35 USC 102 Novelty (BERT): 0.5054495716077938
- Combined Prediction Score: 0.4332751607297224
- Mean Citation Score: 224.464496
- Max Citation Score: 245.18442
- Similarity Product: 163.8379474972093

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test