PATENT CLAIM ANALYSIS

Application Number: 16145160
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["712", "224000"]

Abstract:
Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.

Claim (Index 1):
A system comprising:\n a system memory to store instructions and data; and a first processor coupled to the system memory, the first processor to process a first type of instructions; a second processor coupled to the first processor over an on-chip interconnect, the second processor to process a second type of instructions, the second processor comprising:\n a plurality of 512-bit vector registers including:\n a first source vector register to store a first plurality of data elements; \n a second source vector register to store a second plurality of data elements, each of the second plurality of data elements to be stored in a data element location in the second source vector register corresponding to a data element location of one of the first plurality of data elements in the first source vector register; and \n a destination vector register to store a blended combination of the first and second pluralities of data elements; \n \n a plurality of vector mask registers including a source vector mask register, the source vector mask register to store predicate data comprising a plurality of bits, a value of each bit of the plurality of bits to identify one of the first plurality of data elements or one of the second plurality of data elements; \n a decoder to decode an instruction specifying a data blend operation; and \n execution circuitry to perform the data blend operation, the execution circuitry to select a packed data element from the first plurality of data elements to be stored in a corresponding location in the destination vector register if a corresponding bit of the predicate data has a first value and to select a packed data element from the second plurality of data elements to be stored in the corresponding location in the destination vector register if the corresponding bit of the predicate data has a second value a graphics processor to process graphics instructions, the graphics processor coupled to the first processor over the on-chip interconnect; and \n an integrated memory controller to couple the first processor, the second processor, and the graphics processor to the system memory.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 97.0
- Lexical Diversity: 1.71739
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14976220', '15647123', '14976228', '15941426', '15941995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5855847322363468
- 35 USC 102 Novelty (BERT): 0.4883266906987368
- Combined Prediction Score: 0.5758589280825859
- Mean Citation Score: 233.278462
- Max Citation Score: 235.27808
- Similarity Product: 174.15604226409909

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test