PATENT CLAIM ANALYSIS

Application Number: 15984610
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "595000"]

Abstract:
A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.

Claim (Index 8):
A method, comprising:\n forming a micro-electro-mechanical system (MEMS) substrate by:\n forming a first dielectric layer on a first surface of a first substrate; \n forming a metal layer over the first dielectric layer; \n forming a second dielectric layer over the metal layer; \n forming one or more metal units over the second dielectric layer, wherein a portion of the one or more metal units contacts the metal layer; \n forming a third dielectric layer over the one or more metal units, the third dielectric layer laterally encapsulating at least one of the one or more metal units; \n forming an opening in the third dielectric layer, the opening exposing a portion of a first metal unit of the one or more metal units; \n forming a first bonding feature over the third dielectric layer, the first bonding feature contacting the first metal unit; \n forming a plurality of vias through the first dielectric layer, the plurality of vias exposing the first substrate; and \n etching a first cavity in the first substrate through the plurality of vias, the first cavity extending under a moveable portion of the first dielectric layer, the cavity extending laterally under a non-moveable portion of the first dielectric layer; and \n bonding the first bonding feature to a second bonding feature of a device wafer, the bonding sealing the movable portion of the first dielectric layer in a second cavity, wherein the second cavity includes the first cavity.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.72549
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13916148', '13916197', '13906080', '14798213', '15003332']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9224904647227664
- 35 USC 102 Novelty (BERT): 0.5143470893503906
- Combined Prediction Score: 0.8816761271855289
- Mean Citation Score: 271.842256
- Max Citation Score: 312.4093299999999
- Similarity Product: 236.66408688897

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test