PATENT CLAIM ANALYSIS

Application Number: 16029577
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["326", "098000"]

Abstract:
A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Claim (Index 3):
The plurality of dynamic decode circuits according to  claim 2 , wherein the each conditioning circuit further comprises a second conditioning transistor having a second conditioning gate configured to receive a delayed evaluation clock signal, wherein the first conditioning transistor is connected in series with the second conditioning transistor.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.91111
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15796819', '15613185', '15274322', '11050895', '11050933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7454263863202287
- 35 USC 102 Novelty (BERT): 0.5776235654239559
- Combined Prediction Score: 0.7286461042306015
- Mean Citation Score: 381.345018
- Max Citation Score: 480.05124000000006
- Similarity Product: 473.5437781296444

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test