PATENT CLAIM ANALYSIS

Application Number: 15873027
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["711", "153000"]

Abstract:
A multi-processor system includes a register, a thread generating circuit, a flag determining circuit, a scheduler, an adjusting circuit and an interrupt controller. The register is recorded with availability of a predetermined processor with respect to a shared peripheral interrupt. The thread generating circuit receives multiple requests, and accordingly generates multiple threads to be executed. Each time the thread generating circuit is to generate a thread, the flag determining circuit determines a real-time flag of the thread according to an attribute of the thread. The scheduler selects the predetermined processor to execute a prioritized thread. The adjusting circuit sets, according to the real-time flag of the prioritized thread, the availability for the shared peripheral interrupt recorded in the register. The interrupt controller, while assigning interrupts, takes into account the availability recorded in the register.

Claim (Index 1):
A multi-processor system, comprising:\n a plurality of processors; a register, recorded therein a value representing availability of a predetermined processor, among the plurality of processors, with respect to a shared peripheral interrupt request; a thread generating circuit, generating a plurality of threads to be executed by the plurality of processors, the plurality of threads corresponding to a plurality of applications; a flag determining circuit, coupled to the thread generating circuit, for each thread, determining a real-time flag of one of the threads at least according to an attribute corresponding to the thread; a scheduler, selecting a prioritized thread to be executed by the predetermined processor from a plurality of threads assigned to the predetermined processor; an adjusting circuit, setting in the register, according to the real-time flag of the prioritized thread, the availability of the predetermined processor with respect to the shared peripheral interrupt request while the predetermined processor executes the prioritized thread; and an interrupt controller, assigning a plurality of interrupt requests to the plurality of processors, and taking into account the availability recorded in the register when assigning the plurality of interrupt requests, the plurality of interrupt requests comprising the shared peripheral interrupt request.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.55932
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13830663', '10404175', '14092498', '12646457', '11717623']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5150272455532389
- 35 USC 102 Novelty (BERT): 0.4764216873755467
- Combined Prediction Score: 0.5111666897354696
- Mean Citation Score: 198.973974
- Max Citation Score: 208.39061
- Similarity Product: 163.90857546572332

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test