PATENT CLAIM ANALYSIS

Application Number: 15918536
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "154000"]

Abstract:
A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Claim (Index 14):
The semiconductor memory apparatus according to  claim 13 , wherein the majority determiner comprises:\n a data bit selector configured to output all bits of the received data when both the first and second bit select signals are enabled, and output some bits of the received data when the first bit select signal is disabled and the second bit select signal is enabled; and a decoder configured to decode outputs of the data bit selector and generate the data control flag signal.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.83871
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15706218', '15017994', '12232719', '15597795', '12459106']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5393204865356819
- 35 USC 102 Novelty (BERT): 0.4660357171910113
- Combined Prediction Score: 0.5319920096012148
- Mean Citation Score: 177.27008800000004
- Max Citation Score: 182.9408
- Similarity Product: 149.4055889942169

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test