PATENT CLAIM ANALYSIS

Application Number: 16004517
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["326", "008000"]

Abstract:
An integrated circuit for a physically unclonable function (PUF) includes first and second PUF cells and a combination circuit. The first and second PUF cells respectively output first and second cell signals having unique levels based on a threshold level of a logic gate. The combination circuit includes a first stage that generates a first combination signal based on the first and second cell signals. The first and second PUF cells respectively include first and second logic gates to respectively output the first and second cell signals. The combination circuit includes a third logic gate that receives the first and second cell signals and outputs the first combination signal. The third logic gate has a same structure as each of the first and second logic gates.

Claim (Index 4):
The integrated circuit of  claim 3 , wherein:\n the first to third logic gates are NAND gates, and a level of the deactivated first and second enable signals is a logic low.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 94.0
- Lexical Diversity: 2.73469
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15984685', '14997937', '15939923', '15871306', '14667665']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6940760397763901
- 35 USC 102 Novelty (BERT): 0.4845959925774925
- Combined Prediction Score: 0.6731280350565003
- Mean Citation Score: 207.11221
- Max Citation Score: 210.5526
- Similarity Product: 150.00954849368338

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test