PATENT CLAIM ANALYSIS

Application Number: 16122842
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["257", "324000"]

Abstract:
According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect layer provided above a semiconductor substrate; a plurality of second interconnect layers provided above the first interconnect layer; a semiconductor layer electrically coupled to the first interconnect layer; a first insulating layer provided between the semiconductor layer and the plurality of second interconnect layers; and a plurality of first oxide layers in which one side of the first oxide layers is in contact with the plurality of second interconnect layers while the other side of the first oxide layers is in contact with the first insulating layer, and a voltage is applied to the plurality of second interconnect layers to vary a resistance value.

Claim (Index 4):
The device according to  claim 3 , wherein the plurality of first oxide layers have a film thickness of 5 nm or more and 20 nm or less in the first direction.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 2.88372
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14849023', '15433451', '13847765', '16109363', '14455148']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9190417701342366
- 35 USC 102 Novelty (BERT): 0.4868695544921639
- Combined Prediction Score: 0.8758245485700293
- Mean Citation Score: 176.49942800000005
- Max Citation Score: 180.7405
- Similarity Product: 124.08293409061432

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test