PATENT CLAIM ANALYSIS

Application Number: 15988618
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "076000"]

Abstract:
A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Claim (Index 16):
The method of  claim 12 , comprising oxidizing the third layer in the area exposed by the recess mask to form an oxidized third layer, after removing the fourth layer in the area exposed by the recess mask, wherein the second etch process removes the oxidized third layer.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 2.80392
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13886410', '15353952', '10758871', '14701313', '10849617']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9100015331336158
- 35 USC 102 Novelty (BERT): 0.4958321777836082
- Combined Prediction Score: 0.8685845975986151
- Mean Citation Score: 185.379414
- Max Citation Score: 196.52385
- Similarity Product: 123.80157896049322

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test