PATENT CLAIM ANALYSIS

Application Number: 16106584
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["716", "137000"]

Abstract:
A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.

Claim (Index 1):
A method for electronic circuit generation, comprising:\n receiving a first hierarchical circuit representation comprising a first plurality of electronic component nodes associated with a first component layer and a first plurality of electrical conductor nodes associated with a first metal layer; receiving a second hierarchical circuit representation comprising a second plurality of electronic component nodes associated with a second component layer and a second plurality of electrical conductor nodes associated with a second metal layer; and generating a unified hierarchical circuit representation comprising: a first module comprising a first module root node, a second module comprising a second module root node, a unified component layer, and a unified metal layer; wherein generating the unified hierarchical circuit representation comprises:\n for each electronic component node of the first plurality of electronic component nodes: generating a respective electronic component node associated with the unified component layer, wherein the first module root node is an ancestor node of the respective electronic component node; \n for each electrical conductor node of the first plurality of electrical conductor nodes: generating a respective electrical conductor node associated with the unified metal layer, wherein the first module root node is an ancestor node of the respective electrical conductor node; \n for each electronic component node of the second plurality of electronic component nodes: generating a respective electronic component node associated with the unified component layer, wherein the second module root node is an ancestor node of the respective electronic component node; and \n for each electrical conductor node of the second plurality of electrical conductor nodes: generating a respective electrical conductor node associated with the unified metal layer, wherein the second module root node is an ancestor node of the respective electrical conductor node.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 2.11364
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15816132', '15663582', '11368293', '15277984', '12198172']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2734038528145801
- 35 USC 102 Novelty (BERT): 0.4581540651544587
- Combined Prediction Score: 0.2918788740485679
- Mean Citation Score: 132.267268
- Max Citation Score: 238.44598
- Similarity Product: 234.82640042240607

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test