PATENT CLAIM ANALYSIS

Application Number: 15938922
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "195000"]

Abstract:
Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Claim (Index 21):
A circuit comprising:\n a depletion mode transistor comprising a first source/drain node, a second source/drain node, a first gate, and a second gate, wherein the depletion mode transistor is a normally-on transistor; a first enhancement mode transistor comprising a third source/drain node and a fourth source/drain node, and a third gate, wherein the third source/drain node is coupled to the first source/drain node; and a second enhancement mode transistor comprising a fifth source/drain node and a sixth source/drain node, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node, wherein the circuit is configured to operate in a first mode in which the depletion mode transistor is in a high resistance state, the first enhancement mode transistor is in a low resistance state, the second enhancement mode transistor is in a high resistance state, a second mode in which the depletion mode transistor is in a low resistance state of the depletion mode transistor, the first enhancement mode transistor is in the low resistance state of the first enhancement mode transistor, the second enhancement mode transistor is in a low resistance state of the second enhancement mode transistor, and a third mode in which the depletion mode transistor is in the high resistance state of the depletion mode transistor, the first enhancement mode transistor is in the low resistance state of the first enhancement mode transistor, the second enhancement mode transistor is in the low resistance state of the second enhancement mode transistor.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 90.0
- Lexical Diversity: 2.54545
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14884388', '15363987', '15491920', '14323777', '14222992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9017347054465228
- 35 USC 102 Novelty (BERT): 0.5805955950883926
- Combined Prediction Score: 0.8696207944107098
- Mean Citation Score: 300.790128
- Max Citation Score: 478.9179
- Similarity Product: 404.997701136589

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test