PATENT CLAIM ANALYSIS

Application Number: 15752403
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["363", "098000"]

Abstract:
The invention relates to an inverter circuit for the alternating connection of the phases of single-phase or multi-phase, in particular three-phase load (M) to the positive and to the negative terminal of a DC source (U B ), having pairs of electronic switches (T 1 , T 2 , T 3 , T 4 , T 5 , T 6 ) connected in parallel with one another and integrated into a power module ( 1 ), wherein the two switches belonging to the respective pair are connected in series, and wherein the connection for the respective phase (M 1 , M 2 , M 3 ) of the load (M) is provided at the connection of the two electronic switches belonging to the pair, having an intermediate circuit capacitor (C ZK ), which is connected in parallel to the DC source (U B ), and electric connections ( 2, 3 ) between the intermediate circuit N capacitor (C ZK ) and the power module ( 1 ) for the connection of the switch pairs (T 1 , T 2 , T 3 , T 4 , T 5 , T 6 ), wherein the electric connections ( 2, 3 ) have distributed parasitic inductances (L PAR ) and, as a result, cause electrical oscillations when switched, comprising a circuit arrangement for regenerative damping of the electrical oscillations, having a buffer capacitor (C buff , which is connected by the first connection thereof to a connection of the switch pairs (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ), a first diode (D high ), via which the buffer capacitor (C buff ) is connected to the other connection of the switch pairs (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ), further diodes (D low1 , D low2 , D low3 ), via which the buffer capacitor (C buff ) is connected to the connections for the respective phase (M 1 , M 2 , M 3 ) of the load (M), and a step-down controller (T S ), via which the buffer capacitor (C buff ) is connected to the intermediate circuit capacitor (C ZK ).

Claim (Index 1):
An inverter circuit for alternately connecting the phases of a single-phase or multi-phase load (M) to the positive and negative pole of a DC voltage source (U B ), the inverter circuit comprising:\n pairs of electronic switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; . . . ) which are connected in parallel with one another and are integrated in a power module ( 1 ), each switch of each respective pair of electronic switches being connected in series, and the terminal for the respective phase (M 1 , M 2 , M 3 ; . . . ) of the load (M) being provided at the connection of the two electronic switches belonging to the pair, an intermediate circuit capacitor (C ZK ) which is connected in parallel with the DC voltage source (U B ), and electrical connections ( 2 ,  3 ) between the intermediate circuit capacitor (C ZK ) and the power module ( 1 ) for connecting the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; . . . ), the electrical connections ( 2 ,  3 ) having distributed parasitic inductances (L PAR ) and, as a result, causing electrical oscillations during switching; and a circuit arrangement for regeneratively damping the electrical oscillations, having\n a buffer capacitor (C Buff ), the first terminal of which is connected to a terminal of the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; . . . ), \n a first diode (D High ), via which the buffer capacitor (C Buff ) is connected to the other terminal of the pairs of switches (T 1 , T 2 ; T 3 , T 4 ; T 5 , T 6 ; . . . ), \n further diodes (D Low1 , D Low2 , D Low3 ; . . . ), via which the buffer capacitor (C Buff ) is connected to the terminals for the respective phase (M 1 , M 2 , M 3 ; . . . ) of the load (M), and \n a buck converter (T S ), via which the buffer capacitor (C Buff ) is connected to the intermediate circuit capacitor (C ZK ).

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 3.79279
- Patent Class: 363.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12782001', '12218018', '14035290', '12477948', '12297525']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8177319088356362
- 35 USC 102 Novelty (BERT): 0.4727194415001374
- Combined Prediction Score: 0.7832306621020864
- Mean Citation Score: 212.43481000000003
- Max Citation Score: 223.42596
- Similarity Product: 189.08339368532185

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test