PATENT CLAIM ANALYSIS

Application Number: 15910730
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["716", "119000"]

Abstract:
Respective large block synthesis (LBS) blocks of an integrated circuit (IC) are overlapped along a corner of each respective LBS block to form an overlap area having an area less than respective areas of respective LBS blocks that are overlapped. A first portion of the overlap area is allocated to a first LBS block and configured to be used by the first LBS block, and a second portion of the overlap area is allocated to a second LBS block and configured to be used by the second LBS block.

Claim (Index 19):
The computer program product of  claim 18 , wherein the program instructions configured to allocate a first portion of the overlap area to the first LBS block and a second portion of the overlap area to the second LBS block are further configured to cause the processor to perform a method further comprising:\n forming at least one contiguous area by placing two or more sub-portions of two or more adjacent sub-blocks allocated to a same LBS block along at least one shared edge of the two or more adjacent sub-blocks.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 90.0
- Lexical Diversity: 2.23256
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15170157', '15007754', '15840595', '15195363', '15840631']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3573804044154436
- 35 USC 102 Novelty (BERT): 0.5369656435106751
- Combined Prediction Score: 0.3753389283249668
- Mean Citation Score: 296.721838
- Max Citation Score: 433.23935
- Similarity Product: 312.18246672431826

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test