PATENT CLAIM ANALYSIS

Application Number: 16371174
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-07
Patent Classification: ["375", "240020"]

Abstract:
Power consumption of a decoder is reduced. The decoder includes an FPGA. The FPGA performs at least one processing to decode the data. In the case where the data has first resolution, an input data signal of the FPGA is a binary signal and a clock frequency of the FPGA is a first frequency. In the case where the resolution of the data is lower than the first resolution, the input data signal of the FPGA is a pulse signal and the FPGA operates at a second frequency which is lower than the first frequency. The FPGA operates at the first clock frequency in the case of decoding 8K data and the FPGA operates at the second clock frequency in the case of decoding 4K or 2K data.

Claim (Index 1):
A display device comprising a logic circuit,\n wherein the logic circuit comprises latch circuits, multiplexers, an arithmetic circuit, a delay circuit, and an output timing generation circuit, wherein each of the latch circuits is capable of receiving a pulse signal from an adjacent logic circuit and outputting a first signal and a second signal, wherein a third signal obtained by a logical operation on the first signals controls power supply to the arithmetic circuit and the delay circuit, wherein each of the multiplexers is capable of receiving each of the second signals and a binary data signal from an adjacent logic circuit and outputting the second signal or the binary data signal to the arithmetic circuit, wherein the second signal is obtained by delaying the first signal in each of the latch circuits, wherein the arithmetic circuit is capable of receiving the second signal or the binary data signal and outputting a fourth signal, wherein the delay circuit is capable of receiving the third signal and outputting a fifth signal, wherein the fifth signal is obtained by delaying the third signal so as to correspond to a delay in a critical path of the arithmetic circuit, and wherein the output timing generation circuit is capable of receiving a sixth signal obtained by a logical operation on the third signal and the fifth signal and resetting the latch circuits.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 100.0
- Lexical Diversity: 2.95652
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15083716', '15729191', '15876724', '15729169', '15210068']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4613607207163191
- 35 USC 102 Novelty (BERT): 0.4846466291763891
- Combined Prediction Score: 0.4636893115623261
- Mean Citation Score: 203.097034
- Max Citation Score: 208.0487
- Similarity Product: 154.0365699276805

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test