PATENT CLAIM ANALYSIS

Application Number: 15958497
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-07
Patent Classification: ["714", "748000"]

Abstract:
The disclosure is related to an RF signal processing apparatus. The apparatus includes a processor and a buffer memory circuit. The apparatus includes a host interface for connecting with a host and an RF circuit for transmitting and receiving RF signals. The processor processes the RF signals to or from the RF circuit. The processor converts the received RF signals into data, or converts the data into the RF signals to be transmitted. The buffer memory circuit has a controller and two buffer memories. This memory architecture allows a system to assign a task to a first buffer memory and another task to a second buffer memory without restricting that the conventional buffer memory is limited to doing one task at a time. This memory architecture can solve inefficiency problems due to insufficient data transmission since the conventional buffer memory cannot be filled within a limited time period.

Claim (Index 1):
An RF signal processing apparatus, comprising:\n a processor, used to process radio-frequency signals received or transmitted by an RF circuit, and to digitize the received radio-frequency signals to a data, or to convert the data to the radio-frequency signals to be transmitted; and a buffer memory circuit, electrically connected with the processor, including a controller, a first buffer memory and a second buffer memory, wherein the buffer memory circuit is electrically connected with a host interface; wherein, the controller is used to completely transmit a second data between the second buffer memory and the host interface within a first time slot, and completely transmit a third data between the first buffer memory and the host interface within a second time slot; each time slot is divided into a first proportional time and a second proportional time; wherein, the controller controls the first buffer memory to completely transmit a first data with the processor within the first proportional time of the first time slot; and the controller controls the second buffer memory to completely transmit the second data with the processor within the first proportional time of the second time slot.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 91.0
- Lexical Diversity: 2.22535
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11025673', '11166712', '11479885', '10293452', '13474909']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2528740792639439
- 35 USC 102 Novelty (BERT): 0.4725517378932968
- Combined Prediction Score: 0.2748418451268792
- Mean Citation Score: 165.488854
- Max Citation Score: 180.35022
- Similarity Product: 140.32775673276902

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test