PATENT CLAIM ANALYSIS

Application Number: 16106269
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "798000"]

Abstract:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

Claim (Index 36):
The semiconductor on insulator structure of  claim 21  wherein the dielectric layer in interfacial contact with the semiconductor layer is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.

Metadata:
- Claim Count in Document: 101.0
- Percentile: 96.0
- Lexical Diversity: 2.02174
- Patent Class: 257.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15675001', '14524693', '15984586', '15526798', '16077176']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9501920464831
- 35 USC 102 Novelty (BERT): 0.5795514971750803
- Combined Prediction Score: 0.913127991552298
- Mean Citation Score: 478.520996
- Max Citation Score: 506.38916
- Similarity Product: 390.32461081127406

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test