PATENT CLAIM ANALYSIS

Application Number: 15862926
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "004000"]

Abstract:
Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Claim (Index 3):
The method of  claim 1 , wherein\n in the forming of the second insulation layer, a top of the second insulation layer has a structure which is embossed over the tops of the plurality of first memory cells and is recessed over the gaps between adjacent first memory cells, in the forming of the plurality of trenches, the second insulation layer is exposed to lower portions of both side surfaces of each of the plurality of trenches, and in the forming of the second electrode line layer, lower portions of both side surfaces of each of the plurality of second electrode lines are covered by the second insulation layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 86.0
- Lexical Diversity: 1.59524
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15288233', '14736525', '15285922', '15179068', '15595307']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913471709435333
- 35 USC 102 Novelty (BERT): 0.4905195088303728
- Combined Prediction Score: 0.8711764893748369
- Mean Citation Score: 217.348484
- Max Citation Score: 227.6333
- Similarity Product: 173.23095783072708

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test