PATENT CLAIM ANALYSIS

Application Number: 15927122
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["327", "291000"]

Abstract:
A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first semiconductor die includes buffers in a second-stage configuration to an Nth-stage configuration (N being an integer of 3 or more) in a clock tree structure, and the second semiconductor die includes a logic circuit electrically connected to the buffer in the Nth-stage configuration.

Claim (Index 15):
The manufacturing method of the semiconductor device according to  claim 14 , wherein\n the plural through electrodes are uniformly arranged in an entire lower surface of the first semiconductor.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 1.84615
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10962447', '10718515', '14638624', '10781001', '15211298']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7806579893726074
- 35 USC 102 Novelty (BERT): 0.4926914552291028
- Combined Prediction Score: 0.751861335958257
- Mean Citation Score: 161.610682
- Max Citation Score: 178.24863
- Similarity Product: 109.38794952058733

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test