PATENT CLAIM ANALYSIS

Application Number: 16139636
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "233100"]

Abstract:
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Claim (Index 13):
The DRAM device of  claim 10 , wherein the plurality of mode registers to further store a second value that sets a power down mode in which receivers of the CA interface, and transmitters and receivers of the data interface are powered down in response to the first transition of the power mode signal.

Metadata:
- Claim Count in Document: 57.0
- Percentile: 97.0
- Lexical Diversity: 2.37736
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14573323', '15855535', '13980826', '16032575', '14554904']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8510782007730704
- 35 USC 102 Novelty (BERT): 0.5168971633978334
- Combined Prediction Score: 0.8176600970355468
- Mean Citation Score: 235.44426600000003
- Max Citation Score: 273.66296
- Similarity Product: 212.6208876413393

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test