PATENT CLAIM ANALYSIS

Application Number: 16028918
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "369000"]

Abstract:
An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Claim (Index 16):
An integrated circuit device comprising:\n a substrate; a first fin active area protruding from the substrate; a second fin active area protruding from the substrate; a first insulating liner disposed on a first portion of the substrate and on a sidewall of the first fin active area; a first stress liner disposed on the first insulating liner; a first device isolation layer disposed on the first stress liner; a first gate insulating layer disposed on the first fin active area and on the first device isolation layer; a second insulating liner disposed on a second portion of the substrate and on a sidewall of the second fin active area; a second stress liner disposed on the second insulating liner; a second device isolation layer disposed on the second stress liner; and a second gate insulating layer disposed on the second fin active area and on the second device isolation layer, wherein the first stress liner is a single layer formed between the first device isolation layer and the first insulating liner, the second stress liner is a single layer formed between the second device isolation layer and the second insulating liner, the first gate insulating layer includes a first protruding portion disposed on an end portion of the first stress liner, the second gate insulating layer includes a second protruding portion disposed on an end portion of the second stress liner, and a thickness of a bottom portion of the first insulating liner that is disposed on the first portion of the substrate is less than a thickness of a side portion of the first insulating liner that is disposed on the sidewall of the first fin active area.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15223332', '15191562', '15206868', '15491303', '14965982']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9116903654487534
- 35 USC 102 Novelty (BERT): 0.5497568561974974
- Combined Prediction Score: 0.8754970145236278
- Mean Citation Score: 311.0553500000001
- Max Citation Score: 399.8534
- Similarity Product: 327.49723973300456

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test