PATENT CLAIM ANALYSIS

Application Number: 15904124
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["331", "057000"]

Abstract:
A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Claim (Index 15):
The method of  claim 11 , wherein the first clock edge is a clock edge for a reference clock signal, and wherein the second clock edge is a clock edge for a phase-locked loop (PLL) clock signal, the method further comprising measuring a time internal error for the PLL clock signal responsive to the measurement of the delay.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 1.04348
- Patent Class: 331.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14167852', '12107584', '15488278', '15711012', '14343941']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7592715360157475
- 35 USC 102 Novelty (BERT): 0.4899196645749399
- Combined Prediction Score: 0.7323363488716668
- Mean Citation Score: 223.52531800000003
- Max Citation Score: 232.37146
- Similarity Product: 174.08540936514382

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test