PATENT CLAIM ANALYSIS

Application Number: 15938258
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "401000"]

Abstract:
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

Claim (Index 16):
A method of forming a semiconductor structure comprising:\n forming a plurality of source/drain (S/D) contact structures; etching a first trench; depositing a first conductive material into the first trench to form a via rail structure over two or more S/D contact structures of the plurality of S/D contact structures, wherein the via rail structure is in a different interconnect level than a local interconnect line of the semiconductor structure; etching a second trench; depositing a second conductive material into the second trench to form a deep via over and electrically connected to the via rail structure; etching a third trench; and depositing a third conductive material into the third trench to form one or more conductive structures over and electrically connected to the deep via.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 90.0
- Lexical Diversity: 1.65306
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12216678', '15479633', '15269294', '15213506', '14963235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9038102284990416
- 35 USC 102 Novelty (BERT): 0.4646026136539615
- Combined Prediction Score: 0.8598894670145337
- Mean Citation Score: 133.71507000000005
- Max Citation Score: 135.53804
- Similarity Product: 99.5265868829107

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test