PATENT CLAIM ANALYSIS

Application Number: 15897659
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["711", "118000"]

Abstract:
Techniques are described for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. A memory is partitioned into a group of sub-blocks, a parity block is associated with the sub-blocks, and the sub-blocks are accessed to read data as needed. A pending write buffer is added to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer handles collisions for write accesses to the same block.

Claim (Index 8):
The computer-readable storage medium of  claim 7 , wherein the virtual address comprises a set of higher-order bits associated with the second memory address.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 88.0
- Lexical Diversity: 1.96154
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12870596', '13592793', '14575872', '10695397', '13994116']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5009073782328936
- 35 USC 102 Novelty (BERT): 0.5117712815156276
- Combined Prediction Score: 0.501993768561167
- Mean Citation Score: 209.978142
- Max Citation Score: 274.49347
- Similarity Product: 178.5378288853538

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test