PATENT CLAIM ANALYSIS

Application Number: 15765279
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["711", "122000"]

Abstract:
In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.

Claim (Index 9):
The method of  claim 8  including determining whether a kernel should cache a permutated pattern.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.53846
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14498220', '15525033', '15483641', '15388915', '15190663']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5034963563748182
- 35 USC 102 Novelty (BERT): 0.512780552820767
- Combined Prediction Score: 0.504424776019413
- Mean Citation Score: 213.99325600000003
- Max Citation Score: 219.0153
- Similarity Product: 128.50402259384393

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test