PATENT CLAIM ANALYSIS

Application Number: 16384819
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-10
Patent Classification: ["712", "201000"]

Abstract:
According to some embodiments, a dataflow accelerator comprises a control/command core, a scratchpad and a coarse grain reconfigurable array (CGRA). The scratchpad comprises a write controller to transmit data to an input vector port interface and to receive data from the input vector port interface. The CGRA receives data from the input vector port interface where the CGRA comprising a plurality of interconnects and a plurality of functional units.

Claim (Index 19):
The medium of  claim 18 , wherein the method step of delaying the received data includes at least one of\n storing the received data in a data structure at one or more of the plurality of functional units, storing the received data at one or both of an input vector port and an input vector port interface prior to transmitting the data to the CGRA, altering a path that the received data travels through the CGRA, and storing the received data at a router prior to transmitting the data to the CGRA.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 100.0
- Lexical Diversity: 1.80952
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13012945', '14330675', '13929762', '15215374', '15216624']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5623697112887164
- 35 USC 102 Novelty (BERT): 0.4831263459741226
- Combined Prediction Score: 0.5544453747572571
- Mean Citation Score: 135.25886200000002
- Max Citation Score: 148.15508
- Similarity Product: 96.06507093666076

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test