PATENT CLAIM ANALYSIS

Application Number: 16035251
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-05
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

Claim (Index 19):
The method of  claim 16 , wherein depositing the third sub-spacer comprises depositing a silicon oxide layer using tetraethyl orthosilicate (TEOS) as a precursor.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 95.0
- Lexical Diversity: 3.51111
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14045899', '14039925', '14095588', '15413161', '14040055']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9000975909781544
- 35 USC 102 Novelty (BERT): 0.4841231007255942
- Combined Prediction Score: 0.8585001419528985
- Mean Citation Score: 148.62210399999995
- Max Citation Score: 151.75377
- Similarity Product: 106.48653879648327

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test