PATENT CLAIM ANALYSIS

Application Number: 16019884
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["326", "040000"]

Abstract:
An information processing apparatus includes a processor for an arithmetic processing and a reconfiguration circuit for the arithmetic processing, wherein the reconfiguration circuit includes a plurality of blocks, an inter-block FIFO that couples the blocks, and a common region that is used for a reconfiguration that changes a size of the inter-block FIFO.

Claim (Index 4):
The information processing apparatus according to  claim 3 , wherein the capacity monitor periodically monitors the empty capacity of the inter-block FIFO and notifies the controller of the monitored empty capacity, and the controller controls a number of stages of the target inter-block FIFO so as to change the size of the target inter-block FIFO.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 1.9
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11778457', '15804525', '10323761', '10948702', '15647858']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6514581782190313
- 35 USC 102 Novelty (BERT): 0.4915821161658821
- Combined Prediction Score: 0.6354705720137164
- Mean Citation Score: 127.821269
- Max Citation Score: 133.17245
- Similarity Product: 75.25318951135277

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test