PATENT CLAIM ANALYSIS

Application Number: 16107909
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "194000"]

Abstract:
Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

Claim (Index 10):
An apparatus comprising:\n a clock buffer configured to provide a clock signal; a command decoder configured to receive the clock signal and a command signal, the command decoder further configured to decode the command signal responsive, at least in part, to the clock signal to provide a decoded command signal, the decoded command signal being asynchronous with the clock signal; and a synchronizing circuit configured to receive the clock signal and the decoded command signal, the synchronizing circuit further configured to synchronize the decoded command signal to the clock signal to provide a synchronized command signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 1.96154
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15139102', '15595056', '15063229', '15139120', '15890943']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7907301610383725
- 35 USC 102 Novelty (BERT): 0.5634689614526086
- Combined Prediction Score: 0.7680040410797961
- Mean Citation Score: 316.076746
- Max Citation Score: 447.6691
- Similarity Product: 401.6223483516574

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test