PATENT CLAIM ANALYSIS

Application Number: 16029603
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Claim (Index 1):
A method for conditioning a shared node of a plurality of dynamic decode circuits, each dynamic decode circuit having a decoder, an output transistor and a conditioning transistor, each conditioning transistor of the plurality of dynamic decode circuits connected in parallel to the shared node, the each dynamic decode circuit performing a method, the method comprising:\n receiving input signals, by a plurality of inputs of the decoder; precharging a first node of the decoder to a high state, by a first precharge circuit comprising a first precharge transistor, based on being in a precharge phase of an evaluation clock, the first node being conductively connected to a gate of the output transistor; precharging a second node of the output transistor to the high state, by a second precharge circuit comprising a second precharge transistor, based on being in the precharge phase of the evaluation clock, the output transistor being disposed between the second node and an interconnecting node; pulling a third node of the decoder to a low state, by a first evaluate transistor, based on being in an evaluation phase of the evaluation clock; pulling the interconnecting node of the output transistor to the low state, by a second evaluate transistor, based on being in the evaluation phase of the evaluation clock;\n based on the plurality of inputs being in a predetermined state, causing the first node to be in the high state; and \n based on the plurality of inputs not being in the predetermined state, causing the first node to be in the low state; \n based on the first node being in the high state during the evaluation phase of the evaluation clock, causing the second node of the output transistor to be in the low state; and based on the first node being in the low state during the evaluation phase of the evaluation clock, causing the second node of the output transistor to be in the high state; and causing, by a conditioning transistor, the shared node to be in a conditioned state, wherein the conditioning transistor consists of any one of a precharge transistor of the precharge circuit and an evaluate transistor.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 95.0
- Lexical Diversity: 1.79592
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16029604', '16029577', '15796819', '16029607', '15613185']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.763212675093615
- 35 USC 102 Novelty (BERT): 0.5717314075198556
- Combined Prediction Score: 0.744064548336239
- Mean Citation Score: 465.365266
- Max Citation Score: 497.16586
- Similarity Product: 436.2712494149352

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test