PATENT CLAIM ANALYSIS

Application Number: 16237657
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["716", "108000"]

Abstract:
The present invention provides theoretical bases and practical schematic diagrams for a state machine which is coded in HDL and synthesized to generate a circuit that comprises one or more state groups each of which has an independent clock gating device. A state group will receive a clock pulse on the next cycle when either a synchronous initialization input signal for a state machine is asserted on the current cycle or the state group will change states on the next cycle, reducing power consumption and simplifying the final logic, compared with a traditionally generated state machine circuit. In addition the invention also provides a code designer with a proposed method for HDL standard on how to divide all states in a state machine into state groups at his discretion.

Claim (Index 13):
A method for generating a circuit for a state machine, comprising:\n defining a plurality of jumping signals, a currently asserted jumping signal in the plurality of jumping signals making the state machine jump from a current state of the currently asserted jumping signal to a target state of the currently asserted jumping signal on a next cycle; classifying each jumping signal of the plurality of jumping signals into one of two categories, the two categories comprising:\n a local jumping signal when the current state and the target state of the each jumping signal of the plurality of jumping signals are different; and \n a holding jumping signal when the current state and the target state of the each jumping signal of the plurality of jumping signals are the same; \n feeding each state in a plurality of states with the at least one local jumping signal, and the each state in the plurality of states being the common target state of the at least one local jumping signal; feeding an initial state in the plurality of states with a synchronous initialization input signal SINI for the state machine; storing the plurality of states in at least one memory bit; attaching the at least one memory bit with a clock gating device; generating a clock pulse for the at least one memory bit on the next cycle when either of two conditions is satisfied, the two conditions comprising:\n the synchronous initialization input signal SINI for the state machine is asserted on a current cycle; or \n none of the at least one holding jumping signal is asserted on the current cycle; and \n generating a plurality of state outputs from the at least one memory bit.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.61446
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15861093', '12121827', '11608558', '10262769', '10428170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3232149539445298
- 35 USC 102 Novelty (BERT): 0.4623828431304762
- Combined Prediction Score: 0.3371317428631245
- Mean Citation Score: 164.27026999999995
- Max Citation Score: 197.74767
- Similarity Product: 148.47488201378525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test