PATENT CLAIM ANALYSIS

Application Number: 16057603
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["716", "055000"]

Abstract:
Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

Claim (Index 5):
The memory device of  claim 4 , wherein metal lines of an interconnect level extend in the second direction and have a second pitch that is the same as the periodicity of the repeating connection positions.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.1875
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14637158', '13777811', '15233494', '14982362', '14689409']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3862718217680407
- 35 USC 102 Novelty (BERT): 0.5220350852915795
- Combined Prediction Score: 0.3998481481203946
- Mean Citation Score: 284.6744240000001
- Max Citation Score: 378.2104
- Similarity Product: 277.8681016012192

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test