PATENT CLAIM ANALYSIS

Application Number: 15882607
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["365", "189050"]

Abstract:
Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command und activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal.

Claim (Index 10):
The apparatus of  claim 8 ,\n wherein the memory cell array and the second circuit are arranged in a cell array area, and wherein the first and third circuits are arranged in a peripheral circuit area located outside the cell array area.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.81579
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15236281', '15641118', '12801326', '13317598', '12167719']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7876254486677119
- 35 USC 102 Novelty (BERT): 0.4838127098667956
- Combined Prediction Score: 0.7572441747876203
- Mean Citation Score: 136.144932
- Max Citation Score: 143.82451
- Similarity Product: 87.70900128835916

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test