PATENT CLAIM ANALYSIS

Application Number: 15922929
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-06
Patent Classification: ["710", "074000"]

Abstract:
A host device includes a first serial peripheral interface (SPI) and a second SPI to communicate with an embedded multimedia card (eMMC) device. The host device has a mode controller that controls the first SPI to toggle between first transmission and first reception modes for command transmission and response reception, respectively. The mode controller controls the second SPI to toggle between second transmission and second reception modes for data transmission and data reception, respectively.

Claim (Index 20):
An integrated circuit, comprising:\n a host device comprising a first serial peripheral interface (SPI) having a command output terminal SPI 1  MOSI and a response input terminal SPI 1  MISO, and a second SPI having a data output terminal SPI 2  MISO and a data input terminal SPI 2  MOSI, a first clock terminal SPI 1  CLK, and a first chip-select terminal SPI 1  CS; and an embedded multimedia card (eMMC) device connected to the host device, wherein the eMMC device includes (i) a memory array for storing data received from the host device; (ii) a first terminal connected to the command output terminal SPI 1  MOSI of the first SPI for receiving data-read and data-write commands from the host device, and for transmitting a response to the host device, and (iii) a second terminal connected to the data input terminal SPI 2  MOSI and data output terminal SPI 2  MISO of the second SPI, wherein the eMMC device transmits read-data read from the memory array to the host device in response to a data-read command, and the host device transmits write-data to the eMMC for storing in the memory array in response to a write-data command, wherein the first SPI is operable in first transmission and first reception modes, and the second SPI is operable in second transmission and second reception modes, and wherein the host device further comprises a mode controller that causes the first SPI to operate in one of the first transmission and first reception modes, and the second SPI to operate in one of the second transmission and second reception modes, based on the data-read and data-write commands, and wherein the host device further comprises first and second resistors that act as fail-safe resistors for preventing an open circuit condition of the command and data channels.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.02439
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14025886', '14024655', '14025909', '14025866', '14592114']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6619144079605522
- 35 USC 102 Novelty (BERT): 0.470218084444047
- Combined Prediction Score: 0.6427447756089018
- Mean Citation Score: 170.09868799999995
- Max Citation Score: 176.71739
- Similarity Product: 131.53278766216334

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test