PATENT CLAIM ANALYSIS

Application Number: 15907264
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["327", "201000"]

Abstract:
A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Claim (Index 17):
The semiconductor device according to  claim 12 , wherein the correction circuit includes:\n a fifth inverter having an input terminal connected to receive an inversion delay signal of the first strobe signal and an output terminal through which the first clock signal is supplied; and a sixth inverter having an input terminal connected to receive an inversion delay signal of the second strobe signal and an output terminal through which the second clock signal is supplied.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 3.47619
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14597639', '10095945', '11502572', '15391584', '13424707']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.746998651329842
- 35 USC 102 Novelty (BERT): 0.4838127675417684
- Combined Prediction Score: 0.7206800629510346
- Mean Citation Score: 180.57787
- Max Citation Score: 184.70023
- Similarity Product: 135.1161391704196

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test