PATENT CLAIM ANALYSIS

Application Number: 15761708
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["327", "107000"]

Abstract:
A digitally controlled oscillator, including: a frequency divider chain, configured to perform frequency division on an input clock signal to produce K basic clock signals, wherein frequencies and periods of the K basic dock signals are the same and a time difference between two adjacent basic clock signals is a basic time unit: and a frequency synthesizer, configured to receive the K basic clock signals from the frequency divider chain, determine a first period and a second period according to the basic time unit and a frequency control word, and generate a synthetic clock signal based on the K basic clock signals, wherein the synthetic clock signal uses the first period and the second period in an alternate manner.

Claim (Index 14):
The digitally controlled oscillator according to  claim 13 , wherein a frequency and a period of the synthetic clock signal are calculated by the following formula:\n 1/ f=T=F*\u0394 where F is the frequency control word, \u0394 is the basic time unit, f is the frequency of the synthetic clock signal, and T is the period of the synthetic clock signal.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 90.0
- Lexical Diversity: 2.22414
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15751615', '14726666', '14945468', '15665579', '14669918']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7799757500026262
- 35 USC 102 Novelty (BERT): 0.5346832564569611
- Combined Prediction Score: 0.7554465006480597
- Mean Citation Score: 296.084598
- Max Citation Score: 361.59317
- Similarity Product: 259.4270755238253

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test