PATENT CLAIM ANALYSIS

Application Number: 15933812
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "401000"]

Abstract:
In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor fin that extends from a substrate. The first semiconductor fin has source and drain regions, which are separated from one another by a channel region in the first semiconductor fin. A gate overlies an upper surface and sidewalls of the channel region. A contact is coupled to the source or drain region of the first semiconductor fin, where the source or drain region includes a layer of epitaxial material with a substantially diamond-shaped cross-section. The contact surrounds the source or drain region on top and bottom surfaces of the substantially diamond-shaped cross-section. A first capping material is arranged along outer sidewalls of the first semiconductor fin under the contact. The first capping material has an uppermost surface that is spaced below a lowermost surface of the contact by a non-zero distance.

Claim (Index 14):
A semiconductor device,\n a first semiconductor fin extending from a substrate through an isolation layer, wherein the first semiconductor fin comprises a first source region and a first drain region disposed on opposite ends of the first semiconductor fin; a second semiconductor fin laterally spaced from the first semiconductor fin extending from the substrate and through the isolation layer, wherein the second semiconductor fin comprises a second source region and a second drain region disposed on opposite ends of the second semiconductor fin; a gate electrode overlying the first semiconductor fin between the first source region and the first drain region and overlying the second semiconductor fin between the second source region and the second drain region; a first contact coupled to the first source region; a first capping material arranged along outer sidewalls of the first semiconductor fin, wherein a bottom surface of the first capping material contacts the isolation layer and an uppermost surface of the first capping material is arranged below a bottommost surface of the first contact; and contact residue disposed in the isolation layer between the first semiconductor fin and the second semiconductor fin, wherein a first portion of an upper surface of the isolation layer separates the first capping material from the contact residue.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 90.0
- Lexical Diversity: 2.27536
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15231967', '14196320', '14225912', '14599246', '14880454']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9261484358644002
- 35 USC 102 Novelty (BERT): 0.4945790825974945
- Combined Prediction Score: 0.8829915005377097
- Mean Citation Score: 198.556098
- Max Citation Score: 249.79156
- Similarity Product: 203.34894338191987

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test