PATENT CLAIM ANALYSIS

Application Number: 15872207
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.

Claim (Index 9):
The semiconductor device according to  claim 8 , wherein top surfaces of the additional dielectric layer and the silicide region are at a height above the substrate that is higher than a top surface of the gate structure.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 3.74419
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14967921', '15628329', '15171486', '15654882', '14985943']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9377970784872144
- 35 USC 102 Novelty (BERT): 0.5676449488655245
- Combined Prediction Score: 0.9007818655250454
- Mean Citation Score: 356.77122799999995
- Max Citation Score: 471.14297
- Similarity Product: 371.1999405660319

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test