PATENT CLAIM ANALYSIS

Application Number: 15895541
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "329000"]

Abstract:
A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.

Claim (Index 5):
The vertical transistor of  claim 4 , wherein the distal S/D extension region is formed between a first non-diffused portion of the channel region and a second non-diffused portion of the channel region.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 88.0
- Lexical Diversity: 2.1
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15147342', '15294345', '15834380', '15164046', '14964097']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914415677590847
- 35 USC 102 Novelty (BERT): 0.5715557291346517
- Combined Prediction Score: 0.8801296827452275
- Mean Citation Score: 293.6434700000001
- Max Citation Score: 472.29898
- Similarity Product: 343.16021714277144

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test