PATENT CLAIM ANALYSIS

Application Number: 16049059
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

Claim (Index 20):
The semiconductor device of  claim 19  wherein:\n the lower dielectric layer includes one or more selected from the group consisting of SiON and SiN, and \n the upper dielectric layer includes one or more selected from the group consisting of SiCN, SiOC, SiOCN and a low-k material.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 95.0
- Lexical Diversity: 2.39216
- Patent Class: 257.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16049715', '15602807', '15620063', '15653068', '15649909']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9395868613484352
- 35 USC 102 Novelty (BERT): 0.4907442777470908
- Combined Prediction Score: 0.8947026029883008
- Mean Citation Score: 229.223676
- Max Citation Score: 243.76762
- Similarity Product: 188.57821967685936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test