PATENT CLAIM ANALYSIS

Application Number: 15874444
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "063000"]

Abstract:
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.

Claim (Index 14):
The integrated circuit of  claim 8 , wherein area of the array of bitcells is decreased due to using the third strap to couple the at least one bitcell to the at least one wordline of the one or more wordlines within the boundary of the at least one bitcell.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.21212
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15789715', '14181363', '15439899', '15462549', '14720930']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8088750671960514
- 35 USC 102 Novelty (BERT): 0.4942299067500902
- Combined Prediction Score: 0.7774105511514553
- Mean Citation Score: 204.050526
- Max Citation Score: 214.72023
- Similarity Product: 136.02439111879704

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test