PATENT CLAIM ANALYSIS

Application Number: 15954104
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "270000"]

Abstract:
A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Claim (Index 16):
The semiconductor structure of  claim 15 , further comprising another dummy gate formed at least partially over another footing region formed at an interface between one of the first and second active regions and another isolation region.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 91.0
- Lexical Diversity: 2.85185
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14499949', '15250023', '14464315', '15213179', '13538220']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9022224353172668
- 35 USC 102 Novelty (BERT): 0.5055449330073734
- Combined Prediction Score: 0.8625546850862775
- Mean Citation Score: 238.72467000000003
- Max Citation Score: 301.2449
- Similarity Product: 299.08121486059423

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test