PATENT CLAIM ANALYSIS

Application Number: 15882190
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["438", "284000"]

Abstract:
Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.

Claim (Index 11):
The method of  claim 10  further comprising:\n forming a dummy gate layer on the substrate after forming the device isolation layer, the dummy gate layer comprising an opening exposing the device isolation layer; \n forming a gate separation layer in the opening of the dummy gate layer and on the dummy gate layer; \n forming a mask pattern having a linear shape on the dummy gate layer and the gate separation layer; \n forming the gate separation pattern and first and second dummy gate patterns by etching the gate separation layer and the dummy gate layer using the mask pattern as an etch mask, the first and second dummy gate patterns being on the respective second opposing sidewalls of the gate separation pattern; and \n removing the first and second dummy gate patterns after forming the first and second gate spacers on the respective first opposing sidewalls of the gate separation pattern to form first and second gate recesses between the first and second gate spacers, wherein the first and second gate electrodes are formed in the first and second gate recesses respectively.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 2.88462
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15189312', '15003288', '14499922', '15062553', '13533653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8779736517093023
- 35 USC 102 Novelty (BERT): 0.5380476909760458
- Combined Prediction Score: 0.8439810556359767
- Mean Citation Score: 323.23318000000006
- Max Citation Score: 387.63412
- Similarity Product: 303.21779761448863

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test