PATENT CLAIM ANALYSIS

Application Number: 15981320
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["717", "124000"]

Abstract:
A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

Claim (Index 1):
A computing device comprising:\n a processing unit; and a debug controller communicatively coupled to the processing unit and including at least one input/output interface, wherein the debug controller contains logic that causes the debug controller to perform a debug monitor function, the debug monitor function configured to:\n recognize a first breakpoint for the processing unit in a first code section having a first execution priority, in part, by pausing the processing unit and setting a first halt indication flag as an indication to establish a first debug context; \n establish the first debug context and clear the first halt indication flag; \n receive an indication that a second code section of a higher execution priority than the first execution priority requires servicing while the processing unit is halted at the first breakpoint; \n allow the processing unit to resume execution to service the second code section while maintaining the first debug context and the current state of the first halt indication flag; and \n return to an execution state consistent with the first debug context, in part, by pausing the processing unit in the first code section upon completion of servicing the second code section.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 1.64368
- Patent Class: 717.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13888370', '13888357', '14842784', '11754007', '12120543']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3974511999785394
- 35 USC 102 Novelty (BERT): 0.5003185979285719
- Combined Prediction Score: 0.4077379397735426
- Mean Citation Score: 232.259952
- Max Citation Score: 253.94125
- Similarity Product: 212.87964351907368

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test