PATENT CLAIM ANALYSIS

Application Number: 15918212
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["714", "755000"]

Abstract:
According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.

Claim (Index 36):
The method according to  claim 35 , wherein\n the nonvolatile memory is allowed to store data of a plurality of bits in a memory cell, and the second data item is data which is programmed in a same memory cell as a memory cell in which the program operation of the first data item is failed.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.67347
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15067958', '14833246', '14842626', '11330233', '14636768']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2598533379917278
- 35 USC 102 Novelty (BERT): 0.5178871867681412
- Combined Prediction Score: 0.2856567228693691
- Mean Citation Score: 176.073014
- Max Citation Score: 312.8732
- Similarity Product: 254.2372615569592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test