PATENT CLAIM ANALYSIS

Application Number: 15859863
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "401000"]

Abstract:
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Claim (Index 13):
The method of  claim 12  further comprising:\n performing an oxidation on the dielectric layer, wherein a first portion of the dielectric layer over the template dielectric regions is oxidized, and a second portion of the dielectric layer is protected from the oxidation.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 86.0
- Lexical Diversity: 2.60976
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14739294', '15221123', '14851535', '15726074', '14325768']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9075565715297204
- 35 USC 102 Novelty (BERT): 0.5169901547474635
- Combined Prediction Score: 0.8684999298514947
- Mean Citation Score: 258.01823399999995
- Max Citation Score: 283.4181200000001
- Similarity Product: 194.97856418585067

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test