PATENT CLAIM ANALYSIS

Application Number: 15868620
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

Claim (Index 18):
The semiconductor device of  claim 16 , wherein a top surface of the field gate conductive layer of the field gate structure is lower than a bottom surface of the second gate conductive layer of the second gate structure.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 86.0
- Lexical Diversity: 3.15909
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15011820', '15229351', '14715643', '15865467', '14551857']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9273098357495676
- 35 USC 102 Novelty (BERT): 0.5102839697757825
- Combined Prediction Score: 0.885607249152189
- Mean Citation Score: 252.31011200000003
- Max Citation Score: 319.40878
- Similarity Product: 312.2725025814807

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test