PATENT CLAIM ANALYSIS

Application Number: 16049693
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "193000"]

Abstract:
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Claim (Index 25):
The apparatus of  claim 12 , wherein the apparatus is configured such that at least one of:\n at least one of the communicative couplings is a direct communicative coupling without a component therebetween; at least one of the communicative couplings is an indirect communicative coupling with at least one a component therebetween; the read data path is configured to receive the data bit input signal that is driven by DDR memory; the read data path is configured to receive the signal derived from the data bit input signal; the data bit input signal includes a DQ signal or a signal derived therefrom; the first core domain register is configured to be responsive to the data bit input signal; the first core domain register is configured to be responsive to the signal derived from the data bit input signal; the first core domain register is configured to be clocked by the capture clock; the first core domain register is configured to be clocked by the clock derived from the capture clock; the second core domain register is configured to be clocked by the capture clock; the second core domain register is configured to be clocked by the clock derived from the capture clock; the one or more pre-determined calibration data patterns are written to DDR memory; the one or more pre-determined calibration data patterns are read from DDR memory; the apparatus is configured for requiring a small gate count resulting in implementations requiring a small amount of silicon real estate; the apparatus is configured for requiring a small amount of silicon real estate; the apparatus is configured for offering a high yield for memory controller devices as well as a high yield for memory system implementations using the memory controller devices; the apparatus is configured for offering a high yield for memory system implementations; the apparatus is configured for providing a DDR memory controller device that is calibrated to compensate for system level timing irregularities; the apparatus is configured for providing a DDR memory controller device that is calibrated to compensate for chip process parameter variations; the apparatus is configured for performing the calibration after power-up; said apparatus is configured for transferring, at an earlier point in time, captured data on memory read cycles from a dqs clock domain to a capture clock domain; the apparatus is configured for reducing a possibility that a glitch on a dqs signal that is capable of occurring during a time period when the dqs signal is not driven; the apparatus is configured for avoiding inadvertent clocking of invalid data during read cycles; or the apparatus is configured for utilizing core domain clocking mechanisms, at times combined with circuitry in a Phy, to implement an improved solution for a timing-adaptive DDR memory controller.

Metadata:
- Claim Count in Document: 80.0
- Percentile: 95.0
- Lexical Diversity: 2.11475
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15996365', '15926902', '15722209', '13172740', '14882226']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8764963272512413
- 35 USC 102 Novelty (BERT): 0.6005436555568574
- Combined Prediction Score: 0.8489010600818029
- Mean Citation Score: 599.8854240000003
- Max Citation Score: 637.52344
- Similarity Product: 445.8085841328097

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test