PATENT CLAIM ANALYSIS

Application Number: 16054877
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["341", "143000"]

Abstract:
In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

Claim (Index 1):
A sigma-delta analog-to-digital converter (ADC), comprising:\n a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal; a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator, wherein the processor is configured to increment a first counter value of the first counter based on the second output signal and a second counter value of the second counter based on the second output signal, wherein the processor is configured to compute a value based on the first and second counter values; wherein the controller unit is configured to change the first output signal based on the second output signal; wherein if the second output signal is 1, the controller unit is configured to subtract the first output signal by the second voltage signal, wherein if the second output signal is 0, the controller unit is configured to add the first output signal with first voltage signal.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 96.0
- Lexical Diversity: 3.2449
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14211233', '12072968', '12788896', '12956775', '11901355']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5856733591065094
- 35 USC 102 Novelty (BERT): 0.4792562355812639
- Combined Prediction Score: 0.5750316467539849
- Mean Citation Score: 208.00056
- Max Citation Score: 217.58466
- Similarity Product: 186.06196783979416

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test