PATENT CLAIM ANALYSIS

Application Number: 15867577
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "621000"]

Abstract:
A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Claim (Index 1):
A stacked package comprising:\n a plurality of chip packages stacked on each other, and each chip package of the plurality of chip packages having\n two lateral sides; \n a chip having an active surface and a back surface opposite to the active surface, wherein the back surface of each chip package faces the active surface of an adjacent chip package; \n a passivation layer formed on the active surface of the chip; and \n an exterior conductive element formed on the active surface of the chip and having a cut edge exposed on at least one of the two lateral sides, each of the two lateral sides comprising a lateral side of the chip, a lateral side of the passivation layer, and the cut edge; \n an encapsulant encapsulating the chip packages and having an opening expose the at least one of the two lateral sides; at least one dielectric layer formed on the at least one of the two lateral sides and having patterned recess areas expose the cut edges on the at least one of the two lateral sides; and at least one redistribution layer formed on the at least one dielectric layer, filled with the patterned recess areas of the at least one dielectric layer and electrically connecting to the cut edges on the at least one of the two lateral sides.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.2
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15383560', '15361073', '12622614', '15455143', '15630940']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8979233257007303
- 35 USC 102 Novelty (BERT): 0.4840306838263154
- Combined Prediction Score: 0.8565340615132888
- Mean Citation Score: 196.497476
- Max Citation Score: 202.24214
- Similarity Product: 158.66120155880932

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test