PATENT CLAIM ANALYSIS

Application Number: 16180723
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

Claim (Index 6):
The VT FinFET of  claim 3 , further comprising a boarder liner on at least a portion of the work function layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 3.78571
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15797721', '14953519', '15963402', '15620369', '15866676']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9061965514829016
- 35 USC 102 Novelty (BERT): 0.5666052951251611
- Combined Prediction Score: 0.8722374258471276
- Mean Citation Score: 301.97534
- Max Citation Score: 504.6872
- Similarity Product: 306.9827086894512

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test