PATENT CLAIM ANALYSIS

Application Number: 15921771
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "189011"]

Abstract:
Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Claim (Index 11):
The memory device according to  claim 1 , further comprising:\n a word line switching circuit comprising a plurality of word line switching transistors and performing switching between the plurality of word lines and the assist circuit, each of the plurality of word line switching transistors having one end connected to the assist circuit and having another end and a gate connected to each of the plurality of word lines, wherein the assist circuit is simultaneously connected to the plurality of word line switching transistors.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.15686
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15263724', '14658353', '12457936', '13836902', '15052188']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7685180417214448
- 35 USC 102 Novelty (BERT): 0.4956577517944
- Combined Prediction Score: 0.7412320127287404
- Mean Citation Score: 231.25737
- Max Citation Score: 249.27936
- Similarity Product: 185.27100356025696

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test