PATENT CLAIM ANALYSIS

Application Number: 16142946
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["365", "145000"]

Abstract:
In one embodiment, a device is described for using ferroelectric material in a memory cell without a selector device. In another embodiment, a method of operating a ferroelectric memory cell without a selector device is described. Other embodiments are likewise described.

Claim (Index 7):
An apparatus comprising: an array of respective ferroelectric memory cells;\n the respective ferroelectric memory cells of the array having at least one word-line to be disposed in a first dimension and to be in communication with at least a first sense amplifier and at least one bit-line to be disposed in a second dimension and to be in communication with at least a second sense amplifier, wherein the lines are connected to the respective ferroelectric memory cells of the array so as to respectively generate a voltage signal level difference across the respective ferroelectric memory cells of the array, the respective ferroelectric memory cells of the array comprising a ferroelectric capacitor of ferroelectric material such that polarization of the respective ferroelectric memory cells is capable of being switched to an opposite polarization via a sufficient voltage signal level difference of opposite polarity to be generated across the respective ferroelectric memory cells, the ferroelectric material further being such that polarization of the respective ferroelectric memory cell does not change unless the sufficient voltage signal level difference to be generated is to exceed a coercive voltage signal level value associated with the particular ferroelectric material; wherein the at least one word-line to comprise a first word-line voltage signal level or a second word-line voltage signal level; the first word-line voltage signal level to exceed the second word-line voltage signal level; wherein the at least one bit-line to comprise a first bit-line voltage signal level or a second bit-line voltage signal level; the first bit-line voltage signal level to exceed the second bit-line voltage signal level; wherein the first word-line voltage signal level to comprise a voltage signal level of about half of the sufficient voltage level difference in a first polarity, and the second bit-line voltage signal level to comprise a voltage signal level of about half of the sufficient voltage level difference in a second polarity; wherein a binary signal value state is to be read from or written to any one of the respective ferroelectric memory cells by addressing the first dimension and the second dimension of the array in a manner to result in the at least one word-line of the any one of the respective ferroelectric memory cells to comprise the first word-line voltage signal level and to result the at least one bit-line of the any one of the respective ferroelectric memory cells to comprise the second level bit-line voltage signal level such that the voltage signal level difference across the any one of the respective ferroelectric memory cells to be generated is to exceed the coercive voltage signal level value in the first polarity.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 1.76923
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15224438', '10716565', '11015428', '11482128', '10654352']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7851065177591225
- 35 USC 102 Novelty (BERT): 0.4821935762554364
- Combined Prediction Score: 0.754815223608754
- Mean Citation Score: 204.031742
- Max Citation Score: 241.41295
- Similarity Product: 201.07910244495272

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test