PATENT CLAIM ANALYSIS

Application Number: 15963049
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "300000"]

Abstract:
A method of manufacturing a varactor transistor includes providing a semiconductor structure including a semiconductor fin and an initial insulator layer on the semiconductor fin, and forming a plurality of gate structures spaced apart from each other and surrounding a portion of the semiconductor fin. The gate structures include a first dummy gate structure on a first edge of the semiconductor fin, a second dummy gate structure on a second edge of the semiconductor fin, and a first gate structure between the first and second dummy gate structures and spaced apart from the first and second dummy gate structures. The first and second dummy gate structures and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate.

Claim (Index 1):
A method of manufacturing a varactor transistor, the method comprising:\n providing a semiconductor structure including a semiconductor fin having a first conductivity type and an initial insulator layer on the semiconductor fin; forming a plurality of initial dummy gate structures spaced apart from each other and surrounding a portion of the semiconductor fin, the plurality of initial dummy gate structures comprising at least an edge initial dummy gate structure on an edge of the semiconductor fin, and a first initial dummy gate structure spaced apart from the edge initial dummy gate structure, the edge initial dummy gate structure and the first initial dummy gate structure each comprising an initial gate insulator layer on a surface portion of the semiconductor fin, an initial gate on the initial gate insulator layer, and a spacer on the initial gate; forming a raised source/drain region on the semiconductor fin and between each of the initial dummy gate structures; forming an interlayer dielectric layer surrounding the plurality of initial dummy gate structures and the raised source/drain region and exposing an upper surface of the initial gates of the plurality of initial dummy gate structures; removing the exposed initial gates and portions of the initial insulator layers below the exposed initial gates to form a plurality of recesses; forming a gate insulator layer in the plurality of recesses and gates on the gate insulator to form a plurality of gates structures separated from each other, the plurality of gates structures comprising at least one dummy gate structure on the edge of the semiconductor fin and a first gate structure spaced apart from the dummy gate structure; forming a first dielectric layer on the interlayer dielectric layer covering the plurality of gates structures; forming a first contact through the first dielectric layer and the interlayer dielectric layer to the source/drain region and a dummy gate contact through the first dielectric layer to the gate of the dummy gate structure; and forming a metal connector on the first dielectric layer in contact with the dummy gate contact and the first contact.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 91.0
- Lexical Diversity: 3.45238
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15400201', '15473183', '15918719', '15603754', '15925390']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922273018927842
- 35 USC 102 Novelty (BERT): 0.5316411300418297
- Combined Prediction Score: 0.8832098300392407
- Mean Citation Score: 285.237878
- Max Citation Score: 367.97083
- Similarity Product: 301.63880613041283

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test