PATENT CLAIM ANALYSIS

Application Number: 15903304
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "758000"]

Abstract:
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

Claim (Index 11):
An integrated circuit structure, comprising:\n a transistor device, the transistor device having a source/drain contact; a first interconnect line above but not over the source/drain contact, the first interconnect line having a bottom surface; a second interconnect line above and over the source/drain contact, the second interconnect line above but not over the first interconnect line; a through via structure directly electrically connecting the second interconnect line to the source/drain contact, the through via structure comprising a conductive material continuous from the second interconnect line to a location below the bottom surface of the first interconnect line; a first dielectric material portion below the first interconnect line and above the transistor device, the first dielectric material portion laterally adjacent to the through via structure;\n a second dielectric material portion laterally between the through via structure and the first interconnect line; and \n a third dielectric material portion over and in contact with the first interconnect line.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 88.0
- Lexical Diversity: 1.80769
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15201420', '14139363', '15529484', '14709430', '15528736']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9109024358682783
- 35 USC 102 Novelty (BERT): 0.4875033794077064
- Combined Prediction Score: 0.8685625302222213
- Mean Citation Score: 186.38134
- Max Citation Score: 190.21263
- Similarity Product: 129.7692946173674

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test