PATENT CLAIM ANALYSIS

Application Number: 16256296
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["375", "286000"]

Abstract:
Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

Claim (Index 14):
The apparatus of  claim 13 , wherein the access line further comprises:\n a third portion located between the substrate and the memory die and configured to transmit the signal to a memory cell of the memory die.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 99.0
- Lexical Diversity: 1.88462
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15872456', '16020834', '15892118', '15977815', '15662002']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4886057857066347
- 35 USC 102 Novelty (BERT): 0.4966176030421182
- Combined Prediction Score: 0.4894069674401831
- Mean Citation Score: 167.32568
- Max Citation Score: 235.63994
- Similarity Product: 174.37956920778274

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test