PATENT CLAIM ANALYSIS

Application Number: 16141671
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-07
Patent Classification: ["341", "110000"]

Abstract:
System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Claim (Index 3):
The apparatus of  claim 1 , wherein the input delay circuit is at least one of: a digitally controlled delay and a transmission line producing a fixed delay.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 97.0
- Lexical Diversity: 2.13158
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15455971', '15068231', '15440612', '14475852', '15935045']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6156408217758401
- 35 USC 102 Novelty (BERT): 0.6522994861246123
- Combined Prediction Score: 0.6193066882107173
- Mean Citation Score: 412.63327999999984
- Max Citation Score: 598.2193599999998
- Similarity Product: 585.9941201408002

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test