PATENT CLAIM ANALYSIS

Application Number: 15880294
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["363", "021020"]

Abstract:
A power converter including: a dual output resonant converter including a first output, a second output, a common mode control input, and a differential mode control input, wherein a voltage/current at the first output and a voltage/current at the second output are controlled in response to a common mode control signal received at the common mode control input and a differential mode control signal received at the differential mode control input; and a dual output controller including a first error signal input, a second error signal input, a common mode control output, and a differential mode control output, wherein the dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to a first error signal received at the first error signal input and a second error signal received at the second error signal input, wherein the first error signal is a function of the voltage/current at the first output and the second error signal is a function of the voltage/current at the second output, and wherein the common mode control signal is output from the common mode control output and the differential mode control signal is output from the differential mode control output, wherein the first error signal is limited by a zero output power processor when a first output power becomes zero and the second error signal is limited by a zero output power processor when a second output power becomes zero.

Claim (Index 4):
The power converter of  claim 1 , wherein the zero output power processor includes:\n a track and hold circuit configured to receive the common mode control signal Vcm and an indication that the first output power is zero, wherein the output of the track and hold circuit Vcmreg tracks the value of Vcm when the indication is false and the output Vcmreg is held at the value of Vcm when the indication becomes true; a ramp generator configured to produce a Vcmoffset signal based upon a resample signal and the indication that the first output power is zero, wherein the Vcmoffset signal is a ramped signal that is reset to zero when the indication that the first output power is zero is false and the ramp is started when a resample pulse is received; an adder computing Vcmreg+Vcmoffset\u2212Vcm where Vcmoffset is an offset value for Vcm; a regulator receiving the output of the adder and producing a regulated output; and a minimum detector configured to receive the output of the regulator and the first error signal and to output the minimum of the output of the regulator and the first error signal as the limited first error signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 5.71111
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15880319', '15374562', '13546932', '13531150', '14311116']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8174366792817185
- 35 USC 102 Novelty (BERT): 0.5761786670431968
- Combined Prediction Score: 0.7933108780578664
- Mean Citation Score: 320.91379199999994
- Max Citation Score: 516.4559
- Similarity Product: 356.7108849667669

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test