PATENT CLAIM ANALYSIS

Application Number: 15902092
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["341", "118000"]

Abstract:
An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Claim (Index 16):
An analog-to-digital converter (ADC), comprising:\n a voltage reference circuit; a first capacitive digital-to-analog converter (CDAC) comprising:\n a plurality of capacitors; and \n a first plurality of switches, each of the switches configured to switchably couple a bottom plate of one of the capacitors of the first CDAC to an output of the voltage reference circuit; \n a second CDAC comprising:\n a plurality of capacitors; and \n a first plurality of switches, each of the switches configured to switchably couple a bottom plate of one of the capacitors of the second CDAC to a ground reference; \n a comparator comprising:\n a first input coupled to an output of the first CDAC; and \n a second input coupled to an output of the second CDAC; \n successive approximation control circuitry coupled to the comparator, the first CDAC and the second CDAC, the successive approximation control circuitry configured to:\n determine a value of each bit of a digital value; \n based on the digital value activate at least some switches of the first plurality of switches of the first CDAC; and \n for each switch of the first plurality of switches of the first CDAC activated, activate a corresponding switch of the first plurality of switches of the second CDAC; \n edge rate control circuitry configured to adjust the edge rate of an output signal of the comparator based on a significance of a bit value being determined by the successive approximation circuitry; and bypass circuitry configured to route current generated by switching in a latch of the comparator away from the first input of the comparator and the second input of the comparator.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 3.19444
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15836976', '12383696', '12381741', '12799323', '11358289']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6151049404219433
- 35 USC 102 Novelty (BERT): 0.5110164694991308
- Combined Prediction Score: 0.604696093329662
- Mean Citation Score: 281.697658
- Max Citation Score: 303.87006
- Similarity Product: 265.4025654149866

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test