PATENT CLAIM ANALYSIS

Application Number: 15948487
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["365", "185230"]

Abstract:
An EEPROM and methods for erasing, programming and reading it, the EEPROM includes a plurality of split-gate storage arrays, each of the plurality of split-gate storage cells including a source connected with a first bit line, a drain connected with a second bit line, a firste control gate connected with a first store position, a word line gate connected with a word line and a second control gate connected with a second store position; and the first control gate is connected with a first control gate line, and the second control gate is connected with a second control gate line, wherein every N columns of the split-gate storage cells are formed on a first well structure, adjacent first well structures are separated by a second well structures having a different doping type with that of the first well structures, and N is a positive integer.

Claim (Index 9):
The method according to  claim 7 , wherein the first bit line voltage and the second bit line voltage are equal to the first well voltage.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 91.0
- Lexical Diversity: 2.7069
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14546294', '15226508', '15844806', '10497262', '10944940']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8208608008443062
- 35 USC 102 Novelty (BERT): 0.5063744463251175
- Combined Prediction Score: 0.7894121653923873
- Mean Citation Score: 244.80464
- Max Citation Score: 247.1072
- Similarity Product: 142.02856164474488

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test