PATENT CLAIM ANALYSIS

Application Number: 15864371
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["708", "603000"]

Abstract:
An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

Claim (Index 14):
An arithmetic logic unit for executing arithmetic operations on three binary operands in a single stage of a cycle of a processor, the arithmetic logic unit comprising:\n a first logic circuit for generating a first partial result in a first stage of a single clock cycle of a processor, the first logic circuit having a first part to receive two operands and having a second part to receive a third operand; a second logic circuit for generating a second partial result in the first stage of the same single clock cycle of the processor as the first logic circuit, the second logic circuit having a first part to generate a carry-in result for an addition operation and a second part to select a second part result that is a function of at least one of the operands, wherein the second partial result is at least one of the group consisting of the carry-in result and the second part result; an adder configured to receive the first partial result from the first logic circuit and the second partial result from the second logic circuit, and further configured to generate a secondary result during a second stage of the same single cycle that the first logic circuit and the second logic circuit generate the first partial result and the second partial result, respectively; and a backend circuit for generating a final result, wherein the backend circuit performs additional operations on the secondary result in a third stage of the same single cycle of the processor.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.73913
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10893163', '10406046', '10035033', '11506283', '11760553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.458710259073354
- 35 USC 102 Novelty (BERT): 0.4998273542051921
- Combined Prediction Score: 0.4628219685865378
- Mean Citation Score: 248.514394
- Max Citation Score: 261.6972
- Similarity Product: 208.56399333608155

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test