PATENT CLAIM ANALYSIS

Application Number: 15868280
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["365", "191000"]

Abstract:
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Claim (Index 13):
The method of  claim 10 , further comprising:\n storing, by the characterization circuit, the first delta value in a data store comprising a plurality of delta values, each corresponding to a different layer of the one or more layers.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 86.0
- Lexical Diversity: 1.89231
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12931438', '15197482', '14827292', '13858482', '14476632']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7595643995153024
- 35 USC 102 Novelty (BERT): 0.4854512557617662
- Combined Prediction Score: 0.7321530851399488
- Mean Citation Score: 201.313078
- Max Citation Score: 210.40082
- Similarity Product: 154.30463536971212

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test