PATENT CLAIM ANALYSIS

Application Number: 15907570
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185110"]

Abstract:
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.

Claim (Index 11):
The apparatus of  claim 1 , wherein:\n the group of connected memory cells includes multiple NAND strings connected to a common set of word lines; each of the NAND strings is connected to a common source line; the erase signal is a set of erase voltage pulses; the erase circuit is configured to apply a first erase voltage pulse and additional erase voltage pulses on the common source line; each NAND string has its own source side select gate that connects the common source line to the NAND string; each sub-block has its own source side selection line with respect to the other sub-groups that controls source side select gates for the sub-block; and the erase speed circuit is configured to adjust erase speed by adjusting a voltage on one of the source side selection lines.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 1.51515
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15337522', '15630389', '15191150', '15151951', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.820107558973162
- 35 USC 102 Novelty (BERT): 0.4792062764303538
- Combined Prediction Score: 0.7860174307188812
- Mean Citation Score: 226.306854
- Max Citation Score: 232.60359
- Similarity Product: 187.0747928507101

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test