PATENT CLAIM ANALYSIS

Application Number: 16022896
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "532000"]

Abstract:
A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Claim (Index 17):
The semiconductor structure of  claim 16 , comprising:\n a dielectric layer disposed under the alignment mark layer, wherein the bottom conductive layer is spaced apart from the dielectric layer by the first portion of the alignment mark layer and the second portion of the alignment mark layer.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 94.0
- Lexical Diversity: 2.02941
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15158402', '15063544', '15663671', '15949041', '14981873']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9065427362496288
- 35 USC 102 Novelty (BERT): 0.4791317615663831
- Combined Prediction Score: 0.8638016387813041
- Mean Citation Score: 153.49960600000003
- Max Citation Score: 197.16783
- Similarity Product: 150.1538678875369

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test