PATENT CLAIM ANALYSIS

Application Number: 16229776
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "154000"]

Abstract:
A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

Claim (Index 4):
The semiconductor memory device according to  claim 2 ,\n wherein the negative voltage generation circuit generates the negative voltage multiple times in accordance with the potentials of the pair of first bit lines.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 3.85
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15234910', '15782662', '11609503', '13329671', '13072240']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8258293790031687
- 35 USC 102 Novelty (BERT): 0.5135097801848781
- Combined Prediction Score: 0.7945974191213396
- Mean Citation Score: 268.417238
- Max Citation Score: 329.89297
- Similarity Product: 260.7662894276285

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test