PATENT CLAIM ANALYSIS

Application Number: 15763828
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-12
Patent Classification: ["257", "095000"]

Abstract:
The invention relates to an optoelectronic semiconductor chip ( 100 ), comprising an n-doped semiconductor layer ( 3 ), a p-doped semiconductor layer ( 5 ) and an active layer ( 4 ) arranged between the n-doped semiconductor layer ( 3 ) and the p-doped semiconductor layer ( 5 ), wherein the p-doped semiconductor layer ( 5 ) has an electrically conductive layer ( 7 ) arranged above it that is set up for making electrical contact with the p-doped semiconductor layer ( 5 ), wherein a lateral edge ( 2 ) is arranged laterally with respect to the n-doped semiconductor layer ( 3 ), the p-doped semiconductor layer ( 5 ) and the active layer ( 4 ), wherein the lateral edge ( 2 ) has at least two oblique edge portions, wherein a first edge portion ( 21 ) has at least areas arranged laterally with respect to the p-doped semiconductor layer ( 5 ), wherein a second lateral edge ( 22 ) has at least areas arranged laterally with respect to the n-doped semiconductor layer ( 3 ), wherein the angle of the first edge portion ( 21 ) in relation to the active layer ( 4 ) is shallower than the angle of the second edge portion ( 22 ), and wherein the electrically conductive layer ( 7 ) is at a lateral distance from the lateral edge ( 2 ).

Claim (Index 1):
An optoelectronic semiconductor chip, comprising:\n at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, wherein an electrically conductive layer is arranged above the p-doped semiconductor layer, wherein the electrically conductive layer is designed for electrically contacting the p-doped semiconductor layer, wherein, laterally to the n-doped semiconductor layer, the p-doped semiconductor layer and to the active layer, a side flank is arranged, wherein the side flank comprises at least two angular partial flanks, wherein the first partial flank is arranged at least in regions laterally with respect to the p-doped semiconductor layer, wherein the second partial flank is arranged at least in regions laterally with respect to the n-doped semiconductor layer, wherein the angle of the first partial flank with respect to the active layer is flatter than the angle of the second partial flank, wherein the electrically conductive layer is laterally spaced from the side flank.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 3.72727
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15573467', '15018845', '13821554', '16085934', '15522783']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.923722036498182
- 35 USC 102 Novelty (BERT): 0.5032952946860353
- Combined Prediction Score: 0.8816793623169674
- Mean Citation Score: 274.778632
- Max Citation Score: 299.67538
- Similarity Product: 263.8324903958857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test