PATENT CLAIM ANALYSIS

Application Number: 15970565
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "338000"]

Abstract:
A method for fabricating a semiconductor structure includes providing a substrate, forming a plurality of gate electrodes on the substrate, forming a plurality of first sidewall spacers on the side surfaces of the plurality of gate electrodes, forming an oxide layer on the substrate, and forming a plurality of second sidewall spacers on the oxide layer covering the side surfaces of the plurality of first sidewall spacers. Each gate electrode, first sidewall spacers formed on the side surfaces of the gate electrode, and second sidewall spacers formed on the side surfaces of the first sidewall spacers together form a gate structure. The method includes forming an undercut, having an undercut angle made between the oxide layer and the substrate under each second sidewall spacer, and forming a plurality of grooves through the oxide layer and into the substrate. Each groove includes undercuts under second sidewall spacers of adjacent gate structures.

Claim (Index 15):
The semiconductor structure according to  claim 14 , wherein:\n a thickness of the oxide layer is in a range of approximately 20 \u212b to 30 \u212b.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 3.17647
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14920193', '14161816', '15941225', '15222624', '11626495']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9178720557192313
- 35 USC 102 Novelty (BERT): 0.5050301951026794
- Combined Prediction Score: 0.8765878696575761
- Mean Citation Score: 255.273164
- Max Citation Score: 262.23047
- Similarity Product: 207.20918621105253

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test