PATENT CLAIM ANALYSIS

Application Number: 16171342
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["710", "313000"]

Abstract:
Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Claim (Index 3):
The apparatus of  claim 1 , wherein if the accelerator link protocol upper layer mode is selected, the multiplexing logic is further to enable accelerator link protocols, the accelerator link protocols comprising either a single protocol or multiple protocols.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 97.0
- Lexical Diversity: 2.12963
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12647047', '13534541', '14132610', '14836234', '13477322']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6521338780135475
- 35 USC 102 Novelty (BERT): 0.4947460810337544
- Combined Prediction Score: 0.6363950983155682
- Mean Citation Score: 171.109296
- Max Citation Score: 195.19312
- Similarity Product: 118.51810307767867

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test