PATENT CLAIM ANALYSIS

Application Number: 16127085
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["365", "185120"]

Abstract:
Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.

Claim (Index 2):
The memory device of  claim 1 , wherein the memory region comprises a memory block including a plurality of word line groups, and wherein the portion comprises a subset of the plurality of word line groups.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 97.0
- Lexical Diversity: 2.54348
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15669055', '16102092', '16102067', '11851439', '15689747']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8239969622659813
- 35 USC 102 Novelty (BERT): 0.4830015577401446
- Combined Prediction Score: 0.7898974218133976
- Mean Citation Score: 216.604472
- Max Citation Score: 277.54642
- Similarity Product: 276.07830651544447

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test