PATENT CLAIM ANALYSIS

Application Number: 15974664
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["438", "696000"]

Abstract:
The present invention provides a method for fabricating a semiconductor structure. A multilayer structure on is formed a substrate, the multilayer structure includes at least a first dielectric layer, a second dielectric layer and an amorphous silicon layer, next, a first etching step is performed, to forma first recess in the amorphous silicon layer and in the second dielectric layer, parts of the first dielectric layer is exposed by the first recess, afterwards, a hard mask layer is formed in the first recess, a second etching step is then performed to remove the hard mask layer and to expose a surface of the first dielectric layer, and a third etching step is performed with the remaining hard mask layer, to remove a portion of the first dielectric layer, so as to form a second recess in the first dielectric layer.

Claim (Index 6):
The method of  claim 1 , further comprising forming a boron-phosphorous silicon glass (BPSG) layer under the first dielectric layer, and a contact structure under the boron-phosphorous silicon glass layer.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 93.0
- Lexical Diversity: 2.75
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14621646', '13946166', '15971191', '10197936', '12703991']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8491030217697343
- 35 USC 102 Novelty (BERT): 0.4809779881699595
- Combined Prediction Score: 0.8122905184097569
- Mean Citation Score: 170.076778
- Max Citation Score: 175.81851
- Similarity Product: 123.74187824105144

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test