PATENT CLAIM ANALYSIS

Application Number: 15948543
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

Claim (Index 7):
The integrated circuit of  claim 6 , wherein the via of one of the first and second transistors is at the shallow trench isolation region, and wherein an upper surface of the source region or the drain region that extends across the shallow trench isolation regions includes a notch.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.46154
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12983925', '15810557', '10668349', '15436905', '15844840']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281038326548052
- 35 USC 102 Novelty (BERT): 0.4899033996163585
- Combined Prediction Score: 0.8842837893509606
- Mean Citation Score: 238.256964
- Max Citation Score: 253.73509
- Similarity Product: 215.8633505907005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test