PATENT CLAIM ANALYSIS

Application Number: 15923121
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["712", "225000"]

Abstract:
A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

Claim (Index 18):
The processor of  claim 1 :\n wherein the memory stack comprises a first memory stack in a plurality of memory stacks; wherein each memory stack in the plurality of memory stacks comprises a respective plurality of stack storage spaces; further comprising a plurality of write protection indicators for each respective memory stack of the plurality of memory stacks; and wherein the circuitry for generating is for generating a fault in response to detecting a processor write is directed to a selected stack storage space for which a respective write protection indicator, in a respective one of the plurality of write protection indicators, indicates the selected stack storage space is write protected.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.30769
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12263802', '11014111', '12594715', '14989214', '15443534']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5563014728395314
- 35 USC 102 Novelty (BERT): 0.4801284595976788
- Combined Prediction Score: 0.5486841715153461
- Mean Citation Score: 173.46055800000005
- Max Citation Score: 182.70515
- Similarity Product: 126.73040118072628

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test