PATENT CLAIM ANALYSIS

Application Number: 15957130
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.

Claim (Index 21):
A cache prefetch system, comprising:\n an interconnect configured for communicably coupling a processor, a lower-level cache having a lower-level cache's storage capacity, a higher-level cache having a higher-level cache's storage capacity, and a main memory, wherein the lower-level cache's storage capacity is smaller than the higher-level cache's storage capacity; a prefetcher component configured for prefetching a set of data from the main memory via the interconnect for storage in the lower-level cache, wherein the prefetcher tags a first portion of data of the set of data as optionally one of: (a) a part of a data set that exceeds the lower-level cache's storage capacity, or (b) unused data, wherein the first portion of data is determined to have a first probability of a first future use by the processor, wherein the first portion of data is to be sent to the higher-level cache, and wherein the prefetcher component tags a second portion of data associated with the set of data as used data to indicate that the second portion of data has been used by the processor and is to be sent from the processor cache to the main memory; and an evictor component configured for evicting the first portion of data from the lower-level cache to the higher-level cache via the interconnect, and evicting the second portion of data from the lower-level cache to the main memory.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 1.85246
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14710837', '13158911', '14666771', '12637022', '09745020']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5344270862142172
- 35 USC 102 Novelty (BERT): 0.5390180131785669
- Combined Prediction Score: 0.5348861789106522
- Mean Citation Score: 267.438026
- Max Citation Score: 389.95303
- Similarity Product: 321.5341565942478

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test