PATENT CLAIM ANALYSIS

Application Number: 16029188
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "738000"]

Abstract:
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Claim (Index 6):
The semiconductor package of  claim 1 , wherein the plurality of package level interconnects comprises a plurality of solder balls below the first die and within a periphery of the first die.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 95.0
- Lexical Diversity: 2.56897
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14768209', '15915769', '14811261', '15503377', '15590890']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9089742593712912
- 35 USC 102 Novelty (BERT): 0.5090458684585827
- Combined Prediction Score: 0.8689814202800202
- Mean Citation Score: 214.86728
- Max Citation Score: 243.55884
- Similarity Product: 168.95666947342872

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test