PATENT CLAIM ANALYSIS

Application Number: 15878182
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["711", "167000"]

Abstract:
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.

Claim (Index 31):
A system, comprising:\n field programmable gate array (FPGA) circuitry disposed on an integrated circuit, wherein the FPGA circuitry is configured to be programmed to implement user logic; a processor configured to receive and process data from the FPGA circuitry; user interface circuitry configured to couple to the user logic of the FPGA circuitry to receive memory commands from the user logic of the FPGA circuitry; physical layer circuitry configured to couple to a memory and configured to access the memory in response to the memory commands; and a memory controller circuit, configured to couple between the physical layer circuity and the user interface circuitry, having:\n a plurality of finite state machine circuits configured to operate in parallel to queue the memory commands from the user interface circuitry for accessing the memory; and \n one or more logic circuits configured to order the memory commands for accessing the memory prior to the memory commands issuing to the physical layer circuitry.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.58621
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14256721', '14319103', '15804930', '13734512', '13151123']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5652720495056502
- 35 USC 102 Novelty (BERT): 0.5454364791036397
- Combined Prediction Score: 0.5632884924654492
- Mean Citation Score: 331.3384200000001
- Max Citation Score: 419.47998
- Similarity Product: 322.71906844468475

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test