PATENT CLAIM ANALYSIS

Application Number: 16312317
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["326", "008000"]

Abstract:
A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.

Claim (Index 11):
A method according to  claim 10 , wherein said respective phase-shifted clock signals are assigned in accordance with functions of said input data.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 2.08163
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15636902', '15301409', '14236641', '14377893', '11596312']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6604687282583768
- 35 USC 102 Novelty (BERT): 0.4971052773188644
- Combined Prediction Score: 0.6441323831644256
- Mean Citation Score: 198.099898
- Max Citation Score: 247.79225
- Similarity Product: 173.95310407944024

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test