PATENT CLAIM ANALYSIS

Application Number: 16000911
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-11
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.

Claim (Index 9):
The semiconductor device according to  claim 7 , wherein the second memory structure comprises a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, or a ferroelectric RAM (FeRAM) structure.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 94.0
- Lexical Diversity: 3.09524
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15180095', '15721977', '14616985', '15382755', '15937741']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9049797018423722
- 35 USC 102 Novelty (BERT): 0.4877132194590937
- Combined Prediction Score: 0.8632530536040444
- Mean Citation Score: 174.61377
- Max Citation Score: 186.18993
- Similarity Product: 137.59249801494778

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test