PATENT CLAIM ANALYSIS

Application Number: 15918536
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "154000"]

Abstract:
A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Claim (Index 8):
The semiconductor memory apparatus according to  claim 5 , wherein the data line repeater block provides data received through the data transmission line to the memory bank region, or provides data outputted from the memory bank region to the data transmission line.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.83871
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15706218', '15017994', '12232719', '15597795', '12459106']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5384662407534843
- 35 USC 102 Novelty (BERT): 0.4693577373204439
- Combined Prediction Score: 0.5315553904101803
- Mean Citation Score: 177.27008800000004
- Max Citation Score: 182.9408
- Similarity Product: 145.24865440979005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test