PATENT CLAIM ANALYSIS

Application Number: 15902092
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["341", "118000"]

Abstract:
An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Claim (Index 20):
The ADC of  claim 16 , wherein the edge rate control circuitry is configured to set the edge rate of the output signal of the comparator higher for a bit of higher significance than for a bit of lower significance.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 3.19444
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15836976', '12383696', '12381741', '12799323', '11358289']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6413466341289393
- 35 USC 102 Novelty (BERT): 0.5249979298559156
- Combined Prediction Score: 0.6297117637016371
- Mean Citation Score: 281.697658
- Max Citation Score: 303.87006
- Similarity Product: 198.1308892309606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test