PATENT CLAIM ANALYSIS

Application Number: 15988618
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "076000"]

Abstract:
A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Claim (Index 1):
A method of forming a semiconductor device, comprising the steps:\n forming a low-doped layer of III-N material over a substrate, in an area for an enhancement mode GaN FET; forming a barrier layer of III-N material by a metal-organic chemical vapor deposition (MOCVD) process over the low-doped layer, the barrier layer having less than 1 atomic percent indium; forming a stressor layer of III-N material by an MOCVD process over the barrier layer, the stressor layer having a stoichiometry of In 0.05 Al 0.95 N to In 0.30 Al 0.70 N, and a thickness of 1 nanometers to 5 nanometers; forming a cap layer of III-N material by an MOCVD process over the stressor layer; forming a recess mask over the cap layer which exposes an area for a gate recess in the area for the enhancement mode GaN FET; removing the cap layer in the area exposed by the recess mask by a first etch process to form a portion of a gate recess of the enhancement mode GaN FET, the first etch process leaving at least a portion of the stressor layer under the area exposed by the recess mask; removing the stressor layer in the area exposed by the recess mask by a second etch process to form the gate recess, the second etch process having a different chemistry than the first etch process, the second etch process leaving at least a portion of the barrier layer under the gate recess; forming a gate dielectric layer over the barrier layer in the gate recess; and forming a gate of the enhancement mode GaN FET over the gate dielectric layer in the gate recess.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 2.80392
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13886410', '15353952', '10758871', '14701313', '10849617']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9116895707122618
- 35 USC 102 Novelty (BERT): 0.475266340958436
- Combined Prediction Score: 0.8680472477368791
- Mean Citation Score: 185.379414
- Max Citation Score: 196.52385
- Similarity Product: 153.4923929262221

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test