PATENT CLAIM ANALYSIS

Application Number: 15936396
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "002000"]

Abstract:
The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

Claim (Index 13):
The method of  claim 11 , further comprising forming a dielectric layer covering the first dummy bit line gate and the second dummy bit line gate after the first dummy bit line gate and the second dummy bit line gate are patterned.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 90.0
- Lexical Diversity: 2.64444
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11101446', '10926142', '13196967', '12647918', '15282836']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9216180432559
- 35 USC 102 Novelty (BERT): 0.4964907505780244
- Combined Prediction Score: 0.8791053139881125
- Mean Citation Score: 238.043296
- Max Citation Score: 242.00894
- Similarity Product: 172.8123533005309

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test