PATENT CLAIM ANALYSIS

Application Number: 15962434
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "421000"]

Abstract:
The present disclosure provides a semiconductor structure, including a logic region and a memory region. The memory region includes a first N th  metal line of an N th  metal layer, a magnetic tunneling junction (MTJ) over first N th  metal line, a carbon-based layer between the first N th  metal line and the MTJ, and a first (N+M) th  metal via of an (N+M) th  metal layer. A method of manufacturing the semiconductor structure is also disclosed.

Claim (Index 15):
A method for manufacturing a semiconductor structure, the method comprising:\n forming a first N th  metal line in a memory region and a second N th  metal line in a logic region; forming a carbon-based layer over the first N th  metal line and the second N th  metal line; forming a bottom electrode via in the carbon-based layer; forming a magnetic tunneling junction (MTJ) multilayer over the bottom electrode via; patterning a MTJ cell by an ion beam etch; and forming a first (N+M) th  metal layer directly on the MTJ, wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 91.0
- Lexical Diversity: 2.21951
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14948046', '14953238', '15961157', '15151207', '15159669']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9263308920179998
- 35 USC 102 Novelty (BERT): 0.5020966847289873
- Combined Prediction Score: 0.8839074712890986
- Mean Citation Score: 289.6176240000001
- Max Citation Score: 300.3184
- Similarity Product: 270.9946915384292

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test