PATENT CLAIM ANALYSIS

Application Number: 15925364
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device includes a substrate, a semiconductor fin on the substrate, an isolation region on sidewalls of the semiconductor fin and having an upper surface lower than an upper surface of the semiconductor fin, a gate structure on a portion of the semiconductor fin and on a first portion of the isolation region. The portion of the semiconductor fin covered by the gate structure is referred to as a first region, and a second portion of the isolation region disposed on at least one of two opposite sides of the gate structure is referred to as a second region, which has an upper surface lower than an upper surface of the first region. The semiconductor device also includes a first spacer layer on a sidewall of the gate structure and on a sidewall of a portion of the first region disposed above the second region.

Claim (Index 7):
A method for manufacturing a semiconductor device, comprising:\n providing a substrate structure including a substrate, a semiconductor fin on the substrate, a dielectric layer on a surface of the semiconductor fin, an isolation region on sidewalls of the semiconductor fin and having an upper surface lower than an upper surface of the semiconductor fin, and a dummy gate on a portion of the semiconductor fin and on a first portion of the isolation region, wherein the portion of the semiconductor fin covered by the dummy gate is referred to as a first region, a second portion of the isolation region disposed on at least one of two opposite sides of the dummy gate is referred to as a second region, the first region having an upper surface higher than an upper surface of the second region; and removing a portion of the second region such that an upper surface of a remaining portion of the second region is lower than the upper surface of the first region; forming a first spacer layer on a sidewall of the dummy gate and on a sidewall of a portion of the first region disposed above the second region; removing the dummy gate and a portion of the dielectric layer below the dummy gate to form a trench; and forming a gate structure in the trench.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 90.0
- Lexical Diversity: 3.20833
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14521083', '14710776', '14687030', '14564323', '14802110']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9223177326634904
- 35 USC 102 Novelty (BERT): 0.4897097800514987
- Combined Prediction Score: 0.8790569374022911
- Mean Citation Score: 255.23429
- Max Citation Score: 263.01663
- Similarity Product: 227.62864249470056

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test