PATENT CLAIM ANALYSIS

Application Number: 16051721
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-12
Patent Classification: ["257", "316000"]

Abstract:
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

Claim (Index 20):
The method according to  claim 17 , wherein the CESL is in direct contact with the select gate electrodes within the memory region, and in direct contact with the sidewall spacer within the logic region.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 96.0
- Lexical Diversity: 2.07246
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16015480', '15694098', '15904836', '15651403', '15162761']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9207475787755144
- 35 USC 102 Novelty (BERT): 0.5029385561965091
- Combined Prediction Score: 0.8789666765176138
- Mean Citation Score: 194.72472
- Max Citation Score: 224.91165
- Similarity Product: 145.00014990683198

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test