PATENT CLAIM ANALYSIS

Application Number: 15996444
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["375", "354000"]

Abstract:
Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

Claim (Index 8):
A circuit including multiple clock domains for use in a system for radio frequency (RF) communications, comprising\n TX (transmit) signal path circuitry to receive digital TX baseband signals, and configured\n to capture, into a TX capture memory, TX data including phase data related to the TX baseband signals, \n to perform QMC filtering for quadrature mismatch compensation (QMC) to generate QMC pre-compensated TX baseband signals, and \n to generate, based on the QMC pre-compensated TX baseband signals, TX/RF signals; \n FBRX (feedback receive) signal path circuitry, to selectively receive the QMC pre-compensated TX/RF signals as feedback FBRX/RF signals, and configured\n to generate, from the FBRX/RF signals, feedback digital FBRX baseband signals, and \n to capture, into a RX capture memory, FBRX data including phase data related to the FBRX baseband signals; \n the TX signal path circuitry including QMC circuitry to receive the TX baseband signals and perform the QMC filtering to generate the pre-compensated TX baseband signals; and multi-domain clock generation circuitry including at least a TX domain clock generator to generate for the TX signal path circuitry a TX domain clock, and a FBRX domain clock generator to generate for the FBRX signal path circuitry a FBRX domain clock, each domain clock based on an input global clock with an input global clock frequency, and each domain clock generated with randomization, the TX and FBRX domain clocks having a relative clock skew:\n the TX domain clock generator including a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the TX domain clock; and \n the FBRX domain clock generator including a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the FBRX domain clock.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 2.76667
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15093724', '14834405', '10630159', '10630317', '10630297']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.442905484588551
- 35 USC 102 Novelty (BERT): 0.487687406006039
- Combined Prediction Score: 0.4473836767302998
- Mean Citation Score: 217.496564
- Max Citation Score: 238.06973
- Similarity Product: 204.0262111026871

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test