PATENT CLAIM ANALYSIS

Application Number: 16184994
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-09
Patent Classification: ["712", "221000"]

Abstract:
A method and apparatus for including in processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Claim (Index 4):
The system of  claim 1  wherein the system memory comprises a dynamic random access (DRAM) memory.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 98.0
- Lexical Diversity: 1.91139
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16164736', '13763596', '15345221', '13763598', '11525706']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5883674483828031
- 35 USC 102 Novelty (BERT): 0.5333312752636121
- Combined Prediction Score: 0.582863831070884
- Mean Citation Score: 301.10248800000005
- Max Citation Score: 344.8086
- Similarity Product: 199.51552134947767

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test