PATENT CLAIM ANALYSIS

Application Number: 15905250
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["708", "607000"]

Abstract:
A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result. The RMM anticipates the use of 8, 16, and 32-bit operand reconfigurable matrix datum in conjunction with a typical external memory bus data width of 512 bits and an instruction control unit (ICU) implemented using a series of RMM configuration words (RCW) and streaming opcode functions (SOF).

Claim (Index 1):
A reconfigurable matrix multiplier system comprising:\n at least one register; at least one data bus; at least one buffer; at least one storage memory having an A-multiplier-matrix registered storage memory, a B-multiplicand-matrix registered storage memory, and a C-product-matrix registered storage memory; at least one data array having at least one array of stem array multiplier modules, the at least one array of stem array multiplier modules include at least one array of leaf array multiplier modules; at least one data formatter; wherein the at least one register, the at least one data bus, the at least one buffer, the at least one storage memory, the at least one data array, and the at least one data formatter are selectively electrically coupled; wherein the B-multiplicand-matrix includes a B-multiplicand-matrix-fore registered storage memory and a B-multiplicand-matrix-back registered storage memory each organized as a matrix having a number of rows; wherein the C-product-matrix includes a C-product-matrix-fore registered storage memory and a C-product-matrix-back registered storage memory each organized as a matrix having at least one row; wherein the at least one data array reconfigures data path interconnections between said A-multiplier-matrix, said B-multiplicand-matrix-fore, and said C-product-matrix-fore registered storage memories and said stem array multiplier module, and said leaf array multiplier modules based on data stored in at least one register; wherein the at least one data array calculates a multiplication/accumulation registered result generated by said stem array multiplier module, and said leaf array multiplier modules based on data stored in at least one register, the calculation includes a simultaneous dot product of a row of said A-multiplier-matrix-fore and one or more columns of said B-multiplicand-matrix-fore to produce a resulting C-product-matrix-fore row vector result while the B-multiplicand-matrix-back loads a matrix row from at least one data bus during said calculation; wherein the at least one data formatter transforms a registered row result of said C-product-matrix-back comprising a previously calculated dot product from an initial data format to an output data format to generate a transformed multiplication/accumulation result, the transformed multiplication/accumulation result is stored in a register within the at least one data formatter, the register transfers said transformed multiplication/accumulation result to the at least one data bus during the calculation; and wherein the B-multiplicand-matrix-fore, the C-product-matrix-fore, the C-product-matrix-back, and the B-multiplicand-matrix-back swap their respective functions as calculation and data transfer registers during alternate cycles of each calculation.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 88.0
- Lexical Diversity: 1.75248
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13462648', '15873002', '15224176', '11779935', '13187841']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4063525957751766
- 35 USC 102 Novelty (BERT): 0.4930614382870184
- Combined Prediction Score: 0.4150234800263608
- Mean Citation Score: 184.681574
- Max Citation Score: 190.91678
- Similarity Product: 132.78250978996277

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test