PATENT CLAIM ANALYSIS

Application Number: 16100804
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "329000"]

Abstract:
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

Claim (Index 29):
A semiconductor device comprising:\n a substrate including a first region and a second region; a first source/drain disposed on the first region of the substrate; a second source/drain disposed on the second region of the substrate; a first nanowire disposed on the first region of the substrate and spaced apart from the substrate, the first nanowire being connected with the first source/drain; a second nanowire disposed on the first region of the substrate and spaced apart from the substrate, the second nanowire being connected with the first source/drain, the second nanowire being spaced apart from the first nanowire; a third nanowire disposed on the second region of the substrate and spaced apart from the substrate, the third nanowire being connected with the second source/drain; a fourth nanowire disposed on the second region of the substrate and spaced apart from the substrate, the fourth nanowire being connected with the second source/drain, the fourth nanowire being spaced apart from the third nanowire; a first gate-all-around structure disposed on the first region of the substrate, and encircling the first nanowire and the second nanowire; and a second gate-all-around structure disposed on the second region of the substrate, and encircling the third nanowire and the fourth nanowire, wherein the first and second nanowires are used as a first channel for a first transistor, the third and fourth nanowires are used as a second channel for a second transistor, the first gate-all-around structure includes a first conductive film and a first gate insulating layer surrounding the first and second nanowires,\n the second gate-all-around structure includes a second conductive film and a second gate insulating layer surrounding the third and fourth nanowires, \n the first conductive film includes a first filling film and a first function film, and \n the second conductive film includes a second filling film and a second function film.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 3.56
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15463551', '15430265', '15343860', '15368723', '15353163']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9206610769270724
- 35 USC 102 Novelty (BERT): 0.4900090876899283
- Combined Prediction Score: 0.877595878003358
- Mean Citation Score: 241.749466
- Max Citation Score: 259.5505
- Similarity Product: 220.06845297563075

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test