PATENT CLAIM ANALYSIS

Application Number: 16146140
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["717", "149000"]

Abstract:
Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.

Claim (Index 15):
The method of  claim 10  further comprising:\n comparing an address targeted by the special store instruction to at least one address previously forwarded to the load/store queues to determine when the younger special store instruction is executed ahead of a load instruction targeting the address of the special store instruction.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 97.0
- Lexical Diversity: 1.48936
- Patent Class: 717.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15169736', '15169739', '15826609', '16120249', '15169743']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.448982772944645
- 35 USC 102 Novelty (BERT): 0.5741820026941485
- Combined Prediction Score: 0.4615026959195953
- Mean Citation Score: 443.090702
- Max Citation Score: 466.28513
- Similarity Product: 370.6339856664556

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test