PATENT CLAIM ANALYSIS

Application Number: 16255536
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["375", "376000"]

Abstract:
A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY 1  at a first point t 1  in time and a second delay signal SDLY 2  at a second point in time t 2 . The sampler module is configured to provide a first sample S 1  of the oscillator output signal SOUT at the first point in time t 1  and a second sample S 2  of the oscillator output signal SOUT at the second point in time t 2 . The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S 1  and the second sample S 2 . The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.

Claim (Index 16):
The sub-sampling phase-locked loop according to  claim 5 , further comprising:\n a charge-pump, which acts as an intermediate circuit and arranged between the interpolator and the filter.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 99.0
- Lexical Diversity: 3.14286
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15660424', '15224296', '15224280', '15224199', '16046513']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5145710603014221
- 35 USC 102 Novelty (BERT): 0.5848222021963959
- Combined Prediction Score: 0.5215961744909194
- Mean Citation Score: 319.355008
- Max Citation Score: 553.2161
- Similarity Product: 402.8715938806772

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test