PATENT CLAIM ANALYSIS

Application Number: 16006498
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "149000"]

Abstract:
The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.

Claim (Index 8):
Metastability-containing electronic circuit, usable for synchronizing a number of clock pulses, comprising:\n inputs, for receiving one or more electrical input signals; combinational logic for generating one or more electrical output signals, based on the one or more input signals; outputs, for outputting the one or more output signals; characterized in that the combinational logic generates at least one stable output signal (0, 1), based on at least one combination of stable and metastable input signals (0, 1, M).

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 1.04
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14274956', '15146890', '13306828', '14831784', '14029699']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7544757048860546
- 35 USC 102 Novelty (BERT): 0.4744641159665598
- Combined Prediction Score: 0.7264745459941052
- Mean Citation Score: 172.13580599999997
- Max Citation Score: 174.81987
- Similarity Product: 124.74693340108932

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test