PATENT CLAIM ANALYSIS

Application Number: 15964492
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "368000"]

Abstract:
A memory cell array includes a first memory cell arranged in a first row in a first direction and a second memory cell arranged in a second row in the first direction. The first memory cell or the second memory cell includes a set of active regions, a set of gates and a first set of conductive structures. Each of the active regions of the set of active regions is separated from an adjacent active region in the first direction by a first pitch. The set of active regions extends in a second direction. The set of active regions includes a first active region adjacent to a first side of the first memory cell, and a second active region adjacent to a second side of the first memory cell. A length of the first active region is different from a length of the second active region.

Claim (Index 18):
The memory cell array of  claim 17 , further comprising:\n a second set of conductive structures extending in the first direction and overlapping at least the second active region and the second side of the first memory cell, each conductive structure of the second set of conductive structures being separated from an adjacent structure of the second set of conductive structures in at least the first direction or the second direction, and being located on a fourth level different from the first level, the second level and the third level; a first set of vias between the first set of conductive structures and the first and second active regions, the first set of vias coupling the first set of conductive structures to the first and second active regions, and at least one via of the first set of vias being located where at least one conductive structure of the first set of conductive structures overlaps at least one of the first and second active regions; and a second set of vias between the first set of conductive structures and the set of gates, the second set of vias coupling the first set of conductive structures to the set of gates, and a first via of the second set of vias being located where a first conductive structure of the first set of conductive structures is over a first gate of the set of gates.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 3.94872
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15863090', '15682885', '15861128', '14554958', '15380936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8921050154399262
- 35 USC 102 Novelty (BERT): 0.4837676389776758
- Combined Prediction Score: 0.8512712777937012
- Mean Citation Score: 168.22874199999995
- Max Citation Score: 186.12898
- Similarity Product: 139.93031395437723

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test