PATENT CLAIM ANALYSIS

Application Number: 15973992
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "288000"]

Abstract:
A method for manufacturing a semiconductor device includes forming a plurality of silicon germanium and silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer. The stacked configuration is patterned into a plurality of patterned stacks spaced apart from each other. The patterning forms a plurality of recessed portions in the substrate. In the method, the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of the silicon germanium layers, and inner spacer layers are formed in place of the removed portions. A plurality of lower epitaxial layers are grown in the recessed portions. A plurality of epitaxial source/drain regions are grown from the lower epitaxial layers and from exposed lateral sides of the silicon layers.

Claim (Index 6):
The method according to  claim 1 , wherein the plurality of lower epitaxial layers are carbon (C) doped.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 93.0
- Lexical Diversity: 2.47458
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15873469', '15823684', '15802062', '15847894', '15069468']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9382888290163052
- 35 USC 102 Novelty (BERT): 0.5338217191241379
- Combined Prediction Score: 0.8978421180270886
- Mean Citation Score: 338.676326
- Max Citation Score: 369.9261
- Similarity Product: 264.52325818582176

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test