PATENT CLAIM ANALYSIS

Application Number: 15769318
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["206", "710000"]

Abstract:
Disclosed is a separator for semiconductor wafers vertically stacked in that the stacked wafers do not contact with each other, or the wafer does not contact to an inner top surface or an inner bottom surface of a conveyance container of the semiconductor wafer, the separator being interposed between two of the wafers neighboring vertically, between the wafer and an inner top surface, or between the wafer and an inner bottom surface of the container. The separator includes: a flat annular body; an annular convex portion having a wafer support surface coming into contact with a peripheral line of the wafer along a peripheral edge portion of the flat annular body, the annular convex portion forming cutout portions in a suitable number of places; and shock-absorbing function pieces neighboring to the cutout portions and extending diagonally upward or diagonally downward from a separator reference plane.

Claim (Index 4):
A conveyance container of a semiconductor wafer comprising:\n a main body of a conveyance container in a semiconductor wafer; and the separator according to  claim 2 .

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 2.1831
- Patent Class: 206.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13351911', '12548368', '10859720', '12997414', '11819988']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7565269960015695
- 35 USC 102 Novelty (BERT): 0.4822015950546457
- Combined Prediction Score: 0.729094455906877
- Mean Citation Score: 127.209874
- Max Citation Score: 132.68124
- Similarity Product: 80.41387158445359

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test