PATENT CLAIM ANALYSIS

Application Number: 15923501
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185170"]

Abstract:
A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

Claim (Index 6):
A semiconductor memory device, comprising:\n a plurality of interconnects extending in a first direction and being arranged along a second direction and a third direction, the second direction crossing the first direction, the third direction crossing a plane including the first direction and the second direction; a semiconductor member extending in the second direction and being disposed between two interconnects of the plurality of interconnects adjacent to each other in the third direction; a charge storage member disposed between the semiconductor member and a first interconnect of the plurality of interconnects; and a drive circuit that, when evaluating an amount of charge stored in the charge storage member, applies a voltage between two end portions of the semiconductor member, applies a potential for evaluating the amount of charge to the first interconnect, applies a first potential to a second interconnect of the plurality of interconnects, applies a second potential to a third interconnect of the plurality of interconnects, and applies the first potential to at least one of a plurality of fourth interconnects of the plurality of interconnects, the semiconductor member being settable to a conducting state by the first potential, the second interconnect being arranged in the second direction when viewed from the first interconnect, the third interconnect being arranged in the third direction when viewed from the first interconnect, the semiconductor member being interposed between the third interconnect and the first interconnect, the semiconductor member being settable to a nonconducting state by the second potential, the plurality of fourth interconnects being arranged in the second direction when viewed from the third interconnect and being nonadjacent to the third interconnect in the second direction.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 3.04545
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13619118', '14096371', '12603099', '15868718', '14849082']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7961007947243807
- 35 USC 102 Novelty (BERT): 0.4713501174971033
- Combined Prediction Score: 0.763625727001653
- Mean Citation Score: 206.628214
- Max Citation Score: 210.59702
- Similarity Product: 166.2451205083978

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test