PATENT CLAIM ANALYSIS

Application Number: 15766085
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-04
Patent Classification: ["341", "157000"]

Abstract:
The present application discloses an analog-to-digital conversion (ADC) circuit. The circuit includes an integral circuit including an operational amplifier and an integral capacitor. The circuit further includes a comparator and a timer. The operational amplifier includes a positive input terminal configured to receive a first voltage, a negative input terminal coupled to a signal-collection line configured to collect an analog current signal, and an output terminal configured to output a first output signal. The comparator is configured to compare the first output signal with a second voltage to generate a second output signal to the timer. The timer is configured to start a timing operation when the operational amplifier receives the analog current signal and end the timing operation when the second output signal changes. A binary data resulted from the timing operation characterizes a digital signal corresponding to the analog current signal.

Claim (Index 19):
The method of  claim 18 , wherein the subject circuit is a pixel driving circuit configured to generate a driving current to a driving transistor, wherein the driving current is yet to be compensated for driving a light-emitting device based on a data signal sent from a data line to a gate of the driving transistor, further comprising:\n supplying the data signal from the data line to generate a driving current passing through the driving transistor to a source terminal; coupling the signal-collection line via a switch transistor to the source terminal to generate a second analog current signal in the signal-collection line; collecting the second analog current signal by coupling the signal-collection line to the negative input terminal of the operational amplifier of the ADC circuit; starting a timing operation by the timer of the ADC circuit when the second analog current signal is received at the negative input terminal, during which the timer receives a second output signal at a logic level \u201c1\u201d outputted from the comparator of the ADC circuit; ending the timing operation by the timer upon receiving a change of the second output signal from the logic level \u201c1\u201d to a logic level \u201c0\u201d; generating a binary data from the timing operation which characterizes a second digital signal corresponding to the second analog current signal; and determining the driving current based on the second digital signal and the current calibration parameter.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.48387
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11938795', '14693740', '13688203', '12277465', '11421174']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.59881819780498
- 35 USC 102 Novelty (BERT): 0.4872770162045957
- Combined Prediction Score: 0.5876640796449416
- Mean Citation Score: 198.768292
- Max Citation Score: 203.41335
- Similarity Product: 151.62586535798013

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test