PATENT CLAIM ANALYSIS

Application Number: 16032675
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Claim (Index 7):
The resistance switching memory-based accelerator of  claim 1 , wherein the resistance switching memory module further includes:\n a plurality of row address buffers; and a plurality of row data buffers, wherein the plurality of resistance switching memory cells are divided into a plurality of partitions; wherein the memory controller performs three-phase addressing, and wherein the three-phase addressing comprises: a preactive phase for storing an upper address of a row address, which is divided into at least the upper address and a lower address, for accessing the resistance switching memory module in accordance with the memory request, to a target row address buffer among the plurality of row address buffers; an active phase for bringing read data from the memory cell array to a target row data buffer among the plurality of row data buffers based on a row address composed by merging the lower address with the upper address stored to the target row address buffer, in a case of a read; and a read/write phase for transferring the read data from the target row data buffer to the target processing element.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 95.0
- Lexical Diversity: 2.75862
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14191182', '14877807', '15208903', '15605661', '15134068']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5215688068425873
- 35 USC 102 Novelty (BERT): 0.4928489152594568
- Combined Prediction Score: 0.5186968176842743
- Mean Citation Score: 170.12736999999996
- Max Citation Score: 177.97249
- Similarity Product: 116.93273228163478

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test