PATENT CLAIM ANALYSIS

Application Number: 16041664
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "401000"]

Abstract:
A method includes forming an insulating structure over a substrate, wherein the substrate has a semiconductor fin separated from the insulating structure; depositing a high-κ dielectric layer over the semiconductor fin and a sidewall of the insulating structure facing the semiconductor fin; etching a first portion of the high-κ dielectric layer over the sidewall of the insulating structure, wherein a second portion of the high-κ dielectric layer remains over the semiconductor fin; and depositing a gate electrode over the second portion of the high-κ dielectric layer.

Claim (Index 7):
The method of  claim 1 , further comprising:\n forming a dummy layer across the semiconductor fin; forming a spacer over a sidewall of the dummy layer; etching the dummy layer to form a hole in the dummy layer, the hole being separated from the semiconductor fin, wherein forming the insulating structure is performed such that the insulating structure is formed in the hole; and removing the dummy layer to form an opening, wherein depositing the high-\u03ba dielectric layer is performed such that the high-\u03ba dielectric layer is deposited in the opening.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.62857
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14925680', '15786427', '14887873', '15796955', '15246797']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9133639920872558
- 35 USC 102 Novelty (BERT): 0.4800098245003655
- Combined Prediction Score: 0.8700285753285668
- Mean Citation Score: 202.394032
- Max Citation Score: 214.39337
- Similarity Product: 170.1854818867278

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test