PATENT CLAIM ANALYSIS

Application Number: 15891212
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "154000"]

Abstract:
Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

Claim (Index 9):
The integrated circuit of  claim 6 , wherein the first transistor structure comprises a first transistor transmission gate, and wherein the second transistor structure comprises a second transistor transmission gate.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 88.0
- Lexical Diversity: 2.72917
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15789715', '15256200', '15238551', '15477516', '15490352']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8038771848629184
- 35 USC 102 Novelty (BERT): 0.4794369775230213
- Combined Prediction Score: 0.7714331641289287
- Mean Citation Score: 185.455216
- Max Citation Score: 210.97896
- Similarity Product: 157.86148733837132

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test