PATENT CLAIM ANALYSIS

Application Number: 15887770
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["348", "301000"]

Abstract:
A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.

Claim (Index 44):
An imaging apparatus, comprising:\n an imaging optical unit; a solid-state imaging device; a signal processing unit; a storage unit; a display device; an operation unit; and a power source unit, wherein the solid-state imaging device comprises, a semiconductor substrate having a first side and a second side, opposite the first side, as a light incident side; and a plurality of transistors disposed at the first side of the semiconductor substrate; wherein:\n the plurality of transistors comprises first, second, third, and fourth transfer transistors coupled to a first floating diffusion; \n the first and second transfer transistors are arranged in a first row; \n the third and fourth transfer transistors are arranged in a second row parallel to and adjacent the first row; \n the first floating diffusion is disposed between the first and second rows so as to be surrounded by the first, second, third, and fourth transfer transistors; \n a first reset transistor coupled to the first floating diffusion and a circuit node; \n a first amplification transistor is coupled to the first floating diffusion; \n a first select transistor is coupled to the first amplification transistor; \n the first reset transistor, the first amplification transistor, and the first select transistor are disposed in a third row parallel to and adjacent the second row; \n fifth, sixth, seventh, and eighth transfer transistors are coupled to a second floating diffusion; \n the fifth and sixth transfer transistors are arranged in a fourth row parallel to and adjacent the third row; \n the seventh and eighth transfer transistors are arranged in a fifth row parallel to and adjacent the fourth row; \n the second floating diffusion is disposed between the fourth and fifth rows so as to be surrounded by the fifth, sixth, seventh, and eighth transfer transistors; and \n the fifth, sixth, seventh, and eighth transfer transistors are coupled to a second amplification transistor via the second floating diffusion.

Metadata:
- Claim Count in Document: 158.0
- Percentile: 88.0
- Lexical Diversity: 2.64444
- Patent Class: 348.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15454290', '15272234', '14453298', '14317881', '14257644']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7181336396553403
- 35 USC 102 Novelty (BERT): 0.5502454811803384
- Combined Prediction Score: 0.70134482380784
- Mean Citation Score: 404.823702
- Max Citation Score: 421.97342
- Similarity Product: 386.6417941928244

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test