PATENT CLAIM ANALYSIS

Application Number: 16017286
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-09
Patent Classification: ["327", "261000"]

Abstract:
A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.

Claim (Index 19):
A system comprising:\n an input circuit comprising a clock delay circuit configured to generate a delayed clock signal with a clock delay and a plurality of data delay circuits configured to generate a plurality of delayed data signals with a plurality of data delays; and a write training controller configured to:\n adjust the clock delay of the clock delay circuit until identifying a first threshold number of sampling errors created from sampling circuitry configured to sample the plurality of delayed data signals in response to the delayed clock signal; \n set the clock delay to a reference clock delay amount that produces the first threshold number of sampling errors; \n with the clock delay set to a reference clock delay amount that produces the first threshold number of sampling errors:\n adjust the data delays of the plurality of data delay circuits to identify a plurality of first data delay amounts that produce a second threshold number of sampling errors; and \n further adjust the data delays of the plurality of data delay circuits until identifying a plurality of second data delay amounts that produce a third threshold number of sampling errors; \n \n determine a plurality of average delay amounts, each based on one of the plurality of first data delay amounts and the plurality of second data delay amounts; and \n set the plurality of data delays of the plurality of data delay circuits each to a respective one of the plurality of average delay amounts.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 94.0
- Lexical Diversity: 1.94643
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16008678', '16008640', '13584091', '12318306', '10931358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7637229136412812
- 35 USC 102 Novelty (BERT): 0.4652688179094832
- Combined Prediction Score: 0.7338775040681014
- Mean Citation Score: 181.421728
- Max Citation Score: 195.55617
- Similarity Product: 160.63637449313518

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test