PATENT CLAIM ANALYSIS

Application Number: 16162186
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "382000"]

Abstract:
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Claim (Index 10):
The integrated circuit structure of  claim 9 , wherein a portion of the metal stud above the first dielectric layer has a width greater than a width of a portion of the metal stud in contact with the conductive contact structure.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 97.0
- Lexical Diversity: 2.4717
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14731363', '15299106', '14998092', '12655408', '15827491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9205207499394076
- 35 USC 102 Novelty (BERT): 0.5254630143719572
- Combined Prediction Score: 0.8810149763826625
- Mean Citation Score: 303.7462
- Max Citation Score: 311.8047200000001
- Similarity Product: 218.8671458290959

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test