PATENT CLAIM ANALYSIS

Application Number: 15984779
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185180"]

Abstract:
A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Claim (Index 13):
A memory device, comprising:\n a memory location comprising:\n a first transistor comprising a first control gate, a first floating gate underlying the first control gate, and a first gate dielectric underlying the first floating gate; \n a second transistor comprising a second control gate, a second floating gate underlying the second control gate, and a second gate dielectric underlying the second floating gate, wherein the second floating gate is coupled to the first floating gate to form a common floating gate; \n a processor; and a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for executing a writing operation comprising a programming step, the program including instructions for:\n applying a first voltage to a first control gate of a first transistor in a first programming phase, the first transistor comprising the first control gate, a first floating gate underlying the first control gate, and a first gate dielectric underlying the first floating gate; \n applying the first voltage to a second control gate of a second transistor in the first programming phase, the second transistor comprising the second control gate, a second floating gate underlying the second control gate, and a second gate dielectric underlying the second floating gate; \n applying a programming voltage to a drain of the first transistor and a drain of the second transistor in the first programming phase; \n maintaining the first control gate and the second control gate at the first voltage in a second programming phase subsequent to the first programming phase; \n maintaining the drain of the first transistor at the programming voltage in the second programming phase; and \n applying an auxiliary voltage to the drain of the second transistor in the second programming phase.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.375
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15682102', '15221318', '14795742', '14724229', '15276462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7782141142696353
- 35 USC 102 Novelty (BERT): 0.5828845539952937
- Combined Prediction Score: 0.7586811582422011
- Mean Citation Score: 321.40461399999987
- Max Citation Score: 487.25003
- Similarity Product: 450.0425783921576

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test