PATENT CLAIM ANALYSIS

Application Number: 16057316
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "148000"]

Abstract:
Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode.

Claim (Index 14):
A method for operating a memory cell, comprising:\n providing the memory cell, the memory cell including:\n a first diode, comprising: \n a first well region in a substrate;\n a first N-type doped region adjacent to the first well region and connected to a bit line; and \n a first P-type doped region adjacent to the first well region and separated from the first N-type doped region; \n \n a second diode separated from the first diode, and comprising:\n a second well region in the substrate, wherein the second well region has a conductivity type same as the first well region; \n a second N-type doped region adjacent to the second well region; and \n a second P-type doped region, adjacent to the second well region, connected to a reset line, and separated from the second N-type doped region; \n \n a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively; \n a top electrode connected to a word line; and \n a data storage material layer located between the bottom electrode and the top electrode; and \n performing a setting operation on the memory cell at row i and column j, including:\n applying a set voltage to the word line i and floating word lines other than the word line i; \n applying 0V to the bit line j, and floating bit lines other than the bit line j; and\n floating all reset lines.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 96.0
- Lexical Diversity: 3.52174
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15380899', '13116002', '13595426', '10926470', '14968152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7732056035371355
- 35 USC 102 Novelty (BERT): 0.4871636997980863
- Combined Prediction Score: 0.7446014131632307
- Mean Citation Score: 231.42655
- Max Citation Score: 247.62608
- Similarity Product: 204.15258032579425

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test