PATENT CLAIM ANALYSIS

Application Number: 16043474
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-07
Patent Classification: ["365", "230010"]

Abstract:
A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.

Claim (Index 20):
The memory device as claimed in  claim 19 , further comprising:\n a first string select transistor above the upper dummy memory cell, and a second string select transistor between the upper dummy memory cell and the first string select transistor, wherein, while reading data of at least one of the plurality of upper memory cells and the plurality of lower memory cells, a compensation voltage input to the second string select transistor is greater than a compensation voltage input to the first string select transistor.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 2.92105
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15681479', '15210628', '13784969', '15978230', '14814846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8200038252434266
- 35 USC 102 Novelty (BERT): 0.5003420678518246
- Combined Prediction Score: 0.7880376495042665
- Mean Citation Score: 291.593802
- Max Citation Score: 294.26288
- Similarity Product: 223.5454589153099

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test