PATENT CLAIM ANALYSIS

Application Number: 15958741
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["327", "543000"]

Abstract:
In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Claim (Index 21):
The method of  claim 19 , wherein the local resistor has a resistance value that is k time a resistance value of the main resistor, wherein k is a positive number.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 91.0
- Lexical Diversity: 3.525
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13196633', '13243414', '14487090', '11812682', '11308659']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8112727364764347
- 35 USC 102 Novelty (BERT): 0.5044230087984309
- Combined Prediction Score: 0.7805877637086344
- Mean Citation Score: 239.019126
- Max Citation Score: 252.58691
- Similarity Product: 162.35939632017852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test