PATENT CLAIM ANALYSIS

Application Number: 15961322
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-08
Patent Classification: ["257", "334000"]

Abstract:
A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Claim (Index 13):
The device of  claim 8 , wherein the second conductivity type source region is provided to extend into a depth direction of each of the trenches, along the side surface of each of the trenches.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 91.0
- Lexical Diversity: 2.79167
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13341349', '11211268', '10591192', '14068781', '14943109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9304753046655316
- 35 USC 102 Novelty (BERT): 0.5028664655387644
- Combined Prediction Score: 0.8877144207528549
- Mean Citation Score: 255.084834
- Max Citation Score: 256.999
- Similarity Product: 183.8553945833445

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test