PATENT CLAIM ANALYSIS

Application Number: 15920880
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["257", "763000"]

Abstract:
Implementations of a via for a semiconductor devices may include a first tungsten layer deposited conformally within the via, and may be recessed within the via, and a second tungsten layer deposited into the recess over the first tungsten layer. A plane formed by the second tungsten layer may be substantially parallel with a plane aligned substantially perpendicularly with a longest dimension of the via viewed in cross section.

Claim (Index 3):
The via of  claim 1 , further comprising a first liner coupled to the first tungsten layer.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 1.825
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11323328', '14574855', '12468297', '14982061', '11985686']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8881073286424421
- 35 USC 102 Novelty (BERT): 0.4520163510842633
- Combined Prediction Score: 0.8444982308866242
- Mean Citation Score: 131.008128
- Max Citation Score: 135.70914
- Similarity Product: 114.35922943036792

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test