PATENT CLAIM ANALYSIS

Application Number: 16062890
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["363", "132000"]

Abstract:
Present invention provides resonant load power conversion device capable of decreasing switching frequency of each switching element and reducing the number of main circuit conductors. Resonant load power conversion device has single-phase inverter whose DC input side (Vdc) is connected to DC voltage source and whose output side (Vout) is connected to resonant load and which outputs rectangular wave voltage at resonance frequency. Resonant load power conversion device includes switch group circuits  100 U,  100 V,  100 X,  100 Y connected to respective upper and lower arms of input and output sides of single-phase inverter and configured so that N (N=integer of 2 or more) series bodies each having 2 switching elements are connected parallel by main circuit conductors, and controller switching each switching element (U11 to U32, V11 to V32, X11 to X32, Y11 to Y32) of switch group circuits  100 U,  100 V,  100 X,  100 Y by time division of 1/(M×N).

Claim (Index 3):
A resonant load power conversion device having a single-phase inverter whose DC input side is connected to a DC voltage source and whose output side is connected to a resonant load and which outputs a rectangular wave voltage at resonance frequency, comprising:\n switch group circuits that are connected to respective upper and lower arms of one phase of the single-phase inverter and the other phase of the single-phase inverter, each of the switch group circuits being configured so that n (n=an integer of 2 or more) series bodies each having m (m=an integer of 2 or more) switching elements are connected parallel by main circuit conductors, and wherein,\n the switch group circuit of the upper arm, which is the one phase of the single-phase inverter, has a first series body in which m switching elements of U11 to U1m are connected in series, . . . and an nth series body in which m switching elements of Un1 to Unm are connected in series, and the switch group circuit is configured so that the n series bodies of the first to nth series bodies are connected parallel by the main circuit conductors, \n the switch group circuit of the lower arm, which is the one phase of the single-phase inverter, has a first series body in which m switching elements of X11 to X1m are connected in series, . . . and an nth series body in which m switching elements of Xn1 to Xnm are connected in series, and the switch group circuit is configured so that the n series bodies of the first to nth series bodies are connected parallel by the main circuit conductors, \n the switch group circuit of the upper arm, which is the other phase of the single-phase inverter, has a first series body in which m switching elements of V11 to Vim are connected in series, . . . and an nth series body in which m switching elements of Vn1 to Vnm are connected in series, and the switch group circuit is configured so that the n series bodies of the first to nth series bodies are connected parallel by the main circuit conductors, and \n the switch group circuit of the lower arm, which is the other phase of the single-phase inverter, has a first series body in which m switching elements of Y11 to Y1m are connected in series, . . . and an nth series body in which m switching elements of Yn1 to Ynm are connected in series, and the switch group circuit is configured so that the n series bodies of the first to nth series bodies are connected parallel by the main circuit conductors; and \n a controller that performs switching control of each switching element of the switch group circuits of the single-phase inverter by time division of 1/(m\u00d7n), and has a gate command generator that generates a clock with ON and OFF of an output voltage command of the single-phase inverter being a trigger, a switching element U11 and Y11 gate command signal U11_gate/Y11_gate with (2\u00d7the number M of series connection\u00d7the number N of parallel connection (M, N=an integer of 2 or more)) clocks being one cycle and with an ON signal being outputted for a period of (2\u00d7the number N of parallel connection\u00d7(the number M of series connection\u22121)+1) clocks and an OFF signal being outputted for a period of [(2\u00d7the number M of series connection\u00d7the number N of parallel connection)\u2212(2\u00d7the number N of parallel connection\u00d7(the number M of series connection\u22121)+1)] clocks,\n a switching element X11 and V11 gate command signal X11_gate/V11_gate that is delayed by 1 clock with respect to the gate command signal U11_gate/Y11_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal U11_gate/Y11_gate, \n a switching element U21 and Y21 gate command signal U21_gate/Y21_gate that is delayed by 1 clock with respect to the gate command signal X11_gate/V11_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal X11_gate/V11_gate, \n a switching element X21 and V21 gate command signal X21_gate/V21_gate that is delayed by 1 clock with respect to the gate command signal U21_gate/Y21_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal U21_gate/Y21_gate, \n . \n . \n . \n a switching element Un1 and Yn1 gate command signal Un1_gate/Yn1_gate that is delayed by 1 clock with respect to a gate command signal X(n\u22121)1_gate/V(n\u22121)1_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal \n X(n\u22121)1_gate/V(n\u22121)1_gate, \n a switching element Xn1 and Vn1 gate command signal Xn1_gate/Vn1_gate that is delayed by 1 clock with respect to the gate command signal Un1_gate/Yn1_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal Un1_gate/Yn1_gate, \n a switching element U12 and Y12 gate command signal U12_gate/Y12_gate that is delayed by 1 clock with respect to the gate command signal Xn1_gate/Vn1_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal Xn1_gate/Vn1_gate, \n a switching element X12 and V12 gate command signal X12_gate/V12_gate that is delayed by 1 clock with respect to the gate command signal U12_gate/Y12_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal U12_gate/Y12_gate, \n a switching element U22 and Y22 gate command signal U22_gate/Y22_gate that is delayed by 1 clock with respect to the gate command signal X12_gate/V12_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal X12_gate/V12_gate, \n a switching element X22 and V22 gate command signal X22_gate/V22_gate that is delayed by 1 clock with respect to the gate command signal U22_gate/Y22_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal U22_gate/Y22_gate, \n . \n . \n . \n a switching element Un2 and Yn2 gate command signal Un2_gate/Yn2_gate that is delayed by 1 clock with respect to a gate command signal X(n\u22121)2_gate/V(n\u22121)2_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal X(n\u22121)2_gate/V(n\u22121)2_gate, \n a switching element Xn2 and Vn2 gate command signal Xn2_gate/Vn2_gate that is delayed by 1 clock with respect to the gate command signal Un2_gate/Yn2_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal Un2_gate/Yn2_gate, \n . \n . \n . \n a switching element Unm and Ynm gate command signal Unm_gate/Ynm_gate that is delayed by 1 clock with respect to a gate command signal X(n\u22121)m_gate/V(n\u22121)m_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal X(n\u22121)m_gate/V(n\u20141)m_gate, and \n a switching element Xnm and Vnm gate command signal Xnm_gate/Vnm_gate that is delayed by 1 clock with respect to the gate command signal Unm_gate/Ynm_gate and has the same ON and OFF periods as ON and OFF periods of the gate command signal Unm_gate/Ynm_gate, and wherein \n each of the switching elements is ON/OFF-controlled by each of the generated gate command signals.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 94.0
- Lexical Diversity: 1.97778
- Patent Class: 363.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15318796', '15311068', '11480537', '11507584', '12206668']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7895802546051182
- 35 USC 102 Novelty (BERT): 0.4367352557214339
- Combined Prediction Score: 0.7542957547167498
- Mean Citation Score: 124.1792998
- Max Citation Score: 158.8098
- Similarity Product: 146.95969535315038

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test