PATENT CLAIM ANALYSIS

Application Number: 16105730
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["365", "177000"]

Abstract:
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Claim (Index 36):
The integrated circuit of  claim 35 , wherein the fin structure is an elongate fin structure that includes a longitudinal axis, and further wherein the plurality of gates is spaced apart along the longitudinal axis.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 96.0
- Lexical Diversity: 1.60976
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15730525', '15414009', '14282850', '13296402', '14046986']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8512938610471907
- 35 USC 102 Novelty (BERT): 0.5471495109096713
- Combined Prediction Score: 0.8208794260334388
- Mean Citation Score: 453.801242
- Max Citation Score: 462.9388
- Similarity Product: 264.5739130803585

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test