PATENT CLAIM ANALYSIS

Application Number: 15995452
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "315000"]

Abstract:
Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Claim (Index 2):
The structure of  claim 1 , wherein the protection layer is made of amorphous silicon.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 2.73913
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15228236', '14982228', '15053365', '11059294', '10849152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9273965684406276
- 35 USC 102 Novelty (BERT): 0.5012039102288077
- Combined Prediction Score: 0.8847773026194456
- Mean Citation Score: 200.705484
- Max Citation Score: 287.0437
- Similarity Product: 259.48111857479813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test