PATENT CLAIM ANALYSIS

Application Number: 15862930
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

Claim (Index 19):
The semiconductor structure of  claim 15 , wherein the shared gate comprises a first gate conductor surrounding the first fin and a second gate conductor surrounding the second fin, the gate contact metal layer contacting the first gate conductor and the second gate conductor.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 86.0
- Lexical Diversity: 1.94
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15852109', '15426479', '15819109', '15245634', '15831354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9275473076396392
- 35 USC 102 Novelty (BERT): 0.5182065270224694
- Combined Prediction Score: 0.8866132295779221
- Mean Citation Score: 264.368154
- Max Citation Score: 295.12448
- Similarity Product: 192.6064301133728

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test