PATENT CLAIM ANALYSIS

Application Number: 16184607
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["365", "233100"]

Abstract:
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Claim (Index 12):
The configurable non-volatile memory device as claimed in  claim 2 , wherein the configurable non-volatile memory device is a NOR flash memory device.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 98.0
- Lexical Diversity: 2.53125
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15957120', '15378650', '15655336', '13006005', '15183162']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8134999412487587
- 35 USC 102 Novelty (BERT): 0.5245868785449578
- Combined Prediction Score: 0.7846086349783786
- Mean Citation Score: 319.365812
- Max Citation Score: 346.58768
- Similarity Product: 287.1351786449813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test