PATENT CLAIM ANALYSIS

Application Number: 15878806
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["365", "185130"]

Abstract:
A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Claim (Index 19):
The memory device according to  claim 17 , further comprising:\n an interlayer dielectric layer formed over the substrate to cover the memory cell array; a plurality of bit lines formed over the interlayer dielectric layer; and bit line contacts disposed over the channel structures, respectively, and electrically coupling the channel structures to the bit lines through the interlayer dielectric layer, wherein the supports are electrically decoupled from the bit lines by the interlayer dielectric layer.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 86.0
- Lexical Diversity: 1.75676
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15792983', '15856933', '10944910', '15586307', '15792965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7894279275006206
- 35 USC 102 Novelty (BERT): 0.4697175893351978
- Combined Prediction Score: 0.7574568936840784
- Mean Citation Score: 191.060012
- Max Citation Score: 205.12762
- Similarity Product: 162.0966493444073

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test