PATENT CLAIM ANALYSIS

Application Number: 15917377
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "158000"]

Abstract:
According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

Claim (Index 15):
The device of  claim 13 , wherein:\n the second circuit includes a latch circuit including a first NAND circuit and a second NAND circuit; the first NAND circuit includes a first input terminal supplied with the fourth signal and a second input terminal coupled to an output terminal of the second NAND circuit; and the second NAND circuit includes a first input terminal coupled to an output terminal of the first NAND circuit and a second input terminal supplied with the fifth signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.78049
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15449198', '15261680', '14644167', '15913407', '15438115']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.81145936228913
- 35 USC 102 Novelty (BERT): 0.4982340294033363
- Combined Prediction Score: 0.7801368290005506
- Mean Citation Score: 216.461998
- Max Citation Score: 248.26453
- Similarity Product: 165.7198784016341

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test