PATENT CLAIM ANALYSIS

Application Number: 15880349
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["257", "798000"]

Abstract:
A method for integrating heterogeneous elements with elements residing on a target wafer is described. A source die including a compound semiconductor substrate, an etch stop layer and at least one active semiconductor element is provided. The etch stop layer is between the active semiconductor element(s) and the substrate. The etch stop layer is resistant to a plasma etch for the substrate. A bonding agent is provided on a surface of the target wafer. The source die is aligned to and placed on the part of the surface of the target wafer such that the active semiconductor element(s) are between the target wafer's surface and the substrate. The bonding agent is between the source die and the surface of the target wafer. The source die is bonded to the target wafer using the bonding agent. The substrate of the source die is removed, the removal includes performing the plasma etch.

Claim (Index 19):
A method for integrating heterogeneous elements with circuit elements residing on a target wafer comprising:\n providing a source die including a GaAs substrate, an AIGaAs etch stop layer and at least one active semiconductor element, the AIGaAs etch stop layer residing between the at least one active semiconductor element and the GaAs substrate; applying a spin-on glass (SOG) bonding agent on at least a portion of a surface of the target wafer; aligning the source die to the portion of surface of the target wafer; placing the source die on the portion of the surface of the target wafer such that the at least one active semiconductor element is between the surface of the target wafer and the GaAs substrate, at least a portion of the SOG bonding agent residing between the source die and the surface of the target wafer; applying a force to at least one of the source die and the target wafer such that the SOG bonding agent has a bond thickness; heating at least the SOG bonding agent to a temperature of at least two hundred degrees Celsius and not more than four hundred degrees Celsius; applying a protective layer to at least a side of the source die; removing the GaAs substrate of the source die, the step of removing the GaAs substrate including\n reducing a thickness of the GaAs substrate using at least one of mechanical and chemical processes; and \n performing a plasma etch of a remaining portion of the GaAs substrate, the AIGaAs etch stop layer being a stop layer for the plasma etch; \n wet etching the AIGaAs etch stop layer after the plasma etch; and at least one of performing additional processing on the at least one active semiconductor element and providing additional components on the target wafer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.84746
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15592704', '14707367', '15480239', '15209309', '11046912']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8855035458600551
- 35 USC 102 Novelty (BERT): 0.4908163858677545
- Combined Prediction Score: 0.8460348298608251
- Mean Citation Score: 180.33566
- Max Citation Score: 186.92772
- Similarity Product: 131.390679631176

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test