PATENT CLAIM ANALYSIS

Application Number: 16166262
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["323", "271000"]

Abstract:
A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

Claim (Index 2):
The circuit of  claim 1 , wherein said current limit jitter block adds jitter to the current limit.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 2.34483
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14845381', '15596399', '14260516', '15651785', '15189210']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7196218944745908
- 35 USC 102 Novelty (BERT): 0.5403617673591957
- Combined Prediction Score: 0.7016958817630513
- Mean Citation Score: 254.92866000000004
- Max Citation Score: 395.27536
- Similarity Product: 197.5641131274271

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test