PATENT CLAIM ANALYSIS

Application Number: 15924100
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185020"]

Abstract:
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

Claim (Index 11):
A non-volatile memory device comprising:\n an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, a source line terminal, and no other terminals; a row decoder for receiving row address signals and selecting a row in the array of flash memory cells for a read, program, or erase operation based on the row address signals; an erase gate decoder for receiving erase gate select signals, selecting one of a plurality of different voltages to generate an erase gate voltage, and applying the erase gate voltage to an erase gate line connected to erase gate terminals of a plurality of flash memory cells in the array; a source line decoder for receiving source line select signals, selecting one of the plurality of different voltages to generate a source line voltage, and applying the source line voltage to a source line connected to source line terminals of a plurality of flash memory cells in the array; a voltage shifter for generating one of the plurality of different voltages; and a column of dummy flash memory cells, wherein each dummy flash memory cell is not used to store data and one or more of the dummy flash memory cells are coupled to a source line during a read or erase operation to pull the source line down to a low voltage or ground, wherein each source line is coupled to the source line terminals of two rows of flash memory cells in the array.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 90.0
- Lexical Diversity: 1.7931
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15158460', '15479235', '15238681', '15467174', '14875533']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8555152817893376
- 35 USC 102 Novelty (BERT): 0.6533619321077535
- Combined Prediction Score: 0.8352999468211791
- Mean Citation Score: 518.533778
- Max Citation Score: 647.1237
- Similarity Product: 639.4084972008527

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test