PATENT CLAIM ANALYSIS

Application Number: 16192509
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-03
Patent Classification: ["710", "308000"]

Abstract:
In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Claim (Index 6):
The device of  claim 1 , wherein the bus interface comprises a processor, a direct address storage (DAS), and a multiplexer configured to switch to transmit the respective address of the plurality of addresses comprising a direct address stored in the DAS when the multiplexer is set to transmit an output from the DAS.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.63265
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15280611', '15409351', '15534978', '15280481', '16030479']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.711335725848165
- 35 USC 102 Novelty (BERT): 0.5216592183593042
- Combined Prediction Score: 0.6923680750992789
- Mean Citation Score: 260.03734
- Max Citation Score: 364.7442
- Similarity Product: 284.7916571314573

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test