PATENT CLAIM ANALYSIS

Application Number: 15922929
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-06
Patent Classification: ["710", "074000"]

Abstract:
A host device includes a first serial peripheral interface (SPI) and a second SPI to communicate with an embedded multimedia card (eMMC) device. The host device has a mode controller that controls the first SPI to toggle between first transmission and first reception modes for command transmission and response reception, respectively. The mode controller controls the second SPI to toggle between second transmission and second reception modes for data transmission and data reception, respectively.

Claim (Index 12):
A host device for communication with an embedded multimedia card (eMMC) device, the host device comprising:\n a first serial peripheral interface (SPI) having a command output terminal SPI 1  MOSI connected to a first terminal of the eMMC device for transmitting at least one of a data-write command to execute a data-write operation on the eMMC device and a data-read command to execute a data-read operation on the eMMC device, and a response input terminal SPI 1  MISO connected to the first terminal of the eMMC device for receiving a response to the at least one of the data-write command and the data-read command, wherein the first SPI is operable in one of a first transmission mode and a first reception mode; a second SPI having a data output terminal SPI 2  MISO connected to a second terminal of the eMMC device for transmitting write-data based on the data-write command to the eMMC device, and a data input terminal SPI 2  MOSI connected to the second terminal of the eMMC device for receiving read-data from the eMMC device, based on the data-read command, wherein the second SPI is operable in one of a second transmission mode and a second reception mode; a first control register having a first reserved bit for enabling the first SPI to operate in one of the first transmission mode and the first reception mode, and a second reserved bit for enabling the second SPI to operate in one of the second transmission mode and the second reception mode; a mode controller that sets a value of the first and second reserved bits based on at least one of the data-write command and the data-read command, thereby enabling the first and second SPIs to operate in one of the first transmission mode and the first reception mode, and one of the second transmission mode and the second reception mode, respectively; and first and second resistors that act as fail-safe resistors for preventing an open circuit condition of the command and data channels.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.02439
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14025886', '14024655', '14025909', '14025866', '14592114']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6618345003820066
- 35 USC 102 Novelty (BERT): 0.4705606452721269
- Combined Prediction Score: 0.6427071148710186
- Mean Citation Score: 170.09868799999995
- Max Citation Score: 176.71739
- Similarity Product: 131.13218986474095

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test