PATENT CLAIM ANALYSIS

Application Number: 15904895
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["716", "112000"]

Abstract:
The present disclosure generally relates to semiconductor structures and, more particularly, to rule check structures and methods of manufacture. The method includes matching, by a computing device, patterns in a design layer to approved patterns; determining, by the computing device, a similarity between at least one unmatched pattern and the approved patterns; and correcting, by the computing device, the at least one unmatched pattern to match a pattern with the closest similarity out of the approved patterns.

Claim (Index 2):
The method of  claim 1 , wherein the design layer is a via layer, a front end of line layer or a back end of line layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 1.97778
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14296705', '12208167', '13802738', '11367943', '15210666']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3343488647602048
- 35 USC 102 Novelty (BERT): 0.4774716839136779
- Combined Prediction Score: 0.3486611466755521
- Mean Citation Score: 133.52562799999998
- Max Citation Score: 145.3899
- Similarity Product: 85.35510412620306

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test