PATENT CLAIM ANALYSIS

Application Number: 16031919
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "324000"]

Abstract:
Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Claim (Index 15):
The method of  claim 6  wherein the conductive levels comprise one or more metals and/or metal-containing materials.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 95.0
- Lexical Diversity: 2.02174
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15422335', '15422307', '15933218', '15409412', '15419813']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92928218964935
- 35 USC 102 Novelty (BERT): 0.5119028924563874
- Combined Prediction Score: 0.8875442599300537
- Mean Citation Score: 241.85202
- Max Citation Score: 276.91122
- Similarity Product: 184.6517689396549

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test