PATENT CLAIM ANALYSIS

Application Number: 15910264
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "072000"]

Abstract:
A LTPS TFT comprises a substrate, and a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, a dielectric layer, a source and a drain disposed on the substrate successively. The source contact area and the drain contact area are doped with metal ions individually. The source and the drain are connecting with the source and drain contact areas separately through the dielectric layer. The metal ions include at least one of Cu 2+ , Al 3+ , Mg 2+ , Zn 2+  and Ni 2+ . A method of fabricating the LTPS TFT is also provided. An annealing is performed for driving individually metal ions of the insulation metal oxide layer into the source contact area and the drain contact area. Thus, the step of implanting p-type ions can be omitted, the procedure can be significantly simplified, and the manufacturing cost can be reduced.

Claim (Index 3):
A method of forming a low temperature polysilicon thin film transistor (LTPS TFT), comprising:\n providing a substrate; forming a buffer layer, a low temperature polysilicon layer, a source contact area to be formed, a drain contact area to be formed, a gate insulating layer and a gate layer on the substrate successively; wherein the source contact area to be formed and the drain contact area to be formed are disposed in a same layer with the low temperature polysilicon layer and at two opposite sides of the low temperature polysilicon layer separately; depositing an insulation metal oxide layer on the low temperature polysilicon layer to cover the source contact area to be formed and the drain contact area to be formed, and driving individually metal ions of the insulation metal oxide layer into the source contact area to be formed and the drain contact area to be formed to form the source contact area and the drain contact area after an annealing procedure; wherein the metal ions include at least one of Cu2+, Al3+, Mg2+, Zn2+ and Ni2+; and forming a source contacting the source contact area and a drain contacting the drain contact area on the low temperature polysilicon layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.36486
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15121037', '14779089', '10248770', '14428983', '15393413']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9285993422926688
- 35 USC 102 Novelty (BERT): 0.4976445353614424
- Combined Prediction Score: 0.8855038615995461
- Mean Citation Score: 259.438996
- Max Citation Score: 267.19852000000003
- Similarity Product: 211.20118717265845

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test