PATENT CLAIM ANALYSIS

Application Number: 16035693
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "774000"]

Abstract:
A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.

Claim (Index 7):
A package structure, comprising:\n a first semiconductor die having a plurality of conductive vias; a second semiconductor die disposed adjacent to the first semiconductor die and having a plurality of conductive vias; a molding compound encapsulating the first semiconductor die and the second semiconductor die; a plurality of first conductive features disposed on the molding compound and physically connected to the plurality of conductive vias of the first semiconductor die and the plurality of conductive vias of the second semiconductor die, wherein each of the first conductive features comprises flank portions and a recessed portion joining the flank portions; a plurality of second conductive features disposed adjacent to the plurality of first conductive features and on the molding compound and physically connected to the plurality of conductive vias of the first semiconductor die and the plurality of conductive vias of the second semiconductor die; an interconnect structure disposed on the plurality of second conductive features and electrically connecting the first semiconductor die to the second semiconductor die; a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the first semiconductor die and the second semiconductor die, wherein the plurality of through insulator vias surrounds the interconnect structure; an insulating encapsulant encapsulating the interconnect structure and the plurality of through insulator vias, and separating the interconnection structure from the plurality of through insulator vias; and a redistribution layer disposed on the insulating encapsulant and over the interconnect structure, wherein the redistribution layer is electrically connected to the plurality of through insulator vias.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 3.68182
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15979494', '16016664', '15841331', '14755700', '15964091']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9097524414501964
- 35 USC 102 Novelty (BERT): 0.4596479003736779
- Combined Prediction Score: 0.8647419873425445
- Mean Citation Score: 164.324734
- Max Citation Score: 174.1031
- Similarity Product: 146.11886459059716

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test