PATENT CLAIM ANALYSIS

Application Number: 15878280
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["327", "109000"]

Abstract:
Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Claim (Index 32):
A circuit for linearizing an adjustable resistance of a field effect transistor (FET), the circuit comprising:\n the FET; an amplifier configured to apply a representation of a voltage of a drain of the FET and a representation of a voltage of a source of the FET to a gate of the FET; a first resistor configured to couple the source to a first input of the amplifier; a second resistor configured to couple the drain to the first input of the amplifier; and wherein an average voltage of the voltage of the drain and the voltage of the source provides the representation of the voltage of the drain and the representation of the voltage of the source.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 86.0
- Lexical Diversity: 1.76471
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11154135', '12357221', '14794496', '11092070', '11683074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7440962699216839
- 35 USC 102 Novelty (BERT): 0.4494058567291242
- Combined Prediction Score: 0.714627228602428
- Mean Citation Score: 128.73976199999998
- Max Citation Score: 132.11263
- Similarity Product: 104.04188058346868

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test