PATENT CLAIM ANALYSIS

Application Number: 16105836
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["326", "052000"]

Abstract:
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Claim (Index 16):
The method of  claim 10 , further comprising determining, via a plurality of XOR gates, whether the input data includes a parity error.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 96.0
- Lexical Diversity: 2.65217
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15684734', '15184077', '13331932', '12500240', '11040804']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6789642961005793
- 35 USC 102 Novelty (BERT): 0.5270541273236691
- Combined Prediction Score: 0.6637732792228883
- Mean Citation Score: 255.283186
- Max Citation Score: 372.1415
- Similarity Product: 269.1105822435617

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test