PATENT CLAIM ANALYSIS

Application Number: 15777829
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-07
Patent Classification: ["257", "072000"]

Abstract:
An array substrate and a manufacturing method thereof, and display panel are disclosed. The array substrate includes a substrate, a thin film transistor disposed on the substrate and a common electrode disposed on a side of the thin film transistor away from the substrate. The common electrode includes a first hollowed-out portion. An active layer of the thin film transistor includes a source electrode region, a drain electrode region and a channel region. An orthographic projection of the first hollowed-out portion on the substrate at least covers an orthographic projection of the channel region on the substrate.

Claim (Index 15):
A manufacturing method of the array substrate according to  claim 1 , comprising:\n forming a thin film transistor on a substrate by using a patterning process; forming an insulating layer, a common electrode, a passivation layer and a pixel electrode which are sequentially disposed on a side of the thin film transistor away from the substrate by using the patterning process for three times, on the substrate on which the thin film transistor has been formed, wherein, the insulating layer comprises a first via hole, the common electrode comprises a third via hole and a first hollowed-out portion, the passivation layer comprises a second via hole and a second hollowed-out part, and an orthographic projection of the pixel electrode on the substrate does not overlap with an orthographic projection of the first hollowed-out portion on the substrate; the thin film transistor includes an active layer, the active layer comprising a source electrode region, a drain electrode region and a channel region, the orthographic projection of the first hollowed-out portion on the substrate at least covers an orthographic projection of the channel region on the substrate, the orthographic projection of the first hollowed-out portion on the substrate overlaps with an orthographic projection of the second hollowed-out portion on the substrate; an orthographic projection of the first via hole on the substrate, an orthographic projection of the second via hole on the substrate and an orthographic projection of the third via hole on the substrate are overlapped with each other, a size of the third via hole is greater than or equal to a size of the first via hole, and the size of the third via hole is greater than a size of the second via hole; and the pixel electrode is electrically connected to a drain electrode of the thin film transistor through the first via hole, the second via hole and the third via hole.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 93.0
- Lexical Diversity: 2.44186
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16080207', '15807451', '15750984', '15529495', '15568155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9291917083257746
- 35 USC 102 Novelty (BERT): 0.5160566257295651
- Combined Prediction Score: 0.8878782000661537
- Mean Citation Score: 305.86805
- Max Citation Score: 318.64468
- Similarity Product: 237.9810181596112

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test