PATENT CLAIM ANALYSIS

Application Number: 15937400
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["327", "242000"]

Abstract:
A semiconductor device including a bus master that receives a clock; a first bus slave that receives a first slave clock and has a first number of waits, and a second bus slave that receives a second slave clock and has a second number of waits, wherein the second number of waits is higher than the first number of waits, and wherein a phase difference between the clock and the first slave clock is higher than a phase difference between the clock and the second slave clock.

Claim (Index 1):
A semiconductor device comprising:\n a bus master that receives a clock; a first bus slave that receives a first slave clock and has a first number of waits; and a second bus slave that receives a second slave clock and has a second number of waits, wherein the second number of waits is higher than the first number of waits, and wherein a phase difference between the clock and the first slave clock is greater than a phase difference between the clock and the second slave clock.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 3.17241
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14967024', '13179119', '11741328', '15914971', '11741250']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7514198629211281
- 35 USC 102 Novelty (BERT): 0.5157772217417707
- Combined Prediction Score: 0.7278555988031924
- Mean Citation Score: 192.17229
- Max Citation Score: 324.91803
- Similarity Product: 240.25604020477832

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test