PATENT CLAIM ANALYSIS

Application Number: 15952350
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["438", "675000"]

Abstract:
A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

Claim (Index 4):
The method of  claim 3 , further comprising:\n forming a third spacer when forming the second spacer, wherein the forming the first spacer includes forming a first sub-spacer covering the sidewall of the bit line and a second sub-spacer covering a sidewall of the first sub-spacer, the removing the first sacrificial layer and the upper portion of the contact plug includes partially exposing a sidewall of the second sub-spacer, the method further includes removing a portion of the second sub-spacer to partially expose the sidewall of the first sub-spacer, and the forming the third spacer includes forming the third spacer to cover the sidewall of the first sub-spacer that is partially exposed.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 91.0
- Lexical Diversity: 3.07843
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14755690', '15845141', '14506393', '14057530', '14738421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.876996555411585
- 35 USC 102 Novelty (BERT): 0.5087397541368289
- Combined Prediction Score: 0.8401708752841095
- Mean Citation Score: 299.16161
- Max Citation Score: 307.04077
- Similarity Product: 255.53658384950995

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test