PATENT CLAIM ANALYSIS

Application Number: 16154717
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["257", "040000"]

Abstract:
A display device includes a gate insulating layer disposed on a channel region of a semiconductor layer. A gate electrode is disposed on the gate insulating layer over the channel region of the semiconductor layer. A source electrode is disposed in direct contact with the source region of the semiconductor layer and a drain electrode is disposed in direct contact with a drain region of the semiconductor layer. A passivation layer is disposed on the gate electrode, the source electrode, and the drain electrode. The passivation layer is in direct contact with semiconductor layer in a region between the source electrode and the gate electrode, and is in direct contact with the semiconductor layer in a region between the gate electrode and the drain electrode. The first gate electrode, the first source electrode, and the first drain electrode comprise a same layer and a same material.

Claim (Index 10):
The display device of  claim 8 ,\n wherein the gate pattern is in direct contact with the second semiconductor layer and the buffer layer in an entire overlapping region of the gate pattern and the second semiconductor layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 97.0
- Lexical Diversity: 4.61765
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14983240', '15684785', '15607979', '15298749', '16016306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9326074327219188
- 35 USC 102 Novelty (BERT): 0.5156126207567296
- Combined Prediction Score: 0.8909079515253999
- Mean Citation Score: 283.689256
- Max Citation Score: 301.39432
- Similarity Product: 213.36140079396247

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test