PATENT CLAIM ANALYSIS

Application Number: 16127004
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "678000"]

Abstract:
Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Claim (Index 6):
The device of  claim 2  wherein the cavity is a region having an airtight seal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 1.56364
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13977183', '15289058', '14220912', '15234425', '14925807']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9267301034981436
- 35 USC 102 Novelty (BERT): 0.5185484410223978
- Combined Prediction Score: 0.885911937250569
- Mean Citation Score: 177.359096
- Max Citation Score: 230.00797000000003
- Similarity Product: 114.84598251292172

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test