PATENT CLAIM ANALYSIS

Application Number: 16017600
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "156000"]

Abstract:
A memory array includes a first memory cell and a second memory cell, each including a data storage element, a first access transistor coupled to the data storage element, and a second access transistor coupled to the data storage element. The memory array further includes two word lines configured to selectively enable access to the data storage element of the first memory cell through the two access transistors of the first memory cell respectively, two bit lines coupled to the two access transistors of the first memory cell respectively, two another word lines configured to selectively enable access to the data storage element of the second memory cell through the two access transistors of the second memory cell respectively, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.

Claim (Index 17):
A method of operating a memory array, the memory array comprising:\n a first memory cell and a second memory cell, each comprising:\n a data storage element having a first terminal and a second terminal; \n a first access transistor coupled to the first terminal; and \n a second access transistor coupled to the second terminal; \n a first bit line coupled to the first access transistor of the first memory cell; a second bit line coupled to the second access transistor of the first memory cell; a third bit line coupled to the first access transistor of the second memory cell; a first word line and a second word line configured to selectively enable access to the data storage element of the first memory cell through the first access transistor and the second access transistor of the first memory cell, respectively; a third word line and a fourth word line configured to selectively enable access to the data storage element of the second memory cell through the first access transistor and the second access transistor of the second memory cell, respectively; and a first sense amplifier coupled to the first bit line and the third bit line, wherein the method comprises: pulling a voltage level of the first bit line and a voltage level of the third bit line to a predetermined voltage level; turning on the first access transistor of the first memory cell through the first word line to thereby pull the voltage level of the first bit line to another voltage level; and comparing the another voltage level of the first bit line with the predetermined voltage level of the third bit line using the first sense amplifier.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 94.0
- Lexical Diversity: 4.07692
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13488432', '11015428', '14637297', '13595426', '13460487']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7848202720556146
- 35 USC 102 Novelty (BERT): 0.4594387433392141
- Combined Prediction Score: 0.7522821191839746
- Mean Citation Score: 174.60531400000005
- Max Citation Score: 176.32587
- Similarity Product: 140.18580640073776

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test