PATENT CLAIM ANALYSIS

Application Number: 16243249
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["345", "209000"]

Abstract:
A differential amplifier circuit includes a differential input stage, a first current mirror, a second current mirror, a first current source circuit, and a second current source circuit. The first current source circuit has a first transistor of a first conductivity type with a control terminal supplied with a first bias voltage, and a second transistor of a second conductivity type with a control terminal supplied with a second bias voltage. An output amplifier circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. A control circuit has a fifth transistor of the first conductivity type with a first terminal connected to a connection point between the other end of the second current source circuit and the control terminal of the fourth transistor in the output amplifier circuit, with a second terminal connected to an output node of the second current mirror, and with a control terminal receiving the first bias voltage.

Claim (Index 15):
The output circuit according to  claim 14 , wherein\n the first current mirror includes:\n a first transistor pair of a first conductivity type with first terminals connected together to the first power supply terminal and with control terminals connected to each other; and \n a second transistor pair of a first conductivity type with first terminals respectively connected to second terminals of the first transistor pair, and with a third bias voltage being applied to control terminals connected together, \n the second terminal of one transistor of the second transistor pair is connected to the control terminals connected together in the first transistor pair and acts as an input node of the first current mirror, and the second terminal of the other transistor of the second transistor pair acts as an output node of the first current mirror, the second terminals of the differential transistor pair of the second conductivity type in the differential input stage are connected to the second terminals of the first transistor pair of the first conductivity type in the first current mirror, respectively, the second current mirror includes:\n a third transistor pair of the second conductivity type with first terminals connected together to the second power supply terminal and with control terminals connected to each other; and \n a fourth transistor pair of the second conductivity type with first terminals respectively connected to the second terminals of the third transistor pair and with a fourth bias voltage being applied to the control terminals connected together, \n the second terminal of one transistor of the fourth transistor pair is connected to the control terminals connected together in the third transistor pair and acts as an input node of the second current mirror, and the second terminal of the other transistor of the fourth transistor pair acts as an output node of the second current mirror, and the second terminals of the differential transistor pair of the first conductivity type in the differential input stage are connected to the second terminals of the third transistor pair of the second conductivity type in the second current mirror, respectively.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 3.82222
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15818628', '13204403', '13317858', '14664076', '11648530']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6872158927770912
- 35 USC 102 Novelty (BERT): 0.57834995824558
- Combined Prediction Score: 0.67632929932394
- Mean Citation Score: 374.23268
- Max Citation Score: 450.50867
- Similarity Product: 444.39722277061577

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test