PATENT CLAIM ANALYSIS

Application Number: 15983378
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["381", "098000"]

Abstract:
A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Claim (Index 5):
An integrated circuit according to  claim 3 , wherein the first loop further comprises a first digital filter, for receiving an output of the first subtractor, and filtering it to form the first error signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 3.46667
- Patent Class: 381.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13678300', '15009405', '10986994', '12533422', '11739529']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7414614052703722
- 35 USC 102 Novelty (BERT): 0.5435534425714762
- Combined Prediction Score: 0.7216706090004826
- Mean Citation Score: 291.77845
- Max Citation Score: 404.47803
- Similarity Product: 276.9917740875256

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test