PATENT CLAIM ANALYSIS

Application Number: 15863490
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "326000"]

Abstract:
A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.

Claim (Index 11):
A semiconductor memory device, comprising:\n a first stacked body including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween; a second stacked body including a plurality of second electrode layers alternately stacked with a plurality of second insulating layers therebetween; a first semiconductor film portion covering an outer periphery of a first core insulator part extending inside the first stacked body; a second semiconductor film portion covering an outer periphery of a second core insulator part extending inside the second stacked body; a first intermediate layer provided above the first stacked body and below the second stacked body, a thickness of the first intermediate layer being greater than a thickness of the first insulating layers and a thickness of the second insulating layers, the first semiconductor film portion and the second semiconductor film portion having asymmetric configurations with respect to the first intermediate layer; and a third semiconductor film portion extending inside the first intermediate layer, the first semiconductor film portion being electrically connected to the second semiconductor film portion via the third semiconductor film portion, and the first, second and third semiconductor film portions being provided in a hole piercing the first and second stacked bodies and the first intermediate layer in a stacking direction of the first and second stacked bodies; wherein a first memory cell provided in the first stacked body includes a first charge storage film provided between the first semiconductor film portion and one of the first electrode layers; and a second memory cell provided in the second stacked body includes a second charge storage film provided between the second semiconductor film portion and one of the second electrode layers, the second charge storage film being discontinuous with the first charge storage film.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15264903', '15454618', '13235429', '15062512', '15691931']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8978336567466682
- 35 USC 102 Novelty (BERT): 0.4952795029912945
- Combined Prediction Score: 0.8575782413711308
- Mean Citation Score: 208.083246
- Max Citation Score: 260.5248
- Similarity Product: 229.6439167373657

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test