PATENT CLAIM ANALYSIS

Application Number: 15938505
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["714", "703000"]

Abstract:
In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Claim (Index 4):
The apparatus of  claim 3 , wherein the memory arrangement is a display data buffer of a display engine of the in-vehicle system.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 2.53333
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11834844', '15412763', '14740100', '15664295', '14308911']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2973693362353677
- 35 USC 102 Novelty (BERT): 0.4947734772259888
- Combined Prediction Score: 0.3171097503344298
- Mean Citation Score: 154.15168599999996
- Max Citation Score: 164.99997
- Similarity Product: 95.96247954819916

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test