PATENT CLAIM ANALYSIS

Application Number: 15925762
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189050"]

Abstract:
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Claim (Index 36):
The semiconductor device according to  claim 35 ,\n wherein the first wiring is coupled to the second wiring via the third wiring, and wherein the third wiring is arranged over the first and second wirings.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.53333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15211298', '15607599', '15841950', '14944262', '11320751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.802851779603306
- 35 USC 102 Novelty (BERT): 0.5015578936630591
- Combined Prediction Score: 0.7727223910092813
- Mean Citation Score: 213.51475
- Max Citation Score: 289.29242
- Similarity Product: 224.26471136882424

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test