PATENT CLAIM ANALYSIS

Application Number: 15986886
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "329000"]

Abstract:
Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.

Claim (Index 1):
A method for forming a vertical field effect transistor complementary metal oxide (VFET CMOS) structure, the method comprising:\n forming an n-type field effect transistor (NFET) region including one or more fins and a p-type field effect transistor (PFET) region including one or more fins in a semiconductor substrate, wherein each of the fins include a hardmask disposed on top surface thereof; forming a spacer layer on sidewalls of the fins and the hardmask; forming a first recess in the semiconductor substrate below the fins in the NFET and the PFET regions; epitaxially growing a first in-situ doped semiconductor in the first recess formed in the NFET and the PFET regions, wherein the first in-situ doped semiconductor is a p-type doped or an n-type doped semiconductor; conformally depositing a first dielectric liner layer onto the semiconductor substrate; applying a mask material onto the PFET region if the first in situ doped semiconductor is a p-type doped semiconductor or onto the NFET region if the first in situ doped semiconductor is an n-type doped semiconductor; removing the first dielectric liner layer from horizontal surfaces so as to expose a surface of the first in-situ doped semiconductor in the NFET region or the PFET region that is free of the mask material; removing the mask material; selectively removing the first epitaxial grown in-situ doped semiconductor from the NFET region or the PFET region that is free of the mask material to form a second recess; and epitaxially growing a second in-situ doped semiconductor in the second recess of the NFET region or the PFET region that is free of the mask, wherein the second in-situ doped semiconductor is an n-type doped semiconductor if the first in situ doped semiconductor is the p-type doped semiconductor or wherein the second in-situ doped semiconductor is a p-type doped semiconductor if the first in situ doped semiconductor is the n-type doped semiconductor such that the PFET region includes the p-type dopant semiconductor to define a PFET bottom source or drain (S/D) and the NFET region includes the n-type dopant semiconductor to define a NFET bottom S/D.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 93.0
- Lexical Diversity: 1.51282
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15918077', '13848203', '14750455', '15404466', '14729105']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303249560589488
- 35 USC 102 Novelty (BERT): 0.5174531418244187
- Combined Prediction Score: 0.8890377746354957
- Mean Citation Score: 323.995334
- Max Citation Score: 332.1764
- Similarity Product: 275.3904697230339

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test