PATENT CLAIM ANALYSIS

Application Number: 15950516
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-01
Patent Classification: ["345", "210000"]

Abstract:
A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.

Claim (Index 13):
The scan driver according to  claim 12 , wherein, when the i-th stage circuit is a first stage circuit,\n wherein the gate start pulse is supplied to the first input terminal, and wherein, when the i-th stage circuit is a stage circuit other than the first stage circuit, supply of the shift pulse starts from an i\u22121-th stage circuit.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 3.675
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15692609', '14456995', '13687230', '13249091', '14158709']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6761720378856451
- 35 USC 102 Novelty (BERT): 0.5282920053494609
- Combined Prediction Score: 0.6613840346320267
- Mean Citation Score: 310.9061000000001
- Max Citation Score: 329.3755
- Similarity Product: 240.65124214941247

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test