PATENT CLAIM ANALYSIS

Application Number: 15989609
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["365", "063000"]

Abstract:
A semiconductor memory apparatus includes first and second byte pads. A left-side peri-line couples the first byte pad and a first memory bank region and a right-side peri-line couples the second byte pad and a second memory bank region. A peri-repeater couples the left-side peri-line and the right-side peri-line based on a peri-strobe signal. The peri-strobe signal is generated based on byte information and memory bank selection information.

Claim (Index 22):
The semiconductor memory apparatus of  claim 19 , further comprising:\n a first bank repeater configured to couple the left-side peri-line and a first bank line based on a first bank strobe signal; and a second bank repeater configured to couple the right-side peri-line and a second bank line based on a second bank strobe signal, wherein the control circuit is configured to further generate the first and second bank strobe signals based on the byte information, the memory bank selection information, and the write information.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 93.0
- Lexical Diversity: 2.4
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12469864', '11778380', '15918536', '11701104', '14148254']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.78994056608445
- 35 USC 102 Novelty (BERT): 0.4686166538799359
- Combined Prediction Score: 0.7578081748639987
- Mean Citation Score: 191.334498
- Max Citation Score: 199.30661
- Similarity Product: 156.15805070678

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test