PATENT CLAIM ANALYSIS

Application Number: 16137561
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["710", "009000"]

Abstract:
A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes in an assignment time period. After assigning bus node addresses to the bus nodes of the serial data bus system in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.

Claim (Index 43):
A method for assigning addresses to addressable bus nodes for communication within a serial bus system comprising a bus line having a downstream end and at least first and second addressable bus nodes connecting in series to the bus line such that the second addressable bus node is arranged upstream of the first addressable bus node and zero or more additional addressable bus nodes are arranged upstream of the second addressable bus node and a bus line current coming from the second addressable bus node flows through the first addressable bus node toward the downstream end of the bus line and a respective bus line current coming from each individual of the zero or more additional addressable bus nodes arranged upstream of the second addressable bus node flows through each addressable bus node arranged downstream of the respective individual addressable bus node, wherein the method comprises the steps of:\n starting, in each addressable bus node not yet provided with an address, to source, at a start time, a respective address current up to a first predetermined value to the bus line; adjusting, in each addressable bus node not yet provided with an address, the respective address current such that a sum of the respective address current and the bus line current coming from each individual of the zero or more additional addressable bus nodes arranged upstream of the respective addressable bus node, is substantially equal to a first predetermined value; determining, in each addressable bus node not yet provided with an address, after a predetermined interval after the start time, the value of the respective adjusted address current; identifying an only one addressable bus node for which a value of a respective adjusted addressing current is substantially equal to a second predetermined value; and assigning an address to the identified only one addressable bus node.

Metadata:
- Claim Count in Document: 71.0
- Percentile: 97.0
- Lexical Diversity: 2.86792
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16137562', '16137563', '14043186', '16470585', '14763301']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6549275384134328
- 35 USC 102 Novelty (BERT): 0.5884515859673283
- Combined Prediction Score: 0.6482799431688223
- Mean Citation Score: 318.78442199999995
- Max Citation Score: 515.12213
- Similarity Product: 430.85356988449087

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test