PATENT CLAIM ANALYSIS

Application Number: 15889017
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "741000"]

Abstract:
A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Claim (Index 21):
An integrated circuit device comprising:\n an integrated circuit having electrical lands on a first surface; said integrated circuit first surface having a catalytic adhesive applied thereby forming a second surface of said catalytic adhesive above said integrated circuit first surface, said catalytic adhesive comprising catalytic particles dispersed in a resin, said catalytic particles and said resin cured such that said catalytic particles are disposed an exclusion depth below said second surface, said catalytic adhesive thereby having a lower density of catalytic particles in a region from said second surface to said exclusion depth than other regions of said catalytic adhesive; a plurality of apertures formed in said catalytic adhesive, at least one said aperture located adjacent to at least one said electrical contact of said integrated circuit; a plurality of channels formed onto said second surface, at least one said channel extending from an aperture to a terminal land on said catalytic adhesive second surface; said plurality of channels, said plurality of apertures, and at least one said integrated circuit land having exposed catalytic particles such that a conductor is formed by electroless deposition of copper which interconnects at least one said integrated circuit land, at least one said channel, and a channel terminus on said second surface.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 88.0
- Lexical Diversity: 2.08929
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15635201', '15878398', '15603326', '15240133', '09957401']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9115131359846376
- 35 USC 102 Novelty (BERT): 0.5175728866922434
- Combined Prediction Score: 0.8721191110553983
- Mean Citation Score: 267.567402
- Max Citation Score: 295.43475
- Similarity Product: 213.7133414011896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test