PATENT CLAIM ANALYSIS

Application Number: 15877219
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "316000"]

Abstract:
A three-dimensional memory device includes semiconductor devices located on a semiconductor substrate, lower interconnect level dielectric layers embedding lower interconnect structures, an alternating stack of insulating layers and electrically conductive layers overlying the lower interconnect level dielectric layers and including stepped surfaces, memory stack structures vertically extending through the alternating stack, and contact via structures extending downward from the stepped surfaces through underlying portions of the alternating stack to the lower interconnect structures. Each of the contact via structures laterally contacts an electrically conductive layer located at the stepped surfaces, and provides electrical interconnection to an underlying semiconductor device. A top portion of each contact via structures contacts an electrically conductive layer, and is electrically isolated from other underlying electrically conductive layers.

Claim (Index 12):
A method of forming a three-dimensional memory device, comprising:\n forming semiconductor devices on a semiconductor substrate; forming lower interconnect level dielectric layers embedding lower interconnect structures over the semiconductor devices, wherein the lower interconnect structures are electrically connected to the respective semiconductor devices; forming an alternating stack of insulating layers and sacrificial material layers over the lower interconnect level dielectric layers; forming stepped surfaces on the alternating stack in a word line contact region by patterning the alternating stack; forming contact via structures in the word line contact region, wherein each of the contact via structures laterally contacts a respective one of the sacrificial material layers, vertically extends through a respective opening in at least a bottommost sacrificial material layer of the alternating stack, and contacts a respective one of the lower interconnect structures that underlie the alternating stack; forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film; and replacing the sacrificial materials with electrically conductive layers.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.29825
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15489050', '15269294', '15632983', '15269041', '15638672']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9412506041624824
- 35 USC 102 Novelty (BERT): 0.5588098885262397
- Combined Prediction Score: 0.903006532598858
- Mean Citation Score: 437.393132
- Max Citation Score: 450.66562000000016
- Similarity Product: 367.60662755776167

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test