PATENT CLAIM ANALYSIS

Application Number: 15769708
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["257", "076000"]

Abstract:
A transistor comprises a stack of semiconductor materials including, in particular, a first sub-layer, carefully arranged and with a specific thickness, splitting the buffer layer into two portions and including a third material so that the difference in the piezoelectric and spontaneous polarisation coefficients between the material of the buffer layer and the third material induces, at a first interface between the first portion of the buffer layer and the first sub-layer, a first fixed surface electric charge generating an electrical field directed along the axis z so as to follow the two-dimensional gas to be contained in the channel.

Claim (Index 1):
A field-effect transistor comprising a stack along a z-axis, comprising:\n a barrier layer comprising a first semiconductor; a heterojunction between said barrier layer and a buffer layer; and a two-dimensional gas confined to a channel located in an xy-plane that lies perpendicular to the z-axis and in the vicinity of the heterojunction the buffer layer comprising a second semiconductor comprising Al x Ga (1\u2212x) N being the aluminum content of said buffer layer, wherein the stack furthermore comprises a first sublayer that divides the buffer layer into two portions and that comprises a third semiconductor comprising Al x1 Ga (1\u2212x1) N, x 1  being higher than x+15%, x 1  being the aluminum content of said sublayer, so that the difference between the piezoelectric and spontaneous polarization coefficients of the second semiconductor and the third semiconductor induces, at a first interface between the first portion of the buffer layer and the first sublayer, a first fixed surface electric charge that generates an electric field that is directed along the z-axis and that is oriented toward the first interface, so as to allow the two-dimensional gas to be confined to the channel, the distance between the heterojunction and the first interface that is located between the first portion of the buffer layer and the first sublayer being comprised between one third of the length of the gate in the direction Ox perpendicular to the direction Oz of the stack of the transistor and two times the gate length.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 1.72581
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15300712', '12159599', '12919640', '12566973', '11357752']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9187268234090876
- 35 USC 102 Novelty (BERT): 0.4946697689622309
- Combined Prediction Score: 0.8763211179644019
- Mean Citation Score: 227.069022
- Max Citation Score: 266.68857
- Similarity Product: 218.5130771827251

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test