PATENT CLAIM ANALYSIS

Application Number: 16116734
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "776000"]

Abstract:
A semiconductor package may include: a plurality of slave chips stacked over a master chip through a through silicon via (TSV); a first guard unit disposed around each of the slave chips; and a second guard unit formed at a first distance from the first guard unit and disposed at the master chip.

Claim (Index 2):
The semiconductor package according to  claim 1 , wherein the first chip and each of the second chips include through silicon vias (TSVs), and\n a TSV of the first chip and a TSV of each of the second chips having the same function are electrically coupled to each other.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 1.63889
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15462039', '14804880', '14150092', '14064110', '12941640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9286542361211756
- 35 USC 102 Novelty (BERT): 0.4973029769067024
- Combined Prediction Score: 0.8855191101997283
- Mean Citation Score: 174.901976
- Max Citation Score: 242.77931
- Similarity Product: 182.5043809645766

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test