PATENT CLAIM ANALYSIS

Application Number: 16261517
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "737000"]

Abstract:
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

Claim (Index 5):
The method for manufacturing the WLCSP structures of  claim 4 , wherein the sub-step of forming the chip array on the top surface of the substrate comprises the sub-steps of:\n providing the substrate, the substrate having a front side and a backside opposite the front side, the front side of the substrate comprising an active area; depositing a second metal layer, a passivation layer and a plurality of connection members on a top surface of the active area of the substrate, wherein the second metal layer covers the top surface of the active area of the substrate, the passivation layer covers a top surface of the second metal layer and the connection member is electrically connected to the second metal layer through openings formed on the passivation layer; thinning from the backside of the substrate; and depositing a first metal layer and the protective tape to cover a surface of a backside of the thinned substrate so as to form the chip array; wherein each of the plurality of semiconductor units comprises at least one connection member of the plurality of connection members.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 99.0
- Lexical Diversity: 2.51667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15197609', '11782384', '11951729', '14021708', '14261252']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9144034144032092
- 35 USC 102 Novelty (BERT): 0.5016973740689208
- Combined Prediction Score: 0.8731328103697805
- Mean Citation Score: 190.72019
- Max Citation Score: 266.2746
- Similarity Product: 198.9966341979504

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test