PATENT CLAIM ANALYSIS

Application Number: 15877931
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["438", "276000"]

Abstract:
A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

Claim (Index 12):
A method for providing a semiconductor device comprising:\n providing an undoped silicon fin for each of a plurality of CMOS devices in a first region and a second region, the first region corresponding to a plurality of n-FET devices, the second region corresponding to a plurality of p-FET devices; providing a dummy gate and a spacer on the undoped fin for each of the plurality of CMOS devices; covering the first region with a hard mask if the p-FET devices are to be formed; covering the second region with the hard mask if the n-FET devices are to be formed; cleaning a region exposed by the hard mask; providing a doped Si layer on the undoped Si fin, a dopant for the doped semiconductor layer being selected from a p-type dopant and an n-type dopant, the p-type dopant being selected if the p-FET devices are to be formed, the n-type dopant being selected if the n-FET devices are to be formed; performing an ultraviolet-assisted low temperature (UVLT) anneal of the doped Si layer in an ambient, the ambient being selected from an oxidizing ambient and a nitriding ambient, the oxidizing ambient being used if the n-FET devices are being formed, the nitriding ambient being used if the p-FET devices are being formed, a sacrificial layer being formed by the doped Si layer during the UVLT anneal and the dopant being driven into the at least the portion of the undoped Si fin from the doped Si layer by the UVLT anneal to from a doped Si fin, the sacrificial layer being a nitride layer if the nitriding ambient is used, the sacrificial layer being an oxide if the oxidizing ambient is used; and removing the sacrificial layer.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.80357
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14954166', '15040278', '15215921', '15809122', '14226488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8427425526065229
- 35 USC 102 Novelty (BERT): 0.5121885930203798
- Combined Prediction Score: 0.8096871566479086
- Mean Citation Score: 251.72877000000005
- Max Citation Score: 257.39532
- Similarity Product: 172.9951356979609

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test