PATENT CLAIM ANALYSIS

Application Number: 15921032
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "292000"]

Abstract:
A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Claim (Index 16):
A semiconductor device structure, comprising:\n a first semiconductor die having a first interlayer dielectric layer, a first conductive line in the first interlayer dielectric layer, and a first barrier layer between the first interlayer dielectric layer and the first conductive line; a second semiconductor die stacked on the first semiconductor die having a second interlayer dielectric layer, a second conductive line in the second interlayer dielectric layer, and a second barrier layer between the second interlayer dielectric layer and the second conductive line; a passivation layer between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to at least one of the first interlayer dielectric layer and the second interlayer dielectric layer; a conductive feature passing through the passivation layer, wherein the conductive feature is bonded to the first conductive line; and a third barrier layer between the conductive feature and the passivation layer, wherein the third barrier layer covers sidewalls of the conductive feature and is in direct contact with one of the first conductive line and the second conductive line; wherein the third barrier layer covers a surface of the conductive feature not directly bonded to one of the first conductive line and the second conductive line, the third barrier layer separating the surface of the conductive feature from a nearest neighboring surface of the first semiconductor die or the second semiconductor die.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 3.25581
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14919378', '15865845', '15651834', '15894324', '15016886']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9156343611112184
- 35 USC 102 Novelty (BERT): 0.4722540296486866
- Combined Prediction Score: 0.8712963279649654
- Mean Citation Score: 202.737478
- Max Citation Score: 215.19772000000003
- Similarity Product: 184.67333551348213

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test