PATENT CLAIM ANALYSIS

Application Number: 15866309
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "059000"]

Abstract:
A transistor array panel according to an exemplary embodiment includes a substrate, and a first transistor and a second transistor positioned on the substrate. Each of the first transistor and the second transistor includes: a first electrode; a second electrode overlapping the first electrode; a spacing member positioned between the first electrode and the second electrode; a semiconductor layer extending along a side wall of the spacing member; and a gate electrode overlapping the semiconductor layer. A thickness of the spacing member of the first transistor is larger than a thickness of the spacing member of the second transistor.

Claim (Index 13):
The method of  claim 12 , wherein:\n the spacing member of the first transistor includes a first insulator formed from the first insulating layer, a floating electrode formed from the second conductive layer, and a second insulator formed from the second insulating layer; and the spacing member of the second transistor includes a first insulator formed from the first insulating layer.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 2.7
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15344084', '12472979', '14184361', '14468472', '12753615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9292288649047296
- 35 USC 102 Novelty (BERT): 0.5114877344096431
- Combined Prediction Score: 0.8874547518552209
- Mean Citation Score: 252.310594
- Max Citation Score: 257.46878
- Similarity Product: 159.98539071155784

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test