PATENT CLAIM ANALYSIS

Application Number: 15862397
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "185130"]

Abstract:
A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

Claim (Index 7):
A method for reading a memory cell of a non-volatile memory device provided with a memory array with memory cells arranged in wordlines and bitlines, the bitlines including a first bitline associated with the memory cell to be read and a second bitline distinct from the first bitline, the method comprising:\n pre-charging a first dividing capacitor and a second dividing capacitor to a pre-charging voltage, the first dividing capacitor coupled to a local node of a first circuit branch associated with the first bitline, the second dividing capacitor coupled to a global node of the first circuit branch, the global node of the first circuit branch being coupled to the local node of the first circuit branch by a first local decoding transistor; pre-charging a third dividing capacitor and a fourth dividing capacitor to the pre-charging voltage, the third dividing capacitor coupled to a local node of a second circuit branch associated with the second bitline, the fourth dividing capacitor coupled to a global node of the second circuit branch, the global node of the second circuit branch being coupled to the local node of the second circuit branch by a second local decoding transistor; equalizing, using a first coupling transistor coupled between the global node of the first circuit branch and the global node of the second circuit branch, the global nodes to a common initial voltage; decoupling the local node of the first circuit branch from the global node of the first circuit branch by deactivating the first local decoding transistor; coupling the local node of the first circuit branch to the global node of the first circuit branch by activating the first local decoding transistor; and generating an output signal based upon a comparison between a first comparison voltage that is a function of a voltage of the global node of the first circuit branch, and a second comparison voltage that is a function of a voltage of the global node of the second circuit branch.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 2.72414
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15275362', '15212211', '13746653', '15475609', '12883072']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7953395061952928
- 35 USC 102 Novelty (BERT): 0.5279759852767174
- Combined Prediction Score: 0.7686031541034353
- Mean Citation Score: 253.401934
- Max Citation Score: 376.0495
- Similarity Product: 349.27607068014146

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test