PATENT CLAIM ANALYSIS

Application Number: 16193702
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["313", "506000"]

Abstract:
A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planarization dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap.

Claim (Index 37):
A method of fabricating a pixel, the pixel having an organic light emitting diode (OLED) bottom electrode, one or more OLED layers on the OLED bottom electrode, a transparent top electrode, and a thin-film transistor (TFT) based backplane for electrically driving the OLED and including a substrate, the method comprising the steps of:\n providing the TFT based backplane on said substrate, including forming within the TFT based backplane a thin conductive electrode at least partially on a flat portion of the pixel area and electrically coupled to a source or drain node of the TFT based backplane, the thin conductive electrode defined by a top surface, a bottom surface, and side surfaces, its thickness defined by normal distances between the top and bottom surfaces substantially smaller than its horizontal dimensions defined by the side surfaces; providing a dielectric layer on the TFT based backplane, including the step of planarizing a vertical profile in the dielectric layer so as to planarize the vertical profile on the substrate with the TFT based backplane, said planarized dielectric layer being in direct contact with said TFT based backplane; forming a via in said planarization dielectric layer to provide a communication path between said TFT based backplane and said OLED device and through said thin conductive electrode; depositing said OLED bottom electrode directly on top of said planarized dielectric layer and extending through said via into direct contact with said thin conductive electrode of said TFT based backplane; and depositing a dielectric layer on top of said bottom electrode and covering said via and all the edges of said bottom electrode while leaving the rest of said bottom electrode uncovered.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.59615
- Patent Class: 313.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15403313', '10546695', '15121037', '15968763', '14644040']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.706753151542994
- 35 USC 102 Novelty (BERT): 0.5352652251164646
- Combined Prediction Score: 0.6896043589003411
- Mean Citation Score: 288.897326
- Max Citation Score: 390.6782
- Similarity Product: 381.4440899513722

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test