PATENT CLAIM ANALYSIS

Application Number: 15899995
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "043000"]

Abstract:
This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the active layers. In one or more embodiments, an apparatus is provided that comprises a first transistor comprising a silicon active layer, and a second transistor comprising a metal oxide active layer. The second transistor is vertically stacked on the first transistor, and the first transistor and the second transistor share a gate electrode formed between the silicon active layer and the metal oxide active layer. With these embodiments, the gate electrode corresponds to a top gate of the first transistor and a bottom gate of the second transistor.

Claim (Index 18):
The apparatus of  claim 14 , wherein the second transistor comprises a metal oxide (MO) thin-film transistor (TFT).

Metadata:
- Claim Count in Document: 14.0
- Percentile: 88.0
- Lexical Diversity: 2.0678
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14588193', '14588180', '14588205', '14915848', '14739799']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9247706006348008
- 35 USC 102 Novelty (BERT): 0.4956045763393981
- Combined Prediction Score: 0.8818539982052606
- Mean Citation Score: 217.64919
- Max Citation Score: 223.57059
- Similarity Product: 157.04407762200594

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test