PATENT CLAIM ANALYSIS

Application Number: 15912594
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["326", "038000"]

Abstract:
A semiconductor integrated circuit according to an embodiment includes: a first memory bank that performing a read operation and outputting first data in accordance with a first clock signal; a second memory bank performing a read operation and outputting second data in accordance with the first clock signal; a configurable decoder supplying address information to the first and second memory banks; and an output module reconfigurable in one of a first and second modes, the first mode including a function of holding the first and second data in accordance with the first clock signal, and selecting and outputting the first data or the second data in accordance with a second clock signal having a frequency at least twice higher than the first clock signal, the second mode including a function of selecting and outputting the first data or the second data in accordance with the first clock signal.

Claim (Index 7):
A semiconductor integrated circuit comprising:\n a configurable logic block; a configurable memory block; and a configurable interconnect block that connects the configurable logic block and the configurable memory block to each other, wherein the configurable memory block includes: a first memory bank that performs a read operation in accordance with a first clock signal, and outputs first data in accordance with the first clock signal; a second memory bank that performs a read operation in accordance with the first clock signal, and outputs second data in accordance with the first clock signal; a configurable decoder that supplies address information to the first memory bank and the second memory bank; and an output module reconfigurable in a first mode and a second mode, the first mode including a function of holding the first data and the second data in accordance with the first clock signal, and selecting and outputting the first data or the second data in accordance with a second clock signal having a frequency at least twice higher than the first clock signal, the second mode including at least a function of selecting and outputting the first data or the second data in accordance with the first clock signal.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.78571
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14530576', '10189839', '14180664', '11880141', '15421090']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6553434700906042
- 35 USC 102 Novelty (BERT): 0.4676183494089432
- Combined Prediction Score: 0.6365709580224382
- Mean Citation Score: 176.87999200000004
- Max Citation Score: 196.31085
- Similarity Product: 156.18000894450543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test