PATENT CLAIM ANALYSIS

Application Number: 15862241
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["710", "106000"]

Abstract:
A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Claim (Index 6):
A memory device comprising:\n a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a double command generation unit suitable for generating a double column command signal which is activated twice in response to a column command signal, generating a double read command signal which is activated twice in response to a read command signal, and generating a double write command signal which is activated twice in response to a write command signal; a toggle signal generation unit suitable for generating a first signal which toggles in response to the double column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting the double read command signal or double write command signal activated for the first time to the first bus when the first signal is activated, and transmitting the double read command signal or double write command signal activated for the second time to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more first column address signals corresponding to the read command signal or write command signal to the first bus, and transmitting one or more second column address signals to the second bus, the one or more second column address signals being generated through the one or more first column address signals.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 3.01786
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15395598', '14926834', '14303230', '15149989', '14696030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7030199816872049
- 35 USC 102 Novelty (BERT): 0.5708365087098809
- Combined Prediction Score: 0.6898016343894725
- Mean Citation Score: 327.047572
- Max Citation Score: 470.20425
- Similarity Product: 431.3960970034897

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test