PATENT CLAIM ANALYSIS

Application Number: 15975254
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["710", "260000"]

Abstract:
A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Claim (Index 18):
A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by a storage system comprising at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory, causes the storage system:\n to generate in the input-output controller a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts; if an address of a given one of the write commands falls within a specified data group window, to write the data to the processor memory and to copy the write command to the directly-addressable storage device so as to cause the data to also be written to the volatile memory of that storage device; if the address of the given write command does not fall within the specified data group window and does not fall within a specified interrupt group window, to write the data to the processor memory without copying the write command to the directly-addressable storage device; and if the address of the given write command falls within the specified interrupt group window, to copy the write command to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device; wherein the directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.36923
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15198404', '15223479', '15956309', '14272214', '15086782']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6778530055517026
- 35 USC 102 Novelty (BERT): 0.5341732674442111
- Combined Prediction Score: 0.6634850317409534
- Mean Citation Score: 225.948478
- Max Citation Score: 377.20697
- Similarity Product: 370.4863331642168

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test