PATENT CLAIM ANALYSIS

Application Number: 15947992
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["365", "201000"]

Abstract:
A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.

Claim (Index 11):
The semiconductor device according to  claim 10 ,\n wherein the first input/output circuit comprises: a first write circuit to output a write signal corresponding to write data to the first memory cell according to a write control signal, wherein the second input/output circuit comprises: a second write circuit to output a write signal corresponding to write data to the second memory cell according to the write control signal, wherein the selection circuit comprises: a first selector to output one of first mask data and the test address and to control the activation/non-activation of the first write circuit; and a second selector to output one of second mask data and the inverted data of the test address and to control the activation/non-activation of the second write circuit, and wherein, in the test mode, the first selector and the second selector output the test address and the inverted data of the test address to the first write circuit and the second write circuit, respectively.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.67797
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['09691115', '10829949', '09793612', '10229035', '11165273']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8181072124108594
- 35 USC 102 Novelty (BERT): 0.4916068464752581
- Combined Prediction Score: 0.7854571758172992
- Mean Citation Score: 230.983572
- Max Citation Score: 244.99893
- Similarity Product: 177.2312905708444

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test