PATENT CLAIM ANALYSIS

Application Number: 15887058
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a substrate; and forming a first source/drain region in the semiconductor material layer. The method may continue with forming a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region that is substantially perpendicular to the vertically orientated channel region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region. Thereafter, a gate structure is formed on the vertically orientated channel region, and a second source/drain region is formed on the vertically orientated channel region.

Claim (Index 6):
The vertical transistor of  claim 1 , wherein the metal semiconductor alloy has a thickness ranging from about 2 nm to about 50 nm.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.46
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15418097', '15157012', '15819398', '15462340', '15183034']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.933767741867178
- 35 USC 102 Novelty (BERT): 0.5404083100263717
- Combined Prediction Score: 0.8944317986830974
- Mean Citation Score: 311.647286
- Max Citation Score: 391.94843
- Similarity Product: 275.12381373768864

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test