PATENT CLAIM ANALYSIS

Application Number: 15895837
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["375", "362000"]

Abstract:
A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

Claim (Index 17):
A data transmission circuit comprising:\n a pipe latch circuit configured to output first to fourth data by arranging a plurality of internal data groups; a pre-buffer stage configured to generate first to fourth delayed data by buffering the first to fourth data in synchronization with first to fourth clock signals, respectively; and a main buffer stage configured to generate an output data by buffering the first to fourth delayed data in synchronization with the first to fourth clock signals, respectively.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 88.0
- Lexical Diversity: 2.51351
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15855567', '11850754', '12165171', '14882942', '15366345']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4752208199117275
- 35 USC 102 Novelty (BERT): 0.4844863606636753
- Combined Prediction Score: 0.4761473739869222
- Mean Citation Score: 196.609306
- Max Citation Score: 216.4241
- Similarity Product: 164.06647335271836

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test