PATENT CLAIM ANALYSIS

Application Number: 15954300
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "192000"]

Abstract:
Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×10 20  at./cm 3 . Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

Claim (Index 14):
The device of  claim 13 , wherein the crystalline gallium-doped layer comprises gallium (Ga) and boron (B) doped silicon germanium (SiGe) (SiGe y :Ga:B).

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.97015
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15004756', '15004751', '14245683', '14556638', '15894208']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.933765035554602
- 35 USC 102 Novelty (BERT): 0.5701694740002161
- Combined Prediction Score: 0.8974054793991634
- Mean Citation Score: 321.27289399999995
- Max Citation Score: 501.6634
- Similarity Product: 355.11005223058464

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test