PATENT CLAIM ANALYSIS

Application Number: 16230454
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "288000"]

Abstract:
A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Claim (Index 14):
The electronic system of  claim 11 , wherein the gate comprises a gate electrode, a gate dielectric layer, and a hard mask, wherein the gate dielectric layer disposed between the gate electrode and the microelectronic substrate, wherein the hard mask is on the gate electrode, and wherein the airgap spacer is defined by the microelectronic substrate, the interlayer dielectric, the gate dielectric layer, the gate electrode, and the hard mask.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 98.0
- Lexical Diversity: 1.84314
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15743847', '13992542', '14916093', '13996850', '14618414']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913870363198716
- 35 USC 102 Novelty (BERT): 0.507764947641313
- Combined Prediction Score: 0.8732598216429758
- Mean Citation Score: 191.525358
- Max Citation Score: 264.1654
- Similarity Product: 184.18849290665383

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test