PATENT CLAIM ANALYSIS

Application Number: 15890001
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["438", "157000"]

Abstract:
An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Claim (Index 20):
A method of fabricating an integrated circuit having first and second finFET transistors therein, the method comprising:\n forming, overlaying a semiconductor substrate, a first epitaxial fin; forming an insulating layer overlaying the first epitaxial fin; forming, at least partially overlaying and overlapping the insulating layer, a second epitaxial fin; forming source and drain regions for the first finFET transistor that extend through the insulating layer till a bottom surface of the first epitaxial fin; implanting the source and drain regions for the first finFET transistor and two end portions of the second epitaxial fin as source and drain regions for the second finFET transistor; forming a first recessed metal gate of the first finFET transistor over the first epitaxial fin and adjacent to a first side of the second epitaxial fin and a second recessed metal gate of the first finFET transistor over the first epitaxial fin and adjacent to a second side of the second epitaxial fin, and a recessed metal gate of the second finFET transistor over the second epitaxial fin.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 88.0
- Lexical Diversity: 1.74713
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15238559', '14788341', '10755763', '14024415', '14587872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8712076069707845
- 35 USC 102 Novelty (BERT): 0.5328362004477102
- Combined Prediction Score: 0.8373704663184771
- Mean Citation Score: 297.580736
- Max Citation Score: 370.87787
- Similarity Product: 314.8135609612352

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test