PATENT CLAIM ANALYSIS

Application Number: 15987208
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["327", "117000"]

Abstract:
A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.

Claim (Index 4):
The method of  claim 3 , wherein generating the first signal comprises generating a count based on a modulo set by the current divider ratio and initiated by the fourth signal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.47541
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15453712', '14472431', '11777779', '10690874', '10986994']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7873383315042747
- 35 USC 102 Novelty (BERT): 0.5616843801898602
- Combined Prediction Score: 0.7647729363728333
- Mean Citation Score: 259.26401400000003
- Max Citation Score: 482.8365
- Similarity Product: 338.501413161993

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test