PATENT CLAIM ANALYSIS

Application Number: 15917037
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "185020"]

Abstract:
A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.

Claim (Index 9):
The memory device of  claim 2 , wherein the second voltage level is different from the fifth voltage level that is higher than the threshold voltage.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 3.26531
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12583811', '12797994', '12590701', '14924523', '13962261']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8245659606800575
- 35 USC 102 Novelty (BERT): 0.4960231918743695
- Combined Prediction Score: 0.7917116837994888
- Mean Citation Score: 249.957514
- Max Citation Score: 256.99567
- Similarity Product: 182.16011324715487

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test