PATENT CLAIM ANALYSIS

Application Number: 16118953
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["438", "268000"]

Abstract:
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Claim (Index 9):
The method of  claim 1 , wherein:\n each of the plurality of vertical fin structures comprises a wide first portion, a narrow second portion, and a wide third portion; and the forming of the source and drain contacts comprises subjecting the first portion and third portion to a silicide process followed by the deposition of the metal material in an opening of a dielectric material.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 96.0
- Lexical Diversity: 1.68571
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15296577', '14965988', '14560672', '14965985', '15452818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8768629033614653
- 35 USC 102 Novelty (BERT): 0.4888567462810245
- Combined Prediction Score: 0.8380622876534213
- Mean Citation Score: 256.88817000000006
- Max Citation Score: 261.20688
- Similarity Product: 237.1068114657784

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test