PATENT CLAIM ANALYSIS

Application Number: 16041222
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "487000"]

Abstract:
A semiconductor device includes a substrate of a first conductivity type with relatively low impurity concentration; a first region of a second conductivity type with relatively low impurity concentration, =located in the substrate; a second region of the first conductivity type with relatively high impurity concentration, located in the substrate; first and second conductors, located on the first region and separated from each other by an isolator layer; and a third conductor, separated from the first and second conductors by the isolator layer, and located on the second region. The first conductor provides a drain terminal. The second conductor provides a source terminal. The third conductor provides a gate terminal.

Claim (Index 15):
The dual JFET semiconductor device of  claim 1 , wherein the second JFET further comprises a buried region of the second conductivity type, located between the substrate and the first region of the second JFET.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 95.0
- Lexical Diversity: 2.79545
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14845939', '14942527', '15952845', '15337748', '15369054']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9255532034773132
- 35 USC 102 Novelty (BERT): 0.4776929795672906
- Combined Prediction Score: 0.8807671810863108
- Mean Citation Score: 206.78174
- Max Citation Score: 213.65376
- Similarity Product: 176.48119688621517

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test