PATENT CLAIM ANALYSIS

Application Number: 15912405
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["711", "207000"]

Abstract:
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Claim (Index 1):
A system comprising:\n a system memory to store instructions and data; a processor comprising: a plurality of cores to execute multiple threads; an instruction fetch circuit to fetch instructions of the threads from a memory subsystem; a decoder to decode the instructions; virtualization circuitry to implement a virtualization environment comprising one or more guests and a virtual machine monitor (VMM) to manage the guests; memory management circuitry to translate guest virtual addresses to guest physical addresses using a first set of page tables and to translate the guest physical addresses to host physical addresses using a second set of page tables; a translation lookaside buffer (TLB) to cache address translation entries, including at least one entry with an address from the first set of page tables and at least one entry with an address from the second set of page tables; and execution circuitry to execute a first TLB management instruction having an operand associated with a contiguous region in host physical memory, the execution circuitry to invalidate only those TLB entries associated with the contiguous region.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 2.02632
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14675325', '15620663', '14867024', '14867018', '14675292']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5750632938728973
- 35 USC 102 Novelty (BERT): 0.5202280012429972
- Combined Prediction Score: 0.5695797646099073
- Mean Citation Score: 340.357226
- Max Citation Score: 342.1339
- Similarity Product: 286.0939574244857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test