PATENT CLAIM ANALYSIS

Application Number: 15923174
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["711", "129000"]

Abstract:
In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

Claim (Index 9):
The processor of  claim 8 , wherein the control circuit is to dynamically update a size of the virtual write buffer based on hit histogram information obtained from at least one of the first set of hit counters and the second set of hit counters.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 90.0
- Lexical Diversity: 1.81633
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13942291', '15701795', '14671411', '14137359', '15476816']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5311751997227208
- 35 USC 102 Novelty (BERT): 0.4965357638068982
- Combined Prediction Score: 0.5277112561311386
- Mean Citation Score: 178.78918000000004
- Max Citation Score: 185.46117
- Similarity Product: 113.52776945949913

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test