PATENT CLAIM ANALYSIS

Application Number: 15976706
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "180000"]

Abstract:
This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

Claim (Index 1):
A method of operating an array of thyristor memory cells, each thyristor memory cell having an anode, a cathode, first and second base regions, the array having a plurality of first lines in a first direction, each first line connected to the anodes or cathodes of a plurality of thyristor memory cells aligned in the first direction, a plurality of second lines in a second direction perpendicular to the first direction, each second line connected to the cathodes or anodes of a plurality of thyristor memory cells aligned in the second direction, a plurality of third lines in the first direction, each third line capacitively coupled to one of base regions of thyristor memory cells aligned in the first direction, the method comprising:\n in a standby mode, holding the plurality of first lines at a first voltage and holding the plurality of second lines at a second voltage, the difference in voltage between the first and second voltages sufficient to maintain ON thyristor memory cells in that state but insufficient to turn on OFF thyristor memory cells; and for a write operation engaging one or more thyristor memory cells by a selected first line and one or more selected second lines, driving a subset of first lines connected to thyristor memory cells which are adjacent to the thyristor memory cells connected to the selected first line to a third voltage, the third voltage creating a greater difference with respect to the second voltage than the first voltage so that ON thyristor memory cells connected to the subset of first lines are undisturbed by the write operation.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 93.0
- Lexical Diversity: 1.51111
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14590834', '14740186', '14607023', '15216652', '14740209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7764688837174698
- 35 USC 102 Novelty (BERT): 0.5003659265896331
- Combined Prediction Score: 0.7488585880046862
- Mean Citation Score: 255.32215399999995
- Max Citation Score: 272.45346
- Similarity Product: 209.35377823085548

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test