PATENT CLAIM ANALYSIS

Application Number: 15910725
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "048000"]

Abstract:
A semiconductor package includes a board, a plurality of semiconductor memory chips, a controller chip, and a sealing resin portion. The plurality of semiconductor memory chips are stacked in a thickness direction of the board. The controller chip is disposed between the board and the plurality of semiconductor memory chips or on a side of the plurality of semiconductor chips opposite to the board. The sealing resin portion seals the plurality of semiconductor memory chips and the controller chip. The plurality of semiconductor memory chips include at least one through via that penetrates one or more semiconductor memory chips of the plurality of semiconductor memory chips in the thickness direction of the board to be connected to the controller chip.

Claim (Index 2):
The semiconductor package according to  claim 1 , wherein the plurality of semiconductor memory chips include a first semiconductor memory chip, the at least one through via includes a first through via electrically connected to the first semiconductor memory chip, and the controller chip communicates with the first semiconductor memory chip via the first through via.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 90.0
- Lexical Diversity: 2.84444
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12712284', '12558814', '13613983', '13693458', '13798800']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9224901623068754
- 35 USC 102 Novelty (BERT): 0.4770268411324325
- Combined Prediction Score: 0.8779438301894312
- Mean Citation Score: 163.84733
- Max Citation Score: 169.12292
- Similarity Product: 123.33986746268508

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test