PATENT CLAIM ANALYSIS

Application Number: 15941716
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["257", "347000"]

Abstract:
A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Claim (Index 2):
The method of  claim 1 , wherein the first via and the second via have the same area in a plan view.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.82222
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15493847', '15707634', '14805415', '15063544', '15940329']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9121060124379436
- 35 USC 102 Novelty (BERT): 0.5070680265148474
- Combined Prediction Score: 0.871602213845634
- Mean Citation Score: 145.908296
- Max Citation Score: 147.62833999999995
- Similarity Product: 77.29345336387989

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test