PATENT CLAIM ANALYSIS

Application Number: 15897811
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "063000"]

Abstract:
According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Claim (Index 11):
The semiconductor memory device according to  claim 10 , wherein\n the second bit line is adjacent to the first bit line and the third bit line in the second direction.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.6
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15331026', '15007880', '15388691', '13524750', '14307196']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8348543346579397
- 35 USC 102 Novelty (BERT): 0.4997762634818313
- Combined Prediction Score: 0.8013465275403289
- Mean Citation Score: 284.076744
- Max Citation Score: 295.45004
- Similarity Product: 241.1229768269968

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test