PATENT CLAIM ANALYSIS

Application Number: 15945578
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "401000"]

Abstract:
Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Claim (Index 18):
The semiconductor device according to  claim 16 , the semiconductor device further comprising a set of fins, wherein the S/D contacts are formed atop the set of fins.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 3.11321
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14282089', '14261823', '14949481', '14258488', '13894513']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.928407979582536
- 35 USC 102 Novelty (BERT): 0.5420814781391222
- Combined Prediction Score: 0.8897753294381946
- Mean Citation Score: 326.11507
- Max Citation Score: 412.6339
- Similarity Product: 271.3885298983872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test