PATENT CLAIM ANALYSIS

Application Number: 16141971
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["710", "003000"]

Abstract:
A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

Claim (Index 2):
The method of  claim 1  further comprising;\n providing a random signal on an input of a multiplexer; \n selecting the random signal using a select input to the multiplexer; and \n providing the random signal from the multiplexer to the translation table to randomly select an entry of a translation control entry table during the test mode.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 1.88571
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15675717', '15849597', '14841826', '14798549', '12114945']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7021454812935666
- 35 USC 102 Novelty (BERT): 0.557098070388059
- Combined Prediction Score: 0.6876407402030158
- Mean Citation Score: 283.0904440000001
- Max Citation Score: 428.73654000000016
- Similarity Product: 425.8724982113922

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test