PATENT CLAIM ANALYSIS

Application Number: 15869724
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["345", "213000"]

Abstract:
A display device includes a plurality of pulse output circuits each of which outputs signals to one of the two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs, to the other of the two kinds of scan lines, inverted or substantially inverted signals of the signals output from the pulse output circuits. Each of the plurality of inverted pulse output circuits operates with at least two kinds of signals used for the operation of the plurality of pulse output circuits. Thus, through current generated in the inverted pulse output circuits can be reduced.

Claim (Index 2):
A display device comprising:\n a driver circuit comprising a first circuit, a second circuit, and first to fourth transistors; and a pixel comprising an EL element and fifth to seventh transistors, wherein the first circuit is configured to output a first signal to the second circuit, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is electrically connected to a first wiring, wherein the first wiring is configured to output a first clock signal, wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, wherein a potential of the gate of the second transistor is controlled in accordance with the first signal, wherein the fifth transistor is configured to supply current to the EL element, wherein the sixth transistor is configured to control input of an image signal to the pixel, wherein the fifth transistor and the seventh transistor are electrically connected to each other in series between a power supply line and the EL element, and wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the third transistor.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.37778
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13687744', '13937559', '15203885', '14831939', '14245097']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6676001401928664
- 35 USC 102 Novelty (BERT): 0.5024195843121093
- Combined Prediction Score: 0.6510820846047907
- Mean Citation Score: 260.62538600000005
- Max Citation Score: 302.94638
- Similarity Product: 273.3528163004875

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test