PATENT CLAIM ANALYSIS

Application Number: 15992210
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["257", "678000"]

Abstract:
Semiconductor structures and methods of forming the same are disclosed. The semiconductor structure includes a first die, a second die, a first encapsulating material and a protection layer. The first die includes a first substrate. The second die is bonded to the first die and includes a second substrate. The first encapsulating material encapsulates the first die. The protection layer is disposed on a sidewall of the first substrate and between the first substrate and the first encapsulating material, wherein a material of the protection layer is different from materials of the second substrate and the first encapsulating material.

Claim (Index 18):
The method according to  claim 15 , wherein the first die is disposed between the second die and the carrier, and the planarization process and the thinning process are simultaneously performed on surfaces of the second substrate of the second die and the encapsulating material by the etching process.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 93.0
- Lexical Diversity: 2.91892
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15980541', '14919378', '15169857', '15707237', '14304331']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918656096248144
- 35 USC 102 Novelty (BERT): 0.4788450345946212
- Combined Prediction Score: 0.8746749900827918
- Mean Citation Score: 157.581926
- Max Citation Score: 174.97281999999996
- Similarity Product: 127.57628962704418

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test