PATENT CLAIM ANALYSIS

Application Number: 15874371
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["714", "734000"]

Abstract:
Detection circuit, detection method, and electronic system for detecting an I/O output status are provided. The detection circuit includes a comparison-window generating circuit configured to: detect an I/O data signal, generate a first single pulse signal, determining a first-time window, in response to a rising edge of the I/O data signal, and generate a second single pulse signal, determining a second-time window, in response to a falling edge of the I/O data signal. A first comparison circuit is configured to: receive the first single pulse signal, and compare the I/O drive signal with a preset high-level reference signal within the first time window to obtain a first comparison result. The second comparison circuit is configured to: receive the second single pulse signal, and compare the I/O drive signal with a preset low-level reference signal within the second time window to obtain a second comparison result.

Claim (Index 6):
The detection circuit according to  claim 5 , wherein the second delay chain circuit comprises even-numbered cascaded inverters.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.74576
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12042068', '12213809', '14326501', '15011653', '15632129']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3048962881968513
- 35 USC 102 Novelty (BERT): 0.4850312124123456
- Combined Prediction Score: 0.3229097806184007
- Mean Citation Score: 163.950534
- Max Citation Score: 173.93028
- Similarity Product: 113.78493303515911

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test