PATENT CLAIM ANALYSIS

Application Number: 16047042
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "009000"]

Abstract:
A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

Claim (Index 16):
The method of  claim 12 , wherein the first cavity is partially defined by the sacrificial spacer, the first nanowire, and the second nanowire, wherein the second cavity is partially defined by the spacer and the second nanowire.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15008615', '15368089', '15339665', '15055830', '15257232']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9385732227566448
- 35 USC 102 Novelty (BERT): 0.5755532442944603
- Combined Prediction Score: 0.9022712249104264
- Mean Citation Score: 447.11535
- Max Citation Score: 491.7819
- Similarity Product: 363.81217705530526

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test