PATENT CLAIM ANALYSIS

Application Number: 15872610
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "394000"]

Abstract:
Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.

Claim (Index 1):
A semiconductor structure comprising:\n a plurality of stacked and suspended semiconductor channel material nanosheets located above a semiconductor substrate that is composed of a semiconductor material of a first conductivity type, wherein the semiconductor substrate includes a lower region having a first dopant concentration, a middle region having a second dopant concentration and an upper region having a third dopant concentration, wherein the second dopant concentration is less than the first and third dopant concentrations; a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets; a counter doped semiconductor layer composed of a semiconductor material of a second conductivity type that is different from the first conductivity type and located on a recessed surface of the semiconductor substrate; and a source/drain (S/D) region on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets, wherein the source/drain (S/D) region is located directly on a surface of the counter doped semiconductor layer.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 86.0
- Lexical Diversity: 1.90476
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15727310', '15834380', '15802067', '15005665', '15802021']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9411797453506804
- 35 USC 102 Novelty (BERT): 0.5636319748156591
- Combined Prediction Score: 0.9034249682971784
- Mean Citation Score: 433.26454
- Max Citation Score: 465.0944
- Similarity Product: 376.9571935379028

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test