PATENT CLAIM ANALYSIS

Application Number: 16151410
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["375", "351000"]

Abstract:
One example includes a communication system. The system includes a data transmitter configured to generate a digital communication signal and a data receiver configured to receive the digital communication signal. The system also includes a pulse-width distortion (PWD) correction circuit arranged between the data transmitter and the data receiver and being configured to adjust at least one timing parameter associated with the communication signal.

Claim (Index 3):
The circuit of  claim 2 , wherein the inverter stage comprises a delay transistor interconnecting one transistor of an inverting transistor pair and a respective one of a high-voltage rail and a low-voltage rail, the delay transistor being controlled by the comparison signal to delay a respective one of a rising-edge and a falling-edge of the buffered digital communication signal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 97.0
- Lexical Diversity: 1.81579
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15483408', '15899658', '13858789', '14415642', '15806901']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4500739840104174
- 35 USC 102 Novelty (BERT): 0.4995296417528972
- Combined Prediction Score: 0.4550195497846654
- Mean Citation Score: 194.265612
- Max Citation Score: 284.71594
- Similarity Product: 256.4222228656673

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test