PATENT CLAIM ANALYSIS

Application Number: 15996841
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["257", "433000"]

Abstract:
A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.

Claim (Index 12):
The manufacturing method of the chip package of  claim 11 , further comprising:\n forming a conductive structure on the portion of the redistribution layer.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 94.0
- Lexical Diversity: 3.7907
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15008241', '15848600', '14931633', '15138119', '15364160']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926628658626924
- 35 USC 102 Novelty (BERT): 0.5157885659294963
- Combined Prediction Score: 0.8855446493571811
- Mean Citation Score: 294.4837040000001
- Max Citation Score: 318.50873
- Similarity Product: 241.2753536465717

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test