PATENT CLAIM ANALYSIS

Application Number: 15915042
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "296000"]

Abstract:
A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.

Claim (Index 17):
The fabricating method of a semiconductor structure with a contact plug of  claim 11 , wherein a material of the first dielectric layers is different from a material of the second dielectric layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 2.88636
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11448200', '10722935', '14738421', '11284237', '13297276']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9244348047684916
- 35 USC 102 Novelty (BERT): 0.4957847460416099
- Combined Prediction Score: 0.8815697988958036
- Mean Citation Score: 213.778936
- Max Citation Score: 216.52711
- Similarity Product: 148.35871773088573

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test