PATENT CLAIM ANALYSIS

Application Number: 16049693
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "193000"]

Abstract:
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Claim (Index 30):
A double data rate (DDR) memory controller, comprising:\n DDR memory controller circuitry configured to be communicatively coupled to DDR memory, the DDR memory controller circuitry configured to:\n receive, utilizing a first core domain register that is communicatively coupled to a second core domain register, a data bit input signal; \n clock the first core domain register utilizing a first clock; \n clock the second core domain register utilizing a second clock; \n receive a data strobe (DQS) signal, or a signal derived from the DQS signal; \n generate a delayed DQS signal, utilizing a DQS delay element that is responsive to the DQS signal or the signal derived from the DQS signal; \n based on the delayed DQS signal or a clock signal derived from the delayed DQS signal, clock a DQ read register that is responsive to the data bit input signal or a signal derived from the data bit input signal; and \n during a power-on initialization calibration operation:\n set a DQS delay element delay of the DQS delay element in response to at least one of the first core domain register or the second core domain register, \n for each of a plurality of byte lanes: run, in a plurality of loops, one or more calibrations using one or more pre-determined calibration data patterns and record one or more calibration results that each include a pass or a fail, where: at least one of the one or more pre-determined calibration data patterns is generated by the DDR memory controller, and the one or more pre-determined calibration data patterns include at least a BIST pattern written to DDR memory by the DDR memory controller and a different fixed data pattern read from a Multi-Purpose Register (MPR) of the DDR memory by the DDR memory controller, and \n based on at least one of the recorded one or more calibration results of at least one of the plurality of loops, set, after the DQS delay element delay is set, a capture clock delay that is a difference in time between an active edge of the second clock and a subsequent active edge of the first clock.

Metadata:
- Claim Count in Document: 80.0
- Percentile: 95.0
- Lexical Diversity: 2.11475
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15996365', '15926902', '15722209', '13172740', '14882226']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8564362460914212
- 35 USC 102 Novelty (BERT): 0.6331433823331488
- Combined Prediction Score: 0.834106959715594
- Mean Citation Score: 599.8854240000003
- Max Citation Score: 637.52344
- Similarity Product: 559.4906940011216

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test