PATENT CLAIM ANALYSIS

Application Number: 15904836
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["257", "314000"]

Abstract:
Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Claim (Index 17):
A method for forming an integrated circuit, the method comprising:\n forming an isolation structure in a semiconductor substrate, wherein the isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate; forming a doped well in the peripheral region; forming a seal layer covering the memory and peripheral regions, and further covering the doped well; removing the seal layer from the memory region, but not the peripheral region; forming a gate dielectric layer on the memory region by a thermal oxidation process, wherein the thermal oxidation process recesses a top surface of the semiconductor substrate at the memory region, but not at the peripheral region; forming a memory gate electrode over the gate dielectric layer; after the forming of the memory gate electrode, removing the seal layer from the peripheral region; and forming a peripheral gate electrode on the peripheral region while simultaneously forming a second memory gate electrode bordering the memory gate electrode.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 88.0
- Lexical Diversity: 2.59375
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15694098', '14750071', '14580454', '13763291', '15042157']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8909435766492979
- 35 USC 102 Novelty (BERT): 0.4850090966800237
- Combined Prediction Score: 0.8503501286523705
- Mean Citation Score: 168.41561000000004
- Max Citation Score: 201.19032
- Similarity Product: 156.63202861447334

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test