PATENT CLAIM ANALYSIS

Application Number: 16333206
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-08
Patent Classification: ["323", "271000"]

Abstract:
A voltage reducing circuit comprises a power switch circuit portion comprising a high-side and low-side field-effect-transistors connected at a switch node. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion comprising an inductor connected to the switch node is arranged to provide an output voltage. A timer determines a falltime duration required for the output voltage to fall to a threshold value. A controller switches the voltage reducing circuit between a first mode of operation in which a periodic pulse width modulated drive signal is applied to the high-side and low-side field-effect-transistors; and a second mode of operation in which a pulse is applied to the high-side and low-side field-effect-transistors only if the output voltage reaches the threshold value.

Claim (Index 5):
The voltage reducing circuit as claimed in  claim 3 , wherein the test is carried out periodically while the voltage reducing circuit is running in the first mode of operation.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 99.0
- Lexical Diversity: 2.11429
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15190095', '15716265', '14926555', '15915205', '12827394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7065090959138752
- 35 USC 102 Novelty (BERT): 0.4963001776519147
- Combined Prediction Score: 0.6854882040876792
- Mean Citation Score: 190.42269
- Max Citation Score: 192.98204
- Similarity Product: 125.6284828110266

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test