PATENT CLAIM ANALYSIS

Application Number: 15962474
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["372", "045011"]

Abstract:
An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.

Claim (Index 24):
The improved structure for reducing compound semiconductor wafer distortion according to  claim 1 , wherein said compound semiconductor wafer is made by one material selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN, AlN, ZnSe, InAs, and GaSb.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.31915
- Patent Class: 372.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15684482', '15813596', '11597413', '13054472', '11276653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8037016681054168
- 35 USC 102 Novelty (BERT): 0.5820934458452889
- Combined Prediction Score: 0.781540845879404
- Mean Citation Score: 240.24541600000003
- Max Citation Score: 447.8125
- Similarity Product: 446.12694552168233

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test