PATENT CLAIM ANALYSIS

Application Number: 15862218
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["324", "754010"]

Abstract:
A testing method for testing wafer level chip scale packages formed on a wafer including a wafer substrate and spaced-apart contact electrodes disposed on the wafer substrate, includes: providing a test device including a probe card formed with a plurality of parallel probe holes having a uniform cross-sectional dimension, and a plurality of probes respectively received in the probe holes and extending respectively in the probe holes along axes of the probe holes; and electrically connecting the contact electrodes to the probes. A distance between the axes of two adjacent ones of the probe holes is equal to a smallest spacing between two adjacent ones of the contact electrodes and is not greater than 0.5 mm.

Claim (Index 7):
The testing method of  claim 6 , wherein the probes are formed into spring probes, the testing method further comprising pressing the wafer received in the receiving space toward the upper part of the probe card by using a pressing member.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 86.0
- Lexical Diversity: 1.93651
- Patent Class: 324.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14454746', '15862172', '12787560', '12834807', '12013467']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5139835282682499
- 35 USC 102 Novelty (BERT): 0.4938476551836924
- Combined Prediction Score: 0.5119699409597942
- Mean Citation Score: 187.598312
- Max Citation Score: 199.97292
- Similarity Product: 131.07575198450087

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test