PATENT CLAIM ANALYSIS

Application Number: 15983678
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["330", "288000"]

Abstract:
A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Claim (Index 6):
The pHEMPT amplifier of  claim 5  further comprising a switched current mirror comprising:\n at least one pass transistor having a gate terminus (passgate), a drain terminus, (passdrain), and a source terminus (passsource); \n at least one amplifier transistor having a gate terminus (ampgate), a drain terminus, (ampdrain), and a source terminus (ampsource); and \n a voltage gate bias transistor having a gate terminus (biasgate), a drain terminus, (biasdrain), and a source terminus (biassource), wherein the at least one pass transistor is coupled at its passsource to an ampgate through at least one first gate bias resistor and is further coupled at its passdrain to the biasgate; wherein a passgate of the pass transistor is coupled to all of firstly, ground through a capacitor, secondly, an ESD2, thirdly its own passsource through a diode circuit, and fourthly, a switchable external control voltage connector through a second control voltage resistor; and wherein the biasgate is further coupled by a third resistor to all of firstly, an external current sink, secondly, ground through a capacitor, and thirdly another instance of ESD2.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.17544
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15451096', '14881998', '13528222', '13224430', '13271566']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.803350917139906
- 35 USC 102 Novelty (BERT): 0.547283565329691
- Combined Prediction Score: 0.7777441819588846
- Mean Citation Score: 316.5974
- Max Citation Score: 417.6103
- Similarity Product: 290.6011776866137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test