PATENT CLAIM ANALYSIS

Application Number: 16249482
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["365", "185030"]

Abstract:
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claim (Index 1):
A flash non-volatile memory device comprising:\n a plurality of non-volatile memory banks a flash memory array; a first control port configured to receive a chip select signal from a memory controller; a first clock input port configured to receive a first clock input signal from the memory controller; a second clock output port configured to transmit a second clock output signal, referenced to the first clock input signal, to the memory controller; a configurable data interface configured to transfer command data, address data, write data, and read data only when the chip select signal is at an active low logic state, at least one of the command data, the address data, the write data, and the read data being transferred in synchronization with both rising and falling edges of the clock input signal when the non-volatile memory device is in a double data rate implementation; a control circuitry configured to perform a read-while-program operation, the read-while-program operation comprising a program operation to program data on a selected non-volatile memory bank and a read operation to retrieve data from a different non-volatile memory bank other than the selected non-volatile memory bank while the program operation is in progress; and a status register configured to indicate a status of the program operation, at least one common data port configured to receive command data and address data in synchronization with the first clock signal while the chip select signal is at an active low logic state; and core circuitry configured to retrieve a read data from the flash memory array in response to the command data.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.20339
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15937937', '15345552', '15868219', '13867437', '14984303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8243615182234258
- 35 USC 102 Novelty (BERT): 0.5473758895344315
- Combined Prediction Score: 0.7966629553545265
- Mean Citation Score: 405.235218
- Max Citation Score: 421.07736
- Similarity Product: 343.09047989327433

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test