PATENT CLAIM ANALYSIS

Application Number: 16028364
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "296000"]

Abstract:
A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

Claim (Index 3):
The semiconductor structure for preventing row hammering issue in DRAM cell of  claim 2 , wherein the material of said hard mask is silicon nitride.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 1.3
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15627455', '15090759', '15914599', '15130727', '15613845']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303817056614856
- 35 USC 102 Novelty (BERT): 0.5605927213959995
- Combined Prediction Score: 0.8934028072349369
- Mean Citation Score: 269.930874
- Max Citation Score: 442.91858
- Similarity Product: 353.1810042778421

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test