PATENT CLAIM ANALYSIS

Application Number: 15946666
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "197000"]

Abstract:
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

Claim (Index 1):
An integrated circuit structure, comprising:\n a high voltage transistor comprising:\n a gate electrode over a semiconductor fin, the gate electrode having a first side opposite a second side; \n a first source or drain region at the first side of the gate electrode; and \n a second source or drain region at the second side of the gate electrode; \n a low voltage transistor comprising:\n a gate electrode over a semiconductor fin, the gate electrode having a first side opposite a second side; \n a first source or drain region at the first side of the gate electrode; and \n a second source or drain region at the second side of the gate electrode; \n a first conductive contact on the first source or drain region of the high voltage transistor, the first conductive contact laterally spaced apart from the first side of the gate electrode of the high voltage transistor by a first distance; a second conductive contact on the second source or drain region of the high voltage transistor, the second conductive contact laterally spaced apart from the second side of the gate electrode of the high voltage transistor by approximately the first distance; a third conductive contact on the first source or drain region of the low voltage transistor, the third conductive contact laterally spaced apart from the first side of the gate electrode of the low voltage transistor by a second distance, the second distance less than the first distance; and a fourth conductive contact on the second source or drain region of the low voltage transistor, the fourth conductive contact laterally spaced apart from the second side of the gate electrode of the low voltage transistor by approximately the second distance.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 4.47826
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15784318', '14975645', '13536732', '14641117', '15024750']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.871014378276241
- 35 USC 102 Novelty (BERT): 0.5103721817542201
- Combined Prediction Score: 0.8349501586240389
- Mean Citation Score: 281.65389
- Max Citation Score: 311.26755
- Similarity Product: 261.23848010231853

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test