PATENT CLAIM ANALYSIS

Application Number: 16006573
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["257", "066000"]

Abstract:
A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

Claim (Index 1):
A memory structure, comprising:\n a semiconductor substrate having a planar surface, the semiconductor substrate having circuitry formed therein and thereon; a plurality of memory modules provided one on top of another above the planar surface, wherein each memory module comprises:\n a plurality of stacks of active strips, the stacks being spaced from each other along a first direction substantially parallel the planar surface, each active strip running lengthwise along a second direction that is also substantially parallel the planar surface but orthogonal to the first direction, the active strips within each stack being provided one on top of another along a third direction that is substantially perpendicular to the planar surface, each active strip comprising semiconductor layers that form drain, source and channel regions of thin-film storage transistors organized as NOR strings; \n a set of local word line conductors each running along the third direction to provide as gate electrodes to storage transistors in a designated one of the stacks of active strips; \n a first set of global word line conductors provided below the stacks of active strips, being spaced from each other along the second direction and each running along the first direction, connecting the substrate circuitry to some of the local word lines; and \n a second set of global word line conductors provided above the stacks of active strips, being spaced from each other along the second direction and each running along the first direction, connecting the substrate circuitry to some of the local word lines, wherein the second set of global word line conductors of each memory module, except for one memory module, is provided also as the first set of global word line conductors of another memory module located immediately above it.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 1.7963
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15220375', '15248420', '15837734', '15783201', '15343332']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9145523551341748
- 35 USC 102 Novelty (BERT): 0.4701877600110973
- Combined Prediction Score: 0.870115895621867
- Mean Citation Score: 197.824528
- Max Citation Score: 212.6898
- Similarity Product: 184.58705299032923

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test