PATENT CLAIM ANALYSIS

Application Number: 15893660
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "190000"]

Abstract:
FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

Claim (Index 22):
The FinFET structure of  claim 20 , wherein the III-V bases are configured to provide aspect ratio trapping.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 1.52778
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15350071', '14718425', '15789972', '15350065', '14930258']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9470162073146796
- 35 USC 102 Novelty (BERT): 0.546086752272139
- Combined Prediction Score: 0.9069232618104256
- Mean Citation Score: 410.990276
- Max Citation Score: 421.5079
- Similarity Product: 181.20300125648967

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test