PATENT CLAIM ANALYSIS

Application Number: 15907711
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "148000"]

Abstract:
A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresponding one of the fifth wirings.

Claim (Index 1):
A semiconductor integrated circuit comprising:\n first wirings; second wirings intersecting with the first wirings, respectively; third wirings intersecting with the first wirings, respectively; first current limiters arranged to correspond to the first wirings, at least one of the first current limiters being connected to corresponding one of the first wirings; second current limiters arranged to correspond to the second wirings, at least one of the second current limiters being connected to corresponding one of the second wirings; third current limiters arranged to correspond to the third wirings, at least one of the third current limiters being connected to corresponding one of the third wirings; first drivers arranged to correspond to the first current limiters, at least one of the first drivers being connected to corresponding one of the first current limiters; second drivers arranged to correspond to the second current limiters, at least one of the second drivers being connected to corresponding one of the second current limiters; third drivers arranged to correspond to the third current limiters, at least one of the third drivers being connected to corresponding one of the third current limiter; and a first array and a second array, wherein the first array comprises: fourth wirings arranged to correspond to the first wirings; fifth wirings arranged to correspond to the second wirings, the fifth wirings intersecting with the fourth wirings, respectively; first transistors arranged to correspond to the first wirings, one of a source and drain of at least one of the first transistors being connected to corresponding one of the first wirings, the other of the source and drain of the at least one of the first transistors being connected to corresponding one of the fourth wirings; second transistors arranged to correspond to the second wirings, one of a source and drain of at least one of the second transistors being connected to corresponding one of the second wirings, the other of the source and drain of the at least one of the second transistors being connected to corresponding one of the fifth wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, at least one of the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresponding one of the fifth wirings; and the second array comprises: sixth wirings arranged to correspond to the first wirings; seventh wirings arranged to correspond to the third wirings, the seventh wirings intersecting with the sixth wirings, respectively; third transistors arranged to correspond to the first wirings, one of a source and drain of at least one of the third transistors being connected to corresponding one of the first wirings, the other of the source and drain of the at least one of the third transistors being connected to corresponding one of the sixth wirings; fourth transistors arranged to correspond to the third wirings, one of a source and drain of at least one of the fourth transistors being connected to corresponding one of the third wirings, the other of the source and drain of the at least one of the fourth transistors being connected to corresponding one of the seventh wirings; and second resistive change elements arranged in intersecting areas of the sixth wirings and the seventh wirings, respectively, at least one of the second resistive change elements including a third terminal connected to corresponding one of the sixth wirings and a fourth terminal connected to corresponding one of the seventh wirings.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 3.86047
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15700319', '14884215', '14854361', '12282163', '14988034']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7818820111504964
- 35 USC 102 Novelty (BERT): 0.4768121349003527
- Combined Prediction Score: 0.751375023525482
- Mean Citation Score: 173.96563600000005
- Max Citation Score: 201.73521
- Similarity Product: 147.2087377297801

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test