PATENT CLAIM ANALYSIS

Application Number: 16037767
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "835000"]

Abstract:
Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R on  or R off  to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Claim (Index 13):
The memory device according to  claim 11 , wherein the second RRAM crossbar array comprises a (2N\u22121) rows\u00d7N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array;\n the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N\u22121 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array: O _ 2 , j = { O _ 1 , j + O 1 , j + 1 , j < N - 1 O _ 1 , j , j = N - 1 to obtain voltage signals corresponding to an intermediate binary number, wherein \u014c 1,j  is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j th  bit line of the first RRAM crossbar array, O 1,j+1  is a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1) th  bit line of the first RRAM crossbar array, and \u014c 2,j  is a negation of a value corresponding to a voltage signal output by the j th  bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows\u00d7n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 1.72
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13965459', '14287701', '14308273', '14731933', '14025299']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4127864574091122
- 35 USC 102 Novelty (BERT): 0.491308524935049
- Combined Prediction Score: 0.4206386641617059
- Mean Citation Score: 191.697904
- Max Citation Score: 210.35286
- Similarity Product: 169.36393187642813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test