PATENT CLAIM ANALYSIS

Application Number: 15945665
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "048000"]

Abstract:
Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.

Claim (Index 19):
The apparatus of  claim 18 , wherein the stress reduction structure further includes at least one via coupled to the material on the particular layer and the material on the another layer .

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 1.77083
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14134328', '13847964', '13160713', '15168479', '13917568']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9023072585220676
- 35 USC 102 Novelty (BERT): 0.5019155974059895
- Combined Prediction Score: 0.86226809241046
- Mean Citation Score: 162.92896199999996
- Max Citation Score: 165.29288
- Similarity Product: 101.08197953249932

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test