PATENT CLAIM ANALYSIS

Application Number: 15867036
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "350000"]

Abstract:
Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

Claim (Index 1):
A method comprising:\n providing a substrate; forming a semiconductor fin on the substrate, wherein the semiconductor fin has a first width; and forming a first transistor using the semiconductor fin, the forming of the first transistor comprising: forming a sacrificial gate on a first portion of the semiconductor fin such that second portions of the semiconductor fin extend laterally beyond the sacrificial gate;\n forming a sidewall spacer comprising a gate section on the sacrificial gate and fin sections on the second portions of the semiconductor fin; \n removing the second portions of the semiconductor fin to create source/drain openings with a second width that is essentially equal to the first width of the semiconductor fin and to expose vertical surfaces of the first portion of the semiconductor fin, wherein the first width of the semiconductor fin and the second width of the source/drain openings are measured in a same direction; \n widening the source/drain openings such that the second width of the source/drain openings is greater than the first width of the semiconductor fin; and \n after the widening of the source/drain openings, forming source/drain regions in the source/drain openings.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 86.0
- Lexical Diversity: 1.95181
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15387933', '15658835', '15787009', '15715220', '15862064']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9328675431539012
- 35 USC 102 Novelty (BERT): 0.532863164956036
- Combined Prediction Score: 0.8928671053341146
- Mean Citation Score: 353.47274199999987
- Max Citation Score: 374.74036
- Similarity Product: 309.9894456665945

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test