PATENT CLAIM ANALYSIS

Application Number: 16038705
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["327", "537000"]

Abstract:
The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.

Claim (Index 18):
The integrated circuit of  claim 16 , further comprising a plurality of control circuits positioned in the circuit domains, respectively, wherein for each circuit domain, the control circuit is coupled to the output line of the monitoring circuit of the circuit domain, and is configured to control the biasing circuit of the circuit domain to modify the biasing voltage based on the output signal from the monitoring circuit of the circuit domain.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 1.83051
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15609571', '15927027', '13664007', '11838273', '12337061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.717143237090054
- 35 USC 102 Novelty (BERT): 0.5562721949620681
- Combined Prediction Score: 0.7010561328772554
- Mean Citation Score: 229.924194
- Max Citation Score: 412.14627
- Similarity Product: 403.6049758653653

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test