PATENT CLAIM ANALYSIS

Application Number: 15862554
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["714", "731000"]

Abstract:
A BIST circuit is provided with modes of operation in which the BIST procedure for a circuit-under-test occurs at a system clock rate for the circuit-under-test that is greater than a test clock rate for the BIST circuit.

Claim (Index 5):
The integrated circuit of  claim 1 , wherein the TAP comprises a local TAP and a global TAP.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 1.5
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12160211', '11265488', '10301127', '10780878', '10861247']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3015353099291284
- 35 USC 102 Novelty (BERT): 0.5155576117875865
- Combined Prediction Score: 0.3229375401149743
- Mean Citation Score: 168.169332
- Max Citation Score: 170.32802
- Similarity Product: 77.04035536221565

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test