PATENT CLAIM ANALYSIS

Application Number: 16227038
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["327", "157000"]

Abstract:
The proposed Power Management Integrated Circuit (PMIC) features the option to synchronize the charge-pump of a PMIC with the system clock, and then to swap and self-oscillate and skip pulses, when the digital controls of the PMIC send a first order to the charge-pump. The clock control circuitry of the PMIC also features the option for the charge-pump to then swap and use the system clock again, when the digital controls of the PMIC send a second order to the charge-pump. The designed transition of the clock from clock sync-mode to self-oscillate, and from self-oscillate back to clock sync-mode, does not present any phase discontinuity.

Claim (Index 1):
A Power converter circuit, comprising:\n a.) a course oscillator for generating a system clock; b.) digital controls for programming said system clock for phase and frequency; c.) in phase detection and latch circuitry for synchronization and resynchronization of said system clock with said power converter; and d.) a phase control multiplexer for self-oscillation of the clock of said power converter.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 2.21154
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14792855', '10346435', '15545614', '16201325', '12759519']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7111661504109147
- 35 USC 102 Novelty (BERT): 0.549594907524703
- Combined Prediction Score: 0.6950090261222935
- Mean Citation Score: 210.947902
- Max Citation Score: 416.6216
- Similarity Product: 296.39132438726426

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test