PATENT CLAIM ANALYSIS

Application Number: 16123772
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["365", "185110"]

Abstract:
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

Claim (Index 1):
An apparatus, comprising:\n a block of memory cells configured in multiple sub-blocks of memory cells, wherein multiple sub-blocks are coupled electrically to one another through at least one common data line, wherein each of the sub-blocks includes a respective segmented source, wherein each segmented source is electrically isolated from the other segmented sources of the block of memory cells; and a memory controller configured to apply a first bias voltage to a segmented source of a sub-block selected to be erased during an erase operation, and to apply a second bias voltage to another segmented source of a sub-block not selected to be erased during the erase operation.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 97.0
- Lexical Diversity: 1.73171
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15489276', '13600591', '15082664', '15907570', '14943541']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7653100036517755
- 35 USC 102 Novelty (BERT): 0.4712134848957848
- Combined Prediction Score: 0.7359003517761764
- Mean Citation Score: 216.932504
- Max Citation Score: 240.36432
- Similarity Product: 230.5961154452133

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test