PATENT CLAIM ANALYSIS

Application Number: 15885449
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["365", "154000"]

Abstract:
A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

Claim (Index 5):
The circuit according to  claim 1 ,\n wherein the address control circuit is set as a first address control circuit, the decode circuit is set as a first decode circuit, the word line drive circuit is set as a first word line drive circuit, the clock signal is set as a first clock signal, the word line is set as a first word line, and the memory cell array further includes a plurality of second word lines in addition to a plurality of the first word lines, wherein the circuit further comprises a second address control circuit and a second clock signal and a third address signal are further input into the circuit, and wherein the second address control circuit includes a third latch circuit which latches the third address signal in synchronization with the second clock signal, a second decode circuit which decodes the third address signal which has been latched by the third latch circuit, and a second word line drive circuit which selects and drives one of the second word lines that the memory cell array includes on the basis of an output signal from the second decode circuit.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 3.26531
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15613882', '15281947', '15606562', '11282333', '11338670']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8208164618425629
- 35 USC 102 Novelty (BERT): 0.4832753624259472
- Combined Prediction Score: 0.7870623519009012
- Mean Citation Score: 228.15422200000003
- Max Citation Score: 240.236
- Similarity Product: 190.13785218667985

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test