PATENT CLAIM ANALYSIS

Application Number: 16026298
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["365", "185290"]

Abstract:
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Claim (Index 40):
The method of  claim 37  wherein implanting dopants into the surface of the substrate to form source and drains of the memory transistor and the pass transistor comprises implanting dopants of a first type, and wherein performing the halo implant comprises implanting dopants of a second type, different from the first type.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 95.0
- Lexical Diversity: 2.32075
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15078890', '15419954', '15918704', '15634032', '14858886']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8196850810406118
- 35 USC 102 Novelty (BERT): 0.4918348693013227
- Combined Prediction Score: 0.7869000598666829
- Mean Citation Score: 240.862042
- Max Citation Score: 266.80197000000004
- Similarity Product: 212.6692994370282

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test