PATENT CLAIM ANALYSIS

Application Number: 16029607
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Claim (Index 10):
The dynamic decode circuit according to  claim 9 , wherein the plurality of dynamic decode circuits are configured to enable decoders of only one dynamic decode circuit of the plurality of dynamic decode circuits to conduct in any clock cycle

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 1.43243
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16029577', '15613185', '15796819', '16029604', '15274322']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7971847741521136
- 35 USC 102 Novelty (BERT): 0.5534325590141451
- Combined Prediction Score: 0.7728095526383169
- Mean Citation Score: 483.02547
- Max Citation Score: 489.0524
- Similarity Product: 336.7452771731615

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test