PATENT CLAIM ANALYSIS

Application Number: 15870269
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "185170"]

Abstract:
Disclosed includes a memory device and a method of operating the memory device. A voltage is applied to a word line coupled to first memory transistors of a first plurality of strings of transistors and second memory transistors of a second plurality of strings of transistors. A current flow through one or more of the first plurality of strings of transistors is enabled, while applying the voltage to the word line. A current flow through the second plurality of strings of transistors is disabled by floating source terminals and drain terminals of the second memory transistors, while enabling the current flow through the one or more of the first plurality of strings of transistors.

Claim (Index 14):
The device of  claim 12 , wherein the controller includes:\n a first controller coupled to the first control line, the word line and the second control line; and a second controller coupled to the third control line and the fourth control line, the first plurality of strings of transistors and the second plurality of strings of transistors disposed between the first controller and the second controller.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.92683
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14043256', '12580949', '12486924', '13029518', '14814846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.817245475962898
- 35 USC 102 Novelty (BERT): 0.4875217440719619
- Combined Prediction Score: 0.7842731027738044
- Mean Citation Score: 217.926842
- Max Citation Score: 223.45457
- Similarity Product: 157.14283937532068

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test