PATENT CLAIM ANALYSIS

Application Number: 15915733
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["326", "119000"]

Abstract:
Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition process—in lieu of a lithography process—thereby providing for high speed operation and low cost manufacturing.

Claim (Index 18):
The method of  claim 13 , wherein the unipolar type is P-type MOS transistors.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 90.0
- Lexical Diversity: 1.44872
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15729470', '15316007', '13851937', '13475332', '10411853']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7017789401578182
- 35 USC 102 Novelty (BERT): 0.5248516273794543
- Combined Prediction Score: 0.6840862088799818
- Mean Citation Score: 251.805512
- Max Citation Score: 353.01053
- Similarity Product: 238.7565459424001

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test