PATENT CLAIM ANALYSIS

Application Number: 15914485
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "316000"]

Abstract:
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Claim (Index 13):
The semiconductor device of  claim 12 , wherein a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.39583
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15209370', '15498743', '15428823', '15584314', '14326562']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916592118956888
- 35 USC 102 Novelty (BERT): 0.4853657020639161
- Combined Prediction Score: 0.8734694772675908
- Mean Citation Score: 165.26733000000004
- Max Citation Score: 192.8441
- Similarity Product: 139.2201302318096

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test