PATENT CLAIM ANALYSIS

Application Number: 15947330
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "051000"]

Abstract:
Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.

Claim (Index 15):
The device of  claim 11 , wherein the global control circuit and the SRAM array are in a same level of a multi-layer structure.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 2.84211
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15411285', '14097308', '13972988', '14087029', '15865923']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8344030852857817
- 35 USC 102 Novelty (BERT): 0.5231717957704298
- Combined Prediction Score: 0.8032799563342464
- Mean Citation Score: 302.34007
- Max Citation Score: 358.4975
- Similarity Product: 271.36178401440384

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test