PATENT CLAIM ANALYSIS

Application Number: 15907570
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185110"]

Abstract:
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.

Claim (Index 22):
The non-volatile storage apparatus of  claim 21 , wherein:\n the erase signal is a series of erase voltage bursts; and the control circuit is configured to separately erase verify each of the multiple NAND strings after a first erase voltage burst, characterize erase progress after the first erase voltage burst for each of the NAND strings, and adjust one or more voltages to the selection lines to cause erase performance of the NAND strings to converge during subsequent one or more additional erase voltage bursts.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 1.51515
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15337522', '15630389', '15191150', '15151951', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8196788395777596
- 35 USC 102 Novelty (BERT): 0.4823064552815679
- Combined Prediction Score: 0.7859416011481404
- Mean Citation Score: 226.306854
- Max Citation Score: 232.60359
- Similarity Product: 180.40185790816963

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test