PATENT CLAIM ANALYSIS

Application Number: 16042194
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["327", "203000"]

Abstract:
At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

Claim (Index 7):
A method, comprising:\n providing to a flip-flop an input signal D that is identical to an output signal Q of the flip-flop, the output signal Q having a first value; providing a clock signal to the flip-flop at a first bit value; passing the input signal D and the clock signal at the first bit value through a network of transistor switches, inverters, buffers, and logic gates such that the states of master and slave latches in the flip-flop hold the output signal Q at the first value; toggling the clock signal to a second bit value; and passing the input signal D and the clock signal at the second bit value through the network of transistor switches, inverters, buffers, and logic gates such that the states of the master and slave latches remain static.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.81481
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15391465', '14481992', '14498412', '14498048', '11367535']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8265979639603469
- 35 USC 102 Novelty (BERT): 0.5673027168726273
- Combined Prediction Score: 0.8006684392515749
- Mean Citation Score: 406.543106
- Max Citation Score: 499.91583
- Similarity Product: 370.4155187606961

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test