PATENT CLAIM ANALYSIS

Application Number: 15867670
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "668000"]

Abstract:
A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Claim (Index 8):
A semiconductor package, comprising:\n a first semiconductor die comprising a first active surface; a second semiconductor die electrically connected to the first semiconductor die and comprising a second active surface facing towards the first active surface of the first semiconductor die, wherein the second semiconductor die partially covers the first semiconductor die; a plurality of conductive features disposed over the first active surface of the first semiconductor die and electrically connected to the first semiconductor die and the second semiconductor die, wherein\n a portion of the conductive features laterally surrounds the second semiconductor die s  \n the conductive features comprise a first coupling structure corresponding to the second semiconductor die and a second coupling structure surrounding the first coupling structure, and \n the height of the second coupling structure is greater than the height of the first coupling structure; a first encapsulant encapsulating the second semiconductor die and the conductive features; a second encapsulant laterally encapsulating the first encapsulant and the first semiconductor die, wherein a second back surface of the second semiconductor die opposite to the second active surface and a top surface of the second coupling structure are coplanar with a top surface of the first encapsulant and a top surface of the second encapsulant; and a redistribution layer disposed on the second encapsulant and the first encapsulant, wherein the redistribution layer is electrically connected to the first semiconductor die and the second semiconductor die through the conductive features.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 3.11111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15359403', '15599481', '15713708', '15264606', '15713717']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920220633524552
- 35 USC 102 Novelty (BERT): 0.4843710082365959
- Combined Prediction Score: 0.8766356709957563
- Mean Citation Score: 240.821272
- Max Citation Score: 250.15475
- Similarity Product: 217.70101472690703

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test