PATENT CLAIM ANALYSIS

Application Number: 15877895
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["710", "016000"]

Abstract:
A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Claim (Index 11):
A semiconductor apparatus comprising:\n three or more sequentially stacked chips including a first chip stacked at a first stage and an other chip stacked at a last stage; a common line which is electrically coupled in common with the three or more chips, wherein each of the three or more chips include chip identification (ID) generation units, which are respectively disposed in the three or more chips, are sequentially electrically coupled with one another, and generate a plurality of chip ID signals, wherein the first chip is configured to directly receive the chip ID signal of the other chip and generate a stack information signal from the chip ID signal of the other chip, wherein each of the three or more chips comprises a chip ID transmission unit which is configured to transmit the chip ID signal of the corresponding chip at a current stage to the common line on the basis of whether a stacked chip exists at a next stage, wherein each of the three or more chips comprises a chip stack information generation unit which is configured to be electrically coupled with the common line and generate a stack information signal from the chip ID signal transmitted through the common line, when it is enabled in response to the chip ID signal of the chip in which it is disposed, and wherein the chip stack information generation unit is configured to decode the chip ID signal of the chip in which it is disposed, and, based on the decoding of the chip ID signal, receive the chip ID signal transmitted through the common line to generate the stack information signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.59459
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14014625', '13166094', '14258190', '14711388', '13168241']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6753334097332371
- 35 USC 102 Novelty (BERT): 0.5374061898214073
- Combined Prediction Score: 0.6615406877420542
- Mean Citation Score: 251.805854
- Max Citation Score: 389.6414
- Similarity Product: 370.9423837054252

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test