PATENT CLAIM ANALYSIS

Application Number: 15902957
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["365", "185020"]

Abstract:
A flash memory cell array includes multiple flash memory units. A flash memory unit includes first and second select transistors, and first and second floating-gate transistors on a substrate. The first floating-gate transistor has a source connected to a drain of the first select transistor, and a drain connected to a drain of the second floating-gate transistor. The second floating-gate transistor has a source connected a drain of the second select transistor. The first and second floating-gate transistors of a flash memory unit in a j-th column have a control gate connected to a j-th word line. The first and second select transistors of the flash memory unit in the j-th column have a source connected to a common source line. The first and second floating-gate transistors of a flash memory unit in an i-th row have a drain connected to an i-th bit line.

Claim (Index 5):
The MTP flash memory cell array of  claim 3 , wherein the control circuit is further configured to apply:\n the voltage Vcc 2  to a gate of the second select transistor in the i-th row and j-th column of an MTP flash memory cell unit.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 3.66667
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13595426', '14869820', '15365575', '13109694', '13935027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8435644243801629
- 35 USC 102 Novelty (BERT): 0.5166409229356481
- Combined Prediction Score: 0.8108720742357114
- Mean Citation Score: 321.0834680000001
- Max Citation Score: 336.24072
- Similarity Product: 242.1069161628056

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test