PATENT CLAIM ANALYSIS

Application Number: 16024562
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "106000"]

Abstract:
A semiconductor device and a method for fabricating a semiconductor device are disclosed. The semiconductor device includes a tunnel field-effect transistor and a planar device. The tunnel field-effect transistor includes a first substrate and a first electrical element, and the first electrical element is formed on one side of the first substrate; the planar device includes a second substrate and a second electrical element, the second substrate and the first substrate are an integrated structure and form a main substrate, the second electrical element is formed on one side of the second substrate, and the second electrical element and the first electrical element are disposed on a same side of the main substrate; and the planar device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.

Claim (Index 15):
The semiconductor device according to  claim 10 , wherein:\n when the planar device is the capacitor, the second electrical element comprises a first doping region, a second insulation layer, a third gate dielectric layer, and a third gate region; the first doping region is embedded into the second substrate from the third surface; one end of the first doping region is flush with the third surface; the first doping region is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region; one end of the first doping region is in contact with the third shallow trench isolation region, and the other end of the first doping region is in contact with the fourth shallow trench isolation region; the second insulation layer is disposed in the middle of the first doping region, and the second insulation layer does not cover the both ends of the first doping region; the third gate dielectric layer is stacked on the second insulation layer; and the third gate region is stacked on the third gate dielectric layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 94.0
- Lexical Diversity: 3.30233
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13144182', '11133086', '13138053', '15238696', '11450112']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9288272898453024
- 35 USC 102 Novelty (BERT): 0.495987241789242
- Combined Prediction Score: 0.8855432850396965
- Mean Citation Score: 249.302326
- Max Citation Score: 265.21716000000004
- Similarity Product: 220.06294297439567

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test