PATENT CLAIM ANALYSIS

Application Number: 16166636
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "199000"]

Abstract:
A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source.

Claim (Index 8):
A 3D semiconductor device, the device comprising:\n a first level comprising a first single crystal transistor; a second level comprising second transistors; a third level comprising third transistors; a fourth level comprising fourth transistors,\n wherein said first level is underneath said second level, \n wherein said second level is underneath said third level, and \n wherein said third level is underneath said fourth level; \n at least a first metal layer and a second metal layer,\n wherein said at least first metal layer and second metal layer comprise connections between a plurality of said first single crystal transistor; and \n wherein a plurality of said fourth transistors are aligned to said plurality of said first single crystal transistor with less than 140 nm alignment error, \n wherein said second metal layer is above said first metal layer, \n wherein said first metal layer comprises a first current carrying capacity, \n wherein said second metal layer comprises a second current carrying capacity, \n wherein said first current carrying capacity is significantly greater than said second current carrying capacity, \n wherein said third transistors are junction-less transistors (JLT), \n wherein each of said fourth transistors comprise a transistor channel, a drain and a source, and \n wherein said transistor channel is significantly narrower than said drain or said source.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 2.91837
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15950169', '16004404', '16115519', '15990684', '12963659']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8755427148081782
- 35 USC 102 Novelty (BERT): 0.5235562108201408
- Combined Prediction Score: 0.8403440644093745
- Mean Citation Score: 326.651402
- Max Citation Score: 351.8785
- Similarity Product: 300.75870187208056

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test