PATENT CLAIM ANALYSIS

Application Number: 15863324
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "072000"]

Abstract:
Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Claim (Index 15):
The method of  claim 14 ,\n wherein biasing the first source or drain connection to an erase voltage comprises applying the erase voltage to at least one of a data line or a source.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.17021
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14171426', '13781016', '13525035', '14161170', '14031509']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8119559141698629
- 35 USC 102 Novelty (BERT): 0.5076779730518777
- Combined Prediction Score: 0.7815281200580644
- Mean Citation Score: 203.64866
- Max Citation Score: 295.612
- Similarity Product: 220.8053308427334

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test