PATENT CLAIM ANALYSIS

Application Number: 15904004
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "295000"]

Abstract:
Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.

Claim (Index 20):
The device according to  claim 16 , wherein the gate oxide comprises a high-k dielectric.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 88.0
- Lexical Diversity: 2.30769
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14639159', '13759209', '14527278', '15815326', '14739233']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9348186201050398
- 35 USC 102 Novelty (BERT): 0.5082186735023471
- Combined Prediction Score: 0.8921586254447705
- Mean Citation Score: 253.087836
- Max Citation Score: 267.40475
- Similarity Product: 184.55274132958053

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test