PATENT CLAIM ANALYSIS

Application Number: 16191218
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["375", "297000"]

Abstract:
A power amplifier circuit includes a transistor having a first terminal that is configured to receive an input signal, a second terminal electrically coupled to ground, and a third terminal configured to transmit a combined amplified signal. The power amplifier circuit further includes a combining signal input path electrically coupled to the second terminal and configured to receive a combining signal and provide the combining signal to the second terminal of the transistor to generate, at least in part, the combined amplified signal.

Claim (Index 13):
The method of  claim 12  further comprising forming a cascode transistor on the semiconductor substrate.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 98.0
- Lexical Diversity: 2.17073
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15285456', '15685276', '15429568', '13992804', '15857217']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4844294461835524
- 35 USC 102 Novelty (BERT): 0.5160977834102762
- Combined Prediction Score: 0.4875962799062248
- Mean Citation Score: 232.807366
- Max Citation Score: 305.9401200000001
- Similarity Product: 209.199550903802

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test