PATENT CLAIM ANALYSIS

Application Number: 15879929
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-06
Patent Classification: ["257", "331000"]

Abstract:
The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.

Claim (Index 15):
The transistor structure of  claim 1 , further comprising a plurality of isolation structures disposed over the active region, wherein portions of the source/drain region are exposed through the isolation structures.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 2.35417
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13957121', '14172608', '15137018', '15455588', '13369900']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8967965457509381
- 35 USC 102 Novelty (BERT): 0.5017529079301934
- Combined Prediction Score: 0.8572921819688637
- Mean Citation Score: 199.320172
- Max Citation Score: 200.08583
- Similarity Product: 129.21981669175744

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test