PATENT CLAIM ANALYSIS

Application Number: 15907200
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["375", "355000"]

Abstract:
An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

Claim (Index 21):
The signaling system according to  claim 20  and further including:\n timing control logic to adjust the relative phases of the timing signal and the data signal based on the early/late information.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 88.0
- Lexical Diversity: 2.3
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12868571', '12897661', '10123370', '12624365', '10274513']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4986054701622273
- 35 USC 102 Novelty (BERT): 0.4843396267350451
- Combined Prediction Score: 0.4971788858195091
- Mean Citation Score: 153.861546
- Max Citation Score: 183.45451
- Similarity Product: 130.43589881254852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test