PATENT CLAIM ANALYSIS

Application Number: 15882409
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["711", "103000"]

Abstract:
Described is an improved storage architecture. In a particular aspect an improved storage architecture with increased throughput to Ethernet storage modules due to elimination of data path handling from a main control CPU is set forth. Other method and apparatus are described therein, including a scalable Ethernet storage module particularly suited for usage with the improved storage architecture described herein.

Claim (Index 11):
A method of writing digital data to a storage array system, the method comprising the steps of:\n receiving a write request at the storage array system, the storage array system including a storage processing unit and a central processing unit; determining, using the central processing unit, to allow a write sequence, wherein the central processing unit issues a write command to the storage processing unit, the write command including a hash identifying a logical unit number of a particular one of a plurality of ethernet storage modules into which to write the digital data; receiving the digital data in a write memory buffer that is coupled to the storage processing unit and is not coupled to the central processing unit; writing the digital data, by the storage processing unit, from the write memory buffer to the particular one of the plurality of ethernet storage modules based upon the hash provided by the central processing unit; at the particular ethernet storage module, writing the digital data into a persistent flash memory, including the steps of:\n writing the digital data from the storage processing unit into a protected DRAM through an ESM processor coupled to the protected DRAM of the particular one of the plurality of ethernet storage modules; \n issuing a command to the storage processing unit that the digital data has been completely written upon completion of the step of writing the digital data from the storage processing unit into the protected DRAM; and \n writing the digital data from the protected DRAM into the persistent flash memory using the ESM processor, wherein the ESM processor associates a specific logical block address with the digital data that was written and maintains a table associating the specific logical block address with the digital data that was written.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 86.0
- Lexical Diversity: 1.3913
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14562110', '12481303', '14062374', '13280869', '15338897']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.509809316670885
- 35 USC 102 Novelty (BERT): 0.5774417398191625
- Combined Prediction Score: 0.5165725589857127
- Mean Citation Score: 228.388536
- Max Citation Score: 478.0781
- Similarity Product: 431.6778224844276

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test