PATENT CLAIM ANALYSIS

Application Number: 16173040
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["710", "105000"]

Abstract:
A system on chip includes a display serial interface (DSI) which includes a PHY protocol interface (PPI) used for communication between a DSI host controller and a D-PHY. The DSI host controller includes a register configured to store first indicator data indicating a PPI packetizing method and a lane distributor configured to determine a size of a symbol to be transmitted to the PPI and an order of first processing units to be included in the symbol based on the first indicator data.

Claim (Index 4):
The data processing system of  claim 3 , wherein the lane distributor is further configured to determine transmission orders of the at least one first processing unit and the at least one second processing unit, based on the first indicator data.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 1.71154
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14989823', '16120735', '15139441', '14713080', '11450899']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6810151198575223
- 35 USC 102 Novelty (BERT): 0.5729425885164084
- Combined Prediction Score: 0.6702078667234109
- Mean Citation Score: 239.939102
- Max Citation Score: 516.7654
- Similarity Product: 370.5209805523157

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test