PATENT CLAIM ANALYSIS

Application Number: 16174626
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["257", "339000"]

Abstract:
The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.

Claim (Index 4):
The integrated chip of  claim 2 , wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.06349
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14604885', '15927281', '15424333', '16026290', '16117166']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9280733314773818
- 35 USC 102 Novelty (BERT): 0.5102228691069688
- Combined Prediction Score: 0.8862882852403405
- Mean Citation Score: 243.850146
- Max Citation Score: 285.44763
- Similarity Product: 208.7806197573853

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test