PATENT CLAIM ANALYSIS

Application Number: 16027263
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["710", "316000"]

Abstract:
A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.

Claim (Index 16):
The reconfigurable pin-to-pin interface of  claim 8 , wherein the lane circuits further comprise:\n a third lane circuit, arranged to obtain a third received signal by receiving a third input signal transmitted via a third lane; a fourth lane circuit, arranged to obtain a fourth received signal by receiving a fourth input signal transmitted via a fourth lane; and a fifth lane circuit, arranged to obtain a fifth received signal by receiving a fifth input signal transmitted via a fifth lane; wherein the first switch circuit is further coupled to an output port of the second lane circuit and a clock input port of the first lane circuit, and the first switch circuit is further arranged to selectively redirect the second received signal at the output port of the second lane circuit to the clock input port of the first lane circuit; and the reconfiguration circuit further comprises: a second switch circuit, coupled to an output port and a clock input port of the third lane circuit and an output port and a clock input port of the fourth lane circuit, wherein the second switch circuit comprises switches, and is arranged to:\n selectively redirect the third received signal at the output port of the third lane circuit to the clock input port of the fourth lane circuit; and \n selectively redirect the fourth received signal at the output port of the fourth lane circuit to the clock input port of the third lane circuit; and \n a third switch circuit, coupled to the output ports and the clock input ports of the first lane circuit, the second lane circuit, the third lane circuit and the fourth lane circuit, and an output port and a clock input port of the fifth lane circuit, wherein the third switch circuit comprises switches, and is arranged to:\n selectively redirect the first received signal at the output port of the first lane circuit to the clock input ports of the second lane circuit, the third lane circuit, the fourth lane circuit and the fifth lane circuit; \n selectively redirect the second received signal at the output port of the second lane circuit to the clock input ports of the first lane circuit, the third lane circuit, the fourth lane circuit and the fifth lane circuit; \n selectively redirect the third received signal at the output port of the third lane circuit to the clock input ports of the first lane circuit, the second lane circuit, the fourth lane circuit and the fifth lane circuit; \n selectively redirect the fourth received signal at the output port of the fourth lane circuit to the clock input ports of the first lane circuit, the second lane circuit, the third lane circuit and the fifth lane circuit; and \n selectively redirect the fifth received signal at the output port of the fifth lane circuit to the clock input ports of the first lane circuit, the second lane circuit, the third lane circuit and the fourth lane circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 3.58537
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15262280', '14491884', '14250119', '14939692', '14462327']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6926808908050058
- 35 USC 102 Novelty (BERT): 0.4897771820385714
- Combined Prediction Score: 0.6723905199283624
- Mean Citation Score: 173.56991999999997
- Max Citation Score: 181.8552
- Similarity Product: 115.41479144210815

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test