PATENT CLAIM ANALYSIS

Application Number: 16101528
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-01
Patent Classification: ["257", "401000"]

Abstract:
The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU 1 ) and a first pull-down transistor (PD 1 ), the second inverter includes a second pull-up transistor (PU 2 ) and a second pull-down transistor (PD 2 ). A dummy layer crossing the first a region and the second region, and between the PD 1  in the first region and the PD 1  in the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

Claim (Index 11):
The static random access memory layout pattern of  claim 1 , wherein the dummy layer is an integrally formed structure.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 96.0
- Lexical Diversity: 2.53125
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15795247', '15088122', '15795270', '12721476', '15599581']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.923620941550723
- 35 USC 102 Novelty (BERT): 0.5348779195652458
- Combined Prediction Score: 0.8847466393521753
- Mean Citation Score: 311.2366580000001
- Max Citation Score: 345.16296
- Similarity Product: 235.00528113527287

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test