PATENT CLAIM ANALYSIS

Application Number: 16051281
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "063000"]

Abstract:
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Claim (Index 1):
An apparatus comprising:\n a plurality of data lines configured to transfer respective signals within a plurality of memory cells, a data line of the plurality of data lines being divided into two data line segments; and a bidirectional buffer interposed between the two data line segments; wherein the bidirectional buffer comprises a first transistor coupled to a first of the two data line segments, a second transistor coupled to the first of the two data line segments, a third transistor coupled to a second of the two data line segments, and a fourth transistor coupled to the second of the two data line segments; and wherein the bidirectional buffer is configured in a precharge mode to decouple the two data line segments from each other by disabling each of the first, second, third and fourth transistors; and wherein the bidirectional buffer is further configured in an operation mode to couple the first of the two data line segments to the second of the two data line segments by enabling the first transistor and enabling the fourth transistor via the enabled first transistor, and to couple the second of the two data line segments to the first of the two data line segments by enabling the third transistor and enabling the second transistor via the enabled third transistor.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 95.0
- Lexical Diversity: 2.32836
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15405839', '13846452', '12353661', '13071303', '11367467']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8255625581757589
- 35 USC 102 Novelty (BERT): 0.5335496469550618
- Combined Prediction Score: 0.7963612670536891
- Mean Citation Score: 335.3682520000001
- Max Citation Score: 390.21143
- Similarity Product: 385.5278832387794

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test