PATENT CLAIM ANALYSIS

Application Number: 16029058
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "211000"]

Abstract:
A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

Claim (Index 3):
The zero counter according to  claim 2 , wherein the at least one hardware logic block in the plurality of hardware logic blocks comprises:\n a low section hardware logic block arranged to generate two outputs, the first output, D(v L ), being equal to one if there is no trailing one in an even column of the received section and the second output, B(v L ), being equal to one if there is a one in an odd indexed column of the received section, and a high section hardware logic block arranged to generate one output, G(v H ), being equal to one if there is a trailing one in an odd indexed column of the received section, and wherein the combining logic is arranged to generate the bit of the output value by combining the outputs of the high and low section hardware logic blocks using:\n D ( v L )\u00b7( B ( v L )+ G ( v H )) \n where:\n . represents an AND function, and \n + represents an OR function.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 2.10667
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15810081', '15218306', '15426907', '14598459', '15636100']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5574428182745529
- 35 USC 102 Novelty (BERT): 0.5886080387988214
- Combined Prediction Score: 0.5605593403269797
- Mean Citation Score: 424.202142
- Max Citation Score: 479.53256
- Similarity Product: 464.55356995040887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test