PATENT CLAIM ANALYSIS

Application Number: 15976287
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["327", "536000"]

Abstract:
An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

Claim (Index 17):
The analog time delay filter circuit of  claim 16 , wherein the analog time delay filter circuit is additionally coupled to a secondary coupled circuit at the second other side of the second substrate; wherein the secondary coupled circuit is electrically coupled to the primary coupled circuit via at least two of the first, second, third, and fourth, fifth, sixth, seventh, and eighth circuit pass-throughs.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 2.7037
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15496948', '15652643', '15382335', '15497167', '13494263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7882855060712399
- 35 USC 102 Novelty (BERT): 0.488323285245556
- Combined Prediction Score: 0.7582892839886716
- Mean Citation Score: 169.500123
- Max Citation Score: 289.7153
- Similarity Product: 256.5669224694252

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test