PATENT CLAIM ANALYSIS

Application Number: 15984107
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "148000"]

Abstract:
Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Claim (Index 9):
The method of  claim 8 , wherein at least one Y-line pass gate is disposed in a logic layer between the substrate and a bottommost memory layer.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 93.0
- Lexical Diversity: 2.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14526894', '13588461', '12657911', '12658138', '13840759']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8213316146731452
- 35 USC 102 Novelty (BERT): 0.4976925900011941
- Combined Prediction Score: 0.7889677122059501
- Mean Citation Score: 223.172836
- Max Citation Score: 277.69244
- Similarity Product: 211.82150305114268

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test