PATENT CLAIM ANALYSIS

Application Number: 16184607
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["365", "233100"]

Abstract:
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Claim (Index 2):
A configurable non-volatile memory device comprising:\n plurality of non-volatile memory blocks; a chip enable port configured to receive a chip enable signal for enabling the configurable non-volatile memory device; a first clock input port configured to receive a first clock input signal; a second clock input port configured to receive a second clock input signal, the second clock input signal being complementary to the first clock input signal; a clock output port configured to transfer a clock output signal, wherein the clock output signal is referenced to the first clock input signal; a configurable data interface configurable to an n-bit width where n is a non-zero integer, and further configurable to one of single data rate configuration and double data rate configuration, the data interface configured to transfer common data signals carrying at least one of command data, address data, input data and output data, the input data to be programmed into one of the plurality of non-volatile memory blocks accessible based on the command data and the address data, and the output data to be retrievable from the one of the plurality of non-volatile memory blocks; a configurable clock input buffer configurable to one of a single ended signaling configuration and a differential signaling configuration, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal; and one or more configurable output buffers configurable to one of a plurality of output buffer drive strengths to transfer the output data retrieved from the one of the plurality of non-volatile memory blocks.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 98.0
- Lexical Diversity: 2.53125
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15957120', '15378650', '15655336', '13006005', '15183162']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7944794354444977
- 35 USC 102 Novelty (BERT): 0.5195957913882886
- Combined Prediction Score: 0.7669910710388769
- Mean Citation Score: 319.365812
- Max Citation Score: 346.58768
- Similarity Product: 334.75162657461163

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test