PATENT CLAIM ANALYSIS

Application Number: 15970724
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "713000"]

Abstract:
A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Claim (Index 8):
A method, comprising:\n forming a plurality of connection areas on a semiconductor integrated circuit die; forming a thermal mount comprising a plurality of pillars projecting from a surface thereof, each pillar of the plurality of pillars having an aspect ratio greater than 1:1 and each pillar of the plurality of pillars positioned to connect to one connection area of the plurality of connection areas on a peripheral portion of the semiconductor integrated circuit die; and connecting each pillar of the plurality of pillars to a respective one connection area of the plurality of connection areas with one interface layer of a plurality of interface layers, wherein each connection area of the plurality of connection areas, the thermal mount, each pillar of the plurality of pillars and each interface layer of the plurality of interface layers has a thermal conductivity greater than or equal to 60 Watts per meter degree Kelvin (W/m\u00b7K), wherein flexure of the plurality of pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount, and wherein each pillar of the plurality of pillars has an aspect ratio dependent upon a position of one connection area of the plurality of connection areas corresponding to the respective pillar relative to a center of the semiconductor integrated circuit die, and wherein pillars of the plurality of pillars that are further from the center have a greater aspect ratio than pillars of the plurality of pillars that are closer to the center.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 93.0
- Lexical Diversity: 2.0274
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10820484', '10719451', '14509785', '14850070', '11126571']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914499814305609
- 35 USC 102 Novelty (BERT): 0.4796422019298409
- Combined Prediction Score: 0.8710140530680321
- Mean Citation Score: 197.528338
- Max Citation Score: 199.61003
- Similarity Product: 151.06958136867226

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test