PATENT CLAIM ANALYSIS

Application Number: 16118243
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["438", "108000"]

Abstract:
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Claim (Index 31):
A method according to  claim 17  wherein said process steps comprise:\n providing a first set of middle of the line (MOL) interconnects for said SOI circuits;\n patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer; \n filling and planarizing said vias and said alignment marks with metal; \n completing a first set of BEOL interconnects to connect said SOI circuits; \n providing a first set of bonding pad level atop said first set of BEOL interconnects; \n fabricating a second device wafer with a second set of circuits comprising a second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads; \n flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other; \n bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads; \n removing said silicon substrate from said first SOI wafer by a grinding, polishing and etching or combinations thereof and stopping on said BOX layer and exposing said metal filled vias and alignment marks; \n fabricating a third set of interconnects atop said BOX layer using said alignment marks as reference and connecting to the exposed ends of said vias; and \n providing input output pads and solder connection means atop the top surface of said third set of interconnects to enable connections to a packaging substrate. \n \n associated with said fabrication of said first SOI wafer, bonding, removing said silicon substrate below said BOX layer, and providing additional interconnects atop said BOX layer are repeated using additional SOI wafers so as to enable the incorporation of additional device layers in said 3D stack.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 1.81481
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13016994', '12763596', '13534067', '14537627', '12684779']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8356552269292876
- 35 USC 102 Novelty (BERT): 0.5541329892226019
- Combined Prediction Score: 0.8075030031586191
- Mean Citation Score: 259.32126800000003
- Max Citation Score: 415.94525
- Similarity Product: 308.45266608247164

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test