PATENT CLAIM ANALYSIS

Application Number: 15573904
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "158000"]

Abstract:
A memory circuit ( 11 ) includes: a memory cell (MC ij ) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MC ij ) to be read into a data voltage; a reference circuit (RC1) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MC ij  and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RC i ) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MC ij ) by comparing the data voltage with the reference voltage.

Claim (Index 11):
The memory circuit according to  claim 10 , wherein the plurality of variable-resistance elements included in the reference circuit comprise magnetic tunneling junction elements arranged to be oriented in a same direction.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 96.0
- Lexical Diversity: 2.56452
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15249845', '15068580', '10663674', '10384741', '14730629']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.801065715918828
- 35 USC 102 Novelty (BERT): 0.501276718652097
- Combined Prediction Score: 0.7710868161921549
- Mean Citation Score: 266.77263800000003
- Max Citation Score: 273.89517
- Similarity Product: 216.61712493828887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test