PATENT CLAIM ANALYSIS

Application Number: 15870632
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["712", "002000"]

Abstract:
Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

Claim (Index 27):
The apparatus of  claim 21 , wherein the first buffer and the plurality of second buffers are first in first out (FIFO) buffers.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.5122
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14752047', '14975847', '15282372', '15589653', '15396402']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5752768414787931
- 35 USC 102 Novelty (BERT): 0.5199461838280844
- Combined Prediction Score: 0.5697437757137223
- Mean Citation Score: 231.024918
- Max Citation Score: 322.3553
- Similarity Product: 217.0091880962432

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test