PATENT CLAIM ANALYSIS

Application Number: 16009331
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["257", "329000"]

Abstract:
Disclosed are embodiments of a semiconductor structure that includes a vertical field effect transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an isolation fin. The semiconductor fin extends vertically between lower and upper source/drain regions. The isolation fin is adjacent to and in end-to-end alignment with the semiconductor fin. The VFET gate has a main section that wraps around an outer end and opposing sidewalls of the semiconductor fin and an extension section that extends from the main section along at least the opposing sidewalls of a lower portion the isolation fin and, optionally, around an outer end of that lower portion. A gate contact lands on the isolation fin and extends along the opposing sidewalls and, optionally, the outer end of the isolation fin down to the extension section. Also disclosed are method embodiments for forming these structures.

Claim (Index 14):
A method of forming a semiconductor structure, the method comprising:\n forming a fin-shaped body on a substrate, the fin-shaped body comprising:\n a semiconductor fin having first opposing sidewalls; and \n an isolation fin having second opposing sidewalls, wherein the isolation fin is positioned laterally immediately adjacent to and in end-to-end alignment with the semiconductor fin such that the semiconductor fin and the isolation fin are essentially perpendicular to the substrate, such that the semiconductor fin and the isolation fin are oriented in a same direction across the substrate, and such that an end of the semiconductor fin abuts an adjacent end of the isolation fin; \n forming a gate laterally surrounding the fin-shaped body and having a main section and an extension section,\n wherein the main section is adjacent to the first opposing sidewalls and wrapping around a first end of the semiconductor fin, \n wherein the extension section is adjacent to the second opposing sidewalls and wrapping around a second end of the isolation fin, \n wherein the semiconductor fin extends essentially vertically between a first source/drain region and a second source/drain region, \n wherein the first source/drain region is in the substrate and the second source/drain region is above the main section of the gate, and \n wherein a lower portion of the isolation fin contacts the first source/drain region and an upper portion of the isolation fin extends above the extension section of the gate and contacts the second source/drain region; and \n forming a gate contact to the extension section of the gate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.28986
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15676219', '15873156', '15994392', '15709500', '15723472']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9383140171943324
- 35 USC 102 Novelty (BERT): 0.5718640198015286
- Combined Prediction Score: 0.901669017455052
- Mean Citation Score: 418.613706
- Max Citation Score: 479.88373
- Similarity Product: 404.7651734170365

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test