PATENT CLAIM ANALYSIS

Application Number: 16026081
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["323", "280000"]

Abstract:
A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V fb . The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor M P  is connected to the output terminal of the error amplifier, the source terminal of the power transistor M P  is connected to an input voltage V IN , and the drain terminal of the power transistor M P  is grounded.

Claim (Index 2):
The ripple pre-amplification based fully integrated low dropout regulator according to  claim 1 , wherein\n the transconductance amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; wherein a gate terminal of the second PMOS transistor serve as the negative input terminal of the transconductance amplifier, and a gate terminal of the third PMOS transistor serve as the positive input terminal of the transconductance amplifier; a drain terminal of the first PMOS transistor is connected to source terminals of the second PMOS transistor and the third PMOS transistor, and a gate terminal of the first PMOS transistor is connected to a bias voltage; the first NMOS transistor and the third NMOS transistor constitute a first current mirror, a first mirror ratio is 1:K 1 ; the second NMOS transistor and the fourth NMOS transistor constitute a second current mirror, and a second mirror ratio is 1:K 1 ; a gate terminal and a drain terminal of the first NMOS transistor are short-circuited and connected to a drain terminal of the second PMOS transistor and a gate terminal of the third NMOS transistor; a gate terminal and a drain terminal of the second NMOS transistor are short-circuited and connected to a drain terminal of the third PMOS transistor and a gate terminal of the fourth NMOS transistor; a gate terminal and a drain terminal of the fifth PMOS transistor are short-circuited and connected to a drain terminal of the third NMOS transistor and a gate terminal of the fourth PMOS transistor; a drain terminal of the fourth NMOS transistor and a drain terminal of the fourth PMOS transistor are connected to each other and serve as the output terminal of the transconductance amplifier; source terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected to the ground; and source terminals of the first PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are connected to the input voltage.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 95.0
- Lexical Diversity: 3.41667
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15690290', '15387678', '15509202', '15776780', '11775105']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7975748920885254
- 35 USC 102 Novelty (BERT): 0.5602769818789326
- Combined Prediction Score: 0.7738451010675661
- Mean Citation Score: 378.515386
- Max Citation Score: 461.67987
- Similarity Product: 373.5211740777201

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test