PATENT CLAIM ANALYSIS

Application Number: 16045956
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "185170"]

Abstract:
A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Claim (Index 1):
A memory system comprising:\n a nonvolatile semiconductor memory device comprising:\n first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; \n a bit line electrically connected to the first and the second strings; \n a first select gate line electrically connected to a gate of the select transistor of the first string; \n a second select gate line electrically connected to a gate of the select transistor of the second string; \n a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; \n a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, \n a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; and \n a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string, and \n a controller configured to perform a first write process, to perform a second write process after the first write process, to perform a third write process after the second write process, and to perform a fourth write process after the third write process, wherein the first write process includes writing data in the first memory cell of the first string and writing data in the second memory cell of the first string after the writing in the first memory cell of the first string, the second write process includes writing data in the first memory cell of the second string and writing data in the second memory cell of the second string after the writing in the first memory cell of the second string, the third write process includes writing data in the third memory cell of the first string and writing data in the fourth memory cell of the first string after the writing in the third memory cell of the first string, and the fourth write process includes writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 95.0
- Lexical Diversity: 2.85366
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15230857', '14200641', '13779427', '14847086', '14833719']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7648198111823614
- 35 USC 102 Novelty (BERT): 0.5061669555655677
- Combined Prediction Score: 0.7389545256206821
- Mean Citation Score: 238.338484
- Max Citation Score: 317.62735
- Similarity Product: 315.3669939195543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test