PATENT CLAIM ANALYSIS

Application Number: 15955822
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

Claim (Index 10):
The method of  claim 9 , further comprising forming the bottom source/drain region on the top surface of the substrate surrounding the first portion of the sidewalls of the at least one fin exposed by etching the spacer material.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.84444
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15804622', '15845594', '15705888', '15830665', '15285739']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9276312081328963
- 35 USC 102 Novelty (BERT): 0.5130166843016869
- Combined Prediction Score: 0.8861697557497754
- Mean Citation Score: 300.586056
- Max Citation Score: 309.47324
- Similarity Product: 233.2813079167985

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test