PATENT CLAIM ANALYSIS

Application Number: 16013214
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["438", "296000"]

Abstract:
A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

Claim (Index 11):
The method as recited in  claim 1 , further comprising:\n depositing and planarizing a dielectric fill to fill in gaps between the gate structures in the device region and the cut region; and recessing the dielectric fill to form the recessed dielectric fill and to expose a cap layer at a top portion of the gate structures.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.72917
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14799297', '15156651', '15282836', '14810143', '15449218']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8922085371566585
- 35 USC 102 Novelty (BERT): 0.5814392835984593
- Combined Prediction Score: 0.8611316118008386
- Mean Citation Score: 402.870772
- Max Citation Score: 488.10617
- Similarity Product: 446.7961094955015

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test