PATENT CLAIM ANALYSIS

Application Number: 15992473
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-10
Patent Classification: ["257", "532000"]

Abstract:
Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias.

Claim (Index 18):
The I/O of  claim 17 , further comprising:\n a first interlevel metal via to couple a top planar surface of the BEOL resistor layer to a bottom planar surface of the first BEOL metal layer; and a second interlevel metal via to couple the bottom planar surface of the first BEOL metal layer to a top planar surface of the second BEOL metal layer.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 93.0
- Lexical Diversity: 2.12727
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15351584', '12271942', '13489257', '12559401', '14338354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9071717363484192
- 35 USC 102 Novelty (BERT): 0.4804390068157813
- Combined Prediction Score: 0.8644984633951556
- Mean Citation Score: 158.873018
- Max Citation Score: 162.48273
- Similarity Product: 111.14923038625004

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test