PATENT CLAIM ANALYSIS

Application Number: 16201744
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["177", "025120"]

Abstract:
A system includes modules forming an array. Each module is coupled to a neighboring module and includes flexures. Each flexure is configured to measure a load value of the module. A module board is connected to the flexures, configured to receive the load value and combine into a load module output. The load module output is within an initial module output range. A resistor is configured to set the initial module output range, which is the same for each module in the array. A microcontroller is configured to receive an input for the initial module output range, which is a difference between an output for a full-load state and a zero-load state, and configured to receive the load module output of each module, convert the load module output into a bit number, scale the bit number to generate an adjusted bit number. This represents a weight applied to the array.

Claim (Index 4):
The system of  claim 1 , further comprising an analog to digital converter connected to the microcontroller and configured to receive the load module output and generate the bit number.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.77966
- Patent Class: 177.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14218970', '14873844', '14454845', '15808189', '13726450']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5657612115233734
- 35 USC 102 Novelty (BERT): 0.5002103880898209
- Combined Prediction Score: 0.5592061291800182
- Mean Citation Score: 146.37729
- Max Citation Score: 163.08505
- Similarity Product: 86.06380222657324

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test