PATENT CLAIM ANALYSIS

Application Number: 16036592
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "382000"]

Abstract:
Methods for forming semiconductor devices herein may include forming a trench in a substrate layer, wherein a hardmask is disposed atop the substrate layer, and implanting the trench at an angle relative to a top surface of the hardmask. The method may further include forming an oxide layer within the trench, wherein a thickness of the oxide layer along a bottom portion of the trench is greater than a thickness of the oxide layer along an upper portion of the trench.

Claim (Index 10):
The method of  claim 8 , further comprising:\n removing, from the set of dummy gates and the set of active gates, the following: the etch stop layer, the dummy gate material, and the hardmask; forming a gate dielectric within the set of active gates and the set of dummy gates; depositing a metal over the gate dielectric within the set of active gates and the set of dummy gates; recessing the gate dielectric and the metal within the set of active gates and the dummy gates; forming a capping layer over the gate dielectric and the metal within the set of active gates; and forming a set of S/D contacts between the set of active gates and the set of active gates.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15282836', '15415446', '15397978', '15249534', '14863079']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9221227658743376
- 35 USC 102 Novelty (BERT): 0.500308667530126
- Combined Prediction Score: 0.8799413560399164
- Mean Citation Score: 259.15928
- Max Citation Score: 264.69427
- Similarity Product: 197.3726727404249

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test