PATENT CLAIM ANALYSIS

Application Number: 16145205
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["327", "261000"]

Abstract:
A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.

Claim (Index 8):
The system on chip as recited in  claim 1 , wherein the voltage regulator has a current mirror circuit; when the current setting signal is enabled, a mirror multiple of the current mirror circuit is set to a maximum value so that the voltage regulator is in the high current mode; and when the current setting signal is disabled, the mirror multiple of the current mirror circuit is set to a minimum value so that the voltage regulator is in the low current mode.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 3.36364
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11257706', '14451446', '12554076', '12979705', '10617180']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7759709888010755
- 35 USC 102 Novelty (BERT): 0.4644148966145582
- Combined Prediction Score: 0.7448153795824237
- Mean Citation Score: 163.306062
- Max Citation Score: 177.36598
- Similarity Product: 142.119456855042

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test