PATENT CLAIM ANALYSIS

Application Number: 15908832
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "103000"]

Abstract:
A memory system includes a non-volatile memory device and a memory controller. The memory controller includes a first counting circuit configured to count a number of times reading is performed on a first unit of data, a second counting circuit configured to count a number of times reading is performed on a second unit of data, which has a size smaller than that of the first unit of data and is a part of the first unit of data, when the number of times reading has been performed on the first unit of data exceeds a first threshold value, and a cache control circuit configured to cache the second unit of data in response to a read request for the second unit of data, when the number of times reading has been performed on the second unit of data exceeds a second threshold value.

Claim (Index 16):
The method according to  claim 15 , further comprising:\n upon performing the refresh operation on the first unit of data, resetting the number of times reading has been performed on the first unit of data to zero and also resetting the number of times reading has been performed on the second unit of data to zero.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.14583
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15135953', '15333197', '15402522', '15080592', '14677361']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4926977397428064
- 35 USC 102 Novelty (BERT): 0.4744356385942546
- Combined Prediction Score: 0.4908715296279512
- Mean Citation Score: 147.51022799999996
- Max Citation Score: 149.77864
- Similarity Product: 102.90869767609595

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test