PATENT CLAIM ANALYSIS

Application Number: 16022543
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["711", "122000"]

Abstract:
There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

Claim (Index 15):
The computing apparatus of  claim 1 , wherein the peripheral device is a cache-coherent core-to-core network interface over a peripheral component interconnect express (PCIe) interconnect.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 94.0
- Lexical Diversity: 2.32075
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11823325', '11726238', '15721249', '13702547', '15823516']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4635221209152471
- 35 USC 102 Novelty (BERT): 0.482993784735897
- Combined Prediction Score: 0.4654692872973122
- Mean Citation Score: 128.25142799999998
- Max Citation Score: 135.46013
- Similarity Product: 91.1333937117511

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test