PATENT CLAIM ANALYSIS

Application Number: 16355740
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["257", "774000"]

Abstract:
Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.

Claim (Index 16):
A system as stated in  claim 1 , wherein said three dimensional chip is used in wireless network routers.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 99.0
- Lexical Diversity: 1.4
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12205875', '13192217', '13456968', '12889615', '13304968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9254627335765158
- 35 USC 102 Novelty (BERT): 0.548782346799186
- Combined Prediction Score: 0.8877946948987828
- Mean Citation Score: 266.39407600000004
- Max Citation Score: 415.04346
- Similarity Product: 306.5244874020195

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test