PATENT CLAIM ANALYSIS

Application Number: 16184284
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-06
Patent Classification: ["710", "110000"]

Abstract:
Systems, methods, and apparatus for optimizing bus latency using bit-interleaved bidirectional transmission on a serial bus are described. A method performed at a device coupled to a serial bus includes pairing with a second device in a transaction to be conducted over the serial bus, transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus, and receiving a second data bit transmitted by the second device on the data line in a second part of each cycle. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.

Claim (Index 22):
The apparatus of  claim 21 , wherein the serial bus is operated in accordance with a radio frequency front-end (RFFE) protocol or a system power management interface (SPMI) protocol.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 2.14286
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16162583', '16036273', '16167193', '16036416', '16142419']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7524837283932267
- 35 USC 102 Novelty (BERT): 0.5408328868237814
- Combined Prediction Score: 0.7313186442362822
- Mean Citation Score: 321.881096
- Max Citation Score: 402.16873
- Similarity Product: 320.88878413561343

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test