PATENT CLAIM ANALYSIS

Application Number: 16081215
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "369000"]

Abstract:
Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

Claim (Index 8):
The integrated circuit of  claim 1 , wherein the material is in direct contact with the at least one of the source or drain regions.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 2.175
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15778863', '15115852', '15753739', '15777707', '15862064']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9147650771949772
- 35 USC 102 Novelty (BERT): 0.4745063685638606
- Combined Prediction Score: 0.8707392063318656
- Mean Citation Score: 145.54967599999995
- Max Citation Score: 148.3685
- Similarity Product: 105.62400323036314

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test