PATENT CLAIM ANALYSIS

Application Number: 16203847
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["711", "105000"]

Abstract:
A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

Claim (Index 14):
The system of  claim 9 , wherein the cache further comprises a data storage coupled to the cache controller, wherein the cache controller comprises a data decoder coupled to the data storage, and wherein to increase the number of ways, the cache controller is to reconfigure the data decoder to access the data storage according to a plurality of sets of ways matching the increase in the number of ways.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.34146
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15373701', '14709323', '15794172', '15206589', '15843292']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4974168432005006
- 35 USC 102 Novelty (BERT): 0.5268375662707191
- Combined Prediction Score: 0.5003589155075224
- Mean Citation Score: 224.49737800000003
- Max Citation Score: 329.0537
- Similarity Product: 256.2609450047135

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test