PATENT CLAIM ANALYSIS

Application Number: 16244002
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["327", "175000"]

Abstract:
Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

Claim (Index 8):
The clock distribution circuitry as claimed in  claim 6 , wherein cross-coupled inverters are connected between corresponding or like positions along the parallel clock paths.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 99.0
- Lexical Diversity: 2.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16244025', '13295875', '13930662', '11101958', '11671383']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.779047696135085
- 35 USC 102 Novelty (BERT): 0.4965853097111677
- Combined Prediction Score: 0.7508014574926933
- Mean Citation Score: 192.673962
- Max Citation Score: 248.65811
- Similarity Product: 179.5340462611884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test