PATENT CLAIM ANALYSIS

Application Number: 15960475
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "156000"]

Abstract:
Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

Claim (Index 17):
An integrated circuit, comprising:\n a bitcell coupled to a bitline; read and write circuitry having a first column multiplexer device and a second column multiplexer device, wherein the first column multiplexer device is coupled to the bitline between the bitcell and a write driver, and wherein the second column multiplexer device is coupled to the bitline between the bitcell and a sense amplifier; multiple signal lines including a first signal line, a second signal line, a third signal line, and a fourth signal line, wherein the first signal line is coupled to a gate of the first column multiplexer device and provides a first transition signal, wherein the second signal line is coupled to the write driver and provides a second transition signal that is substantially similar to the first transition signal, wherein the third signal line is coupled to a gate of the second column multiplexer device and provides a third transition signal, and wherein the fourth signal line is coupled to a logic device and provides a fourth transition signal that is substantially similar to the third transition signal; and multiple coupling devices including a first coupling device and a second coupling device, wherein the first coupling device is coupled between the first signal line and the second signal line, and wherein the second coupling device is coupled between the third signal line and the fourth signal line.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 91.0
- Lexical Diversity: 2.70455
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15907951', '15256200', '15891212', '15188873', '15477516']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7660790655460624
- 35 USC 102 Novelty (BERT): 0.4880823733361141
- Combined Prediction Score: 0.7382793963250676
- Mean Citation Score: 219.36693800000003
- Max Citation Score: 242.19717000000003
- Similarity Product: 193.4581903043336

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test