PATENT CLAIM ANALYSIS

Application Number: 15871643
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["327", "109000"]

Abstract:
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Claim (Index 19):
The method of  claim 18 , wherein the first supply voltage and the second supply voltage are inverted versions of each other.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 1.35211
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15256453', '15279302', '12735954', '15376471', '14638917']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7286271003724883
- 35 USC 102 Novelty (BERT): 0.5331701292761054
- Combined Prediction Score: 0.7090814032628501
- Mean Citation Score: 253.206168
- Max Citation Score: 376.70914
- Similarity Product: 230.24549264640928

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test