PATENT CLAIM ANALYSIS

Application Number: 15859726
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["370", "411000"]

Abstract:
Systems and methods to automatically generate various multi-stage pyramid network based fabrics, applicable to including Field programmable gate arrays, are disclosed. Significantly optimized multi-stage pyramid networks either partially connected or fully connected, useful in wide target applications, with VLSI layouts (or floor plans) substantially using horizontal and vertical links to route signals between inlet and outlet links of large scale sub-integrated circuit blocks and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks, (for example in an FPGA where the sub-integrated circuit blocks are Lookup Tables, or memory blocks, or DSP blocks) are disclosed. The optimized multi-stage networks in each block employ a plurality of slices of rings of stages of switches with different size multiplexer having inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side, or from right-hand side, or from both left-hand side and right-hand side, or through any incoming and outgoing links of any stage. The VLSI layouts exhibit spatial locality so that sub-integrated circuit blocks that are spatially nearer are connected with shorter hop wires. Fabrics are generated iteratively either manually or automatically by changing different parameters including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers which may be in any switch, connections between stages of rings which may be between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

Claim (Index 1):
A two-dimensional layout of hierarchical routing network comprising a total of a\u00d7b blocks with one side of said layout having the size of a blocks and the other side of said layout having the size of b blocks where a\u22651 and b\u22651, and\n Said routing network comprising a total of N 1  inlet links and a total of N 2  outlet links wherein either N 2 =N 1 \u00d7d 2 , N 1 =(a\u00d7b)\u00d7d, and said each block comprising d inlet links and d\u00d7d 2  outlet links, and said each block comprising r rings where d 2 =r\u00d7p, and y r  hierarchical stages in each said ring, (i.e., the number of stages in ring 1 is y 1 , the number of stages in ring 2 is y 2 , . . . , and the number of stages in ring r is y r ), where r\u22651; p\u22652; or N 1 =N 2 \u00d7d 1 , N 2 =(a\u00d7b)\u00d7d, and said each block comprising d outlet links and d\u00d7d 1  inlet links, and said each block comprising r rings where d 1 =r\u00d7p, and y r  hierarchical stages in each said ring, (i.e., the number of stages in ring 1 is y 1 , the number of stages in ring 2 is y 2 , . . . , and the number of stages in ring r is y r ), where r\u22651, p\u22652, y r \u22651; and Said each stage comprising a switch of size d\u00d7d, where d\u22654 and each said switch of size d\u00d7d having d incoming links and d outgoing links; and Said all inlet links are connecting to one or more of the said incoming links of any said switch of any stage of any ring of any block, and said all outlet links are connecting from one or more of the said outgoing links of any said switch of any stage of any ring of any block, Said incoming links and outgoing links in each switch in said each stage of said each block comprising a plurality of forward connecting links connecting from switches in lower stage to switches in the immediate succeeding higher stage in the same ring, and also comprising a plurality of backward connecting links connecting from switches in higher stage to switches in the immediate preceding lower stage in the same ring; and Said forward connecting links comprising a plurality of straight links connecting from a switch in a stage of a ring in a block to a plurality of switches in a plurality of stages of the same ring in the same block and also comprising a plurality of cross links connecting from a switch in a stage of a ring in a block to a plurality of switches in a plurality of stages of another ring in the same block or to a plurality of switches in a plurality of stages of another ring in a different block, and Said backward connecting links comprising a plurality of straight links connecting from a switch in a stage of a ring in a block to a plurality of switches in a plurality of stages of the same ring in the same block and also comprising a plurality of cross links connecting from a switch in a stage of a ring in a block to a plurality of switches in a plurality of stages of another ring the same block or to a plurality of switches in a plurality of stages of another ring in a different block.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 2.37584
- Patent Class: 370.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14329876', '14199168', '15140470', '15331855', '14522599']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6106009131384816
- 35 USC 102 Novelty (BERT): 0.6040234696361966
- Combined Prediction Score: 0.6099431687882532
- Mean Citation Score: 494.5352959999999
- Max Citation Score: 556.9894
- Similarity Product: 470.3187555174352

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test