PATENT CLAIM ANALYSIS

Application Number: 16195275
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["341", "069000"]

Abstract:
Transmitter circuitry transmits: a first voltage as the return-to-zero signal that is higher than a first positive threshold, the first voltage being decodable to a first order of data bits; a second voltage as a return-to-zero signal that is between a second positive threshold and the first positive threshold, the second voltage being decodable to a second order of the data bits, and the second positive threshold being lower than the first positive threshold; a third voltage as the return-to-zero signal that is between a first negative threshold and a second negative threshold, the third voltage being decodable to a third order of the data bits, and the second negative threshold being higher than the first negative threshold; and a fourth voltage as the return-to-zero signal that is lower than the first negative threshold, the fourth voltage being decodable to a fourth order of the data bits. Clock circuitry transitions a clock signal for the return-to-zero signal crossing the second positive threshold, and for the return-to-zero signal crossing the second negative threshold.

Claim (Index 1):
A method of transmitting data bits and a clock signal as a return-to-zero signal, the method comprising:\n from transmitter circuitry, transmitting a first voltage as the return-to-zero signal that is higher than a first positive threshold, the first voltage being decodable to a first order of the data bits; from the transmitter circuitry, transmitting a second voltage as the return-to-zero signal that is between a second positive threshold and the first positive threshold, the second voltage being decodable to a second order of the data bits, and the second positive threshold being lower than the first positive threshold; from the transmitter circuitry, transmitting a third voltage as the return-to-zero signal that is between a first negative threshold and a second negative threshold, the third voltage being decodable to a third order of the data bits, and the second negative threshold being higher than the first negative threshold; from the transmitter circuitry, transmitting a fourth voltage as the return-to-zero signal that is lower than the first negative threshold, the fourth voltage being decodable to a fourth order of the data bits; and transitioning the clock signal for the return-to-zero signal crossing the second positive threshold, and for the return-to-zero signal crossing the second negative threshold.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 4.74359
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14983776', '15832882', '14985254', '14317339', '10618017']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5848887152706783
- 35 USC 102 Novelty (BERT): 0.524273137347803
- Combined Prediction Score: 0.5788271574783908
- Mean Citation Score: 222.703436
- Max Citation Score: 303.67477
- Similarity Product: 236.03933961247208

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test