PATENT CLAIM ANALYSIS

Application Number: 15746553
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["365", "230060"]

Abstract:
A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.

Claim (Index 6):
Decoder of  claim 4  wherein the capacitance of said lines cooperating with said resonating circuit remains substantially constant when said input signals change.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.18056
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15746615', '12826570', '10864024', '10395306', '11633518']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7955799735591867
- 35 USC 102 Novelty (BERT): 0.5004016870032854
- Combined Prediction Score: 0.7660621449035967
- Mean Citation Score: 173.47932399999996
- Max Citation Score: 223.73317000000003
- Similarity Product: 134.73726948943258

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test