PATENT CLAIM ANALYSIS

Application Number: 16112277
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["713", "160000"]

Abstract:
An electronic circuit ( 200 ) includes one or more programmable control-plane engines ( 410, 460 ) operable to process packet header information and form at least one command, one or more programmable data-plane engines ( 310, 320, 370 ) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor ( 100 ) coupled to such a data-plane engine ( 310 ) and such a control-plane engine ( 410 ). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Claim (Index 3):
The accelerated cryptographic engine of  claim 1  in which the buffer circuitry is a FIFO buffer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 1.86441
- Patent Class: 713.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15728035', '14712396', '13165190', '15045948', '09880701']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.488061136655303
- 35 USC 102 Novelty (BERT): 0.5614443201311462
- Combined Prediction Score: 0.4953994550028874
- Mean Citation Score: 400.5185100000001
- Max Citation Score: 475.73163
- Similarity Product: 293.8230665318084

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test