PATENT CLAIM ANALYSIS

Application Number: 15984518
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["712", "001000"]

Abstract:
A multivalued microprocessor including a multivalued processing module having a plurality of multivalued processing units constructed with multivalued logic gates. The microprocessor also includes a multivalued register file having a plurality of registers, wherein the registers are constructed with multivalued memory cells. The multivalued microprocessors utilizes two memory modules constructed with multivalued memory cells: one for storing solely instructions and one for storing solely data. A plurality of multivalued buses transmit multivalued data between the processing module, the register file, and the memory modules. A methodology for designing multivalued circuits that are constructed with multivalued logic gates and memory cells. The designs of multivalued memory cells, multivalued tristate buffers, and multivalued decoders using multivalued logic gates.

Claim (Index 1):
A multivalued microprocessor configured to accept an n-valued input and generate an n-valued output, where n is at least 3, the microprocessor comprising:\n (a) a multivalued processing module including a plurality of multivalued processing units constructed of multivalued logic gates, wherein the plurality of multivalued processing units include at least a Not, an And, an Or, and an Add processing unit; (b) a multivalued register file including a plurality of registers, wherein the registers are constructed with multivalued memory cells; (c) a multivalued instruction memory constructed with multivalued memory cells, the instruction memory configured to transmit an instruction to multiple decoders; (d) a multivalued data storage constructed with multivalued memory cells; (e) a plurality of multivalued buses transmitting multivalued data between the processing module, the register file, the instruction memory, and the data storage; and (f) a multivalued tristate buffer with a control input positioned between each processing unit and the bus to which the processing unit transmits data.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 93.0
- Lexical Diversity: 2.46154
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11698160', '10773423', '10207176', '13769313', '09612797']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5488779991065565
- 35 USC 102 Novelty (BERT): 0.4737586241752034
- Combined Prediction Score: 0.5413660616134213
- Mean Citation Score: 152.4485
- Max Citation Score: 155.37236
- Similarity Product: 107.2367389127779

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test