PATENT CLAIM ANALYSIS

Application Number: 15961080
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["365", "185220"]

Abstract:
There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.

Claim (Index 9):
The memory device of  claim 7 , wherein the control logic includes a voltage setup code table in which various different voltage setup codes are stored, to output the voltage setup code.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 91.0
- Lexical Diversity: 1.80645
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15628808', '13325787', '15466070', '15651477', '13455016']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8248059359400315
- 35 USC 102 Novelty (BERT): 0.4944703162721663
- Combined Prediction Score: 0.791772373973245
- Mean Citation Score: 252.749738
- Max Citation Score: 260.07977
- Similarity Product: 191.6195855195838

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test