PATENT CLAIM ANALYSIS

Application Number: 16173583
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["716", "102000"]

Abstract:
A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

Claim (Index 20):
The method of  claim 15 , further comprising:\n comparing the schematic of the integrated circuit to the layout of the semiconductor device.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.0
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14969647', '14799762', '14193527', '12341152', '14307788']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2930659453131238
- 35 USC 102 Novelty (BERT): 0.5241648391053096
- Combined Prediction Score: 0.3161758346923424
- Mean Citation Score: 226.679828
- Max Citation Score: 374.67477
- Similarity Product: 335.49575459172434

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test