PATENT CLAIM ANALYSIS

Application Number: 16244493
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["257", "366000"]

Abstract:
Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Claim (Index 10):
A semiconductor device, comprising:\n a first semiconductor fin; a first gate stack formed over the first semiconductor fin; source and drain regions formed on respective sides of the first gate stack; an interlayer dielectric formed around the first gate stack; and a gate cut plug, comprising a first layer of dielectric material formed conformally on spacer sidewalls and a second layer of planarizing material that completely fills any space between the spacer sidewalls that is not filled by the first layer of dielectric material, at an end of the first gate stack.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 99.0
- Lexical Diversity: 1.85714
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15841933', '15841887', '15295277', '15966664', '15918668']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9187007646799924
- 35 USC 102 Novelty (BERT): 0.5085817338922017
- Combined Prediction Score: 0.8776888616012134
- Mean Citation Score: 248.258776
- Max Citation Score: 308.02228
- Similarity Product: 263.0314473117161

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test