PATENT CLAIM ANALYSIS

Application Number: 15874965
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "213000"]

Abstract:
Device and method for fabricating a field effect transistor (FET) include forming plurality of dummy dielectric layers separated by a corresponding plurality of source/drain regions overlying a substrate. One or more nanosheets of active transistor channels alternating between the plurality of dummy dielectric layers are formed extending at least part way into the plurality of source/drain regions. A high-k dielectric layer is formed about and overlying the source/drain regions and portions of the one or more nanosheets not covered by the plurality of dummy dielectric layers. A conductive metal cap layer is formed overlying the high-k dielectric layer.

Claim (Index 2):
The semiconductor device of  claim 1 , further comprising a plurality of etch stop layers formed overlying the substrate and underlying and aligned with the plurality of dummy layers.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 86.0
- Lexical Diversity: 1.85714
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15868683', '15339096', '15813634', '15868742', '13398339']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9075066909294328
- 35 USC 102 Novelty (BERT): 0.5117897672404188
- Combined Prediction Score: 0.8679349985605315
- Mean Citation Score: 259.14548
- Max Citation Score: 271.72003
- Similarity Product: 194.6306634164548

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test