PATENT CLAIM ANALYSIS

Application Number: 16052581
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Claim (Index 19):
A computer system comprising:\n a processor having a plurality of cores for executing instructions and processing data and one or more processor caches for caching instructions and data according to a first cache management policy; a first-level memory having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and a second-level memory having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory maintains its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of the computer system; a memory controller to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller configurable to cause the first level memory to operate in a plurality of different modes of operation in which the first-level memory operates as a memory cache for the second-level memory, at least one of the modes comprising a write-back caching mode of operation such that a write operation is performed to update the second-level memory only when a cache line within the first-level memory is to be replaced by another cache line.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 2.45333
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13994731', '15192871', '13997189', '15457847', '13994729']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.609497515628204
- 35 USC 102 Novelty (BERT): 0.5524638823875627
- Combined Prediction Score: 0.6037941523041399
- Mean Citation Score: 403.159092
- Max Citation Score: 423.2226
- Similarity Product: 405.61165067160135

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test