PATENT CLAIM ANALYSIS

Application Number: 15913190
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "324000"]

Abstract:
An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Claim (Index 9):
The integrated circuit of  claim 1 , wherein the circuit structure comprises a 3D memory structure; and the substrate includes a conductive layer in current flow communication with the plurality of trench conductors configured as a common source line, and one or more patterned conductor layers overlying a stack of active and inactive layers including connections to the plurality of trench conductors.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14863633', '15597965', '15344899', '11106887', '14637204']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.93081602020834
- 35 USC 102 Novelty (BERT): 0.5111729915767497
- Combined Prediction Score: 0.888851717345181
- Mean Citation Score: 241.90314400000003
- Max Citation Score: 255.32495
- Similarity Product: 164.6493721485436

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test