PATENT CLAIM ANALYSIS

Application Number: 15944032
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "171000"]

Abstract:
The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.

Claim (Index 16):
The circuit of  claim 11 , wherein the inverter comprises a PMOS device and a NMOS device, and the inverter is further configured to be between the first reference data MTJ1, the first data MTJ1, and the second data MTJ2 to create the voltage divider to mimic the at least one logic operation.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.24138
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13613205', '15636970', '12784848', '14970564', '13764139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7749952341631442
- 35 USC 102 Novelty (BERT): 0.4862813328261609
- Combined Prediction Score: 0.7461238440294459
- Mean Citation Score: 180.946558
- Max Citation Score: 188.29303
- Similarity Product: 131.64937525315406

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test