PATENT CLAIM ANALYSIS

Application Number: 16026890
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["710", "071000"]

Abstract:
An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.

Claim (Index 3):
The memory system of  claim 1 , wherein each of the DDR shift registers comprises a multiplexor that multiplexes output streams of the at least two SDR shift registers.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 95.0
- Lexical Diversity: 1.76596
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15606194', '15730552', '10613462', '15410602', '13616173']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6796393174592981
- 35 USC 102 Novelty (BERT): 0.5406759195459553
- Combined Prediction Score: 0.6657429776679639
- Mean Citation Score: 213.085498
- Max Citation Score: 390.28427
- Similarity Product: 369.2692319281417

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test