PATENT CLAIM ANALYSIS

Application Number: 16043653
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["257", "296000"]

Abstract:
Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Claim (Index 16):
An apparatus, comprising:\n a first memory cell having two transistors and one capacitor; the two transistors of the first memory cell being a first transistor and a second transistor; the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions; the capacitor of the first memory cell being a first capacitor; the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor; the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor; a second memory cell having two transistors and one capacitor; the two transistors of the second memory cell being a third transistor and a fourth transistor; the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions; the capacitor of the second memory cell being a second capacitor; the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor; the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor; the second memory cell sharing first and second comparative bitlines with the first memory cell; a first body connection line coupling the first body region of the first memory cell to a first reference voltage; a second body connection line coupling the second body region of the first memory cell to a second reference voltage; a third body connection line coupling the third body region of the second memory cell to a third reference voltage; and a fourth body connection line coupling the fourth body region of the second memory cell to a fourth reference voltage.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 95.0
- Lexical Diversity: 3.38636
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15986628', '15664143', '16033377', '15900403', '16006301']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9279912992783084
- 35 USC 102 Novelty (BERT): 0.5095478428101673
- Combined Prediction Score: 0.8861469536314943
- Mean Citation Score: 302.212054
- Max Citation Score: 316.32907
- Similarity Product: 278.86956854490995

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test