PATENT CLAIM ANALYSIS

Application Number: 15878452
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "384000"]

Abstract:
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.

Claim (Index 4):
The structure of  claim 1 , wherein a contact area between the metal contact and the self-aligned silicide contact is equal to a surface area of the first upper surface of the self-aligned silicide contact.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.13559
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15333262', '15854052', '14021594', '13957991', '15665897']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9408093460491868
- 35 USC 102 Novelty (BERT): 0.5538853938617838
- Combined Prediction Score: 0.9021169508304466
- Mean Citation Score: 335.983288
- Max Citation Score: 438.1313
- Similarity Product: 316.7184197593272

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test