PATENT CLAIM ANALYSIS

Application Number: 16158560
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["257", "076000"]

Abstract:
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

Claim (Index 16):
A method of fabricating a heterostructure semiconductor device comprising:\n forming a first active layer on a substrate, forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that a two-dimensional electron gas layer is formed therebetween; forming a first gate dielectric layer on the second active layer, the first gate dielectric layer having a first thickness, forming a second gate dielectric layer on the first gate dielectric layer, the second gate dielectric layer having a second thickness greater than the first thickness; forming a third gate dielectric layer on the second gate dielectric layer, the third gate dielectric layer having a third thickness smaller than the second thickness and greater than the first thickness; forming first and second ohmic contacts that each extend vertically through the third gate dielectric layer, the second gate dielectric layer, and the first gate dielectric layer, the first and second ohmic contacts being laterally spaced-apart and electrically connected to the second active layer; and forming a gate that contacts the third gate dielectric layer at a lateral position between the first and second ohmic contacts.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 97.0
- Lexical Diversity: 2.65116
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14539086', '13780192', '15700087', '16081012', '13533610']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9196997389044036
- 35 USC 102 Novelty (BERT): 0.4774719400495176
- Combined Prediction Score: 0.8754769590189151
- Mean Citation Score: 220.263382
- Max Citation Score: 243.29625
- Similarity Product: 221.7488065865636

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test