PATENT CLAIM ANALYSIS

Application Number: 15991268
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["257", "328000"]

Abstract:
At least one diode, lower-level metal interconnect structures embedded within lower-level dielectric material layers, and a doped semiconductor material layer are formed over a semiconductor substrate. An electrically conductive path is provided between the at least one diode and the doped semiconductor material layer. An alternating stack of insulating layers and spacer material layers and memory stack structures extending therethrough are formed above the doped semiconductor material layer. A backside trench is formed through the alternating stack. The electrically conductive path is employed during plasma etch processes employed to form the memory stack structures and the backside trench to provide a discharge path for accumulated electrical charges. The electrically conductive path is subsequently disconnected by removing a conductive component underlying the backside trench. The spacer material layers can be replaced with electrically conductive layers employing the backside trench.

Claim (Index 10):
The three-dimensional memory device of  claim 1 , wherein:\n the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; the semiconductor substrate comprises a silicon substrate; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate; and the array of monolithic three-dimensional NAND strings comprises: a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 2.07042
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15489050', '15638672', '15877219', '15175450', '15269294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.938775101961948
- 35 USC 102 Novelty (BERT): 0.5603812511150595
- Combined Prediction Score: 0.9009357168772592
- Mean Citation Score: 420.340858
- Max Citation Score: 436.81467
- Similarity Product: 411.313868797894

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test