PATENT CLAIM ANALYSIS

Application Number: 15865923
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "156000"]

Abstract:
Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.

Claim (Index 1):
A memory device comprising:\n a first memory array disposed in a first memory array layer; a second memory array disposed in a second memory array layer over the first memory array layer; a first memory layer decoder communicatively coupled to the first memory array, the first memory layer decoder being configured to decode a portion of a memory address to determine if the memory address corresponds to the first memory array; a second memory layer decoder communicatively coupled to the second memory array, the second memory layer decoder being configured to decode a portion of the memory address to determine if the memory address corresponds to the second memory array; a plurality of first word lines disposed on the first memory array layer; a plurality of second word lines disposed on the second memory array layer; a first word line driver circuit communicatively coupled to the first memory array, the first work line driver circuit of the first memory array being configured to drive one of the plurality of first word lines disposed on the first memory array layer, wherein only one word line coupled to the first memory array is selected at a time; a second word line driver circuit communicatively coupled to the second memory array, the second word line driver circuit of the second memory array being configured to drive one of the plurality of second word lines disposed on the second memory array layer, wherein only one word line coupled to the second memory array is selected at a time; and a first bit line coupled to a single memory cell in the first memory array layer and a single memory cell in the second memory array layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.46479
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14087029', '13972988', '14562056', '15199167', '09829046']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.815087943950984
- 35 USC 102 Novelty (BERT): 0.5169383573030214
- Combined Prediction Score: 0.7852729852861878
- Mean Citation Score: 280.171346
- Max Citation Score: 345.6362
- Similarity Product: 256.3625906437158

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test