PATENT CLAIM ANALYSIS

Application Number: 15745548
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["257", "072000"]

Abstract:
A array substrate comprises: a substrate including a display area and a peripheral wiring area, wherein active switches, pixel units and signal lines are disposed in the display area, the pixel units are coupled to the active switches, the active switches are coupled to the signal lines, and the signal lines include gate lines and source lines, each pixel unit includes a first subpixel and a second subpixel are coupled to different gate lines, and coupled to a common source line, input interface of the gate lines is disposed in the wiring area; a gate driving module disposed in the wiring area and including output interfaces; connecting lines disposed between the input interfaces and the output interfaces, wherein the connecting lines include wiring line groups and jumper line groups, a sequence of signals of jumper line groups is different from a sequence of signals of wiring line groups.

Claim (Index 16):
The array substrate according to  claim 1 , wherein the plurality of wiring line groups and the plurality of jumper line groups are disposed to be interlaced in a partially continuous way.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.94545
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12085529', '14296063', '12526700', '15745550', '13517872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9250907277095533
- 35 USC 102 Novelty (BERT): 0.474651538010882
- Combined Prediction Score: 0.880046808739686
- Mean Citation Score: 193.805564
- Max Citation Score: 195.40915
- Similarity Product: 156.3385153780043

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test