PATENT CLAIM ANALYSIS

Application Number: 15953708
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "669000"]

Abstract:
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Claim (Index 14):
The device of  claim 8 , wherein the first conductive feature has a first sidewall surface and the catalyst layer has a second sidewall surface that interfaces the first sidewall surface of the first conductive feature, and\n wherein the dielectric layer completely covers the first sidewall surface of the first conductive feature and the second sidewall surface of the catalyst layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 1.82609
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14266069', '13724342', '14733487', '15430852', '15088134']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8628573780785814
- 35 USC 102 Novelty (BERT): 0.4785572811895286
- Combined Prediction Score: 0.8244273683896762
- Mean Citation Score: 169.53538600000005
- Max Citation Score: 176.99858
- Similarity Product: 130.67192660725357

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test