PATENT CLAIM ANALYSIS

Application Number: 16017308
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["375", "316000"]

Abstract:
A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.

Claim (Index 5):
The receiver of  claim 2 , further comprising:\n a clock data recovery (CDR) lock detector configured to assert a lock detection signal responsive to the phase detector output signal to indicate when the divided clock signal is locked to the serial data stream, wherein the selector circuit is configured to set the adjustable divisor equal to the second divisor responsive to the assertion of the lock detection signal and to set the adjustable divisor equal to the first divisor responsive to a de-assertion of the lock detection signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 1.74286
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13235628', '15346434', '15959104', '11005465', '12372946']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4977881197921825
- 35 USC 102 Novelty (BERT): 0.4957232245236158
- Combined Prediction Score: 0.4975816302653259
- Mean Citation Score: 234.881726
- Max Citation Score: 247.64339
- Similarity Product: 185.93029154822293

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test