PATENT CLAIM ANALYSIS

Application Number: 16174088
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-06
Patent Classification: ["341", "143000"]

Abstract:
Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Claim (Index 16):
The analog-to-digital modulator circuit assembly of  claim 12  wherein the first set of capacitors are coupled to an output of the first set of integrators during the charging phase to charge the first set of capacitors.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 1.34783
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15490759', '15007054', '13205512', '12827522', '12119658']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5614318379408071
- 35 USC 102 Novelty (BERT): 0.5412785417222353
- Combined Prediction Score: 0.55941650831895
- Mean Citation Score: 230.289388
- Max Citation Score: 341.95117
- Similarity Product: 233.9132141523916

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test