PATENT CLAIM ANALYSIS

Application Number: 15925740
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["365", "185290"]

Abstract:
A non-volatile memory device including a first floating-gate element, a second floating-gate element, and a selection gate element. The first floating-gate element includes a gate electrode configured to generate a read current based on the read voltage, the control voltage, and the electrical state of the gate electrode. The second floating-gate element shares a gate electrode with the first floating-gate element and is configured to determine the electrical state of the gate electrode based on the write voltage and the control voltage. The selection gate element is electrically coupled to the first floating-gate element and the second floating-gate element and is configured to generate the control voltage according to the word driving voltage and the source driving voltage.

Claim (Index 11):
The method of  claim 8 , further comprising:\n erasing the electrical state of the first floating-gate element and the second floating-gate element, by an erase gate element electrically coupled to the gate sharing by the first floating-gate element and the second floating-gate element, according to an erase voltage in an erase voltage line.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 90.0
- Lexical Diversity: 3.0
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11492994', '12718353', '15481889', '12035412', '11488983']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8040473962999934
- 35 USC 102 Novelty (BERT): 0.4838050103196453
- Combined Prediction Score: 0.7720231577019587
- Mean Citation Score: 240.19691200000003
- Max Citation Score: 251.54062
- Similarity Product: 201.3554265178824

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test