PATENT CLAIM ANALYSIS

Application Number: 16036906
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["714", "820000"]

Abstract:
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects

Claim (Index 2):
The SoC of  claim 1  further comprising a comparator in communication with the controller, wherein the controller provides a controller output signal to the comparator and the comparator determines if there is an error when the controller determines the mismatch.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 95.0
- Lexical Diversity: 2.29167
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15391727', '15396416', '13590159', '15494544', '13994282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2356978441673395
- 35 USC 102 Novelty (BERT): 0.520961391909164
- Combined Prediction Score: 0.264224198941522
- Mean Citation Score: 180.885234
- Max Citation Score: 332.62067
- Similarity Product: 289.56349150662305

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test