PATENT CLAIM ANALYSIS

Application Number: 15918770
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "004000"]

Abstract:
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Claim (Index 14):
The memory array of  claim 10 , further comprising:\n a second plurality of memory cells, each memory cell of the second plurality coupled with a corresponding second bit line and a corresponding second word line; a second plurality of selector switches, each selector switch of the second plurality in contact with a corresponding memory cell of the second plurality; a second sealing layer in contact with an upper surface and a pair of sidewalls of each of the selector switches of the second plurality and a pair of sidewalls of each of the memory cells of the second plurality, wherein the each memory cell of the plurality is at a first level of the memory array and each memory cell of the second plurality is at a second level of the memory array.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 90.0
- Lexical Diversity: 1.47222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15297925', '12957286', '14947455', '13301521', '14571235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8920517038496675
- 35 USC 102 Novelty (BERT): 0.5027065540973326
- Combined Prediction Score: 0.853117188874434
- Mean Citation Score: 185.216794
- Max Citation Score: 242.84421
- Similarity Product: 179.3628266512871

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test