PATENT CLAIM ANALYSIS

Application Number: 15961912
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "509000"]

Abstract:
Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

Claim (Index 24):
The integrated circuit structure in  claim 21 , wherein the etch stop layer is positioned only along a first surface of the source/drain regions extending from the insulating spacers of the complementary transistors, and a second surface of the source/drain regions that is perpendicular to the first surface and that is distal to the insulating spacers.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.90244
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15164420', '15175540', '15139478', '15435894', '12473610']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9282549012098168
- 35 USC 102 Novelty (BERT): 0.5018198139107635
- Combined Prediction Score: 0.8856113924799115
- Mean Citation Score: 242.45785
- Max Citation Score: 248.73485
- Similarity Product: 175.31604891655144

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test