PATENT CLAIM ANALYSIS

Application Number: 16291231
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-06
Patent Classification: ["708", "204000"]

Abstract:
Embodiments of an instruction, its operation, and executional support for the instruction are described. In some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a single precision floating point data element of a least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as 32-bit integer and a 32-bit integer exponent in the two least significant packed data element positions of the identified packed data destination operand, and zero of all remaining packed data elements of the identified packed data destination operand.

Claim (Index 2):
The processor of  claim 1 , wherein the integer component is stored in a least significant packed data element position of the identified packed data destination operand.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.18033
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15721573', '15721602', '16291245', '13991885', '12549724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4942953676452857
- 35 USC 102 Novelty (BERT): 0.5636301606840619
- Combined Prediction Score: 0.5012288469491634
- Mean Citation Score: 286.750904
- Max Citation Score: 415.42297
- Similarity Product: 410.8503800646997

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test