PATENT CLAIM ANALYSIS

Application Number: 15956704
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "692000"]

Abstract:
A semiconductor process includes: applying an encapsulation material on an upper surface of a first substrate to encapsulate a die and first conductive parts, wherein the encapsulation material is a B-stage adhesive; forming a plurality of openings on the encapsulation material to expose the first conductive parts; pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate includes second conductive parts, and each of the first conductive parts contacts a corresponding one of the second conductive parts; and heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and solidify the encapsulation material to form a C-stage adhesive.

Claim (Index 1):
A semiconductor process comprising:\n (a) electrically connecting a die to an upper surface of a first substrate, wherein the first substrate comprises a plurality of first substrate upper conductive pads, and wherein the first substrate upper conductive pads are exposed on the upper surface of the first substrate; (b) forming a plurality of first conductive parts on the first substrate upper conductive pads; (c) applying an encapsulation material on the upper surface of the first substrate to encapsulate the die and the first conductive parts, wherein the encapsulation material is a B-stage adhesive; (d) forming a plurality of openings on the encapsulation material to expose the first conductive parts; (e) pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate comprises a plurality of second substrate lower conductive pads and a plurality of second conductive parts, wherein the second substrate lower conductive pads are exposed on the lower surface of the second substrate, wherein the second conductive parts are deposited on the second substrate lower conductive pads, and wherein each of the first conductive parts contacts a corresponding one of the second conductive parts; and (f) heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and to solidify the encapsulation material to a C-stage adhesive.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 2.62
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14303421', '14536253', '11497617', '12264823', '10785122']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9185272366397662
- 35 USC 102 Novelty (BERT): 0.543772369629695
- Combined Prediction Score: 0.8810517499387591
- Mean Citation Score: 232.586158
- Max Citation Score: 348.81067
- Similarity Product: 292.8966881106389

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test