PATENT CLAIM ANALYSIS

Application Number: 16273337
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["438", "257000"]

Abstract:
A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

Claim (Index 5):
A memory device, comprising:\n a substrate of semiconductor material of a first conductivity type; spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction; each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:\n first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, \n a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, \n a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, \n an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, \n a first coupling gate disposed over and insulated from the first floating gate, and \n a second coupling gate disposed over and insulated from the second floating gate; \n control circuitry configured to erase one of the pairs of memory cells by applying to the one pair of memory cells:\n a zero voltage to the first region, \n a zero voltage to the second region, \n a first negative voltage to the first coupling gate, \n a second negative voltage to the second coupling gate, and \n a positive voltage to the erase gate.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 99.0
- Lexical Diversity: 3.0
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11950331', '14252929', '11950345', '10863030', '15476663']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.860688014973163
- 35 USC 102 Novelty (BERT): 0.5114652354654903
- Combined Prediction Score: 0.8257657370223958
- Mean Citation Score: 301.949938
- Max Citation Score: 304.98328
- Similarity Product: 272.13701999279976

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test