PATENT CLAIM ANALYSIS

Application Number: 16153225
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "185240"]

Abstract:
Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

Claim (Index 10):
A solid state drive (SSD), comprising:\n a flash memory comprising a plurality of semiconductor dies each having programmable flash memory cells arranged into a plurality of erasure blocks, each erasure block characterized as a smallest grouping of the memory cells that can be concurrently erased on each of the associated dies; a top level controller circuit configured to interface with a host device; a read/write/erase (R/W/E) circuit configured to read data from the respective erasure blocks, write data to the respective erasure blocks and erase selected erasure blocks responsive to respective read, write and erase commands from the top level controller circuit; and a read refresh circuit configured to concurrently perform a background read operation upon the flash memory by directing the R/W/E circuit to concurrently read data from every erasure block on every die during each of a succession of time intervals to reduce first read bit errors during the reading of data by the R/W/E circuit responsive to the read commands from the top level controller circuit.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 1.81707
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15498595', '14871148', '15078151', '15585429', '13969049']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7733097202782928
- 35 USC 102 Novelty (BERT): 0.5331619302497785
- Combined Prediction Score: 0.7492949412754414
- Mean Citation Score: 272.340866
- Max Citation Score: 373.05783
- Similarity Product: 305.9676551999796

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test