PATENT CLAIM ANALYSIS

Application Number: 15957130
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.

Claim (Index 30):
A cache system comprising:\n a processor; a data-holding component, the data-holding component comprising one of (a) a register or (b) a first cache; a second cache; a system memory; an interconnect configured for communicably coupling the processor, the data-holding component, the second cache, and the system memory, wherein a first latency for transferring data from the data-holding component to the processor is smaller than a second latency for transferring data from the second cache to the processor; and wherein the cache system is configured to facilitate performance of operations, comprising:\n retrieve a set of data from a system memory for storage in the data-holding component; \n tagging a first portion of data associated with the set of data with a first indication that the first portion of data is executed data that was executed by the processor and is to be sent from the data-holding component to the system memory; \n tagging a second portion of data of the set of data with a second indication based on determining at least one of (a) that the second portion of data exceeds the storage capacity of the first cache or (b) that the second portion of data has been unused, and that the second portion is predicted to be possibly executed by the processor within a defined period of time; and \n evicting the second portion of data from the processor cache to the second cache based on the tagging of the second portion of data.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 1.85246
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14710837', '13158911', '14666771', '12637022', '09745020']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5347725625491605
- 35 USC 102 Novelty (BERT): 0.538681577656509
- Combined Prediction Score: 0.5351634640598953
- Mean Citation Score: 267.438026
- Max Citation Score: 389.95303
- Similarity Product: 312.11701792029857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test