PATENT CLAIM ANALYSIS

Application Number: 16162328
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["463", "042000"]

Abstract:
One or more hardware components identify a bottleneck stage within a processor pipeline that processes frames of a video stream. The bottleneck stage has a first clock. An upstream stage receives a feedback signal from the bottleneck stage. The upstream stage has a second clock and the feedback signal includes information as to time required by the bottleneck stage to operate on data and information as to time the data spent queued. The upstream stage adjusts the speed at which the upstream stage operates and queues data to approximate the speed at which the bottleneck stage is operating and queuing data.

Claim (Index 5):
The method of  claim 4 , wherein the first device and the second device are in different geographic locations associated with different data centers or in a same geographic location of a data center.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 1.96296
- Patent Class: 463.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15269968', '13430269', '13232985', '13232971', '13232979']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2983046775531487
- 35 USC 102 Novelty (BERT): 0.512368133937444
- Combined Prediction Score: 0.3197110231915783
- Mean Citation Score: 180.176524
- Max Citation Score: 262.8721
- Similarity Product: 134.22499353245496

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test