PATENT CLAIM ANALYSIS

Application Number: 15989873
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "031000"]

Abstract:
Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.

Claim (Index 4):
The superconducting structure of  claim 3 , wherein the third pattern mirrors the fourth pattern.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.47727
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15989925', '15934348', '15934375', '15669139', '15813441']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.93274648885784
- 35 USC 102 Novelty (BERT): 0.5835107785696569
- Combined Prediction Score: 0.8978229178290217
- Mean Citation Score: 418.66305
- Max Citation Score: 610.8532
- Similarity Product: 357.0865586323738

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test