PATENT CLAIM ANALYSIS

Application Number: 16101728
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "369000"]

Abstract:
An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.

Claim (Index 2):
The device of  claim 1 , wherein:\n the first SRAM cell is contiguous with the second SRAM cell; and the second SRAM cell is contiguous with the third SRAM cell.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 96.0
- Lexical Diversity: 2.51163
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15492777', '13312828', '13312810', '14177521', '16051199']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9292780700618296
- 35 USC 102 Novelty (BERT): 0.522495956781652
- Combined Prediction Score: 0.888599858733812
- Mean Citation Score: 237.584362
- Max Citation Score: 319.92032
- Similarity Product: 217.4943724357414

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test