PATENT CLAIM ANALYSIS

Application Number: 16122745
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2020-01
Patent Classification: ["365", "158000"]

Abstract:
Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Claim (Index 9):
The memory device of  claim 1 , wherein the one or more memory circuits include:\n a word line circuit, a bit line circuit and a source line circuit configured to bias the selected plurality of MBCs with a first set of sense voltage or current levels, and a sense circuit to sense a first instance of a sense level of the selected plurality of MBCs; the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a first set of program voltage or current levels; the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with the first set of sense voltage or current levels, and the sense circuit to sense a second instance of the sense level of the selected plurality of MBCs; the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a second set of sense voltage or current levels, and the sense circuit to sense a third instance of the sense level of the selected plurality of MBCs; the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a second set of program voltage or current levels; the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with the second set of sense voltage or current levels, and the sense circuit to sense a fourth instance of the sense level of the selected plurality of MBCs; and a read logic circuit configured to determine the read state of the selected plurality of MBCs based on a presence or absence of a change between the first instance of the sense level and the second instance of the sense level and a presence or absence of a change between the third instance of the sense level and the fourth instance of the sense level.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 97.0
- Lexical Diversity: 2.01923
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16122773', '16028415', '16028412', '11610739', '13613168']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8300838259061866
- 35 USC 102 Novelty (BERT): 0.5993481065454187
- Combined Prediction Score: 0.8070102539701098
- Mean Citation Score: 369.257888
- Max Citation Score: 522.14526
- Similarity Product: 488.3838076799011

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test