PATENT CLAIM ANALYSIS

Application Number: 15866982
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "203000"]

Abstract:
Methods of operating a memory include concurrently discharging a voltage level of a data line and source of the memory, monitoring a representation of a voltage difference between a voltage level of a control gate of a transistor connected between the data line and the source and a voltage level of the data line, activating a current path between the control gate of the transistor and the source if the voltage difference is deemed to be greater than a first value, and deactivating the current path if the voltage difference is deemed to be less than a second value. Memory configured to perform such methods include comparators configured to monitor voltage nodes capacitively coupled to the data line and to the control gate of the transistor connected between the data line and the source, and a current path selectively connecting the control gate of the transistor to the source.

Claim (Index 16):
A memory, comprising:\n a plurality of memory cells; a common source selectively connected to the plurality of memory cells; a data line selectively connected to the plurality of memory cells, and selectively connected to the common source through a transistor, the transistor having a control gate; a first comparator having a first input, a second input, and an output; a second comparator having a first input, a second input, and an output; a first voltage node connected to the first input of the first comparator, and capacitively coupled to the data line; a second voltage node connected to the second input of the second comparator, and capacitively coupled to the data line; a third voltage node connected to the second input of the first comparator, and capacitively coupled to the control gate of the transistor; a fourth voltage node connected to the first input of the second comparator, and capacitively coupled to the control gate of the transistor; a fifth voltage node selectively connected to the first voltage node and configured to receive a first reference voltage; a sixth voltage node selectively connected to the second voltage node and configured to receive a second reference voltage; a logic having a first input connected to the output of the first comparator and a second input connected to the output of the second comparator, and having an output configured to provide a first logic level when the first comparator indicates that a voltage level of its second input is greater than a voltage level of its first input, and to provide a second logic level, different from the first logic level, when the second comparator indicates that a voltage level of its first input is less than a voltage level of its second input; and a current path between the control gate of the transistor and the common source, wherein the current path is configured to be activated in response to the output of the logic having the first logic level, and to be deactivated in response to the output of the logic having the second logic level.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.98077
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15693133', '12850130', '13317678', '15692154', '14283209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7587710779305947
- 35 USC 102 Novelty (BERT): 0.4669352267895226
- Combined Prediction Score: 0.7295874928164875
- Mean Citation Score: 175.038326
- Max Citation Score: 181.32487
- Similarity Product: 145.1745581591332

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test