PATENT CLAIM ANALYSIS

Application Number: 15975721
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "295000"]

Abstract:
In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Claim (Index 9):
The method of  claim 8 , wherein the ferroelectric insulating layer comprises at least one selected from the group consisting of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), and gadolinium (Gd).

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.35294
- Patent Class: 257.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15632146', '15604092', '15292756', '10776394', '14203745']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9215969836664868
- 35 USC 102 Novelty (BERT): 0.5117963563730467
- Combined Prediction Score: 0.8806169209371428
- Mean Citation Score: 225.746828
- Max Citation Score: 274.67554
- Similarity Product: 200.11992823237185

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test