PATENT CLAIM ANALYSIS

Application Number: 16030584
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["365", "063000"]

Abstract:
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Claim (Index 18):
The memory device of  claim 17 , wherein the first level comprises a first memory cell coupled with the first access line and the second access line, wherein the second level comprises a second memory cell coupled with the third access line and the fourth access line, and wherein the memory controller is operable to:\n transmit a first signal to the first memory cell via the first interconnect; and transmit a second signal to the second memory cell via the second interconnect.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 95.0
- Lexical Diversity: 1.39024
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14982362', '13777811', '13651149', '14689409', '14543708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8176465562796926
- 35 USC 102 Novelty (BERT): 0.4797710408279597
- Combined Prediction Score: 0.7838590047345194
- Mean Citation Score: 222.68064
- Max Citation Score: 229.7155
- Similarity Product: 181.80021848633885

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test