PATENT CLAIM ANALYSIS

Application Number: 15983461
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-08
Patent Classification: ["257", "315000"]

Abstract:
A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

Claim (Index 16):
A method of forming a memory cell of a semiconductor device, the method comprising:\n forming first and second floating gate structures over a substrate; forming a first oxide region over the first floating gate structure and a second oxide region over the second floating gate structure, wherein the formation of the first and second oxide regions forms a first upwardly-pointing floating gate tip region of the first floating structure and a second upwardly-pointing floating gate tip region of the second floating gate structure; forming a non-conformal spacer layer including:\n a first spacer sidewall region laterally adjacent a first sidewall of the first floating gate structure facing the second floating gate and extending over the first upwardly-pointing floating gate tip region; and \n a second spacer sidewall region laterally adjacent a second sidewall of the second floating gate structure facing the first floating gate and extending over the second upwardly-pointing floating gate tip region; and \n performing a source implant into the substrate, wherein the first and second spacer sidewall regions substantially prevent penetration of source implant material through the first and second spacer sidewall regions, to thereby (a) protect the first and second upwardly-pointing floating gate tip regions from receiving the source implant material and (b) define a self-aligned source implant region in the substrate laterally between the first and second floating gate structures.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.03659
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15921858', '13666712', '11671809', '15922571', '11122726']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9212607546119
- 35 USC 102 Novelty (BERT): 0.5211592910395062
- Combined Prediction Score: 0.8812506082546606
- Mean Citation Score: 272.059348
- Max Citation Score: 342.11386
- Similarity Product: 298.39424142350674

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test