PATENT CLAIM ANALYSIS

Application Number: 15922849
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "506000"]

Abstract:
A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Claim (Index 1):
A manufacturing method of a package structure, comprising:\n providing a carrier; bonding a semiconductor chip on the carrier, wherein the semiconductor chip comprises a plurality of conductive pads exposed at an active surface of the semiconductor chip; forming an insulating material layer over the carrier and encapsulating the semiconductor chip after the semiconductor chip is bonded on the carrier, wherein the insulating material layer comprises a first surface and a second surface opposite to the first surface, a thickness of the insulating material layer is greater than a thickness of the semiconductor chip, and the plurality of conductive pads are covered by the insulating material layer; patterning the first surface of the insulating material layer to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer; forming a plurality of conductive posts in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip, and the plurality of conductive posts extend onto the first surface of the insulating layer; forming a plurality of conductive vias in the second openings, wherein the plurality of conductive vias extend onto the first surface of the insulating layer; forming a redistribution layer over the first surface of the insulating material layer, wherein the redistribution layer is electrically connected to the plurality of conductive posts and the plurality of conductive vias; de-bonding the carrier; and forming a plurality of conductive terminals on the second surface of the insulating material layer, wherein the plurality of conductive terminals is electrically connected to the redistribution layer through the plurality of conductive vias.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.75926
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14814524', '15816360', '15816396', '15629072', '15816312']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9040728420342428
- 35 USC 102 Novelty (BERT): 0.4967901163698009
- Combined Prediction Score: 0.8633445694677986
- Mean Citation Score: 227.17201
- Max Citation Score: 234.08388
- Similarity Product: 177.80295380501747

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test