PATENT CLAIM ANALYSIS

Application Number: 15887417
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "207000"]

Abstract:
The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.

Claim (Index 19):
A system for improving noise performance, comprising:\n a CPU, a computer readable memory and a computer readable storage media; first program instructions to apply a source supply voltage to a back gate of a device; and second program instructions to selectively control the applied source supply voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 88.0
- Lexical Diversity: 1.52273
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14479940', '15232177', '15748866', '14957227', '13317678']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8975893536227469
- 35 USC 102 Novelty (BERT): 0.4799486012608142
- Combined Prediction Score: 0.8558252783865538
- Mean Citation Score: 122.66546680000002
- Max Citation Score: 125.02424
- Similarity Product: 79.86629245463372

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test