PATENT CLAIM ANALYSIS

Application Number: 15971435
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "072000"]

Abstract:
A thin-film transistor (TFT) array substrate is provided. The TFT array substrate includes a base substrate, a semiconductor layer disposed on the base substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer. A top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on the same level.

Claim (Index 17):
A method of manufacturing a TFT array substrate, comprising:\n forming a semiconductor layer on a base substrate; forming an insulating layer on the semiconductor layer; forming a gate electrode on the insulating layer; and forming a source electrode and a drain electrode on the insulating layer, wherein the forming of the gate electrode comprises depositing a gate electrode material layer on the insulating layer, forming a gate electrode pattern layer by patterning the gate electrode material layer, and polishing the gate electrode pattern layer through chemical mechanical polishing (CMP).

Metadata:
- Claim Count in Document: 12.0
- Percentile: 93.0
- Lexical Diversity: 2.23684
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11289506', '11316895', '15134869', '12591657', '13535553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90898085569917
- 35 USC 102 Novelty (BERT): 0.4944256081657573
- Combined Prediction Score: 0.8675253309458286
- Mean Citation Score: 259.45401000000004
- Max Citation Score: 262.52194
- Similarity Product: 233.48626375672345

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test