PATENT CLAIM ANALYSIS

Application Number: 16029194
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-07
Patent Classification: ["257", "777000"]

Abstract:
According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

Claim (Index 15):
An electronic device, comprising:\n a first chip including a first connection region and a second connection region; a second chip including a third connection region facing the first connection region of the first chip; and a third chip including a fourth connection region facing the second connection region of the first chip, the first chip including a first memory element and a plurality of first interconnects, the first chip including a plurality of first signal terminals provided in the first connection region and electrically connected to the first memory element, the plurality of first interconnects being provided in the first connection region and the second connection region, the second chip including a plurality of second signal terminals and a plurality of third signal terminals, the plurality of second signal terminals being provided in the third connection region, the plurality of third signal terminals being provided in the third connection region, the third chip including a second memory element and a plurality of fourth signal terminals electrically connected to the second memory element, the plurality of fourth signal terminals being provided in the fourth connection region, the second signal terminals of the second chip being connected to the first signal terminals of the first chip, the first interconnects being connected to the third signal terminals of the second chip and the fourth signal terminals of the third chip.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 4.46429
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13053525', '14851696', '14807559', '15420558', '15819541']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9075266239080776
- 35 USC 102 Novelty (BERT): 0.4519914301677821
- Combined Prediction Score: 0.861973104534048
- Mean Citation Score: 147.24414599999997
- Max Citation Score: 149.9021
- Similarity Product: 124.72638564670682

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test