PATENT CLAIM ANALYSIS

Application Number: 15918668
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.

Claim (Index 3):
The method of  claim 1  further comprising forming a gate spacer comprising opposite portions contacting opposite sidewalls of the elongated dummy gate stack, wherein after the etching the portions of the dielectric layer, portions of the dielectric layer contacting the gate spacer remain.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.06977
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15225304', '15798742', '15429894', '15859893', '15610981']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9136097978611384
- 35 USC 102 Novelty (BERT): 0.5073323101582884
- Combined Prediction Score: 0.8729820490908535
- Mean Citation Score: 235.043682
- Max Citation Score: 255.34213
- Similarity Product: 184.9563046527136

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test