PATENT CLAIM ANALYSIS

Application Number: 16036234
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-07
Patent Classification: ["385", "014000"]

Abstract:
An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Claim (Index 17):
A method as in  claim 13  further comprising\n controlling a stoichiometry of Si, O, and N of each layer of the stack to provide the stress with the magnitude less than or equal to 20 MPa.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 1.63291
- Patent Class: 385.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16036208', '16036151', '12510273', '12860307', '12126883']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8167710650506443
- 35 USC 102 Novelty (BERT): 0.5583976584514945
- Combined Prediction Score: 0.7909337243907294
- Mean Citation Score: 289.396098
- Max Citation Score: 434.7552
- Similarity Product: 398.90578455848686

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test