PATENT CLAIM ANALYSIS

Application Number: 16057872
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region, a fourth doping region and at least one junction formed by different conductivities. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the first conductivity is disposed in the first well. The second doping region having the second conductivity is disposed in the first well. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The at least one junction is formed by the first doping region and the second doping region, or formed by the third doping region and the fourth doping region.

Claim (Index 14):
The method according to  claim 11 , further comprising remaining the second doping region in the floating state, when the internal circuit is subjected to the ESD stress.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 96.0
- Lexical Diversity: 4.30556
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15086119', '15941235', '15084557', '13369455', '14728053']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5718982429202937
- 35 USC 102 Novelty (BERT): 0.5412100200526646
- Combined Prediction Score: 0.5688294206335308
- Mean Citation Score: 329.4099379999999
- Max Citation Score: 410.20514
- Similarity Product: 292.426264105165

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test