PATENT CLAIM ANALYSIS

Application Number: 15915272
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["438", "696000"]

Abstract:
Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.

Claim (Index 8):
The method of  claim 1 , wherein the first CMP process includes determining an end point by detecting the etch stop layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.77778
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15236210', '13873298', '15434840', '14880379', '12428011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8717330692210821
- 35 USC 102 Novelty (BERT): 0.5223744813365979
- Combined Prediction Score: 0.8367972104326337
- Mean Citation Score: 232.734922
- Max Citation Score: 306.81155
- Similarity Product: 193.49569152100085

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test