PATENT CLAIM ANALYSIS

Application Number: 16011308
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "190000"]

Abstract:
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Claim (Index 15):
The integrated circuit structure of  claim 14 , wherein the gate dielectric layer further comprises a layer comprising a high-k material, wherein the layer comprising the high-k material is on the layer of native oxide.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.2381
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13749139', '15134093', '14821561', '15135262', '13629154']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919753894202198
- 35 USC 102 Novelty (BERT): 0.5120416788879968
- Combined Prediction Score: 0.878982672670778
- Mean Citation Score: 275.11944000000005
- Max Citation Score: 304.9434
- Similarity Product: 234.89509309762715

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test