PATENT CLAIM ANALYSIS

Application Number: 16138934
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["706", "031000"]

Abstract:
Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Claim (Index 9):
The method of  claim 8 , wherein causing the change in gate voltage includes causing a negative gate voltage, thereby causing injection of holes into the semiconductor layer and net positive charge trapping.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 97.0
- Lexical Diversity: 1.55357
- Patent Class: 706.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14684346', '14684343', '15262145', '14181245', '14846750']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4665876015577486
- 35 USC 102 Novelty (BERT): 0.553738962486753
- Combined Prediction Score: 0.475302737650649
- Mean Citation Score: 388.180918
- Max Citation Score: 436.18588
- Similarity Product: 343.4691962546444

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test