PATENT CLAIM ANALYSIS

Application Number: 16029207
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["257", "774000"]

Abstract:
An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

Claim (Index 19):
A semiconductor assembly comprising:\n a semiconductor wafer having a first coefficient of thermal expansion; a circuit board having a second coefficient of thermal expansion that is distinct from the first coefficient of thermal expansion; an elastomeric connector that is interposed between the semiconductor wafer and the circuit board, wherein the elastomeric connector comprises a plurality of conductive elements that when under compression come into contact and form a plurality of signal conducting paths between the semiconductor wafer and the circuit board.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.02857
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16019882', '10229837', '10656452', '09960089', '09908212']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90812779396649
- 35 USC 102 Novelty (BERT): 0.4670215681100827
- Combined Prediction Score: 0.8640171713808493
- Mean Citation Score: 162.151232
- Max Citation Score: 171.05708
- Similarity Product: 135.9466924668646

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test