PATENT CLAIM ANALYSIS

Application Number: 15880565
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["257", "076000"]

Abstract:
A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced.

Claim (Index 8):
An electronic device, comprising:\n a substrate having a top surface, a bottom surface and a plurality of vias; a first Field Effect Transistor (FET) device disposed on the top surface of the substrate and connected with a first voltage terminal, wherein the first FET device is a Gallium Nitride FET; a second FET device disposed on the top surface of the substrate and connected with the first FET and a second voltage terminal, wherein the second FET device is a Gallium Nitride FET; a driver integrated circuit (IC) disposed on the bottom surface of the substrate beneath the first and second FET devices and electrically connected with a gate of the first and second FET devices through the vias to send a control signal to the gate such that a gate loop distance between the driver IC and the first and second FET devices is minimized; and a plurality of gate resistors that are on the bottom surface of the substrate and that are electrically connected with a gate terminal of the Gallium Nitride FETs through the vias of the substrate, wherein the substrate includes a first ceramic layer sandwiched between a first conductive layer and a second conductive layer, a second ceramic layer sandwiched between the second conductive layer and a third conductive layer, and a third ceramic layer sandwiched between the third conductive layer and a fourth conductive layer; wherein one or more vias are formed between the first and second conductive layers to electrically connect the second conductive layer with the first conductive layer, wherein one or more vias are formed between the second and third conductive layers to electrically connect the third conductive layer with the second conductive layer, and wherein one or more vias are formed between the third and fourth conductive layers to electrically connect the fourth conductive layer with the third conductive layer.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 86.0
- Lexical Diversity: 3.13725
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14023038', '14876709', '14021802', '14483925', '14876631']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8933390237909301
- 35 USC 102 Novelty (BERT): 0.4927803268751662
- Combined Prediction Score: 0.8532831540993537
- Mean Citation Score: 180.03241
- Max Citation Score: 186.3241
- Similarity Product: 128.28136400570273

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test