PATENT CLAIM ANALYSIS

Application Number: 16049849
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods.

Claim (Index 1):
A semiconductor structure comprising:\n a semiconductor fin extending upward from a semiconductor substrate, the semiconductor fin comprising a lower semiconductor layer, a buried insulator on a top surface of the lower semiconductor layer and an upper semiconductor layer on a top surface of the buried insulator, wherein the buried insulator comprises a dielectric material layer between the lower semiconductor layer and the upper semiconductor layer and wherein the dielectric material layer comprises a dielectric material comprising silicon nitride, silicon oxynitride, or a low-K dielectric material having a dielectric constant of less than 3.9; shallow trench isolation on the semiconductor substrate and laterally surrounding the lower semiconductor layer of the semiconductor fin, wherein a top surface of the shallow trench isolation is below a level of the top surface of the buried insulator; a gate structure above the shallow trench isolation and positioned laterally adjacent to opposing sides of the semiconductor fin at a channel region; a gate sidewall spacer adjacent to the gate structure; source/drain recesses in the semiconductor fin adjacent to the channel region; source/drain regions in the source/drain recesses; and a diffusion break region in the semiconductor fin positioned laterally adjacent to one of the source/drain regions, wherein the diffusion break region extends through the upper semiconductor layer to the buried insulator.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 95.0
- Lexical Diversity: 1.88636
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15487636', '16046368', '15658835', '15632922', '15387933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5829931348160629
- 35 USC 102 Novelty (BERT): 0.52251613795585
- Combined Prediction Score: 0.5769454351300416
- Mean Citation Score: 335.456856
- Max Citation Score: 345.0775
- Similarity Product: 248.13568606853485

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test