PATENT CLAIM ANALYSIS

Application Number: 15937454
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "156000"]

Abstract:
A SRAM cell, including, in a stack of layers, transistors including at least first and second access transistors connected to a word line, the first access transistor coupling a first bit line and a first storage node and the second access transistor coupling a second bit line and a second storage node, and a flip-flop including a first conduction transistor coupling the first storage node to a source of a first reference potential and having its gate coupled to the second storage node and a second conduction transistor coupling the second storage node to the source of the first reference potential and having its gate coupled to the first storage node.

Claim (Index 1):
A SRAM, comprising SRAM cells arranged in rows and in columns, electrically-conductive tracks extending along the rows and the columns including word lines, first bit lines, and second bit lines and a circuit for providing signals of variable amplitudes on the conductive tracks, each memory cell comprising in a stack of layers transistors including at least first and second access transistors connected to one of the word lines, the first access transistor coupling one of the first bit lines and a first storage node and the second access transistor coupling one of the second bit lines and a second storage node, and a flip-flop comprising a first conduction transistor coupling the first storage node to a source of a first reference potential and having its gate coupled to the second storage node and a second conduction transistor coupling the second storage node to the source of the first reference potential and having its gate coupled to the first storage node, the transistors being distributed into a first plurality of transistors located at a first level of the stack and a second plurality of transistors located at at least a second level of the stack, the memory cell comprising an electrically-conductive portion of the second level connected to an inner node of the memory cell or to one of the conductive tracks and located opposite a channel area of a transistor of the first plurality of transistors and separated from said channel area via an insulating area provided or electrically-connected to a semiconductor portion containing said channel area to allow a coupling between the electrically-conductive portion and said channel area.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 90.0
- Lexical Diversity: 3.16216
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12466733', '12005666', '13097370', '12235870', '12533394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7957991564856925
- 35 USC 102 Novelty (BERT): 0.4899071372969344
- Combined Prediction Score: 0.7652099545668167
- Mean Citation Score: 228.86845
- Max Citation Score: 281.59042
- Similarity Product: 244.3089124768925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test