PATENT CLAIM ANALYSIS

Application Number: 15950610
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "185110"]

Abstract:
A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.

Claim (Index 9):
A method of operating a memory device, comprising:\n programming first and second select transistors so that the first and second select transistors have different threshold voltages, wherein the first select transistors are included in a first memory block and the second select transistors are included in a second memory block stacked on the first memory block; and selecting the first memory block by turning on all of the first select transistors and by turning off part of the second select transistors, or selecting the second memory block by turning on all of the second select transistors and by turning off part of the first select transistors.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.875
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15060726', '15873069', '15648681', '15148123', '14691263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.764224086901639
- 35 USC 102 Novelty (BERT): 0.4961549227132201
- Combined Prediction Score: 0.7374171704827971
- Mean Citation Score: 225.527866
- Max Citation Score: 272.6365
- Similarity Product: 227.0369627082348

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test