PATENT CLAIM ANALYSIS

Application Number: 15941716
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["257", "347000"]

Abstract:
A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Claim (Index 8):
A method of manufacturing a semiconductor device, the method comprising:\n forming a transistor over a substrate, the transistor having a source region and a drain region; on the source region:\n forming a first via surrounded by a first protective layer in a first interlayer dielectric (ILD) layer on the source region; \n forming a first metal layer:on the first via, the first metal layer extending along a first direction; \n forming a second via surrounded by a second protective layer in a second ILD layer over the first metal layer, the second via overlapping the first via; and \n forming a second metal layer on the second via, the second metal layer extending along a second direction different from the first direction, and on the drain region: \n forming a third via surrounded by a third protective layer in the first ILD layer over the drain region, the third via being at a same height level as the first via; \n forming a third metal layer on the third via; \n forming a fourth via surrounded by a fourth protective layer in the second ILD layer over the third metal layer, the fourth via overlapping the third via; and \n forming a controlled device on the fourth via, the controlled device is at a same height level as the second metal layer and is controlled by the transistor.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.82222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15493847', '15707634', '14805415', '15063544', '15940329']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9069340955462004
- 35 USC 102 Novelty (BERT): 0.4526861198341662
- Combined Prediction Score: 0.8615092979749969
- Mean Citation Score: 145.908296
- Max Citation Score: 147.62833999999995
- Similarity Product: 121.54190255189891

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test