PATENT CLAIM ANALYSIS

Application Number: 16113235
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["327", "115000"]

Abstract:
A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.

Claim (Index 37):
The method of  claim 36 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

Metadata:
- Claim Count in Document: 128.0
- Percentile: 96.0
- Lexical Diversity: 2.62903
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15811223', '15167216', '15192970', '12270131', '12731591']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7664963459999199
- 35 USC 102 Novelty (BERT): 0.556291160749938
- Combined Prediction Score: 0.7454758274749217
- Mean Citation Score: 281.92408
- Max Citation Score: 430.516
- Similarity Product: 323.95669415998464

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test