PATENT CLAIM ANALYSIS

Application Number: 15936696
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["365", "148000"]

Abstract:
A nonvolatile memory device includes a memory cell including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, a dummy word line bias circuit connected to the dummy cells through dummy word lines, a write driver and sense amplifier connected to the memory cells through bit lines, and a dummy bit line bias circuit connected to the dummy cells through a dummy bit line. The dummy word line bias circuit is configured to apply a same or a different voltage to respective ones of the dummy word lines to turn off selected dummy cells and adjust a leakage current flowing through the dummy cells; and a leakage current in the memory cells is maintained at a substantially uniform level through adjustment of the leakage current in the dummy cells.

Claim (Index 10):
The nonvolatile memory device of  claim 8 , wherein the body bias circuit is configured to adjust the bias voltage such that the amount of the first leakage current is substantially uniform.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.6
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15681479', '13919564', '15210628', '15009856', '13772868']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8237709581463418
- 35 USC 102 Novelty (BERT): 0.4968269242043328
- Combined Prediction Score: 0.791076554752141
- Mean Citation Score: 247.283304
- Max Citation Score: 252.18561
- Similarity Product: 173.03893364227116

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test