PATENT CLAIM ANALYSIS

Application Number: 16119462
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["375", "355000"]

Abstract:
A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Claim (Index 2):
The circuit of  claim 1 , wherein the output switching circuit further comprises:\n a first series circuit comprising first and second transistors coupled in series with each other and having a complementary type with each other, a gate of the first transistor coupled to the output of the sampling circuit, and a gate of the second transistor coupled to an inverse of the output of the sampling circuit, wherein an output node for the output switching circuit is a common node between the first and second transistors; a second series circuit comprising third and fourth transistors coupled in series with each other and having a complementary type with each other, a gate of the third transistor coupled to the inverse of the output of the sampling circuit, and a gate of the fourth transistor coupled to the output of the sampling circuit, wherein the first and second series circuits are coupled together in parallel at first and second common nodes; a fifth transistor coupled between a supply node and the first common node; a sixth transistor coupled between a circuit reference node and the second common node; and a voltage divider network coupled between the supply node and the circuit reference node, the voltage divider network configured to provide a voltage to a common node between the third and fourth transistors.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.54167
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15394506', '14108834', '10820691', '09712104', '16052027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4762249371812858
- 35 USC 102 Novelty (BERT): 0.52255821571926
- Combined Prediction Score: 0.4808582650350832
- Mean Citation Score: 239.427052
- Max Citation Score: 348.4434
- Similarity Product: 332.35051500681635

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test