PATENT CLAIM ANALYSIS

Application Number: 16109656
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["327", "299000"]

Abstract:
A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.

Claim (Index 4):
The quadrature clock generation circuit of  claim 3 , wherein the:\n the first injector buffer comprises a first transistor and a second transistor, wherein:\n a gate of the first transistor is configured to receive a positive differential signal from the approximate in-phase clock; \n a gate of the second transistor is configured to receive a negative differential signal from the approximate in-phase clock; and \n a drain of the first transistor and a drain of the second transistor are connected to the first in-phase output; \n the second injector buffer comprises a third transistor and a fourth transistor, wherein:\n a gate of the third transistor is configured to receive a positive differential signal from the approximate quadrature clock; \n a gate of the fourth transistor is configured to receive a negative differential signal from the approximate quadrature clock; and \n a drain of the third transistor and a drain of the fourth transistor are connected to the first quadrature output; the first resonator buffer comprises a fifth transistor and a sixth transistor, wherein:\n a gate of the fifth transistor is connected to is connected to the drain of the fourth transistor; \n a drain of the fifth transistor is connected to the drain of the second transistor; \n a gate of the sixth transistor is connected to the drain of the third transistor; and \n a drain of the sixth transistor is connected to the drain of the first transistor; and \n the second resonator buffer comprises a seventh transistor and a eighth transistor, wherein:\n a gate of the seventh transistor is connected to is connected to the drain of the second transistor; \n a drain of the seventh transistor is connected to the drain of the third transistor; \n a gate of the eighth transistor is connected to the drain of the first transistor; and \n a drain of the eighth transistor is connected to the drain of the fourth transistor.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 96.0
- Lexical Diversity: 3.0625
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12492419', '15788617', '09747163', '15932298', '11392966']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7933331556156287
- 35 USC 102 Novelty (BERT): 0.473896757416098
- Combined Prediction Score: 0.7613895157956756
- Mean Citation Score: 214.274754
- Max Citation Score: 223.43446
- Similarity Product: 190.2088504479504

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test