PATENT CLAIM ANALYSIS

Application Number: 15941169
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["377", "064000"]

Abstract:
A shift register unit includes an input circuit configured to output a pre-output signal in response to an input signal and a first clock signal, a first output circuit configured to output a first output signal in response to the pre-output signal and a second clock signal; and a second output circuit configured to output a second output signal in response to the pre-output signal and a third clock signal.

Claim (Index 16):
The gate driving circuit of  claim 15 ,\n wherein the first clock signal has a period of 2H and a duty cycle of 50%, wherein the second clock signal has a period of 2H and a duty cycle of 25%, wherein the third clock signal is a delayed version of the second clock signal delayed by 1/2H, wherein the fourth clock signal is an inverted version of the first clock signal, wherein the fifth clock signal is a delayed version of the third clock signal delayed by 1/2H, and wherein the sixth clock signal is a delayed version of the fifth clock signal delayed by 1/2H.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.92
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12012964', '12012845', '15773873', '15103983', '12012846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7109438770617981
- 35 USC 102 Novelty (BERT): 0.4844181276117192
- Combined Prediction Score: 0.6882913021167902
- Mean Citation Score: 249.769604
- Max Citation Score: 251.78151
- Similarity Product: 175.5268063716638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test