PATENT CLAIM ANALYSIS

Application Number: 15978783
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "659000"]

Abstract:
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other. A lowermost wiring layer of the wiring layers is embedded in the frame and has a lower surface exposed from a lowermost insulating layer of the frame.

Claim (Index 1):
A fan-out semiconductor package comprising:\n a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein a lowermost wiring layer of the plurality of wiring layers is embedded in the frame and has a lower surface exposed from a lowermost insulating layer of the plurality of insulating layers of the frame.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 2.50877
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15978727', '15969480', '15970307', '15969359', '15941334']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9367657513007458
- 35 USC 102 Novelty (BERT): 0.5483232581488419
- Combined Prediction Score: 0.8979215019855554
- Mean Citation Score: 357.5884
- Max Citation Score: 402.87485
- Similarity Product: 394.9727021547467

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test