PATENT CLAIM ANALYSIS

Application Number: 16159704
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["257", "774000"]

Abstract:
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

Claim (Index 12):
The 3D circuit of  claim 1 , wherein the plurality of connections allows the data to pass from one die to the other in one clock cycle.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 2.18478
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16159703', '16159705', '15976817', '15976827', '15976815']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9411533442776344
- 35 USC 102 Novelty (BERT): 0.5693513688870452
- Combined Prediction Score: 0.9039731467385757
- Mean Citation Score: 384.115824
- Max Citation Score: 469.62216
- Similarity Product: 361.4074582927609

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test