PATENT CLAIM ANALYSIS

Application Number: 15995736
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["345", "605000"]

Abstract:
A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

Claim (Index 19):
The method of  claim 11 , further comprising changing one or more bits in a register of the processor to cause the processor to be in the second mode.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 3.41176
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13931739', '15331940', '13854089', '14491548', '13977171']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.706894244830305
- 35 USC 102 Novelty (BERT): 0.5547127513207769
- Combined Prediction Score: 0.6916760954793523
- Mean Citation Score: 381.849996
- Max Citation Score: 469.2003
- Similarity Product: 313.80974466041926

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test