PATENT CLAIM ANALYSIS

Application Number: 16458852
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["716", "052000"]

Abstract:
A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

Claim (Index 7):
The method of  claim 1 , wherein the design criteria comprises at least one of:\n a layout requirement of the integrated circuit; a place and route requirement of the integrated circuit; a mask count; or one or more via spacing rules.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.48889
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15258932', '15465167', '15966693', '14554958', '14484588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3569280759551613
- 35 USC 102 Novelty (BERT): 0.51448328788622
- Combined Prediction Score: 0.3726835971482671
- Mean Citation Score: 222.11727
- Max Citation Score: 357.15204
- Similarity Product: 279.3326629887843

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test