PATENT CLAIM ANALYSIS

Application Number: 15991023
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["257", "029000"]

Abstract:
The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.

Claim (Index 7):
A two-dimensional material field effect transistor comprising:\n a two-dimensional material disposed on an insulating substrate; a recessed gate dielectric disposed on the two-dimensional material; a top gate disposed on the recessed gate dielectric; a hard mask disposed on the top gate; an interlayer dielectric oxide disposed on the hard mask; a set of sidewall spacers, wherein each of the set of sidewall spacers is disposed on opposing sides of the recessed gate dielectric, the top gate, and the hard mask wherein the set of sidewall spacers fails to be disposed along each side of the interlayer dielectric oxide; a gate metal contact layer disposed on the two-dimensional material and disposed directly on each side of the set of sidewall spacers and on each side of the interlayer dielectric oxide, and wherein a width of the interlayer dielectric oxide is greater than a width of the recessed gate dielectric.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 93.0
- Lexical Diversity: 2.43284
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15786047', '15611981', '15643940', '15705888', '15407592']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.906597305637042
- 35 USC 102 Novelty (BERT): 0.5222702174621667
- Combined Prediction Score: 0.8681645968195545
- Mean Citation Score: 259.199074
- Max Citation Score: 283.49908
- Similarity Product: 173.66796214520215

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test