PATENT CLAIM ANALYSIS

Application Number: 16127894
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["365", "156000"]

Abstract:
A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.

Claim (Index 2):
The memory circuit according to  claim 1 , wherein in the third n-channel MOS transistor, the source terminal is connected to the drain terminal, and in the fifth n-channel MOS transistor, the source terminal is connected to the drain terminal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 3.30233
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13360904', '12889881', '13774668', '15478237', '14932254']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8265124495818663
- 35 USC 102 Novelty (BERT): 0.4918552147781364
- Combined Prediction Score: 0.7930467261014933
- Mean Citation Score: 252.638442
- Max Citation Score: 259.87628
- Similarity Product: 198.74596246135712

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test