PATENT CLAIM ANALYSIS

Application Number: 16160223
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "043000"]

Abstract:
Disclosed is an array substrate and a display device. The array substrate includes: a plurality of gate lines and a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other, wherein each pixel unit includes a thin film transistor and a pixel electrode connected with the thin film transistor, the pixel electrode, the data line, as well as an active layer, a source and a drain of the thin film transistor are disposed in a same layer and are formed through a single patterning process,

Claim (Index 3):
The array substrate of  claim 2 , wherein the array substrate further comprises a common electrode line and a comb-shaped common electrode connected with the common electrode line, both the common electrode line and the comb-shaped common electrode being disposed over the insulating layer.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 97.0
- Lexical Diversity: 2.16981
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14421947', '13985196', '14379818', '14380168', '14436995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9287755620239444
- 35 USC 102 Novelty (BERT): 0.5250684361758889
- Combined Prediction Score: 0.8884048494391388
- Mean Citation Score: 277.96001800000005
- Max Citation Score: 330.26465
- Similarity Product: 223.6264474547416

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test