PATENT CLAIM ANALYSIS

Application Number: 15947114
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "360000"]

Abstract:
An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.

Claim (Index 21):
The method of  claim 13 , wherein forming the second fin in the I/O region comprises forming the I/O region around a peripheral area of the IC.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 2.30137
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15371512', '14741418', '15345612', '13962322', '12403418']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9070380405308992
- 35 USC 102 Novelty (BERT): 0.5055551481386412
- Combined Prediction Score: 0.8668897512916736
- Mean Citation Score: 200.859692
- Max Citation Score: 217.88942000000003
- Similarity Product: 145.4314645770228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test