PATENT CLAIM ANALYSIS

Application Number: 15897526
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "751000"]

Abstract:
A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.

Claim (Index 6):
The method of  claim 1 , wherein the metal capping layer comprises at least one layer comprising one or more of: Co, Ru, W, Ta, Ti, P, and Rh.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 88.0
- Lexical Diversity: 2.72222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15070411', '14339704', '15078066', '12608377', '13415159']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9278066565624034
- 35 USC 102 Novelty (BERT): 0.5232575885273972
- Combined Prediction Score: 0.8873517497589027
- Mean Citation Score: 274.890626
- Max Citation Score: 329.72226
- Similarity Product: 286.1913063867903

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test