PATENT CLAIM ANALYSIS

Application Number: 15779843
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["708", "707000"]

Abstract:
Ripple-carry and carry look-ahead adders for ternary addition and other operations include circuits that produce carry values or carry status indicators that can be stored on qutrit registers associated with input values to be processed. Inverse carry circuits are situated to reverse operations associated with the production of carry values or carry status indicators, and restored values are summed with corresponding carry values to produce ternary sums.

Claim (Index 16):
A ripple carry circuit for quantum ternary addition, comprising:\n a first n-qutrit register that includes n qutrits, the n qutrits including a least significant qutrit, at least one intermediate qutrit, and a most significant qutrit that store a least significant trit value, at least one intermediate trit value, and a most significant trit value, respectively, wherein n is a positive integer; a second n-qutrit register that includes n qutrits, the n qutrits including a least significant qutrit, at least one intermediate qutrit, and a most significant qutrit that store a least significant trit value, at least one intermediate trit value, and a most significant trit value, respectively; a carry qutrit; a first carry circuit coupled to the least significant qutrit of the first n-qutrit register and the least significant qutrit second n-qutrit register so as to produce and store a carry value associated with a sum of the least significant trit values stored in the first and second n-qutrit quantum registers; n\u22122 carry circuits serially coupled to respective intermediate qutrits of the first n-qutrit register and the second n-qutrit register, wherein a k th  carry circuit is coupled to a preceding carry circuit so as to receive a carry value associated with a sum of (k\u22121) th  trit values and to k th  qutrits of the first and second n-qubit registers so as to receive k th  trit values stored in the first and second n-qubit registers, the k th  carry circuit producing and storing a k th  carry value in a k th  qutrit of the second n-qutrit register; an n th  carry circuit coupled to an n th  qutrit of the first n-qutrit register and an n th  qutrit of the second n-qutrit register so as to receive nth trit values stored in the first and second n-qubit registers, wherein the n th  carry circuit is coupled to an (n\u22121) th  carry circuit so as to receive an (n\u22121) th  carry value, the n th  carry circuit producing an n th  carry value based a sum of the n th  trit values in stored in the first and second n-qubit registers and the (n\u22121) th  carry value; and an adder circuit coupled to the n th  carry circuit so as to couple the n th  carry value to the carry qubit.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 1.66667
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15640108', '14449477', '13420247', '15316500', '13957113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3477148529000941
- 35 USC 102 Novelty (BERT): 0.4959030235447149
- Combined Prediction Score: 0.3625336699645561
- Mean Citation Score: 170.875822
- Max Citation Score: 194.21594
- Similarity Product: 139.81899788747307

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test