PATENT CLAIM ANALYSIS

Application Number: 15911555
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-07
Patent Classification: ["257", "043000"]

Abstract:
The present disclosure discloses a manufacturing method of a thin film transistor, including: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer and the substrate; forming an active layer on the gate insulating layer; and simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method. In the present disclosure, the chemical plating method is combined with the lift-off method, so that the wet-etching method is not used for forming the source and the drain, and thus the IGZO at the channel is not required to be protected by the etching-stop-layer. Therefore, while simplifying the production process, but also can reduce costs.

Claim (Index 12):
The thin film transistor according to  claim 7 , wherein the semiconductor portion is made of IGZO, the first conductor portion and the second conductor portion are made of IGZO doped with hydrogen.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.10938
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15308991', '15579530', '14416005', '15328201', '14603369']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9246224964911964
- 35 USC 102 Novelty (BERT): 0.486611550802318
- Combined Prediction Score: 0.8808214019223087
- Mean Citation Score: 211.79891
- Max Citation Score: 213.88153
- Similarity Product: 161.38070918905615

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test