PATENT CLAIM ANALYSIS

Application Number: 15934179
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["712", "208000"]

Abstract:
A data processor in which execution threads may be grouped together into thread groups in which the plural threads of a thread group can each execute a set of instructions in lockstep, one instruction at a time. The data processor comprises a plurality of execution lanes for executing respective execution threads of a thread group. For each thread group in a pool 51 of thread groups available to be issued to the execution lanes, an indication 54 of the active threads of the thread group is stored, and sets of at least one thread group from the pool 51 of available thread groups to issue 73 to the execution lanes for execution are selected 72 based on the indications of the active threads for the thread groups in the thread group pool.

Claim (Index 1):
A data processor in which execution threads may execute program instructions to perform data processing operations and in which execution threads may be grouped together into thread groups in which the plural threads of a thread group can each execute a set of instructions in lockstep, one instruction at a time;\n the data processor comprising: execution processing circuitry operable to execute instructions to perform processing operations for execution threads executing a program to perform data processing operations, and comprising a set of at least one functional unit operable to perform data processing operations for an instruction being executed by an execution thread; wherein:\n the execution processing circuitry is operable as a plurality of execution lanes, each lane being operable to perform processing operations for a respective execution thread of a thread group; \n the data processor further comprising: thread group managing circuitry operable to maintain a pool of thread groups available to be issued to the execution lanes, and storing for each available thread group: an indication of a set of at least one next instruction to be executed by the thread group, and an indication of the active threads of the thread group; and thread group selection circuitry operable to select thread groups from the pool of available thread groups and to issue the selected thread groups from the pool of available thread groups to the execution lanes for execution; wherein:\n the thread group selection circuitry is configured to select sets of at least one thread group to issue to the execution lanes for execution based on the indications of the active threads for the thread groups in the thread group pool.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 90.0
- Lexical Diversity: 2.22581
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15346931', '15218015', '15657014', '15401639', '13918664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6292942393781961
- 35 USC 102 Novelty (BERT): 0.5178898723330211
- Combined Prediction Score: 0.6181538026736786
- Mean Citation Score: 327.1961859999999
- Max Citation Score: 347.45135
- Similarity Product: 310.7962740251124

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test