PATENT CLAIM ANALYSIS

Application Number: 15970724
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "713000"]

Abstract:
A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Claim (Index 15):
A heat dissipation structure, comprising:\n a semiconductor integrated circuit die having a plurality of copper connection areas; a copper thermal mount comprising a plurality of copper pillars projecting from a surface thereof, each copper pillar of the plurality of copper pillars positioned to connect to one copper connection area of the plurality of copper connection areas on a peripheral portion of the semiconductor integrated circuit die; and a plurality of copper nanoparticle interface layers, each copper nanoparticle interface layer of the plurality of copper nanoparticle interface layers connecting one copper pillar of the plurality of copper pillars and the respective one copper connection area of the plurality of copper connection areas, wherein flexure of the plurality of copper pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the copper thermal mount, and wherein the copper thermal mount further comprises a central copper support projecting from the surface thereof, the central copper support connected to one copper connection area of the plurality of copper connection areas on a central portion of the semiconductor integrated circuit die by an additional copper nanoparticle interface layer.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 93.0
- Lexical Diversity: 2.0274
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10820484', '10719451', '14509785', '14850070', '11126571']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9137033365841248
- 35 USC 102 Novelty (BERT): 0.489730563044463
- Combined Prediction Score: 0.8713060592301586
- Mean Citation Score: 197.528338
- Max Citation Score: 199.61003
- Similarity Product: 136.01147869544027

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test