PATENT CLAIM ANALYSIS

Application Number: 15961212
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "666000"]

Abstract:
A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

Claim (Index 4):
The method of  claim 3  further comprising:\n filling spaces between the gate contact plug and the source/drain contact plug with an inter-layer dielectric.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.17778
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15286670', '14213051', '15386952', '15429894', '15462001']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8364198697202019
- 35 USC 102 Novelty (BERT): 0.5163594175035445
- Combined Prediction Score: 0.8044138244985362
- Mean Citation Score: 231.64985800000005
- Max Citation Score: 292.6564
- Similarity Product: 220.41154708886145

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test