PATENT CLAIM ANALYSIS

Application Number: 15909929
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["714", "764000"]

Abstract:
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Claim (Index 11):
The apparatus of  claim 9 , further comprising:\n a data interface to provide the particular error correction codeword to a controller; wherein the controller is configured to correct one or more errors in the data included in particular error correction codeword.

Metadata:
- Claim Count in Document: 54.0
- Percentile: 90.0
- Lexical Diversity: 1.89744
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13792597', '14844843', '13365064', '15787644', '11391000']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2730117557954469
- 35 USC 102 Novelty (BERT): 0.5314452375011328
- Combined Prediction Score: 0.2988551039660155
- Mean Citation Score: 256.56980200000004
- Max Citation Score: 365.56512
- Similarity Product: 332.76038173862463

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test