PATENT CLAIM ANALYSIS

Application Number: 16037767
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "835000"]

Abstract:
Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R on  or R off  to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Claim (Index 11):
The memory device according to  claim 10 , wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows\u00d7N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits;\n the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j th  word line in the N word lines is a voltage value corresponding to B j , a resistance value of a resistor in the j th  row at the first RRAM crossbar array is a resistance value corresponding to A j , B j  is the j th  element of vector B, A j  is the j th  element of vector A, and a value of j ranges from 0 to N\u22121, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and obtain, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the second RRAM crossbar array, voltage signals corresponding to the intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array receives the voltage signals corresponding to the intermediate binary number from the bit lines of second RRAM crossbar array, and convert the intermediate binary number into the second binary number, wherein the second binary number is a binary representation of K.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 1.72
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13965459', '14287701', '14308273', '14731933', '14025299']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4105761426951146
- 35 USC 102 Novelty (BERT): 0.5005722029786353
- Combined Prediction Score: 0.4195757487234667
- Mean Citation Score: 191.697904
- Max Citation Score: 210.35286
- Similarity Product: 153.83737744947553

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test