PATENT CLAIM ANALYSIS

Application Number: 15904346
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["257", "306000"]

Abstract:
This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Claim (Index 15):
A manufacturing method of a semiconductor device comprising the steps of:\n (a) providing a substrate having a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a semiconductor layer formed over the first insulating layer, and further having, in a main surface of the semiconductor substrate, a first region where a first capacitive element and a second capacitive element are to be formed, a second region where a first MISFET is to be formed, and a third region where a second MISFET is to be formed; (b) removing the semiconductor layer and the first insulating layer in the third region; (c) forming a semiconductor region in the semiconductor substrate in the first region; (d) forming a second insulating layer over the semiconductor layer in the first region and over the semiconductor substrate in the third region; (e) forming a third insulating layer having a smaller thickness than the second insulating layer over the semiconductor layer in the second region; (f) forming a first conductor layer over the second insulating layer in the first region, a second conductor layer over the third insulating layer in the second region, and a third conductor layer over the second insulating layer in the third region, respectively; (g) in the second region, forming a second semiconductor region in the semiconductor layers at both ends of the second conductor layer; and (h) in the third region, forming a third semiconductor region in the semiconductor substrate at both ends of the third conductor layer, wherein in the first region, the first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the first conductor layer, wherein in the first region, the second capacitive element is comprised of the semiconductor region, the first insulating layer, and the semiconductor layer, and wherein each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 3.52632
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15212331', '14860700', '15266914', '15239193', '14869988']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9205620659527476
- 35 USC 102 Novelty (BERT): 0.5025043701224683
- Combined Prediction Score: 0.8787562963697197
- Mean Citation Score: 247.054064
- Max Citation Score: 278.07376
- Similarity Product: 215.6485211756801

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test