PATENT CLAIM ANALYSIS

Application Number: 15885076
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["365", "230030"]

Abstract:
A semiconductor memory device according to an embodiment includes a first memory cell transistor and a second memory cell transistor, a select transistor, a bit line, a first word line and a second word line, a select gate line, and a controller. During the program operation in the write operation with the first word line selected, the controller applies a first voltage to the select gate line and a second voltage lower than the first voltage to the first word line before applying the program pulse to the first word line, and applies a third voltage lower than the first voltage and higher than the second voltage to the select gate line while applying the program pulse to the first word line.

Claim (Index 8):
The device of  claim 7 , wherein\n the controller is configured to apply, in the program operation before selection of the second word line, the first voltage to the select gate line and the second voltage to the plurality of word lines before applying the program pulse to the selected word line when consecutive write operations with the plurality of memory cell transistors in the NAND string selected are to be performed.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 3.19512
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15688846', '15174114', '15881662', '14096371', '15061967']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.789626636209505
- 35 USC 102 Novelty (BERT): 0.4999052366437085
- Combined Prediction Score: 0.7606544962529254
- Mean Citation Score: 234.344958
- Max Citation Score: 267.24435
- Similarity Product: 210.300102072376

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test