PATENT CLAIM ANALYSIS

Application Number: 15915597
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["365", "185030"]

Abstract:
According to one embodiment, a memory system comprising: a semiconductor storage device including a memory cell connected to a word line and capable of storing n-bit data (n is an integer of 2 or more); and a controller circuit, wherein the semiconductor storage device determines a value of the n-bit read data stored in the memory cell, by a first reading operation using k reading voltages different from each other (k is an integer equal to or higher than 2̂(n−1) and less than 2̂n−1), and the controller circuit converts the value of the n-bit read data into data corresponding to (k+1) decimal data.

Claim (Index 2):
The system of  claim 1 ,\n wherein the controller circuit is configured to issue a first read command and a second read command, and the semiconductor storage device executes the first reading operation in accordance with receiving the first read command, and determines the n-bit read data, by a second reading operation using (2\u0302n\u22121) reading voltages different from each other in accordance with receiving the second read command.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 1.77612
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15698141', '15693430', '15896365', '15459294', '14790331']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8050105815035881
- 35 USC 102 Novelty (BERT): 0.4609780900251187
- Combined Prediction Score: 0.7706073323557412
- Mean Citation Score: 175.92388400000004
- Max Citation Score: 183.78108
- Similarity Product: 150.2835562513161

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test