PATENT CLAIM ANALYSIS

Application Number: 16405701
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["365", "158000"]

Abstract:
An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

Claim (Index 19):
The integrated circuit of  claim 18 , wherein each of the MRAM cells comprises a spin transfer torque (STT) memory cell, spin orbit torque (SOT) memory cell, orthogonal spin transfer (OST) MRAM cell, or magnetoelectric RAM (MeRAM) cell.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 100.0
- Lexical Diversity: 1.98611
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15726084', '15150179', '16403679', '13768858', '16403678']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7947831552702094
- 35 USC 102 Novelty (BERT): 0.4772096151287079
- Combined Prediction Score: 0.7630258012560592
- Mean Citation Score: 152.266932
- Max Citation Score: 234.80746
- Similarity Product: 197.07438558303832

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test