PATENT CLAIM ANALYSIS

Application Number: 16144544
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["365", "189070"]

Abstract:
A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Claim (Index 38):
The semiconductor memory instance of  claim 36 , wherein said second decoder circuit is configured to apply a bias to said first and second collectors within one of said at least two memory sub-arrays_to maintain the states of said semiconductor memory cells in said one of said at least two memory sub-arrays during a high portion of a clock cycle and to be turned-off during a low portion of the clock cycle.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 1.94118
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14825268', '15712041', '15867877', '15403757', '15287903']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8352813700184551
- 35 USC 102 Novelty (BERT): 0.5697808209939771
- Combined Prediction Score: 0.8087313151160074
- Mean Citation Score: 422.81033400000007
- Max Citation Score: 478.25507000000016
- Similarity Product: 387.0260326184463

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test