PATENT CLAIM ANALYSIS

Application Number: 15935426
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "686000"]

Abstract:
An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.

Claim (Index 15):
A method comprising:\n forming a buffer layer over a carrier substrate; forming a passivation layer over the buffer layer, the passivation layer having a first surface and a second surface, the first surface of the passivation layer being opposite the second surface of the passivation layer, the second surface of the passivation layer facing the buffer layer; patterning the passivation layer to form a first opening therein, a width of the first opening decreasing as the first opening extends from the first surface of the passivation layer toward the second surface of the passivation layer; conformally depositing a first conductive material over the first surface of the passivation layer and in the first opening to form a first conductive layer; forming a first sacrificial layer over the first conductive layer; patterning the first sacrificial layer to form a second opening and a third opening therein, the second opening exposing a first portion of the first conductive layer disposed on a bottom and sidewalls of the first opening, the third opening exposing a second portion of the first conductive layer disposed on the first surface of the passivation layer; depositing a second conductive material in the second opening to form a second conductive layer over the first portion of the first conductive layer; depositing the second conductive material in the third opening to form a third conductive layer over the second portion of the first conductive layer; removing the first sacrificial layer; forming a second sacrificial layer over the first conductive layer, the second conductive layer, and the third conductive layer; patterning the second sacrificial layer to form a fourth opening therein, the fourth opening exposing the second conductive layer; depositing a third conductive material in the fourth opening to form a conductive pillar over the second conductive layer; removing the second sacrificial layer; removing portions of the first conductive layer not covered by the conductive pillar, the second conductive layer and the third conductive layer; attaching an integrated circuit die to the passivation layer, the third conductive layer being interposed between the integrated circuit die and the passivation layer; encapsulating the integrated circuit die and the conductive pillar with a molding compound; removing the carrier substrate; and patterning the buffer layer and the passivation layer to form a fifth opening, the fifth opening exposing the first portion of the first conductive layer.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 1.90244
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14137231', '15178265', '14743451', '13890162', '15670843']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8980330023898253
- 35 USC 102 Novelty (BERT): 0.4894500962179405
- Combined Prediction Score: 0.8571747117726368
- Mean Citation Score: 195.29566
- Max Citation Score: 208.832
- Similarity Product: 158.39919229125974

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test