PATENT CLAIM ANALYSIS

Application Number: 15926127
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["438", "109000"]

Abstract:
Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

Claim (Index 5):
The package of  claim 1 , wherein the package does not comprise a sequential build-up (SBU) laminate substrate.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 90.0
- Lexical Diversity: 3.01852
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15612971', '15221464', '14730171', '14638925', '15141028']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8981257827477694
- 35 USC 102 Novelty (BERT): 0.6195103893136931
- Combined Prediction Score: 0.8702642434043618
- Mean Citation Score: 381.7622640000001
- Max Citation Score: 559.3194
- Similarity Product: 530.113181785834

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test