PATENT CLAIM ANALYSIS

Application Number: 15940058
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["257", "533000"]

Abstract:
An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.

Claim (Index 11):
The method of  claim 1 , wherein said etching said capacitor dielectric layer and etching said metal layer both utilize said pattern on said capacitor dielectric layer.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 90.0
- Lexical Diversity: 2.30189
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15855576', '15855635', '15184748', '12433042', '12868659']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921211589611139
- 35 USC 102 Novelty (BERT): 0.4913752976079391
- Combined Prediction Score: 0.8782279604108191
- Mean Citation Score: 192.4456
- Max Citation Score: 221.16869
- Similarity Product: 162.84671551377772

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test