PATENT CLAIM ANALYSIS

Application Number: 16297596
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.

Claim (Index 10):
The integrated circuit of  claim 9  wherein:\n each switch matrix of the first stage of switch matrices is configured in a radix-a network, where a is a whole number which is greater than or equal to 2, and \n each switch matrix of the second stage of switch matrices is configured in a radix-b, where (i) b is whole number and (ii) b is not equal to a.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 99.0
- Lexical Diversity: 2.74576
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15898796', '15041085', '15375309', '15347071', '16186882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7900951819444977
- 35 USC 102 Novelty (BERT): 0.6568243025492195
- Combined Prediction Score: 0.7767680940049698
- Mean Citation Score: 569.8603059999998
- Max Citation Score: 659.7848
- Similarity Product: 624.6438169879914

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test