PATENT CLAIM ANALYSIS

Application Number: 15762292
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "029000"]

Abstract:
A manufacturing method of an array substrate, an array substrate and a display apparatus are provided. The manufacturing method includes: providing a base substrate; sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate; performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer; forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; conducting a grinding process to form a source electrode, a drain electrode and a pixel electrode are formed respectively.

Claim (Index 3):
The manufacturing method of the array substrate claimed as  claim 2 , wherein the graphene conductor layer includes a first area and a second area insulated from each other, and the first area is treated to form the active layer, and the second area is used for forming a gate line.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 90.0
- Lexical Diversity: 2.48333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14362038', '12888171', '15326383', '11853297', '13824540']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9302818295078208
- 35 USC 102 Novelty (BERT): 0.5062210229166619
- Combined Prediction Score: 0.887875748848705
- Mean Citation Score: 228.002524
- Max Citation Score: 231.72682000000003
- Similarity Product: 148.76982461388113

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test