PATENT CLAIM ANALYSIS

Application Number: 16117361
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["327", "105000"]

Abstract:
A nested mixed-radix DDSM can guarantee zero systematic frequency error when used as a divider controller in a fractional-N frequency synthesizer is described. This disclosure presents a nested cascaded mixed-radix DDSM architecture which can also guarantee zero systematic frequency error. In addition, the disclosure allows one to use higher order auxiliary modulators and shaped dither signal to eliminate feedthrough spurs completely. By increasing the number of levels in the cascade, the moduli of the individual modulator stages can be reduced, thereby increasing the speed of the synthesizer.

Claim (Index 12):
The fractional-N frequency synthesizer of  claim 1  wherein the divider controller is configured to operate with a plurality of individual moduli and comprises a plurality of modulator stages, wherein the sizes of the individual moduli are reduced by cascading modulator stages over more than two levels.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 96.0
- Lexical Diversity: 1.49206
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16041648', '13715529', '14326816', '10638529', '14952138']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.808265598977481
- 35 USC 102 Novelty (BERT): 0.5405343013271292
- Combined Prediction Score: 0.7814924692124458
- Mean Citation Score: 300.979962
- Max Citation Score: 399.98755
- Similarity Product: 323.2932075256765

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test