PATENT CLAIM ANALYSIS

Application Number: 16053794
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["257", "029000"]

Abstract:
A nanowire transistor includes: a nanowire channel layer on a substrate; a gate structure on and around the nanowire channel layer, wherein the gate structure comprises a high-k dielectric layer on the nanowire channel layer; a first spacer on a lateral sidewall of the gate structure, wherein a lateral sidewall of the first spacer is aligned with a lateral sidewall of the nanowire channel layer; a second spacer on the lateral sidewall of the first spacer and the lateral sidewall of the nanowire channel layer, wherein top surfaces of the first spacer and the second spacer are coplanar and the second spacer contacts the lateral sidewall of the first spacer and the lateral sidewall of the nanowire channel layer directly; and a source/drain structure adjacent to two sides of the second spacer.

Claim (Index 19):
The nanowire transistor of  claim 18 , wherein the first spacer and the third spacer comprise different heights.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 3.35714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15146898', '16021949', '15867036', '14283404', '15822724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9168923772719956
- 35 USC 102 Novelty (BERT): 0.5183579288510597
- Combined Prediction Score: 0.8770389324299022
- Mean Citation Score: 264.15868600000005
- Max Citation Score: 296.0273
- Similarity Product: 225.28234435988068

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test