PATENT CLAIM ANALYSIS

Application Number: 16039067
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["714", "727000"]

Abstract:
A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Claim (Index 10):
The method of  claim 8 , in which the test access port complies with IEEE Standard 1149.1.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 95.0
- Lexical Diversity: 2.19178
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15226898', '12410599', '12835358', '11936880', '13852223']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3084082017139405
- 35 USC 102 Novelty (BERT): 0.5398907686666655
- Combined Prediction Score: 0.331556458409213
- Mean Citation Score: 226.103994
- Max Citation Score: 390.03903
- Similarity Product: 372.2424874972916

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test