PATENT CLAIM ANALYSIS

Application Number: 15868955
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "298000"]

Abstract:
A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

Claim (Index 1):
A method for fabricating a dynamic random access memory (DRAM) device with an embedded flash memory, comprising:\n providing a semiconductor substrate having a DRAM array region and a peripheral region, wherein the peripheral region includes an embedded flash memory forming region and a first transistor forming region; forming at least an oxide-nitride-oxide (ONO) layer on the DRAM array region and the peripheral region; patterning the ONO layer to form an ONO storage structure in the embedded flash memory forming region and reveal the semiconductor substrate in the first transistor forming region; forming a first gate oxide layer on the semiconductor substrate in the first transistor forming region; blanket depositing a first gate conductive layer over the DRAM array region and the peripheral region; performing a contact hole etching process on the DRAM array region to etch through the first gate conductive layer, the ONO layer and a portion of the semiconductor substrate to form a contact hole; blanket depositing a second gate conductive layer over the DRAM array region and the peripheral region and filling the second gate conductive layer into the contact hole to form a contact structure; forming a metal layer on the second gate conductive layer; and patterning the metal layer and the first and second gate conductive layers, thereby forming a flash memory gate on the ONO storage structure in the embedded flash memory forming region, a first transistor gate structure in the first transistor forming region, and at least one bit line in the DRAM array region.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.48649
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13332259', '13135220', '12259032', '11050988', '12576231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914645193046671
- 35 USC 102 Novelty (BERT): 0.4780664028118089
- Combined Prediction Score: 0.8709873140231849
- Mean Citation Score: 194.978674
- Max Citation Score: 203.99953
- Similarity Product: 159.02572113887368

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test