PATENT CLAIM ANALYSIS

Application Number: 15956090
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "288000"]

Abstract:
Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

Claim (Index 12):
The field effect transistor of  claim 7 , the interlayer dielectric layer comprising a silicon dioxide layer and the dielectric cap layer comprising a silicon nitride layer.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15878486', '15851774', '15388400', '15354212', '15468170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9388882645014964
- 35 USC 102 Novelty (BERT): 0.5468431682201443
- Combined Prediction Score: 0.8996837548733614
- Mean Citation Score: 405.260168
- Max Citation Score: 414.2269
- Similarity Product: 346.2717002146125

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test