PATENT CLAIM ANALYSIS

Application Number: 16133164
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "719000"]

Abstract:
Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

Claim (Index 17):
The apparatus of  claim 16 , further comprising solderballs on a surface of the BBUL package, the solderballs electrically coupled to the first semiconductor die.

Metadata:
- Claim Count in Document: 54.0
- Percentile: 97.0
- Lexical Diversity: 2.38235
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13995479', '13995629', '13996495', '13537573', '13891475']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.899270755085563
- 35 USC 102 Novelty (BERT): 0.5645190111788391
- Combined Prediction Score: 0.8657955806948906
- Mean Citation Score: 266.33498999999995
- Max Citation Score: 445.80023
- Similarity Product: 342.89227730086736

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test