PATENT CLAIM ANALYSIS

Application Number: 15749103
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "072000"]

Abstract:
The present invention provides a TFT substrate. The TFT substrate includes: a first display area and a second display area that are sequentially arranged in a vertical direction. Main pixel electrodes and sub pixel electrodes of the first display area are arranged in mirror symmetry with respect to main pixel electrodes and sub pixel electrodes of the second display area, respectively, about a horizontal division line of the first display area and the second display area. A scanning direction of the first display area is such that scanning is conducted from the side that the sub pixel electrode of one of the sub-pixels of the first display area is located toward the side that the main pixel electrode of the one of the sub-pixels is located. A scanning direction of the second display area is opposite to the scanning direction of the first display area. Thus, the first display area and the second display area generate, during scanning, a coupling signal first and then a pixel voltage is written in to thereby prevent the coupling signal from affecting the pixel voltage to cause poor displaying.

Claim (Index 10):
A thin-film transistor (TFT) substrate, comprising: a first display area and a second display area that are arranged sequentially in a vertical direction;\n wherein the first display area and the second display area each comprise: a plurality of sub-pixels arranged in an array, a plurality of horizontal scan lines that are arranged parallel to and spaced from each other, and a plurality of array substrate common electrode lines; each of rows of the sub-pixels corresponds to one of the scan lines, and each of the sub-pixels comprises: a main pixel electrode and a sub pixel electrode respectively located on two opposite sides of the one of the scan lines to which the sub-pixel correspond; and the plurality of array substrate common electrode lines and the plurality of scan lines are both located on a first metal layer and are arranged alternate with and spaced from each other; the main pixel electrodes and the sub pixel electrodes of the first display area are in mirror symmetry with respect to the main pixel electrodes and the sub pixel electrodes of the second display area, respectively, about a horizontal division line of the first display area and the second display area; the first display area has a scanning direction in which scanning is conducted from one side that the sub pixel electrode of one of the sub-pixels is located in the first display area toward one side that the main pixel electrode of the one of the sub-pixels is located and the second display area has a scanning direction that is opposite to the scanning direction of the first display area; wherein the first display area and the second display area each further comprise: a plurality of vertical data lines that are arranged parallel to and spaced from each other and each of the data lines corresponds to one of columns of the sub-pixels; wherein each of the sub-pixels further comprises: a main thin-film transistor, a sub thin-film transistor, and a charge-sharing thin-film transistor; the main thin-film transistor has a gate electrode electrically connected to the one of the scan lines to which the sub-pixel corresponds, a source electrode electrically connected to the one of the data lines to which the sub-pixel corresponds, and a drain electrode electrically connected to the main pixel electrode; the sub thin-film transistor has a gate electrode electrically connected to the one of the scan lines to which the sub-pixel corresponds, a source electrode electrically connected to the one of the data lines to which the sub-pixel corresponds, and a drain electrode electrically connected to the sub pixel electrode; the charge-sharing thin-film transistor has a gate electrode electrically connected to the one of the scan lines to which the sub-pixel corresponds, a source electrode electrically connected to the sub pixel electrode, and a drain electrode electrically connected to the array substrate common electrode line on one side of the sub-pixel where the sub pixel electrode is located; and the main pixel electrode and the array substrate common electrode line on the side where the main pixel electrode is located have parts overlapping each other to form a main storage capacitor and the sub pixel electrode and the array substrate common electrode line on the side where the sub pixel electrode is located have parts overlapping each other to form a sub storage capacitor; wherein the main pixel electrode and the sub pixel electrode are both of a Pozidriv structure; and wherein scanning of the first display area and scanning of the second display area are conducted simultaneously and independently.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 86.0
- Lexical Diversity: 2.9403
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15539689', '13699633', '11928804', '15725997', '12844837']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920519433124854
- 35 USC 102 Novelty (BERT): 0.4958415464586785
- Combined Prediction Score: 0.8780516444582365
- Mean Citation Score: 241.925614
- Max Citation Score: 265.60056000000003
- Similarity Product: 214.3036313942242

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test