PATENT CLAIM ANALYSIS

Application Number: 16058431
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["375", "300000"]

Abstract:
A signal distribution circuit including an equalization circuit, a signal distribution part, an operational amplifying circuit, a feedback circuit, and a time sequence circuit. The equalization circuit is configured to collect an initial broadband signal. The signal distribution part is configured to distribute a first-stage broadband signal resulting from amplitude attenuation process to obtain a plurality of same second-stage broadband signals. The operational amplifying circuit is configured to perform amplification processing on the second-stage broadband signal obtained after distribution to obtain a third-stage broadband signal. The feedback circuit is configured to feedback the third-stage broadband signal to the equalization circuit. The time sequence circuit is configured to adjust an amplification gain of the third-stage broadband signal, and transmit the third-stage broadband signal to an analog to digital converter.

Claim (Index 5):
The signal distribution circuit of  claim 4 , wherein the first-stage switching circuit comprises a first metal-oxide semiconductor (MOS) transistor (Q 1 ), a second MOS transistor (Q 2 ), a first amplifier (A 1 ) and a third capacitor (C 3 ), the second-stage switching circuit comprising a third MOS transistor (Q 3 ), a fourth MOS transistor (Q 4 ), a second amplifier (A 2 ) and a fourth capacitor (C 4 ), a drain of the Q 1  being coupled to a power source (AVDD), a source of the Q 1  being coupled to a gate of the Q 2 , a gate of the Q 1  being coupled to a bias voltage (Vbottom), a drain of the Q 3  being coupled to the AVDD, a source of the Q 3  being coupled to a gate of the Q 4 , a gate of the Q 3  being coupled to the Vbottom, a source of the Q 2  being coupled to a drain of the Q 4 , a drain of the Q 2  being coupled to the equalization circuit, a source of the Q 4  being coupled to the operational amplifying circuit, an input terminal of the A 1  being configured to receive a clock signal, an output terminal of the A 1  being coupled to one terminal of the C 3 , and the other terminal of the C 3  being coupled to the source of the Q 1 , an input terminal of the A 2  being configured to receive another clock signal, an output terminal of the A 2  being coupled to one terminal of the C 4 , the other terminal of the C 4  being coupled to the source of the Q 3 , and the first-stage broadband signal being configured to input from the drain of the Q 2  and output from the source of the Q 4 .

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.72549
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14917634', '16017672', '11520717', '15132471', '15118813']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.477767185239569
- 35 USC 102 Novelty (BERT): 0.4831975939518277
- Combined Prediction Score: 0.4783102261107949
- Mean Citation Score: 195.88048200000003
- Max Citation Score: 199.16809
- Similarity Product: 144.60193558192492

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test