PATENT CLAIM ANALYSIS

Application Number: 16110917
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["711", "108000"]

Abstract:
A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an instruction cache. In response to the CLA subsequently hitting in the instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the instruction cache.

Claim (Index 18):
The data processing system of  claim 17 , wherein the prefetch filter queue is implemented as a first-in first-out (FIFO) CAM.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.56897
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15151609', '15072717', '10197714', '12185219', '13023615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5685774761196295
- 35 USC 102 Novelty (BERT): 0.5830028646448927
- Combined Prediction Score: 0.5700200149721558
- Mean Citation Score: 315.798144
- Max Citation Score: 477.6528
- Similarity Product: 463.07642041425714

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test