PATENT CLAIM ANALYSIS

Application Number: 15940490
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["711", "206000"]

Abstract:
Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of the security properties, such as tamper resistant/detection and confidentiality, on a per TD basis. In one embodiment, a processing device including a memory controller and a memory paging circuit operatively coupled to the memory controller is provided. The memory paging circuit is to evict a memory page associated with a trust domain (TD) executed by the processing device. A binding of the memory page to a first memory location of the TD is removed. A transportable page that includes encrypted contents of the memory page is created. Thereupon, the memory page is provided to a second memory location.

Claim (Index 3):
The processing device of  claim 1 , wherein to remove the binding, the memory paging circuit is further to:\n decrypt contents of the memory page using a physical memory address associated with the TD.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.84932
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15712968', '15682056', '14048515', '14613307', '15282300']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5140943499227786
- 35 USC 102 Novelty (BERT): 0.4877190334883876
- Combined Prediction Score: 0.5114568182793395
- Mean Citation Score: 145.030846
- Max Citation Score: 170.27791000000005
- Similarity Product: 111.0572190836394

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test