PATENT CLAIM ANALYSIS

Application Number: 16039960
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["711", "118000"]

Abstract:
A lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed, as well as a barrier request that requests ordering of memory access requests prior to and after the barrier request. The barrier request precedes a copy-type request and a paste-type request of the memory move in program order. Prior to completion of processing of the barrier request, the lower level cache allocates first and second state machines to service the copy-type and paste-type requests. The first state machine speculatively reads a data granule identified by a source real address of the copy-type request into a non-architected buffer. After processing of the barrier request is complete, the second state machine writes the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.

Claim (Index 1):
A method of data processing in a data processing system implementing a weak memory model, wherein the data processing system includes an interconnect fabric and a processor core having a store-through upper level cache and a store-in lower level cache, the method comprising:\n the lower level cache receiving, from the processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed; the lower level cache receiving, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request, wherein the barrier request precedes a copy-type request and a paste-type request of the memory move in program order; prior to completion of processing of the barrier request by the lower level cache, the lower level cache speculatively reading a data granule identified by a source real address of the copy-type request into a non-architected buffer; and after processing of the barrier request is complete, the lower level cache writing the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 95.0
- Lexical Diversity: 2.35294
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15243628', '15243601', '15243446', '15243650', '15243385']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6828707340006023
- 35 USC 102 Novelty (BERT): 0.678381624653731
- Combined Prediction Score: 0.6824218230659151
- Mean Citation Score: 641.892852
- Max Citation Score: 699.80066
- Similarity Product: 688.6982612901353

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test