PATENT CLAIM ANALYSIS

Application Number: 16237836
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "189020"]

Abstract:
Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Claim (Index 7):
The design structure of  claim 4 , wherein the first latch and the second latch are different latch types.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 99.0
- Lexical Diversity: 2.78049
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15855243', '15974033', '13295992', '12168142', '11171540']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7888183251821946
- 35 USC 102 Novelty (BERT): 0.5259155644218498
- Combined Prediction Score: 0.7625280491061601
- Mean Citation Score: 251.558396
- Max Citation Score: 329.83194
- Similarity Product: 210.60779050266984

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test