PATENT CLAIM ANALYSIS

Application Number: 16263964
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["341", "141000"]

Abstract:
A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

Claim (Index 3):
The converter of  claim 1 , wherein the shuffle control switch circuitry is further configured to shuffle a second capacitor between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC after each conversion by the PDAC and NDAC, wherein the shuffle control switch circuitry is configured to selectably shuffle the first capacitor and the second capacitor between the PDAC and the NDAC.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 99.0
- Lexical Diversity: 1.22727
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15271697', '12113307', '12773768', '14919830', '13673103']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6161778310779923
- 35 USC 102 Novelty (BERT): 0.5529884333753592
- Combined Prediction Score: 0.609858891307729
- Mean Citation Score: 261.224594
- Max Citation Score: 396.1421
- Similarity Product: 307.752594538492

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test