PATENT CLAIM ANALYSIS

Application Number: 16013813
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["326", "080000"]

Abstract:
A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.

Claim (Index 9):
A system comprising:\n a controller configured to provide a command and a clock signal comprising a first frequency; and a command path coupled to the controller and configured to receive the command and the clock signal, comprising:\n a clock divider configured to generate an even clock signal and an odd clock signal based on the clock signal, wherein the even clock signal and the odd clock signal each comprises a second frequency that is half the first frequency; \n clock splitting circuitry configured to:\n when the clock signal and the even clock signal are in phase:\n output the command and the even clock signal to an even command path; and \n output the odd clock signal to an odd command path; and \n \n when the clock signal and the odd clock signal are in phase:\n output the command and the odd clock signal to the odd command path; and \n output the even clock signal to the even command path; \n \n \n the even command path coupled to the clock divider comprising a first set of logic and a first set of flip-flops, wherein the even command path is configured to output an even output signal based at least in part on receiving an output of the clock splitting circuitry; \n the odd command path coupled to the clock divider comprising a second set of logic and a second set of flip-flops, wherein the odd command path is configured to output an odd output signal based at least in part on receiving the output of the clock splitting circuitry; \n shift selection circuitry coupled to the even command path and the odd command path and configured to generate an output command based at least in part on the even output signal and the odd output signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 3.16279
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15649145', '12071198', '11647761', '11600079', '15693194']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6584347422923982
- 35 USC 102 Novelty (BERT): 0.551054591717878
- Combined Prediction Score: 0.6476967272349462
- Mean Citation Score: 258.226084
- Max Citation Score: 417.29547
- Similarity Product: 403.95780696634057

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test