PATENT CLAIM ANALYSIS

Application Number: 15884133
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["714", "773000"]

Abstract:
Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

Claim (Index 16):
The memory controller of  claim 15 , where the LLR measurement and update module instructions are executed after the flash memory detects the execution of a predetermined number of program-and-erase cycles in the flash memory.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 86.0
- Lexical Diversity: 2.08861
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14198862', '14064524', '14147825', '14094900', '14059229']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3781541299069546
- 35 USC 102 Novelty (BERT): 0.5597203283315144
- Combined Prediction Score: 0.3963107497494106
- Mean Citation Score: 366.088696
- Max Citation Score: 497.77356
- Similarity Product: 331.3788161423635

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test