PATENT CLAIM ANALYSIS

Application Number: 15928604
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["257", "040000"]

Abstract:
The present disclosure discloses an OLED display panel, including: a first substrate, a planarization layer, an auxiliary electrode, an anode formed on the planarization layer, a pixel definition layer, a cathode isolation column, an organic light-emitting layer, a cathode formed on the organic light-emitting layer. The cathode including a light-emitting cathode and an isolation cathode, the light-emitting cathode being disposed on the pixel definition layer and the pixel region, the isolation cathode being disposed on the cathode isolation column, the light-emitting cathode and the isolation cathode being isolated from each other by the cathode isolation column. An electrode stage electrically connected directly or indirectly to the auxiliary electrode, the cathode isolation column being formed on the electrode stage, the electrode stage electrically connected to the light-emitting cathode for the light-emitting cathode to receive a voltage on the auxiliary electrode. A manufacturing method of an OLED display panel also disclosed.

Claim (Index 4):
The OLED display panel according to  claim 3 , wherein the connection electrode comprises a first connection electrode and a second connection electrode, the OLED display panel further comprises a buffer layer and an interlayer insulating layer, the buffer layer is located on the first substrate, the interlayer insulating layer is located on the buffer layer, the planarization layer is located on the interlayer insulating layer, wherein the transfer electrode is located between the first substrate and the buffer layer, the first connection electrode is located on the interlayer insulating layer and electrically connected to the transfer electrode by a dug hole on the interlayer insulating layer, the second connection electrode is located on the planarization layer and electrically connected to the first connection electrode by a dug hole on the planarization layer, the electrode stage is located above the second connection electrode.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 2.98214
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15508103', '15367938', '15700385', '14919182', '15571037']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9304088443826942
- 35 USC 102 Novelty (BERT): 0.4997035538549834
- Combined Prediction Score: 0.8873383153299231
- Mean Citation Score: 257.88281800000004
- Max Citation Score: 263.0756
- Similarity Product: 203.6921088042021

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test