PATENT CLAIM ANALYSIS

Application Number: 15891032
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["375", "291000"]

Abstract:
A circuit includes a ring oscillator and a state capture register to receive a multi-bit state of the ring oscillator captured upon occurrence of an edge of input periodic signal. The circuit also includes an edge-phase detector to assert an edge detect high signal in response to a first reference clock derived from the ring oscillator being high upon occurrence of the edge of the input periodic signal and to assert an edge detect low signal in response to the first reference clock derived from the ring oscillator being low upon occurrence of the edge of the input periodic signal. A first register receives data from the state capture register upon occurrence of one of a rising or falling edge of a second clock derived from the ring oscillator.

Claim (Index 10):
The circuit of  claim 8 , wherein the register is a first register and the state encode is a first state encoder,\n wherein, upon occurrence of one of a rising or falling edge of a second clock derived from the ring oscillator, the first register is to receive the multi-bit state of the ring oscillator; wherein the first state encoder is to read the multi-bit state from the first register, invert even numbered bits of the multi-bit state read from the first register, and pad the multi-bit state read from the first register, with the even numbered bits inverted, with a plurality of logic 1's; wherein the circuit further includes a second register to receive the multi-bit state from the state capture register upon occurrence of the other of the rising or falling edge of the second clock; and wherein the circuit further includes a second state encoder to read the multi-bit state from the second register, invert odd numbered bits of the multi-bit state read from the second register, and pad the multi-bit state read from the second register, with the odd numbered bits inverted, with a plurality of logic 0's.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 88.0
- Lexical Diversity: 2.80851
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13533341', '14265148', '15866237', '11730508', '13756670']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5092274036623166
- 35 USC 102 Novelty (BERT): 0.483727560268366
- Combined Prediction Score: 0.5066774193229215
- Mean Citation Score: 205.174156
- Max Citation Score: 220.48187
- Similarity Product: 175.05709176601763

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test