PATENT CLAIM ANALYSIS

Application Number: 15906578
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["327", "156000"]

Abstract:
Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Claim (Index 28):
The method of  claim 24 , wherein a multiplexer coupled to said plurality of VCOs feeds back an output of one of said plurality of VCOs to said frequency divider.

Metadata:
- Claim Count in Document: 54.0
- Percentile: 88.0
- Lexical Diversity: 2.38806
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15236369', '15399040', '13353806', '12710595', '12535753']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7783735564501959
- 35 USC 102 Novelty (BERT): 0.531025308364929
- Combined Prediction Score: 0.7536387316416692
- Mean Citation Score: 222.74163000000004
- Max Citation Score: 369.58728
- Similarity Product: 342.52014611071587

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test