PATENT CLAIM ANALYSIS

Application Number: 16114958
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["708", "603000"]

Abstract:
A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

Claim (Index 1):
A circuit, comprising:\n a multiplier configured to operate on a first number and a second number; a first result register having an input coupled to an output of the multiplier, the first result register being configured to store an accumulated product; a first selection unit configured to select the first number from a first plurality of values and to provide the first number to the multiplier, wherein the first plurality of values comprises a first operand; a second selection unit configured to select the second number from a second plurality of values and to provide the second number to the multiplier, wherein the second plurality of values comprises a second operand; an adder configured to operate on a third number and a fourth number; a second result register having an input coupled to an output the adder, the second result register being configured to store an accumulated sum; a third selection unit configured to select the third number from a third plurality of values and to provide the third number to the adder; and a fourth selection unit configured to select the fourth number from a fourth plurality of values and to provide the fourth number to the adder, wherein the fourth plurality of values comprises a third operand, wherein an output of the first result register is coupled to a first input of the first selection unit and to a first input of the third selection unit, and wherein an output of the second result register is coupled to a first input of the second selection unit and to a first input of the fourth selection unit.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 96.0
- Lexical Diversity: 4.15
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15275037', '10435976', '11749224', '15283606', '11019735']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3909611847966156
- 35 USC 102 Novelty (BERT): 0.5225202490313431
- Combined Prediction Score: 0.4041170912200884
- Mean Citation Score: 234.556014
- Max Citation Score: 320.34332
- Similarity Product: 295.61119414613245

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test