PATENT CLAIM ANALYSIS

Application Number: 15742850
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["710", "061000"]

Abstract:
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.

Claim (Index 16):
The apparatus of  claim 15 , wherein the control circuit further comprises:\n a sync pulse circuit to generate, based on the synchronization command, a sync pulse having a selected transition aligned with a selected transition of the clock signal; a counter circuit to increment, after initialization by the sync pulse, a value of the counter circuit on every selected transition of the clock signal; and a latch circuit to store, in response to the event, the value of the counter circuit, wherein the information about the elapsed time is based at least in part on the value of the counter circuit.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 2.38806
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14949534', '13901771', '14616572', '15295222', '14595030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.738777764823279
- 35 USC 102 Novelty (BERT): 0.5012231196310148
- Combined Prediction Score: 0.7150223003040526
- Mean Citation Score: 254.894122
- Max Citation Score: 266.9466
- Similarity Product: 191.06008604106896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test