PATENT CLAIM ANALYSIS

Application Number: 16073479
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["257", "531000"]

Abstract:
To inhibit a decrease in inductance of an inductor in a plurality of semiconductor chips that are stacked. A semiconductor device includes: first and second semiconductor chips that are stacked; a first inductor; an arrangement-restricted region; and a circuit. In the semiconductor device, the first inductor is arranged in the first semiconductor chip. The arrangement-restricted region is provided in a region of the second semiconductor chip corresponding to the first inductor. The circuit is arranged in a region of the second semiconductor chip not corresponding to the arrangement-restricted region.

Claim (Index 8):
The semiconductor device according to  claim 1 ,\n wherein the first inductor includes first wiring wound clockwise from a predetermined start point to a predetermined connection point, and second wiring wound counterclockwise from the predetermined connection point to a predetermined end point.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.60526
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11368614', '15499233', '13146603', '10722561', '15858529']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9197374547205748
- 35 USC 102 Novelty (BERT): 0.4716805140196999
- Combined Prediction Score: 0.8749317606504873
- Mean Citation Score: 171.88918
- Max Citation Score: 174.0586
- Similarity Product: 134.79771229058505

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test