PATENT CLAIM ANALYSIS

Application Number: 15980503
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "316000"]

Abstract:
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Claim (Index 15):
A memory array, comprising:\n multiple strings of memory cells, separated by alternating dielectrics, separating each memory cell in the string by a respective alternating dielectric from an adjacent memory cell in the string, wherein each memory cell string includes,\n a respective channel material forming a channel for memory cells of the string, and \n wherein each memory cell of a memory cell string includes,\n a control gate extending between first alternating dielectric at a first surface of the memory cell and a second alternating dielectric at a second surface of the memory cell; \n a floating gate extending between the first alternating dielectric and the second alternating dielectric, the floating gate including a first portion and a second portion,\n wherein the first portion has a first dimension along the direction of current flow through the channel material, and \n wherein the second portion has a second dimension along the direction of current flow through the channel material that is less than the first dimension to form a protrusion extending from the first portion toward the control gate; \n \n a third dielectric between the second portion of the floating gate and the control gate, a portion of the third dielectric extending between the second portion and at least one of the first and second alternating dielectrics; and \n a fourth dielectric between the first portion of the floating gate and the channel material.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 93.0
- Lexical Diversity: 2.52778
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15691477', '14925589', '13838297', '14987147', '13864794']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9119993122940688
- 35 USC 102 Novelty (BERT): 0.4900654308801286
- Combined Prediction Score: 0.8698059241526749
- Mean Citation Score: 212.31179
- Max Citation Score: 242.12383
- Similarity Product: 190.51196918090525

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test