PATENT CLAIM ANALYSIS

Application Number: 15971875
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["711", "110000"]

Abstract:
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

Claim (Index 3):
A digital data processor comprising:\n an instruction memory storing instructions each specifying a data processing operation and at least one data operand field; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results; a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said specified sequence including at least one loop having a circular addressing mode with a first circular block size number and a second circular block size number, said streaming engine including\n an address generator for generating stream memory addresses corresponding to said stream of an instruction specified sequence of a plurality of data elements in said at least one loop employing circular addressing having a block size of a selected on of a first block size corresponding to said first block size number and a second block size corresponding to a sum of said first block size number and a second block size number, \n a stream head register storing a data element of said stream next to be used by said at least one functional unit; and \n wherein said at least one functional unit is responsive to a stream operand instruction to receive at least one operand from said stream head register.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.57895
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15384514', '15384451', '15384487', '15635409', '15395028']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5636625135739876
- 35 USC 102 Novelty (BERT): 0.6059856234602741
- Combined Prediction Score: 0.5678948245626163
- Mean Citation Score: 420.085866
- Max Citation Score: 534.4614
- Similarity Product: 510.84030695918807

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test