PATENT CLAIM ANALYSIS

Application Number: 15973992
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "288000"]

Abstract:
A method for manufacturing a semiconductor device includes forming a plurality of silicon germanium and silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer. The stacked configuration is patterned into a plurality of patterned stacks spaced apart from each other. The patterning forms a plurality of recessed portions in the substrate. In the method, the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of the silicon germanium layers, and inner spacer layers are formed in place of the removed portions. A plurality of lower epitaxial layers are grown in the recessed portions. A plurality of epitaxial source/drain regions are grown from the lower epitaxial layers and from exposed lateral sides of the silicon layers.

Claim (Index 1):
A method for manufacturing a semiconductor device, comprising:\n forming a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer; patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, wherein the patterning forms a plurality of recessed portions in the semiconductor substrate; etching the plurality of silicon germanium layers to remove portions of the plurality of silicon germanium layers from exposed lateral sides of each of the plurality of silicon germanium layers; forming an inner spacer layer in place of each of the removed portions of the plurality of silicon germanium layers; growing a plurality of lower epitaxial layers in the plurality of recessed portions in a first epitaxial growth process, wherein the plurality of lower epitaxial layers have one or more edges aligned with outer edges of adjacent ones of the plurality of patterned stacks; and growing a plurality of epitaxial source/drain regions adjacent the plurality of patterned stacks, wherein the plurality of epitaxial source/drain regions are grown from the plurality of lower epitaxial layers and from exposed lateral sides of the plurality of silicon layers in a second epitaxial growth process.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 93.0
- Lexical Diversity: 2.47458
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15873469', '15823684', '15802062', '15847894', '15069468']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9304493979700564
- 35 USC 102 Novelty (BERT): 0.5311589897894103
- Combined Prediction Score: 0.890520357151992
- Mean Citation Score: 338.676326
- Max Citation Score: 369.9261
- Similarity Product: 354.7344314934612

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test