PATENT CLAIM ANALYSIS

Application Number: 15860786
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["365", "063000"]

Abstract:
A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

Claim (Index 15):
The non-volatile memory as claimed in  claim 13 , further comprising:\n a third word line; a fourth word line; a third auxiliary line; a fourth auxiliary line; a second control line; a second erase line; and a third memory cell comprising an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a fifth capacitor and a sixth capacitor, wherein the eleventh transistor comprises an eleventh gate, a twenty-first terminal and a twenty-second terminal, the twelfth transistor includes a twelfth gate, a twenty-third terminal and a twenty-fourth terminal, the thirteenth transistor comprises a thirteenth gate, a twenty-fifth terminal and a twenty-sixth terminal, the fourteenth transistor comprises a fourteenth gate, a twenty-seventh terminal and a twenty-eighth terminal, the fifteenth transistor comprises a fifteenth gate, a twenty-ninth terminal and a thirtieth terminal, the fifth capacitor is connected between the thirteenth gate and the second control line, and the sixth capacitor is connected with the thirteenth gate and the second erase line, wherein the thirteenth gate is a floating gate, the twenty-second terminal is connected with the twenty-third terminal, the twenty-fourth terminal is connected with the twenty-fifth terminal, the twenty-sixth terminal is connected with the twenty-seventh terminal, the twenty-eighth terminal is connected with the twenty-ninth terminal, the twenty-first terminal is connected with the first bit line, the thirtieth terminal is connected with the first source line, the eleventh gate is connected with the third word line, the twelfth gate is connected with the third auxiliary line, the fourteenth gate is connected with the fourth auxiliary line, and the fifteenth gate is connected with the fourth word line.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 86.0
- Lexical Diversity: 4.65714
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15151013', '15257359', '14471613', '15481889', '15257292']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8180093265653152
- 35 USC 102 Novelty (BERT): 0.5037948113895493
- Combined Prediction Score: 0.7865878750477386
- Mean Citation Score: 290.654716
- Max Citation Score: 299.1154
- Similarity Product: 217.6612117551804

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test