PATENT CLAIM ANALYSIS

Application Number: 15872610
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "394000"]

Abstract:
Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.

Claim (Index 11):
A method of forming a semiconductor structure, the method comprising:\n providing a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet located on a surface of a semiconductor substrate composed of a semiconductor material of a first conductivity type, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack, and the semiconductor substrate has physically exposed recessed surfaces that lay adjacent the sacrificial gate structure and the dielectric spacer material layer, wherein the semiconductor substrate includes a lower region having a first dopant concentration, a middle region having a second dopant concentration and an upper region having a third dopant concentration, wherein the second dopant concentration is less than the first and third dopant concentrations; recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets; forming an additional dielectric spacer material layer on the dielectric spacer material layer and within each gap and on the recessed surfaces of the semiconductor substrate; removing the additional dielectric spacer material layer from the recessed surfaces to re-expose the recessed surface; forming a counter doped semiconductor layer composed of a semiconductor material of a second conductivity type that differs from the first conductivity type on the re-exposed recessed surfaces of the semiconductor substrate; physically exposing sidewalls of each semiconductor channel material nanosheet; and forming a source/drain (S/D) region by epitaxial growth of a semiconductor material on the physically exposed sidewalls of each semiconductor channel material nanosheet, wherein each S/D region is present on a surface of one of the counter doped semiconductor layers.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 86.0
- Lexical Diversity: 1.90476
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15727310', '15834380', '15802067', '15005665', '15802021']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.941007545156908
- 35 USC 102 Novelty (BERT): 0.5652903787076137
- Combined Prediction Score: 0.9034358285119783
- Mean Citation Score: 433.26454
- Max Citation Score: 465.0944
- Similarity Product: 387.7916439117432

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test