PATENT CLAIM ANALYSIS

Application Number: 15860266
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["320", "107000"]

Abstract:
The present disclosure provides a power adapter, an electronic device and a charging apparatus. In the process of charging a battery in a conventional charge mode after the power adapter is powered on, the power adapter carries out quick charge inquiry communication with the electronic device when an output current value of the power adapter is within a conventional current range for a preset time interval; after the electronic device sends a quick charge command to the power adapter, the power adapter adjusts the output voltage according to the battery voltage information fed back by the electronic device; and when the output voltage meets a voltage requirement for quick charge preset by the electronic device, the power adapter adjusts the output current and the output voltage for charging the battery in a quick charge mode.

Claim (Index 3):
The power adapter of  claim 1 , wherein,\n the main control circuit comprises: a main control chip, a third resistor, a reference voltage chip, a fourth resistor, a fifth resistor, a fourth capacitor, a sixth resistor, a seventh resistor, a first NMOS transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor; a power pin of the main control chip is configured as the power terminal of the main control circuit; a ground pin of the main control chip is grounded, a first input/output pin of the main control chip is suspended, a first terminal of the third resistor is coupled to the power pin of the main control chip, a second terminal of the third resistor and a first terminal of the fourth resistor are jointly coupled to a cathode of the reference voltage chip, an anode of the reference voltage chip is grounded, a vacant pin of the reference voltage chip is suspended; a second terminal of the fourth resistor is coupled to a second input/output pin of the main control chip; a third input/output pin of the main control chip is configured as the current detection terminal of the main control circuit; a fourth input/output pin of the main control chip is coupled to a first terminal of the fifth resistor; a second terminal of the fifth resistor and a first terminal of the fourth capacitor are jointly coupled to the power pin of the main control chip, a second terminal of the fourth capacitor is grounded; a fifth input/output pin of the main control chip is configured as the switch control terminal of the main control circuit; a sixth input/output pin of the main control chip is coupled to a first terminal of the sixth resistor; a second terminal of the sixth resistor and a gate electrode of the first NMOS transistor are jointly coupled to a first terminal of the seventh resistor; a second terminal of the seventh resistor and a source electrode of the first NMOS transistor are jointly grounded; a drain electrode of the first NMOS transistor is coupled to a first terminal of the eighth resistor; a second terminal of the eighth resistor is configured as the high-potential terminal of the main control circuit; a seventh input/output pin and an eighth input/output pin of the main control chip are configured as the clock output terminal and the data output terminal of the main control circuit respectively; a tenth input/output pin and a ninth input/output pin of the main control chip are configured as the first voltage detection terminal and the second voltage detection terminal of the main control circuit respectively; an eleventh input/output pin and a twelfth input/output pin of the main control chip are coupled to a first terminal of the ninth resistor and a first terminal of the tenth resistor respectively; a first terminal of the eleventh resistor and a first terminal of the twelfth resistor are coupled to a second terminal of the ninth resistor and a second terminal of the tenth resistor respectively; a second terminal of the eleventh resistor and a second terminal of the twelfth resistor are jointly grounded; a first terminal of the thirteenth resistor and a first terminal of the fourteenth resistor are coupled to the second terminal of the ninth resistor and the second terminal of the tenth resistor respectively; a second terminal of the thirteenth resistor and a second terminal of the fourteenth resistor are jointly coupled to the power pin of the main control chip; and the second terminal of the ninth resistor and the second terminal of the tenth resistor are configured as the first communication terminal and the second communication terminal of the main control circuit respectively.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.50877
- Patent Class: 320.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15113973', '15596009', '15596884', '15115203', '15115251']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7702091333539725
- 35 USC 102 Novelty (BERT): 0.5345852982638969
- Combined Prediction Score: 0.7466467498449649
- Mean Citation Score: 351.751086
- Max Citation Score: 371.28656
- Similarity Product: 361.0810137653448

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test