PATENT CLAIM ANALYSIS

Application Number: 15748156
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["327", "427000"]

Abstract:
A switch control circuit includes: a clock circuit ( 110 ) configured to generate a first clock control signal (CLK 1 ) and a second clock control signal (CLK 2 ); a voltage boosting circuit ( 120 ) configured to receive the second clock control signal (CLK 2 ) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H 1 ) under the control of the second clock control signal (CLK 2 ); and an inverting circuit ( 130 ) configured to receive the first clock control signal (CLK 1 ) and the switch control signal (H 1 ), and determine whether or not to output the switch control signal (H 1 ) to the switch circuit according to the first clock control signal (CLK 1 ), so as to control on/off of the switch circuit.

Claim (Index 10):
The switch control circuit of  claim 9 , wherein the fourth inverting unit is a CMOS inverter and comprises a fifth MOS transistor and a sixth MOS transistor; the fifth MOS transistor is a PMOS transistor, and the sixth MOS transistor is an NMOS transistor; a gate of the fifth MOS transistor is coupled to a gate of the sixth MOS transistor and then coupled to the clock circuit to receive the second clock control signal; a source of the fifth MOS transistor is coupled to the power source; a drain of the fifth MOS transistor is coupled to a drain of the sixth MOS transistor and then coupled to the negative plate of the bootstrap capacitor; and a source of the sixth MOS transistor is grounded.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 3.14815
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16328402', '12437422', '11480341', '11844728', '12125589']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7921846459658524
- 35 USC 102 Novelty (BERT): 0.4692257376075898
- Combined Prediction Score: 0.7598887551300262
- Mean Citation Score: 209.077094
- Max Citation Score: 214.20322
- Similarity Product: 184.4631002721977

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test