PATENT CLAIM ANALYSIS

Application Number: 15969252
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "369000"]

Abstract:
A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.

Claim (Index 10):
The method of  claim 8 , wherein the channel region of the first transistor area and the second transistor area comprise a first channel type, and the channel region of the third transistor area and the fourth transistor area are a second channel type that is different than the first channel type.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.48485
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14994650', '15723283', '13780003', '13733936', '12954946']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927483723861369
- 35 USC 102 Novelty (BERT): 0.5059726685265646
- Combined Prediction Score: 0.8853326183278886
- Mean Citation Score: 240.75942
- Max Citation Score: 250.53867
- Similarity Product: 167.11620591808676

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test