PATENT CLAIM ANALYSIS

Application Number: 16029677
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["714", "752000"]

Abstract:
A method for dynamically adapting a clock frequency used to perform low-density parity check (LDPC) decoding includes: setting a first clock frequency for performing a first LDPC decoding iteration on a received codeword to generate a decoded codeword; performing a successive plurality of LDPC decoding iterations on the decoded codeword; at the end of each LDPC decoding iteration, determining a number of error bits of the decoded codeword and a throughput of the LDPC decoding iteration; and when a number of the error bits increases, increasing the clock frequency for performing a next LDPC decoding iteration so that a throughput of the next LDPC decoding iteration is the same as the throughput of the immediately preceding iteration. The first clock frequency is set according to a number of error bits in an immediately previous decoding operation.

Claim (Index 6):
The LDPC decoder of  claim 4 , wherein the first clock frequency is set according to a number of error bits in an immediately previous decoding operation.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.28125
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15073606', '14723565', '15075986', '15086006', '13194952']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.317723496607284
- 35 USC 102 Novelty (BERT): 0.5580069518287958
- Combined Prediction Score: 0.3417518421294352
- Mean Citation Score: 334.90765
- Max Citation Score: 456.43628
- Similarity Product: 309.5428998923779

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test