PATENT CLAIM ANALYSIS

Application Number: 15881186
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "409000"]

Abstract:
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

Claim (Index 18):
The device of  claim 17 , further comprising a plurality of conductive vias, wherein:\n a first conductive via of the plurality of conductive vias is electrically connected to and disposed directly over the first source/drain region and the first conductive via of the plurality of conductive vias is electrically connected to and disposed directly under the first conductive via; a second conductive via of the plurality of conductive vias is electrically connected to and disposed directly over the anode and the second conductive via of the plurality of conductive vias is electrically connected to and disposed directly under the second conductive via; a third conductive via of the plurality of conductive vias is electrically connected to and disposed directly over the guard ring and the third conductive via of the plurality of conductive vias is electrically connected to and disposed directly under the third conductive via, wherein top surfaces of each of the conductive vias of the plurality of conductive vias are co-planar with a top surface of the third dielectric layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.48148
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15215306', '13149547', '14059123', '13349723', '13362411']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.910266766254528
- 35 USC 102 Novelty (BERT): 0.5030764414971878
- Combined Prediction Score: 0.869547733778794
- Mean Citation Score: 193.701854
- Max Citation Score: 243.10864
- Similarity Product: 161.3177277785492

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test