PATENT CLAIM ANALYSIS

Application Number: 15963297
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "368000"]

Abstract:
Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

Claim (Index 9):
The method of  claim 1 , further comprising forming a gate isolation region between the first gate structure and the second gate structure.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 2.12069
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15938812', '15707682', '15799555', '14192742', '15282836']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9112627207502888
- 35 USC 102 Novelty (BERT): 0.4866825295216219
- Combined Prediction Score: 0.8688047016274221
- Mean Citation Score: 185.6864
- Max Citation Score: 198.18988
- Similarity Product: 139.45389874875067

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test