PATENT CLAIM ANALYSIS

Application Number: 15959398
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["716", "113000"]

Abstract:
Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Claim (Index 1):
A computer program product using a computing device to reduce the runtime overhead needed for testing of an integrated circuit design, the computer program product comprising:\n one or more non-transitory computer-readable storage media and program instructions stored on the one or more non-transitory computer-readable storage media, the program instructions, when executed by the computing device, cause the computing device to perform a method comprising:\n determining, by the computing device, parameters that clock routing and data routing in an integrated circuit are dependent upon, the parameters comprising any source of variation in the integrated circuit which impact a delay or slew of voltage through the integrated circuit; \n determining, by the computing device, whether the parameters are suitable for compaction by determining whether the parameters are utilized in only one of clock routing and data routing; \n redefining, by the computing device, the parameters suitable for compaction into at least one proxy compacted parameter; \n performing, by the computing device, a path-based or a block-based statistical static timing analysis for the integrated circuit using the at least one proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction; and \n generating an updated circuit design for the integrated circuit if the integrated circuit design fails the statistical static timing analysis, \n wherein the parameters are selected from a group consisting of one or more of the following: variation in a thickness of a fabricated component in the integrated circuit, variation in a wire segment or silicon transistor shape in the integrated circuit, variation in dopants or implants utilized in the manufacture of the integrated circuit, variations in device threshold voltage, variations in supply voltage for the integrated circuit, variations in device threshold voltage, variations in supply voltage for the integrated circuit, and variations in a temperature across the integrated circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.96429
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15620992', '15704429', '15959381', '13780413', '15244541']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3547394904155495
- 35 USC 102 Novelty (BERT): 0.4392839318502306
- Combined Prediction Score: 0.3631939345590176
- Mean Citation Score: 175.57767800000005
- Max Citation Score: 206.7151
- Similarity Product: 197.22151983831523

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test