PATENT CLAIM ANALYSIS

Application Number: 15988805
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "066000"]

Abstract:
The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.

Claim (Index 9):
The method of fabricating a thin film transistor of  claim 8 , wherein, prior to the step of forming the first source and the first drain above the base substrate, the method further comprises:\n forming a first conductive pattern on the base substrate such that the first conductive pattern extends beyond a region surrounded by the first drain which will be formed later; forming a first insulation layer at a side of the first conductive pattern facing away from the base substrate, and forming a first via in the first insulation layer such that the first source which will be formed later is connected with the first conductive pattern through the first via, and wherein, after the step of forming the second source and the second drain at the side of the second active layer facing away from the base substrate, the method further comprises: forming a second insulation layer at a side of the second source and the second drain facing away from the base substrate, and forming a second via in the second insulation layer; forming a second conductive pattern at a side of the second insulation layer facing away from the base substrate such that the second conductive pattern is connected with the second source through the second via, and the second conductive pattern extends beyond a region surrounded by the second drain, wherein, a portion of the second conductive pattern located outside of the region surrounded by the second drain is connected with a portion of the first conductive pattern located outside of the region surrounded by the first drain, and wherein, a third conductive pattern connected with the first drain is formed at a same time when the first source and the first drain are formed above the base substrate, wherein, a fourth conductive pattern connected with the second drain is formed at a same time when the second source and the second drain are formed at the side of the second active layer facing away from the base substrate, and wherein, the fourth conductive pattern is connected with the third conductive pattern.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 3.975
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14764307', '14769577', '14912822', '11316967', '15127262']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9266344924589592
- 35 USC 102 Novelty (BERT): 0.4933551781584067
- Combined Prediction Score: 0.8833065610289041
- Mean Citation Score: 230.082852
- Max Citation Score: 236.87231
- Similarity Product: 179.23826479404332

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test