PATENT CLAIM ANALYSIS

Application Number: 16007885
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.

Claim (Index 19):
The method of  claim 15 , wherein etching the protection layer and etching the foot portions facing each other of the first gate and the second gate are performed in single one process or in sequential processes.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 3.89474
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14220299', '15194711', '15222334', '14828652', '14833627']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9082060538118304
- 35 USC 102 Novelty (BERT): 0.4752937066729192
- Combined Prediction Score: 0.8649148190979392
- Mean Citation Score: 110.41713
- Max Citation Score: 112.67836
- Similarity Product: 74.47102171396257

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test