PATENT CLAIM ANALYSIS

Application Number: 15911415
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Claim (Index 14):
The transistor structure of  claim 10 , wherein a width of the gate area is substantially equal along an entire height of the fin.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 90.0
- Lexical Diversity: 2.71429
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15073740', '15626321', '15868224', '15793419', '14754958']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9234096688839482
- 35 USC 102 Novelty (BERT): 0.5303529801161817
- Combined Prediction Score: 0.8841040000071716
- Mean Citation Score: 241.043104
- Max Citation Score: 347.99800000000016
- Similarity Product: 231.4804687705041

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test