PATENT CLAIM ANALYSIS

Application Number: 16057826
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "048000"]

Abstract:
A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.

Claim (Index 3):
The semiconductor pattern for monitoring overlay and critical dimension at post-etching stage of  claim 1 , wherein said spacer patterns are self-aligned double patterns.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 1.82222
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15630966', '15938002', '12266459', '14225329', '11759055']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8985234764883123
- 35 USC 102 Novelty (BERT): 0.4818092614419209
- Combined Prediction Score: 0.8568520549836732
- Mean Citation Score: 145.27557199999995
- Max Citation Score: 189.57446
- Similarity Product: 150.23606823809385

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test