PATENT CLAIM ANALYSIS

Application Number: 16227383
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["712", "208000"]

Abstract:
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can receive, from a software application, a request to perform an operation on a first set of variables that includes a first input value and a register value and perform the operation on a second set of variables that includes a second input value and the first register value. The processor core can vectorize the operation on the first set of variables and the second set of variables. The processor core can perform the operation on the first set of variables and the second set of variables in parallel to obtain a first operation value and a second operation value. The processor core can perform a horizontal add operation on the first operation value and the second operation value and write the result to memory.

Claim (Index 6):
A system comprising:\n a memory device; and a processor coupled to the memory device, the processor comprising:\n a register array comprising a first element that stores a first register value that identifies a first memory location, a second element that stores a second register value that identifies a second memory location, and a third element that stores a third register value that identifies a third memory location; \n a decoder circuit to:\n receive a single instruction multiple data (SIMD) instruction from an application, the SIMD instruction identifying the register array and an array of input values comprising at least a first input value, a second input value, and a third input value; and \n decode the SIMD instruction; and \n \n a processor core to:\n perform an operation on the first input value and the first register value to obtain a first operation value, and wherein the first register value is stored at a first location of the register array; \n perform the operation on the second input value and the second register value to obtain a second operation value, and wherein the second register value is stored at a second location of the register array; and \n perform the operation the third input value and the third register value, and wherein the second register value is stored at a third location of the register array, wherein the operation on the first, second, and third input values are performed in parallel; \n associate the first operation value with the first location; \n associate the second operation value with the second location; \n associate a third operation value with the third location; \n determine that the first register value and the second register value are the same value, wherein the third register value is different than the first register value and the second register value; \n perform a horizontal add operation on the first operation value and the second operation value to obtain a result value; \n write the result value to the second memory location, wherein the second memory location and the first memory location are the same when the first register value and the second register value are the same; and \n write the third operation value to the third memory location.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 3.03846
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15301206', '15301224', '13795234', '15396568', '13487184']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4993655528401994
- 35 USC 102 Novelty (BERT): 0.4818179056584968
- Combined Prediction Score: 0.4976107881220292
- Mean Citation Score: 162.34383200000005
- Max Citation Score: 243.65208
- Similarity Product: 223.08860007486825

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test