PATENT CLAIM ANALYSIS

Application Number: 16033377
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "303000"]

Abstract:
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

Claim (Index 33):
An apparatus comprising a semiconductor base and a plurality of memory cells, each of the plurality of memory cells comprising:\n a first transistor including first and second source/drain regions formed in the semiconductor base, a first channel region therebetween and a first gate controlling the first channel region, the first gate being electrically connected to a first wordline; a second transistor including third and fourth source/drain regions, a second channel region therebetween and a second gate controlling the second channel region, the third and fourth source/drain regions and the second channel region being vertically disposed with one another between a first bit line and a common plate over the semiconductor base, and the second gate being electrically coupled to the second source/drain region of the first transistor; wherein each of the plurality of memory cells further comprises a third transistor disposed above the second transistor, the third transistor including fifth and sixth source/drain regions vertically disposed with one another and a third channel region therebetween, the fifth source/drain region electrically coupled with the fourth source/drain region; and wherein the second channel region is larger than the third channel region in length.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 3.44681
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16006301', '15664183', '15664217', '15664143', '15664161']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9272215844257802
- 35 USC 102 Novelty (BERT): 0.5181023847846019
- Combined Prediction Score: 0.8863096644616624
- Mean Citation Score: 301.80616999999995
- Max Citation Score: 329.5861
- Similarity Product: 260.2062019005358

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test