PATENT CLAIM ANALYSIS

Application Number: 15912363
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["711", "207000"]

Abstract:
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Claim (Index 6):
The processor of  claim 1  wherein the execution circuitry is to execute a second TLB management instruction having an operand to identify an individual guest virtual address, the execution circuitry to invalidate at least one TLB entry associated with the guest virtual address.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 2.02632
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15620663', '14675292', '14675297', '14675325', '14867024']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6012022900325241
- 35 USC 102 Novelty (BERT): 0.5194819569539098
- Combined Prediction Score: 0.5930302567246627
- Mean Citation Score: 339.909782
- Max Citation Score: 342.6068
- Similarity Product: 307.49239331951145

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test