PATENT CLAIM ANALYSIS

Application Number: 15867427
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "421000"]

Abstract:
The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.

Claim (Index 9):
A semiconductor structure, comprising:\n a logic region; and a memory region, comprising:\n an N th  metal layer; \n an (N+M) th  metal layer over the N th  metal layer, N and M being positive integers; and \n a magnetic random access memory (MRAM) structure between the N th  metal layer and the (N+M) th  metal layer, \n wherein the MRAM structure comprises a bottom electrode via (BEVA) and a recap layer covering only an entire top surface of the BEVA.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 86.0
- Lexical Diversity: 2.63889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15130065', '15159669', '15151207', '14969697', '15834726']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9259552256997688
- 35 USC 102 Novelty (BERT): 0.5364820320636456
- Combined Prediction Score: 0.8870079063361566
- Mean Citation Score: 311.53208
- Max Citation Score: 382.064
- Similarity Product: 320.9799787416458

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test