PATENT CLAIM ANALYSIS

Application Number: 16358613
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["438", "151000"]

Abstract:
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Claim (Index 1):
An integrated circuit structure, comprising:\n a semiconductor fin; a first gate stack portion above the semiconductor fin, the first gate stack portion comprising a gate dielectric material on a top surface, on a bottom surface and on sidewalls of a gate electrode material; a nanowire on the first gate stack portion; a pair of insulative spacers beneath the nanowire, wherein a first of the pair of insulative spacers is in contact with a first side of the first gate stack portion, and a second of the pair of insulative spacers is in contact with a second side of the first gate stack portion; and a second gate stack portion on the nanowire, the second gate stack portion comprising a gate dielectric material on a bottom surface and on sidewalls of a gate electrode material; a first source or drain structure laterally adjacent to and in contact with the first of the pair of insulative spacers and a first end of the nanowire; and a second source or drain structure laterally adjacent to and in contact with the second of the pair of insulative spacers and a second end of the nanowire.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.51613
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16153456', '15859226', '13539195', '15333123', '15118838']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8569738819630011
- 35 USC 102 Novelty (BERT): 0.5150412747376322
- Combined Prediction Score: 0.8227806212404641
- Mean Citation Score: 302.51335200000005
- Max Citation Score: 331.07196
- Similarity Product: 308.1871446725893

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test