PATENT CLAIM ANALYSIS

Application Number: 16053665
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-01
Patent Classification: ["257", "344000"]

Abstract:
A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer.

Claim (Index 12):
The method for fabricating semiconductor device of  claim 9 , wherein each of the first gate structure and the second gate structure comprises:\n a gate insulation layer on the substrate; and a gate layer, stacked from multiple layers, on the gate insulating layer.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 96.0
- Lexical Diversity: 2.80488
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13562659', '13875746', '13895376', '12706191', '12179395']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9320727347747187
- 35 USC 102 Novelty (BERT): 0.5001909193634934
- Combined Prediction Score: 0.8888845532335964
- Mean Citation Score: 249.09399
- Max Citation Score: 261.60583
- Similarity Product: 198.4980758168776

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test