PATENT CLAIM ANALYSIS

Application Number: 15891032
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["375", "291000"]

Abstract:
A circuit includes a ring oscillator and a state capture register to receive a multi-bit state of the ring oscillator captured upon occurrence of an edge of input periodic signal. The circuit also includes an edge-phase detector to assert an edge detect high signal in response to a first reference clock derived from the ring oscillator being high upon occurrence of the edge of the input periodic signal and to assert an edge detect low signal in response to the first reference clock derived from the ring oscillator being low upon occurrence of the edge of the input periodic signal. A first register receives data from the state capture register upon occurrence of one of a rising or falling edge of a second clock derived from the ring oscillator.

Claim (Index 16):
A circuit, comprising:\n a ring oscillator; a state capture register, coupled to the ring oscillator, to capture a state of the ring oscillator upon occurrence of an edge of an input periodic signal; a first register to receive the captured state from the state capture register upon occurrence of one of a rising or falling edge of a first clock derived from the ring oscillator; a first state encoder, coupled to the first register, to read data from the first register, invert even numbered bits of the data read from the first register, and pad the data read from the first register, with the even numbered bits inverted, with a plurality of digital 1's; a second register to receive the captured state from the state capture register upon occurrence of the other of the rising or falling edge of the first clock; a second state encoder, coupled to the second register, to read data from the second register, invert odd numbered bits of the data read from the second register, and pad the data read from the second register, with the odd numbered bits inverted, with a plurality of logic 0's; and a selection circuit to select an output of the first state encoder or the second state encoder.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 88.0
- Lexical Diversity: 2.80851
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13533341', '14265148', '15866237', '11730508', '13756670']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4798293242029108
- 35 USC 102 Novelty (BERT): 0.4801453444474753
- Combined Prediction Score: 0.4798609262273672
- Mean Citation Score: 205.174156
- Max Citation Score: 220.48187
- Similarity Product: 177.4728464889115

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test