PATENT CLAIM ANALYSIS

Application Number: 16006301
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "296000"]

Abstract:
Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Claim (Index 16):
A memory cell, comprising:\n an electrically conductive rail at a common plate voltage; a capacitor under the rail; the capacitor having an inner node, an outer node, and a capacitor dielectric material between the inner and outer nodes; the inner node being electrically coupled with the rail; a first transistor under the capacitor and comprising a first channel region between first and second source/drain regions; a bitline under the first transistor; the first source/drain region being electrically coupled with the bitline and the second source/drain region being electrically coupled with the outer node; a second transistor having a second transistor gate electrically coupled with the outer node; the second transistor comprising a second channel region between third and fourth source/drain regions; a third transistor under the second transistor; the third transistor comprising a third channel region between fifth and sixth source/drain regions; a semiconductor pillar extending along the second and third gates; the second and third channel regions being within semiconductor material of the semiconductor pillar; the third, fourth, fifth and sixth source/drain regions being within the semiconductor material of the semiconductor pillar; and the semiconductor pillar being against the bitline, the sixth source/drain region being electrically coupled with the bitline.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.86364
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15664183', '15664217', '15664161', '15664140', '15986628']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9289690284557376
- 35 USC 102 Novelty (BERT): 0.5426621191074854
- Combined Prediction Score: 0.8903383375209125
- Mean Citation Score: 329.175366
- Max Citation Score: 396.0863
- Similarity Product: 361.0537594576955

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test