PATENT CLAIM ANALYSIS

Application Number: 15959619
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["361", "761000"]

Abstract:
In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

Claim (Index 1):
A vertically integrated microelectronic package, comprising:\n a circuit platform having an upper surface and a lower surface opposite the upper surface thereof, the upper surface of the circuit platform having a wire bond-only surface area; a first microelectronic device coupled to the upper surface of the circuit platform; first wire bond wires coupled to and extending away from an upper surface of the first microelectronic device; second wire bond wires coupled to the upper surface of the circuit platform in the wire bond-only surface area and coupled to the upper surface of the first microelectronic device; a protective layer disposed over the circuit platform and the first microelectronic device, the protective layer having a lower surface and an upper surface opposite the lower surface thereof with the lower surface of the protective layer being in contact with the upper surface of the circuit platform, the upper surface of the protective layer having a surface mount-only area; and a second microelectronic device in a face-down orientation coupled to upper ends of the first wire bond wires in the surface mount-only area, the second microelectronic device located above and at least partially overlapping the first microelectronic device.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 91.0
- Lexical Diversity: 2.78182
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14997774', '14993586', '14880967', '15344990', '15804122']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8870611295029773
- 35 USC 102 Novelty (BERT): 0.5701249896992383
- Combined Prediction Score: 0.8553675155226035
- Mean Citation Score: 396.301942
- Max Citation Score: 470.88477
- Similarity Product: 447.856367799114

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test