PATENT CLAIM ANALYSIS

Application Number: 16038063
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "203000"]

Abstract:
Apparatuses and methods for reducing rots address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

Claim (Index 19):
The method of  claim 17 , wherein a delay between the first and second times is based on time to precharge the first and second gut nodes to the precharge voltage.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 95.0
- Lexical Diversity: 2.66667
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16017826', '16009806', '16013618', '15591015', '12399757']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8481853299846664
- 35 USC 102 Novelty (BERT): 0.5438168722464659
- Combined Prediction Score: 0.8177484842108464
- Mean Citation Score: 359.086276
- Max Citation Score: 446.5499
- Similarity Product: 289.79131711317297

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test