PATENT CLAIM ANALYSIS

Application Number: 15911922
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "369000"]

Abstract:
Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

Claim (Index 12):
The semiconductor device of  claim 1 , wherein the PMOSFET region of the first logic cell is adjacent to the PMOSFET region of the second logic cell in the first direction, and\n wherein the NMOSFET region of the third logic cell is adjacent to the NMOSFET region of the first logic cell in the first direction.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 2.78
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15496015', '14505788', '15478234', '15821116', '15409202']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9360509726357854
- 35 USC 102 Novelty (BERT): 0.5315194609683774
- Combined Prediction Score: 0.8955978214690445
- Mean Citation Score: 320.386532
- Max Citation Score: 345.9213
- Similarity Product: 260.65165303462743

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test