PATENT CLAIM ANALYSIS

Application Number: 15884192
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["711", "106000"]

Abstract:
Disclosed herein is an apparatus that includes a memory cell array including a normal memory region assigned to first value of a redundant signal and a redundancy memory region assigned to a second value of the redundant signal; a first circuit configured to receive a row address signal, produce the first value of the redundant signal if the first circuit detects that the row address signal is inconsistent to any of redundancy information, and produce the second value of the redundant signal and additional row address signal if the first circuit detects that the row address signal is consistent to any of the redundancy information; and a second circuit configured to produce further additional row address signal based on the row address signal and the first value of the redundant signal or based on the additional row address signal and the second value of the redundant signal.

Claim (Index 16):
The apparatus of  claim 15 , wherein the hit signal is a most significant bit of the first refresh address.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 3.37778
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15281818', '15876566', '15881256', '13474502', '15715846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4998016741334138
- 35 USC 102 Novelty (BERT): 0.5186252219190031
- Combined Prediction Score: 0.5016840289119728
- Mean Citation Score: 204.778094
- Max Citation Score: 218.54132
- Similarity Product: 117.13510233564855

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test