PATENT CLAIM ANALYSIS

Application Number: 16054959
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "382000"]

Abstract:
A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claim (Index 3):
The RF switch circuit of  claim 2 , further comprising a shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground, and the shunt transistor grouping comprising a second one more ACC N-MOSFETs,\n wherein:\n (a\u2032) each second ACC N-MOSFET of the one more second ACC N-MOSFETs comprises:\n (i\u2032) a second gate, a second drain, a second source and a second gate oxide layer, where the second gate oxide layer is positioned between the second gate and a second body; and \n (ii\u2032) a second accumulated charge sink (ACS) region connected to the second body; \n \n (b\u2032) in a first shunt state, the shunt transistor grouping is configured to be enabled, thereby isolating first port from the second port; \n (c\u2032) in a second shunt state, the shunt transistor grouping is configured to be disabled, thereby isolating the first port from the ground, and each second ACC N-MOSFET of the one or more ACC N-MOSFETs is configured to operate in the accumulated charge regime where a second bias voltage is applied to the second ACS region to control or to remove accumulated charge from the second body via the second ACS region; and \n (d\u2032) the second bias voltage is negative with respect to the ground, the second drain and the second source.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 96.0
- Lexical Diversity: 1.95181
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13053211', '16046974', '14845154', '15707970', '13412529']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8834945953564219
- 35 USC 102 Novelty (BERT): 0.68044900009609
- Combined Prediction Score: 0.8631900358303888
- Mean Citation Score: 667.546126
- Max Citation Score: 701.98737
- Similarity Product: 675.6046669144392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test