PATENT CLAIM ANALYSIS

Application Number: 15984739
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-02
Patent Classification: ["712", "300000"]

Abstract:
A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

Claim (Index 14):
The system of  claim 10 , wherein the plurality of indices are stored in a plurality of positions within the first GPR in an order relating to the order of the plurality of source data items stored in the source register after the sorting.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 2.25
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14757609', '13994060', '14975804', '13995457', '09850239']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5210796813330747
- 35 USC 102 Novelty (BERT): 0.5086387270925233
- Combined Prediction Score: 0.5198355859090196
- Mean Citation Score: 172.026072
- Max Citation Score: 279.68726000000004
- Similarity Product: 221.67329728121285

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test