PATENT CLAIM ANALYSIS

Application Number: 16153248
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["327", "108000"]

Abstract:
The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well.

Claim (Index 2):
The device of  claim 1  wherein:\n the buffered clock signals further comprising a third buffered clock signal and a fourth buffered clock signal; \n the DAC module further comprising a third DAC block and a fourth DAC block, the third DAC block being configured to process the third buffered clock signal and contribute to the intermediate clock signal at a third time interval at a third predetermined weight.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 1.46154
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15343608', '15464750', '14826051', '13152571', '11122518']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7163185394819188
- 35 USC 102 Novelty (BERT): 0.5477780239159993
- Combined Prediction Score: 0.6994644879253269
- Mean Citation Score: 222.04761800000003
- Max Citation Score: 393.7439
- Similarity Product: 392.2158356698394

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test