PATENT CLAIM ANALYSIS

Application Number: 15768710
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["345", "173000"]

Abstract:
The present invention is related to a gate driving circuit. The gate driving circuit may comprise at least two scan modules coupled to a same clock signal. Each of the at least two scan modules may have an input terminal, a reset terminal, and at least one stage of shift register unit. The reset terminal of at least one of the at least two scan modules is coupled to a touch control enable signal line.

Claim (Index 10):
The gate driving circuit according to  claim 9 , wherein each of the at least one stage of the shift register unit further comprises a sixth transistor T 6 , a seventh transistor T 7 , an eighth transistor T 8 , a ninth transistor T 9 , a tenth transistor T 10 , and an eleventh transistor T 11 ,\n wherein a gate of the sixth transistor T 6  is coupled to a gate of the seventh transistor T 7 , a first electrode thereof is coupled to the first electrode of the first capacitor C 1 , a second electrode thereof is coupled to the inactive level voltage line Vss; a first electrode of the seventh transistor T 7  is coupled to the output terminal of the shift register unit, and a second electrode thereof is coupled to the invalid level voltage line Vss; a gate of the eighth transistor T 8  is coupled to a second electrode of the tenth transistor T 10 , a first electrode of the eighth transistor T 8  is coupled to the second clock signal line, and a second electrode thereof is coupled to the gate of the sixth transistor T 6 ; a gate of the ninth transistor T 9  is coupled to the first electrode of the first capacitor C 1 , a first electrode is coupled to the gate of the sixth transistor T 6 , a second electrode is coupled to the invalid level voltage line Vss; a gate and a first electrode of the tenth transistor T 10  are coupled to the second clock signal line CK 2 , and a gate of the eleventh transistor T 11  is coupled to the first electrode of the first capacitor C 1 , a first electrode thereof is coupled to the gate of the eighth transistor T 8 , and a second electrode thereof is coupled to the invalid level voltage line Vss.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 1.97561
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15513154', '15133398', '15131470', '15502983', '14429026']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6980106335854255
- 35 USC 102 Novelty (BERT): 0.4968894415864008
- Combined Prediction Score: 0.6778985143855231
- Mean Citation Score: 263.147496
- Max Citation Score: 268.4536
- Similarity Product: 220.0136220824241

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test