PATENT CLAIM ANALYSIS

Application Number: 16194821
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["327", "094000"]

Abstract:
A sample hold circuit includes at least one capacitor C S  and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal V GN  of the NMOS transistor is adjusted to a voltage level V REG  lower than a power supply voltage V DD  of a chip on which the CMOS switch is integrated.

Claim (Index 14):
The semiconductor device according to  claim 12 , wherein the shield line is a multilayer wiring.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 98.0
- Lexical Diversity: 1.66038
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12630708', '12630662', '10986630', '16019150', '15293675']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8031277155271562
- 35 USC 102 Novelty (BERT): 0.5088677646873964
- Combined Prediction Score: 0.7737017204431802
- Mean Citation Score: 254.650006
- Max Citation Score: 268.15918
- Similarity Product: 167.56449954699158

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test