PATENT CLAIM ANALYSIS

Application Number: 15993714
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["257", "186000"]

Abstract:
A photodetector is provided. The photodetector is an avalanche photodiode of indium aluminum arsenide (InAlAs). An epitaxial-layers structure with n-side down is used. The strongest electric field of a multiplication layer (M-layer) is coated in inner bottom layers to avoid surface breakdown. An intrinsic layer is thickened; only one absorption layer is used; and a DBR layer is added below an n-type ohmic contact layer. A graded bandgap layer is etched to form a single mesa shape. Through the single mesa shape, all layers are far below breakdown except the M-layer has a particularly high electric field for restraining the electric field. Thus, the present invention changes holes into electrons through p-type-doping the absorption layer; because electrons run fast, carriers is made run fast; and junction capacitance is reduced with surface area increased by depletion layer thickened. Consequently, fast response speed is obtained while sensitivity is effectively improved.

Claim (Index 1):
A device of avalanche photodetector having a single mesa shape, comprising\n a p-type ohmic contact layer, wherein said p-type ohmic contact layer is a first semiconductor being p + -type doped; a semiconductor substrate; a p-type window layer, wherein said p-type window layer is a third semiconductor being p + -type doped and interposed between said p-type ohmic contact layer and said semiconductor substrate; a first graded bandgap layer, wherein said first graded bandgap layer is a fourth semiconductor being p + -type doped and interposed between said p-type window layer and said semiconductor substrate; a p-type absorption layer, wherein said p-type absorption layer is a fifth semiconductor being graded p-type doped and interposed between said first graded bandgap layer and said semiconductor substrate; a second graded bandgap layer, wherein said second graded bandgap layer is a sixth semiconductor being undoped and interposed between said p-type absorption layer and said semiconductor substrate; a field buffer layer, wherein said field buffer layer is a seventh semiconductor being undoped and interposed between said second graded bandgap layer and said semiconductor substrate; a first p-type field control layer, wherein said first p-type field control layer is an eighth semiconductor being p-type doped and interposed between said field buffer layer and said semiconductor substrate; a second p-type field control layer, wherein said second p-type field control layer is a ninth semiconductor being p-type doped and interposed between said second graded bandgap layer and said semiconductor substrate; a spacer layer, wherein said spacer layer is a tenth semiconductor being undoped and interposed between said second p-type field control layer and said semiconductor substrate; a multiplication layer (M-layer), wherein said M-layer is an eleventh semiconductor being undoped and interposed between said first p-type field control layer and said semiconductor substrate; an n-type field control layer, wherein said n-type field control layer is a twelfth semiconductor being undoped and interposed between said M-layer and said semiconductor substrate; an intrinsic layer (i-layer), wherein said i-layer is a thirteenth semiconductor being undoped and interposed between said n-type field control layer and said semiconductor substrate; and an n-type ohmic contact layer, wherein said n-type ohmic contact layer is a fourteenth semiconductor being n + -type doped and interposed between said i-layer and said semiconductor substrate; wherein, from top to bottom, the device comprises said p-type ohmic contact layer, said p-type window layer, said first graded bandgap layer, said p-type absorption layer, said second graded bandgap layer, said field buffer layer, said first p-type field control layer, said second p-type field control layer, said spacer layer, said M-layer, said n-type field control layer, said i-layer, said n-type ohmic contact layer and said semiconductor substrate; wherein an epitaxial-layers structure with n-side (said M-layer) down is obtained; wherein a mesa shape is obtained between said second p-type field control layer and said spacer layer; and wherein said mesa shape confines electric field at center of the device.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 93.0
- Lexical Diversity: 1.69
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15060787', '12187525', '13549425', '12827587', '10720117']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9159070841846148
- 35 USC 102 Novelty (BERT): 0.5676403135887016
- Combined Prediction Score: 0.8810804071250236
- Mean Citation Score: 348.683102
- Max Citation Score: 458.47128
- Similarity Product: 356.7949344281673

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test