PATENT CLAIM ANALYSIS

Application Number: 16049855
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "190000"]

Abstract:
A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.

Claim (Index 35):
An apparatus, comprising:\n first and second specialized processing blocks, wherein the first specialized processing block includes\n first, second, and third inputs that respectively receive first, second, and third signals, \n a first adder stage that computes a first sum of the second and third signals, \n first configurable interconnect circuitry that routes the second and third signals from the second and third inputs to the first adder stage, wherein the first adder stage receives the second signal via additional configurable interconnect circuitry, and \n a first multiplier stage that receives the first signal via the configurable interconnect circuitry, wherein the first configurable interconnect circuitry routes the first signal from the first input to the first multiplier stage and the first sum from the first adder stage to the first multiplier stage, and \n the second specialized processing block includes\n a second multiplier stage that computes a second product, \n a first output that outputs the third signal, and \n second configurable interconnect circuitry that routes the second product from the second multiplier stage to the first output.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 1.94444
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14919429', '13752661', '15478056', '14880633', '15988458']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4939337618606744
- 35 USC 102 Novelty (BERT): 0.5626783461393625
- Combined Prediction Score: 0.5008082202885432
- Mean Citation Score: 357.683708
- Max Citation Score: 437.87836
- Similarity Product: 378.1645995399094

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test