PATENT CLAIM ANALYSIS

Application Number: 16278718
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "072000"]

Abstract:
A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.

Claim (Index 1):
A manufacturing method of thin film transistor (TFT) substrate, which comprises:\n Step  1 : providing a base substrate, and forming a data line and a source connected to the data line on the base substrate; Step  2 : forming an active layer, the active layer being at least partially above the source; Step  3 : forming a gate insulating layer on top of the active layer, the source, the data line and the base substrate, patternizing the gate insulating layer to form a first via corresponding to the active layer; Step  4 : forming a first gate, a second gate and a drain, the first gate and the second gate being on the gate insulating layer and corresponding respectively to the both sides of the active layer, the drain being at least partially inside the first via and connected to the active layer through the first via; Step  5 : forming a passivation layer on the drain, the first gate, the second gate and the gate insulating layer, patternizing the passivation layer to form a second via corresponding to the drain; and Step  6 : forming a pixel electrode, the pixel electrode being at least partially inside the second via and connected to the drain through the second via.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.47619
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15115914', '15749101', '15736132', '15749107', '15748631']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9179192575003592
- 35 USC 102 Novelty (BERT): 0.5344005840632796
- Combined Prediction Score: 0.8795673901566511
- Mean Citation Score: 283.036354
- Max Citation Score: 347.74277
- Similarity Product: 269.8071920356536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test