PATENT CLAIM ANALYSIS

Application Number: 15752172
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["375", "297000"]

Abstract:
Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system ( 550 ) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization ( 518 ) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage “chained” feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).

Claim (Index 21):
A multi-stage chained feedback regulated voltage supply circuit for providing two or more output voltages, comprising:\n (a) a first output stage comprising stacked transistors configured to be coupled between a first voltage and a second voltage, each transistor having a corresponding control input, the first output stage configured to provide a first output voltage at a first output node; (b) at least one subsequent output stage, each subsequent output stage comprising stacked transistors configured to be coupled between (1) either the output node of a previous output stage or the first voltage and (2) the second voltage, each transistor having a corresponding control input, each subsequent output stage configured to provide a corresponding subsequent output stage output voltage at a corresponding output node; and (c) a controller, configured to be coupled to a reference voltage and coupled to the first output voltage from the first output stage, the controller outputting a first output pulse signal and a non-overlapping and complementary second output pulse signal, wherein the first output pulse signal is coupled to the control input of one of the two transistors in each output stage, and the second output pulse signal is coupled to the control input of the other of the two transistors in each output stage, wherein the controller regulates the duty cycles of the first and second output pulse signals as a function of a comparison of the reference voltage to the first output voltage.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.95946
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13742505', '14306720', '10386013', '14704122', '14064572']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4273321330549353
- 35 USC 102 Novelty (BERT): 0.4946519016077098
- Combined Prediction Score: 0.4340641099102128
- Mean Citation Score: 222.085378
- Max Citation Score: 228.62914
- Similarity Product: 173.90523792916056

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test