PATENT CLAIM ANALYSIS

Application Number: 15886645
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

Claim (Index 17):
A method of manufacturing a semiconductor device, the method comprising:\n forming an interlayer dielectric (ILD) layer over a gate structure and a source/drain (S/D) structure, the gate structure including a gate electrode layer disposed between gate sidewall spacers made of an insulating material and a cap insulating layer, the S/D structure including a S/D region and an insulating layer disposed over the S/D region; forming a contact hole by etching the ILD layer and the insulating layer; forming a source/drain (S/D) contact by filling the contact hole with a conductive material, the S/D contact being not in direct contact with the gate electrode and passing through an insulating layer formed adjacent to the gate spacer layers and contacting the S/D region; etching a part of the interlayer dielectric layer, a part of the cap insulating layer, a part of one of the gate sidewall spacers and a part of the insulating layer, thereby forming an opening in which at least a part of an upper surface of the gate electrode layer and at least a part of an upper surface and at least a part of a side surface of the S/D contact are exposed; and forming a contact layer and a first wiring layer by filling the opening with a conductive material, wherein: the contact layer is connected to the gate electrode layer and the S/D contact.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.74468
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15090202', '15649909', '15157283', '15485606', '14958769']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9160952286284773
- 35 USC 102 Novelty (BERT): 0.4831299167625232
- Combined Prediction Score: 0.8727986974418819
- Mean Citation Score: 180.450376
- Max Citation Score: 231.23462
- Similarity Product: 192.95860921926737

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test