PATENT CLAIM ANALYSIS

Application Number: 15907570
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185110"]

Abstract:
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.

Claim (Index 15):
A method of performing an erase process, the method comprising:\n applying an erase voltage pulse via a control line to multiple sub-blocks of a block of memory cells, the control line connected to the memory cells via selection gates having input signals; sensing information about erase speed for each of the multiple sub-blocks in response to the erase voltage pulse; applying one or more additional erase voltage pulses via the control line to the multiple sub-blocks; and adjusting an input signal for at least a subset of the selection gates based on the information about erase speed to cause erase speed for each of the multiple sub-blocks to converge in response to the one or more additional voltage pulses so that all of the sub-blocks will complete the erase process at a same time.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 1.51515
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15337522', '15630389', '15191150', '15151951', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.802040937604947
- 35 USC 102 Novelty (BERT): 0.4759460489502438
- Combined Prediction Score: 0.7694314487394768
- Mean Citation Score: 226.306854
- Max Citation Score: 232.60359
- Similarity Product: 189.15709294086105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test