PATENT CLAIM ANALYSIS

Application Number: 16113470
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-11
Patent Classification: ["365", "189011"]

Abstract:
According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.

Claim (Index 9):
The semiconductor memory device according to  claim 7 , wherein\n a third bit line included in the plurality of bit lines is connected to a third memory cell to be programmed to the first threshold voltage, and the control circuit applies the first voltage to the third bit line at the first time and applies the second voltage to the third bit line at a fourth time that is within the first period and after the third time.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 96.0
- Lexical Diversity: 2.52381
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15174114', '15909404', '16112378', '15410470', '15051546']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7888456191599201
- 35 USC 102 Novelty (BERT): 0.4804162127850357
- Combined Prediction Score: 0.7580026785224316
- Mean Citation Score: 222.07650400000003
- Max Citation Score: 228.69054
- Similarity Product: 193.45163123182297

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test