PATENT CLAIM ANALYSIS

Application Number: 16182924
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-06
Patent Classification: ["257", "762000"]

Abstract:
Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Claim (Index 4):
The method of  claim 3  wherein forming the containment layer includes forming the containment layer over a surface of the solder material.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 1.83099
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15853512', '15825055', '14287418', '15354447', '14853807']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9039597336861248
- 35 USC 102 Novelty (BERT): 0.5109222381811159
- Combined Prediction Score: 0.864655984135624
- Mean Citation Score: 191.043318
- Max Citation Score: 249.28822
- Similarity Product: 173.22540048178672

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test