PATENT CLAIM ANALYSIS

Application Number: 16206501
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "774000"]

Abstract:
A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

Claim (Index 12):
The method of  claim 11 , further comprising routing a global conductive element through the first dielectric layer and the second dielectric layer to electrically connect the second active circuit block to the first active circuit block and to the central processing chip.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 98.0
- Lexical Diversity: 3.175
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15291474', '14015262', '14855494', '12716902', '10233149']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9212024817104576
- 35 USC 102 Novelty (BERT): 0.523872052222083
- Combined Prediction Score: 0.8814694387616201
- Mean Citation Score: 274.04031000000003
- Max Citation Score: 346.05054
- Similarity Product: 282.45318109992746

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test