PATENT CLAIM ANALYSIS

Application Number: 16135778
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["710", "038000"]

Abstract:
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Claim (Index 17):
An electronic memory device comprising:\n a package housing providing a set of pins allowing electrical communication from circuitry within the package housing to circuitry outside of the package housing; and an integrated circuit held within the package housing and including:\n at least one random access storage element providing memory cells for storage and access of data words, the memory cells arranged in addressable logical rows and columns according to an address word; and \n a serial interface communicating with the storage element providing serial communication of memory access words including data words and address words communicated between the storage element and the circuitry outside the package housing through at least one pin, the serial interface operating to allow read and write access to the storage element according to data words and address words of the serially communicated memory access words.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14267190', '11072106', '09872478', '12910867', '14492551']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.650350972128372
- 35 USC 102 Novelty (BERT): 0.4879135817895569
- Combined Prediction Score: 0.6341072330944906
- Mean Citation Score: 166.558238
- Max Citation Score: 245.9379
- Similarity Product: 191.15307590231896

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test