PATENT CLAIM ANALYSIS

Application Number: 16031990
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "124000"]

Abstract:
A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Claim (Index 1):
A vertical thyristor memory array comprising:\n a vertical thyristor memory cell, the vertical thyristor memory cell comprising: a p+ anode; an n-base disposed below the p+ anode; a p-base disposed below the n-base; a n+ cathode disposed below the p-base; an isolation trench disposed around the vertical thyristor memory cell; an assist gate disposed in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the n-base.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 2.47222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15349978', '16007992', '15283141', '14841615', '15832636']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9153544082592536
- 35 USC 102 Novelty (BERT): 0.5239385973655463
- Combined Prediction Score: 0.876212827169883
- Mean Citation Score: 244.542602
- Max Citation Score: 351.21646
- Similarity Product: 336.63862106648327

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test