PATENT CLAIM ANALYSIS

Application Number: 16191763
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-11
Patent Classification: ["323", "315000"]

Abstract:
A bias current circuit which includes: a main unit including first PMOS and NMOS transistors constituting a first current path, and second PMOS and NMOS transistors constituting a second current path together with a first resistor; an output unit; and a supply voltage adapting unit including a third MOS transistor, a pull-up current source and a pull-down current source. The third MOS transistor is connected between a first node to which gates of the first and second PMOS transistors are connected and a second node to which drains of the second NMOS and PMOS transistors are connected. The pull-up current source is mirrored to the first PMOS transistor and configured to provide a current equal to a current provided by the pull-down current source. The bias current circuit has an operating voltage range encompassing low-voltage band such that it is operable at high and low voltages.

Claim (Index 9):
The bias current circuit of  claim 8 , wherein the current from the pull-up current source is lower than the current from the first current path.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 98.0
- Lexical Diversity: 2.31343
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15817830', '10948524', '10402472', '14840257', '11636876']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7696689393179095
- 35 USC 102 Novelty (BERT): 0.5143659133848314
- Combined Prediction Score: 0.7441386367246017
- Mean Citation Score: 261.664708
- Max Citation Score: 267.82306
- Similarity Product: 145.3276662128496

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test