PATENT CLAIM ANALYSIS

Application Number: 16003780
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["710", "313000"]

Abstract:
A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Claim (Index 1):
An integrated circuit comprising:\n (a) functional circuitry having stimulus inputs and response outputs; (b) an external bi-directional data lead; (c) an external clock lead; (d) data input and output circuitry having:\n a first lead coupled to the external bi-directional data lead; \n an internal data input lead coupled to the first lead; and \n an internal data output lead coupled to the first lead; \n (e) controller circuitry including state machine circuitry, the state machine circuitry having:\n a clock input coupled to the external clock lead; \n a data input coupled to the internal data input lead \n data control outputs; and \n instruction control outputs; \n (f) data circuitry having an input coupled to the internal data input lead, an output coupled to the internal data output lead, control inputs coupled to the data control outputs, stimulus outputs coupled with the stimulus inputs of the functional circuitry, and response inputs coupled with the response outputs of the functional circuitry; and (g) instruction circuitry having an input coupled to the internal data input lead, an output coupled to the internal data output lead, and control inputs coupled to the instruction control outputs.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 1.88889
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11258315', '15270673', '14148031', '14160163', '15591770']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.728757617887035
- 35 USC 102 Novelty (BERT): 0.5645559241924064
- Combined Prediction Score: 0.7123374485175722
- Mean Citation Score: 377.84800400000006
- Max Citation Score: 458.42596
- Similarity Product: 419.00724523117066

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test