PATENT CLAIM ANALYSIS

Application Number: 15920743
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["330", "253000"]

Abstract:
An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

Claim (Index 6):
An amplifier comprising:\n a differential input stage including a non-inverting input and an inverting input; a hysteresis stage coupled to the differential input stage; a cascode stage coupled to the hysteresis stage, wherein the hysteresis stage is configured to provide hysteresis to an output of the cascode stage; a feedback stage coupled to the output of the cascode stage and configured to provide a feedback signal to the hysteresis stage; and an output stage coupled to the output of the cascode stage, the output stage including an amplifier output, wherein the output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output; wherein the hysteresis inverter of the output stage comprises:\n a first transistor of a first conductivity type and a second transistor of a second conductivity type opposite the first conductivity type, the first transistor and the second transistor each include a control electrode connected to an input of the hysteresis inverter and a current electrode connected to an output of the hysteresis inverter; \n a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the third transistor and the fourth transistor each include a control electrode connected to the output of the hysteresis inverter and a current electrode connected to an input of the hysteresis inverter; \n wherein the third transistor is characterized as being weaker than the first transistor and the fourth transistor is characterized as being weaker than the second transistor.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 90.0
- Lexical Diversity: 3.36
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13827044', '13848403', '14937671', '13224430', '11171957']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7684410206989671
- 35 USC 102 Novelty (BERT): 0.4921146493943031
- Combined Prediction Score: 0.7408083835685008
- Mean Citation Score: 188.235288
- Max Citation Score: 207.40112
- Similarity Product: 145.34229197322844

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test