PATENT CLAIM ANALYSIS

Application Number: 15895290
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "191000"]

Abstract:
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Claim (Index 4):
The apparatus of  claim 2 , wherein each microcontroller associated with a respective tile of the plurality of tiles, wherein each microcontroller is configured to provide the respective biasing signal to the respective tile.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.70732
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15474353', '13651093', '14989678', '12385964', '15365367']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8505486108750714
- 35 USC 102 Novelty (BERT): 0.514263738428682
- Combined Prediction Score: 0.8169201236304324
- Mean Citation Score: 240.72186399999995
- Max Citation Score: 324.8509200000001
- Similarity Product: 247.5439022753192

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test