PATENT CLAIM ANALYSIS

Application Number: 15911910
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185180"]

Abstract:
Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

Claim (Index 16):
An apparatus comprising:\n a first conductive material located in a first level of the apparatus; a second conductive material located in a second level of the apparatus; a pillar including a length extending between the first and second levels and contacting the first and second conductive materials; memory cells and control lines located along the pillar and between the first and second conductive materials; a first select gate and a first select line located along the pillar between the first conductive material and the memory cells; a second select gate and a second select line located along the pillar and between the first conductive material and the first select line; a first additional conductive material located along the pillar and between the conductive material and the second select line; a second additional conductive material located along the pillar and between the first conductive material and the first additional conductive material, wherein the pillar includes a conductive portion and a dielectric portion, the conductive portion contacts the dielectric portion at a first interface, and the first interface is located at a level between levels of the first select line and the second additional conductive material. a third select gate and a third select line located along the pillar and between the memory cells and the second conductive material; a fourth select gate and a fourth select line located along the pillar and between the third line and the second conductive material; a third additional conductive material located along the pillar and between the fourth select line and the second conductive material; and a fourth additional material located along the pillar and between the third additional conductive material and the second conductive material, wherein the pillar includes and additional conductive portion and an additional dielectric portion, the additional conductive portion contacts the additional dielectric portion at a second interface, and the second interface is located at a level between levels of the third select line and the fourth additional conductive material.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 90.0
- Lexical Diversity: 3.7561
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15416870', '15205640', '15844007', '15205574', '15450638']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8116056244204717
- 35 USC 102 Novelty (BERT): 0.5215759260256456
- Combined Prediction Score: 0.7826026545809891
- Mean Citation Score: 290.712526
- Max Citation Score: 363.90256
- Similarity Product: 347.0359357944872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test