PATENT CLAIM ANALYSIS

Application Number: 16041455
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "130000"]

Abstract:
Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.

Claim (Index 1):
An electronic memory device, comprising:\n a first array of memory cells configured in a cross point architecture, the first array comprising a plurality of sections, each cell of the first array comprising a ferroelectric memory cell coupled with an access line oriented in a first direction and an access line oriented in a second direction that is orthogonal to the first direction; a second array of memory cells configured in the cross point architecture, the second array comprising a plurality of sections, wherein the first array overlies the second array, each cell of the second array comprising a ferroelectric memory cell coupled with an access line oriented in the first direction and an access line oriented in the second direction; a plurality of first plate lines oriented in the first direction and coupled with ferroelectric memory cells of a section of the first array; a plurality of second plate lines oriented in the first direction, each of the second plate lines coupled with a first plate line and to ferroelectric memory storage elements of a section of the second array; and a third plate line oriented in the first direction and spanning two or more sections of the first array or the second array, the third plate line coupled with plate lines of the first plurality.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.84706
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15469865', '15434395', '15434401', '15969302', '15690895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8062279981457822
- 35 USC 102 Novelty (BERT): 0.5317026722447117
- Combined Prediction Score: 0.7787754655556751
- Mean Citation Score: 257.87404000000004
- Max Citation Score: 379.70767
- Similarity Product: 359.22146355880136

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test