PATENT CLAIM ANALYSIS

Application Number: 15866888
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-06
Patent Classification: ["257", "335000"]

Abstract:
The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.

Claim (Index 13):
A semiconductor layout structure comprising:\n an active region surrounded by an isolation structure, the active region comprising:\n two first regions comprising a first length; \n a second region disposed between the two first regions, the second region comprising a second length less than the first length; \n a third region disposed between one of the first regions and the second region; and \n a fourth region disposed between the other of the first regions and the second region; \n at least one first gate structure disposed over the active region and the isolation structure, the first gate structure comprising a first portion and a second portion perpendicular to each other; at least one second gate structure disposed over the active region and the isolation structure, the second gate structure comprising a third portion parallel to the first portion and a fourth portion parallel to the second portion; and a plurality of source/drain regions disposed in the active region, wherein the second portion of the first gate structure overlaps the third region and a portion of the second region, and the fourth portion of the second gate structure overlaps the fourth region and a portion of the second region.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 3.45455
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15808395', '15861050', '14877247', '15656272', '15094280']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9156703410862266
- 35 USC 102 Novelty (BERT): 0.4971901442622384
- Combined Prediction Score: 0.8738223214038278
- Mean Citation Score: 219.490572
- Max Citation Score: 287.00986
- Similarity Product: 260.326480978682

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test