PATENT CLAIM ANALYSIS

Application Number: 16053429
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["375", "371000"]

Abstract:
A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Claim (Index 3):
The clock jitter measurement circuit of  claim 2 , wherein the edge detector comprises a flip-flop, and\n the flip-flop comprises:\n a clock terminal configured to receive the input signal; \n a data terminal configured to receive a logic high level; \n an output terminal configured to output the edge detection signal; and \n a reset terminal connected to the output terminal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 96.0
- Lexical Diversity: 2.42373
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15432731', '12912513', '15658272', '12509152', '13033057']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.472073378771905
- 35 USC 102 Novelty (BERT): 0.5522258211048595
- Combined Prediction Score: 0.4800886230052005
- Mean Citation Score: 267.53052599999995
- Max Citation Score: 403.72513
- Similarity Product: 304.68057702757176

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test