PATENT CLAIM ANALYSIS

Application Number: 16022357
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["327", "291000"]

Abstract:
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.

Claim (Index 3):
The IC chip of  claim 1 , wherein the scalar multiple is based on an evaluation of one of the first time duration or the second time duration.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.57627
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16019924', '14626441', '14106269', '12757597', '13945607']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7670043681090241
- 35 USC 102 Novelty (BERT): 0.4747358256825974
- Combined Prediction Score: 0.7377775138663814
- Mean Citation Score: 144.85056400000005
- Max Citation Score: 155.35028
- Similarity Product: 108.0328069563198

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test