PATENT CLAIM ANALYSIS

Application Number: 16055129
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.

Claim (Index 18):
The method of  claim 13 , wherein a gate length of the vertical transistor is based on a thickness of the gate.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 2.95652
- Patent Class: nan
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16055128', '12765483', '11344574', '11860459', '15898314']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.58528634785633
- 35 USC 102 Novelty (BERT): 0.5072771867960116
- Combined Prediction Score: 0.5774854317502982
- Mean Citation Score: 211.401268
- Max Citation Score: 299.48544
- Similarity Product: 223.5976241157532

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test