PATENT CLAIM ANALYSIS

Application Number: 16051721
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-12
Patent Classification: ["257", "316000"]

Abstract:
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

Claim (Index 17):
A method for forming an integrated circuit (IC), the method comprising:\n providing a substrate including a memory region and a logic region; forming and patterning a multilayer film to form a plurality of memory cell structures on the memory region; forming and patterning a dummy capping layer protecting the memory cell structures; forming and patterning a logic gate dielectric layer and a polysilicon layer to form a plurality of logic devices on the logic region, a logic device of the plurality of logic devices comprises a logic gate electrode and a logic gate dielectric stacked on the logic region; with the dummy capping layer covering the plurality of memory cell structures, forming a sidewall spacer along a sidewall surface of the logic gate electrode; removing the dummy capping layer from the memory region; forming source/drain regions on opposite sides of the pair of select gate electrodes within the memory region and on opposite sides of the logic gate electrode within the logic region; forming a contact etch stop layer (CESL) along an outline of the plurality of memory cell structures and the plurality of logic device; and filling a lower inter-layer dielectric layer between and over the plurality of memory cell structures.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 96.0
- Lexical Diversity: 2.07246
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16015480', '15694098', '15904836', '15651403', '15162761']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9126018609168628
- 35 USC 102 Novelty (BERT): 0.4878969181364095
- Combined Prediction Score: 0.8701313666388175
- Mean Citation Score: 194.72472
- Max Citation Score: 224.91165
- Similarity Product: 170.10220297642348

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test