PATENT CLAIM ANALYSIS

Application Number: 16104144
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["345", "173000"]

Abstract:
Provided are an array substrate and a display panel. The array substrate includes: a substrate; a plurality of scan lines formed on the substrate and extending along a first direction, a plurality of data lines formed on the substrate and extending along a second direction; a plurality of pixel units are defined by the scan lines and data lines, at least four semiconductor pressure sensing units formed on the substrate. In each of the plurality of the pixel units, a thin film transistor is provided. The substrate is further provided with a plurality of connection wires thereon, for connecting the semiconductor pressure sensing units to form at least one Wheatstone bridge structure. The plurality of connection wires includes a plurality of first direction connection wires extending along the first direction and a plurality of second direction connection wires extending along the second direction.

Claim (Index 1):
An array substrate, comprising:\n a substrate; a plurality of scan lines formed on the substrate, the plurality of scan lines extending along a first direction, a plurality of data lines formed on the substrate, the plurality of data lines extending along a second direction; and wherein a plurality of pixel units are defined by the scan lines and data lines, wherein in each of the plurality of the pixel units, a thin film transistor is provided, the thin film transistor comprising a gate electrode layer, an active layer and a source/drain electrode layer; at least four semiconductor pressure sensing units formed on the substrate, wherein the semiconductor pressure sensing units and the active layers of the thin transistors are arranged in a same plane, and the semiconductor pressure sensing units are at least partially located in a display region of the array substrate; wherein the array substrate further comprises a first metal layer arranged between the gate electrode layer and the source/drain electrode layer; the substrate is further configured with a plurality of connection wires thereon, for connecting the semiconductor pressure sensing units to form at least one Wheatstone bridge structure, the plurality of connection wires comprises a plurality of first direction connection wires extending along the first direction and a plurality of second direction connection wires extending along the second direction.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 96.0
- Lexical Diversity: 2.67241
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15194308', '15115945', '15327767', '15398717', '14768347']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6067595091650028
- 35 USC 102 Novelty (BERT): 0.5162840491037686
- Combined Prediction Score: 0.5977119631588794
- Mean Citation Score: 235.39185000000003
- Max Citation Score: 323.3659
- Similarity Product: 316.899609695524

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test