PATENT CLAIM ANALYSIS

Application Number: 15760743
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["348", "243000"]

Abstract:
A semiconductor element includes a semiconductor region ( 11 ) of a first conductivity type, a buried charge-generation region ( 16 ) of a second conductivity type, buried in an upper portion of the semiconductor region ( 11 ) to implement a photodiode (D 1 ) together with the semiconductor region ( 11 ) to generate charges, a charge-readout region ( 15 ) of the second conductivity type, provided in the semiconductor region ( 11 ) to accumulate the charges transferred from the buried charge-generation region ( 16 ), and a reset-performing region ( 12 ) of the second conductivity type, provided in the semiconductor region ( 11 ), a variable voltage is applied to the reset-performing region ( 12 ) to change the height of a potential barrier generated in the semiconductor region ( 11 ) sandwiched between the charge-readout region ( 15 ) and the reset-performing region ( 12 ) to exhaust the charges accumulated in the charge-readout region ( 15 ). The semiconductor element has a high pixel conversion gain, ultralow noise of a photon counting level and implements a solid-state imaging device.

Claim (Index 1):
A semiconductor element comprising:\n a semiconductor region of a first conductivity type; a buried charge-generation region of a second conductivity type, buried in an upper portion of the semiconductor region to implement a photodiode together with the semiconductor region for generating charges; a charge-readout functional region of the second conductivity type, disposed in another portion of the semiconductor region to be separated from the buried charge-generation region for accumulating the charges transferred from the buried charge-generation region; a charge transfer mechanism disposed on the semiconductor region between the buried charge-generation region and the charge-readout functional region, configured to control the transfer of the charges from the buried charge-generation region to the charge-readout functional region; a reset-performing region of the second conductivity type, disposed in still another portion of the semiconductor region to be separated from the charge-readout functional region; and a pinning layer of the first conductivity type having a higher impurity concentration than that of the semiconductor region, disposed in still another portion of the semiconductor region in contact with the charge-readout functional region on a side close to the buried charge-generation region, wherein the pinning layer is provided on a side closer to the charge-readout functional region than a lower side of the charge transfer mechanism, and a variable voltage is applied to the reset-performing region so as to change a height of a potential barrier generated in the semiconductor region sandwiched between the charge-readout functional region and the reset-performing region, for exhausting the charges accumulated in the charge-readout functional region.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.81429
- Patent Class: 348.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12295443', '12516635', '13142141', '12065158', '13056816']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6655114855410103
- 35 USC 102 Novelty (BERT): 0.5031968184669493
- Combined Prediction Score: 0.6492800188336041
- Mean Citation Score: 295.80387
- Max Citation Score: 302.21594
- Similarity Product: 262.70594324448825

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test