PATENT CLAIM ANALYSIS

Application Number: 15880512
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "392000"]

Abstract:
A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Claim (Index 1):
An apparatus having multiple n-channel metal-oxide-semiconductor (NMOS) fin-shaped field effect transistors (FinFETs) with different threshold voltages comprising:\n a first NMOS FinFET comprising:\n a first fin; and \n a first gate stack formed over a gate surface of the first fin, wherein the first gate stack comprises a first portion of a high-K dielectric layer that is formed directly on the gate surface of the first fin, a first portion of a capping layer, a first portion of a work-function metal layer formed from a work-function metal, a first barrier layer formed from a barrier layer material, and a first gate electrode metal, and wherein the first portion of the work-function metal layer is formed directly on the first portion of the capping layer; and \n a second NMOS FinFET comprising:\n second fin; and \n a second gate stack formed over a gate surface of the second fin, wherein the second gate stack comprises a second portion of the high-K dielectric layer that is formed directly on the gate surface of the second fin, a second portion of the capping layer, a second portion of the work-function metal layer formed from the work-function metal, a second barrier layer formed from an oxide of the work-function metal, and a second gate electrode metal, and wherein the first portion of the capping layer and the second portion of the capping layer have a substantially identical thickness, and wherein the second portion of the work-function metal layer is formed directly on the second portion of the capping layer, \n wherein the first NMOS FinFET has a first threshold voltage, and wherein the second NMOS FinFET has a second threshold voltage that differs from the first threshold voltage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.675
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14815626', '15830412', '14975917', '13451183', '14221108']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9225004032638028
- 35 USC 102 Novelty (BERT): 0.5031464329720912
- Combined Prediction Score: 0.8805650062346316
- Mean Citation Score: 260.66851
- Max Citation Score: 265.94153
- Similarity Product: 189.5762068466097

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test