PATENT CLAIM ANALYSIS

Application Number: 15871643
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["327", "109000"]

Abstract:
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Claim (Index 2):
An integrated circuit block comprising:\n a first node; a second node; a resistive network; a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node; and supply rails providing a first supply voltage and a second supply voltage; wherein: a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node; the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node; each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage; the resistive network comprises a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches; the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable or disable the FET switches and thereby adjusting a capacitance between the first node and the second node; and the first supply voltage and the second supply voltage are independent of a number of FET switches of the plurality of FET switches.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 1.35211
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15256453', '15279302', '12735954', '15376471', '14638917']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.701519834670333
- 35 USC 102 Novelty (BERT): 0.5320792425009317
- Combined Prediction Score: 0.6845757754533928
- Mean Citation Score: 253.206168
- Max Citation Score: 376.70914
- Similarity Product: 351.7668791665042

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test