PATENT CLAIM ANALYSIS

Application Number: 15865892
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "185170"]

Abstract:
A method of operating a three-dimensional memory device includes applying a target string bias voltage to a selected drain select gate electrode which partially surrounds a row of memory stack structures that directly contact a drain select isolation structure, and applying a neighboring string bias voltage that has a greater magnitude than the target string bias voltage to an unselected drain select gate electrode that contacts the drain select level isolation structure.

Claim (Index 16):
The method of  claim 1 , wherein:\n the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; the substrate comprises a silicon substrate; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; the word line electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and the array of monolithic three-dimensional NAND strings comprises: a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 86.0
- Lexical Diversity: 1.68182
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15850073', '15818146', '15818061', '15628495', '15704286']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7946609666095784
- 35 USC 102 Novelty (BERT): 0.5212817888710644
- Combined Prediction Score: 0.767323048835727
- Mean Citation Score: 322.257094
- Max Citation Score: 343.7213700000001
- Similarity Product: 285.34165029231553

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test