PATENT CLAIM ANALYSIS

Application Number: 15954213
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["257", "531000"]

Abstract:
A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

Claim (Index 1):
A semiconductor device comprising:\n a first semiconductor chip; a second semiconductor chip located opposite to the first semiconductor chip; a first insulating film interposed between the first semiconductor chip and the second semiconductor chip facing each other; and a sealing body sealing the first semiconductor chip, the second semiconductor chip, and the first insulating film, the first semiconductor chip comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a first multilayer wiring layer provided between the first surface of the first semiconductor substrate and the first insulating film; and a first coil provided in the first multilayer wiring layer, the second semiconductor chip comprising: a second semiconductor substrate having a third surface facing the first surface of the first semiconductor chip and a fourth surface opposite to the third surface; a second multilayer wiring layer provided between the third surface of the second semiconductor substrate and the first insulating film; and a second coil provided in the second multilayer wiring layer, facing the first coil through the first insulating film, and magnetically coupled to the first coil, wherein the first coil is located in a manner to overlap part of a first circuit region located in the first surface of the first semiconductor substrate in plan view, and wherein the second coil is located in a manner to overlap part of a second circuit region located in the third surface of the second semiconductor substrate in plan view.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 2.51786
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15424059', '14863264', '14651643', '14594063', '15817267']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8984729543543809
- 35 USC 102 Novelty (BERT): 0.4781013104343908
- Combined Prediction Score: 0.8564357899623819
- Mean Citation Score: 196.644444
- Max Citation Score: 208.4238
- Similarity Product: 176.6506672657013

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test