PATENT CLAIM ANALYSIS

Application Number: 15890127
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["341", "155000"]

Abstract:
The present disclosure provides a simplified, multiple-gain, front-end circuit for analog-to-digital converter systems. In an example, a front-end circuit for an analog-to-digital converter (ADC) can include first and second input amplifiers configured to receive an input signal, and a gain selection circuit coupled to the first input amplifier and the second input amplifier; the gain selection circuit comprising a plurality resistor strings, each resistor string including a plurality of resistors coupled in series, and wherein each string includes a first end node coupled to an output of the first input amplifier and a second end node coupled to an output of the second input amplifier.

Claim (Index 15):
A method for providing a scaled representation of an input signal to an analog-to-digital converter, the method comprising:\n receiving an input signal at a first JFET input amplifier and at a second JFET input amplifier; and selecting a gain of each of the first and second JFET input amplifiers, wherein selecting the gain of each of the first and second JFET input amplifiers includes, in a first selection state, selectively coupling a first intermediate node of a resistor string of a plurality of resistor strings with a first input of the first JFET input amplifier, and selectively coupling a second intermediate node of the resistor string of the plurality of resistor strings with a first input of the second JFET input amplifier; receiving an output of the first JFET input amplifier at a first differential input of a differential amplifier; receiving an output of the second JFET input amplifier at a second differential input of the differential amplifier; and providing a differential output signal to the analog-to-digital converter, wherein a matched set of resistors determine a gain of the differential amplifier, wherein a first end node of the resistor string is coupled to an output of the first JFET input amplifier, and a second end node of the resistor string is coupled to an output of the second JFET input amplifier; wherein each resistor string of the plurality of resistor strings includes a plurality of resistors coupled in series, and wherein each resistor string of the plurality of resistor strings includes a first end node coupled to an output of the first JFET input amplifier and a second end node coupled to an output of the second JFET input amplifier; providing an output signal representative of the input signal scaled by the gain; and wherein the plurality of resistor strings includes a plurality of individual integrated circuits, each individual integrated circuit of the plurality of individual integrated circuits including one resistor string of the plurality of resistor strings.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.14815
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14622750', '13719091', '14694428', '12196313', '15877098']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5528624720078089
- 35 USC 102 Novelty (BERT): 0.463408390100352
- Combined Prediction Score: 0.5439170638170632
- Mean Citation Score: 137.64908799999998
- Max Citation Score: 139.32381999999998
- Similarity Product: 108.56518380109785

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test