PATENT CLAIM ANALYSIS

Application Number: 16227383
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["712", "208000"]

Abstract:
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can receive, from a software application, a request to perform an operation on a first set of variables that includes a first input value and a register value and perform the operation on a second set of variables that includes a second input value and the first register value. The processor core can vectorize the operation on the first set of variables and the second set of variables. The processor core can perform the operation on the first set of variables and the second set of variables in parallel to obtain a first operation value and a second operation value. The processor core can perform a horizontal add operation on the first operation value and the second operation value and write the result to memory.

Claim (Index 3):
The system of  claim 2 , wherein the register array comprises a third cell that stores a third register value that identifies a third memory location and a fourth cell that stores a fourth register value that identifies a fourth memory location, wherein the array of input values further comprises a third input value and a fourth input value, wherein the execution unit is further to:\n perform the operation on the third input value and the third register value to obtain a third operation value; perform the operation on the fourth input value and the fourth register value to obtain a fourth operation value, wherein the operation on the first input value, the second input value, the third input value, and the fourth input value are performed in parallel; determine that the operation on the third input value and the operation on the fourth input value are in conflict when the third register value and the fourth register value are the same; perform the horizontal add operation on the third operation value and the fourth operation value to obtain a second result value when the third register value and the fourth register value are the same; and write the second result value to the fourth memory location, wherein the fourth memory location and the third memory location are the same when the third register value and the fourth register value are the same.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 3.03846
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15301206', '15301224', '13795234', '15396568', '13487184']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5299963642777636
- 35 USC 102 Novelty (BERT): 0.4799312942375061
- Combined Prediction Score: 0.5249898572737379
- Mean Citation Score: 162.34383200000005
- Max Citation Score: 243.65208
- Similarity Product: 233.3273017324448

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test