PATENT CLAIM ANALYSIS

Application Number: 15979194
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["716", "108000"]

Abstract:
A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.

Claim (Index 12):
The method of  claim 9 , wherein the control signal comprises a single bit.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 93.0
- Lexical Diversity: 2.7551
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14679954', '11561833', '11001617', '14300165', '14975572']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3515861575932669
- 35 USC 102 Novelty (BERT): 0.5361513657744424
- Combined Prediction Score: 0.3700426784113845
- Mean Citation Score: 224.11406
- Max Citation Score: 407.5838
- Similarity Product: 404.4148081239225

Labels:
- Claim Label 101: 0
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test