PATENT CLAIM ANALYSIS

Application Number: 15742517
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["257", "040000"]

Abstract:
A method of manufacturing an OLED panel and an OLED panel are provided. The method includes forming an anode connected to a source of a TFT, and a strap electrode connected to an auxiliary electrode on a TFT substrate. A sharp shaped corner is formed on the strap electrode, therefore an area of the electron transport layer and the electron injection layer corresponding to the sharp shaped corner have a thinner thickness. By applying a voltage between the auxiliary electrode and the cathode, the electron transport layer and the electron injection layer corresponding to the sharp shaped corner are punctured, the cathode is directly connected to the strap electrode and further conducted to the auxiliary electrode, resulting in a signal is inputted to the cathode through the auxiliary electrode during display. The problem of uneven display of the OLED panel due to the IR drop of the cathode is improved.

Claim (Index 3):
The method of manufacturing an OLED panel according to  claim 1 , wherein the TFT comprises: an active layer disposed above a base substrate, a gate insulating layer and a gate electrode sequentially disposed on the active layer, an interlayer insulating layer covering the active layer and the gate electrode, and a source electrode and a drain electrode formed on the interlayer insulating layer at intervals;\n the auxiliary electrode comprises a first sub-auxiliary electrode disposed on the interlayer insulating layer spacing apart from the source electrode and the drain electrode, the second via hole exposes the first sub-auxiliary electrode; the interlayer insulating layer is provided with a fourth via hole and a fifth via hole located above both sides of the active layer, the source electrode and the drain electrode are connected to the both sides of the active layer through the fourth via hole and the fifth via hole; the TFT substrate further comprises a passivation layer covering the interlayer insulating layer, the source electrode, the drain electrode and the first sub-auxiliary electrode, the passivation layer is provided with a seventh via hole and an eighth via hole respectively exposing the source electrode and the first sub-auxiliary electrode; in the step S 2 , the planarization layer is disposed on the passivation layer, the first via hole and the second via hole are respectively located above the seventh via hole and the eighth via hole.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 86.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14892883', '15579530', '14806415', '15569776', '11131963']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9296153343183076
- 35 USC 102 Novelty (BERT): 0.4885317602057126
- Combined Prediction Score: 0.885506976907048
- Mean Citation Score: 243.50892800000003
- Max Citation Score: 246.80093
- Similarity Product: 206.12409424853803

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test