PATENT CLAIM ANALYSIS

Application Number: 16174088
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-06
Patent Classification: ["341", "143000"]

Abstract:
Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Claim (Index 5):
The analog-to-digital modulator of  claim 4  further comprising a passive summer including a first set of capacitors associated with the first set of integrators and a second set of capacitors associated with the second set of integrators.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 1.34783
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15490759', '15007054', '13205512', '12827522', '12119658']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5321343966909028
- 35 USC 102 Novelty (BERT): 0.5405809877396092
- Combined Prediction Score: 0.5329790557957734
- Mean Citation Score: 230.289388
- Max Citation Score: 341.95117
- Similarity Product: 210.47224044411183

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test