PATENT CLAIM ANALYSIS

Application Number: 15884615
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["257", "295000"]

Abstract:
The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. The ferroelectric memory device also includes a conductive well region, doped with a dopant of the second conductivity type. The conductive well region is disposed in the base doped region and spaced apart from the ferroelectric gate insulation layer.

Claim (Index 16):
The method of  claim 15 , further comprising:\n forming an interfacial insulation layer on the inner wall of the trench before forming the ferroelectric gate insulation layer on the interfacial insulation layer.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 86.0
- Lexical Diversity: 2.98
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15858056', '15860851', '14998227', '11393142', '14852521']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9216042758467629
- 35 USC 102 Novelty (BERT): 0.5100302172546485
- Combined Prediction Score: 0.8804468699875514
- Mean Citation Score: 247.196662
- Max Citation Score: 296.23465
- Similarity Product: 220.1925457475781

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test