PATENT CLAIM ANALYSIS

Application Number: 16016347
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["716", "102000"]

Abstract:
An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.

Claim (Index 2):
The integrated circuit of  claim 1  wherein the plurality of blocks spans more than one process design kit.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 1.44231
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15691969', '13210179', '12471968', '14681028', '12605209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3410540770533884
- 35 USC 102 Novelty (BERT): 0.4613735355410012
- Combined Prediction Score: 0.3530860229021497
- Mean Citation Score: 140.495154
- Max Citation Score: 142.33217
- Similarity Product: 95.93650121938944

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test