PATENT CLAIM ANALYSIS

Application Number: 16116807
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["327", "109000"]

Abstract:
A gate driver integrated circuit drives an output signal onto its output terminal and onto the gate of a power transistor. In a turn-on episode, a digital input signal transitions to a digital logic high level. In response, the gate driver integrated circuit couples the output terminal to a positive supply voltage terminal, thereby driving a positive voltage onto the gate of the power transistor. In response to a high-to-low transition of the digital input signal, the driver drives a negative voltage onto the output terminal and power transistor gate for a short self-timed period of time, and then couples the output terminal to a ground terminal, thereby driving the output terminal and power transistor gate up to ground potential. The output terminal and power transistor gate are then held at ground potential in anticipation of the next turn-on episode of the power transistor.

Claim (Index 21):
A method comprising:\n receiving a digital input signal onto an input terminal of a gate driver integrated circuit having a delay circuit, wherein the digital input signal has a digital logic high level during a first period of time and transitions to a digital logic low level so that the digital input signal has a digital logic low level during a second period of time, and wherein the digital input signal does not transition digital logic levels between the second period of time and a third period of time such that the digital input signal maintains the digital logic low level into and throughout the third period of time; in response to the digital logic high level of the digital input signal during the first period of time coupling an output terminal of the gate driver integrated circuit to a positive supply voltage terminal of the gate driver integrated circuit; in response to the digital logic low level of the digital input signal during the second period of time driving the output terminal to a negative voltage; and at the beginning of the third period of time coupling the output terminal of the gate driver integrated circuit to a ground terminal of the gate driver integrated circuit using the delay circuit.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 96.0
- Lexical Diversity: 2.76786
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15423421', '15901829', '13453649', '12214478', '15088124']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7746987067230127
- 35 USC 102 Novelty (BERT): 0.5310089764034494
- Combined Prediction Score: 0.7503297336910564
- Mean Citation Score: 264.827718
- Max Citation Score: 376.53314
- Similarity Product: 341.3666722700084

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test