PATENT CLAIM ANALYSIS

Application Number: 16029603
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Claim (Index 3):
The method according to  claim 1 , further comprising:\n precharging the interconnecting node of the output transistor to the high state, by a third precharge circuit comprising a third precharge transistor, based on being in a precharge phase of the evaluation clock.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 95.0
- Lexical Diversity: 1.79592
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16029604', '16029577', '15796819', '16029607', '15613185']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7678947434968937
- 35 USC 102 Novelty (BERT): 0.5566589330367923
- Combined Prediction Score: 0.7467711624508836
- Mean Citation Score: 465.365266
- Max Citation Score: 497.16586
- Similarity Product: 357.9674048071444

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test