PATENT CLAIM ANALYSIS

Application Number: 15884654
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["365", "185200"]

Abstract:
Disclosed are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells which are programmed to a plurality of program states, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to control the peripheral circuit to divide the plurality of program states into two or more program groups and sequentially program the two or more program groups during the program operation, wherein the control logic controls the peripheral circuit to simultaneously program the memory cells which are to be programmed to program states included in the same program group among the plurality of memory cells.

Claim (Index 10):
The semiconductor memory device of  claim 9 , wherein the peripheral circuit includes a read and write circuit connected with bit lines of the memory cell array, and\n the read and write circuit applies a plurality of program allowable voltages to first bit lines corresponding to a selected program group between the first program group and the second program group.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.52
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15873069', '15290625', '15658516', '15798525', '15606674']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8306429169902113
- 35 USC 102 Novelty (BERT): 0.505103679785247
- Combined Prediction Score: 0.7980889932697149
- Mean Citation Score: 278.52767
- Max Citation Score: 298.88422
- Similarity Product: 223.7716472116529

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test