PATENT CLAIM ANALYSIS

Application Number: 15893982
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["711", "154000"]

Abstract:
A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Claim (Index 9):
A method comprising:\n detecting multiple page faults; providing aggregated page fault information for the multiple page faults to a page fault communication interface; and signaling a single multi-page page fault for the multiple page faults.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 88.0
- Lexical Diversity: 2.125
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13977106', '14214910', '15163372', '12268881', '15290696']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4995738883026434
- 35 USC 102 Novelty (BERT): 0.5525217753295291
- Combined Prediction Score: 0.5048686770053319
- Mean Citation Score: 246.939908
- Max Citation Score: 436.0692
- Similarity Product: 335.2574434168339

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test