PATENT CLAIM ANALYSIS

Application Number: 15914168
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["257", "298000"]

Abstract:
A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Claim (Index 23):
The method of  claim 21 , wherein the forming of the memory cell region includes forming a plurality of gate conductive layers on the second upper substrate and a plurality of channel layers penetrating the plurality of gate conductive layers, the plurality of channel layers extending in a direction perpendicular to a top surface of the second upper substrate.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 90.0
- Lexical Diversity: 3.32258
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14574079', '15608076', '15426081', '15388369', '15385152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9245233419101696
- 35 USC 102 Novelty (BERT): 0.5023690071505127
- Combined Prediction Score: 0.8823079084342039
- Mean Citation Score: 217.691482
- Max Citation Score: 231.87033
- Similarity Product: 153.25488927316368

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test