PATENT CLAIM ANALYSIS

Application Number: 15948563
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

Claim (Index 20):
The vertical transport field effect transistor of  claim 19 , further comprising a work function layer on the gate dielectric layer and a gate fill layer on the work function layer.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 91.0
- Lexical Diversity: 2.57447
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15948554', '15498112', '15492745', '15586830', '15873279']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.94106528995745
- 35 USC 102 Novelty (BERT): 0.5488778682438594
- Combined Prediction Score: 0.9018465477860907
- Mean Citation Score: 421.02074000000016
- Max Citation Score: 469.60037
- Similarity Product: 276.65876557270525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test