PATENT CLAIM ANALYSIS

Application Number: 15967812
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["708", "552000"]

Abstract:
A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Claim (Index 13):
The method of  claim 12 , wherein the operands comprise two operands, and the overflow detector checks the carry-out of a 3-way add or subtract of the two operands and the padding vector P.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 93.0
- Lexical Diversity: 1.86
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15372867', '14873469', '14749002', '15840033', '10892686']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.479988166601965
- 35 USC 102 Novelty (BERT): 0.6047667322938137
- Combined Prediction Score: 0.4924660231711499
- Mean Citation Score: 285.525284
- Max Citation Score: 517.5333
- Similarity Product: 475.17653491078016

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test