PATENT CLAIM ANALYSIS

Application Number: 16004404
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "497000"]

Abstract:
A  3 D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Claim (Index 1):
A 3D semiconductor device, the device comprising:\n a first level comprising a plurality of first single crystal transistors, contacts, and a first metal layer,\n wherein a portion of said first single crystal transistors are interconnected, \n wherein said interconnected comprises said first metal layer and said contacts, and \n wherein said portion of said first single crystal transistors are interconnected forms memory control circuits; \n a second level overlaying said first level, said second level comprising a plurality of second transistors; a third level overlaying said second level, said third level comprising a plurality of third transistors; a fourth level overlaying said third level, said fourth level comprising a plurality of fourth transistors; a second metal layer overlaying said fourth level; and a memory cell,\n wherein said plurality of second transistors are aligned to said plurality of first transistors with a less than 40 nm alignment error, \n wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain, \n wherein said source, said channel, and said drain have the same dopant type, \n wherein said second metal comprises bit lines, \n wherein said plurality of second transistors each comprise a region of high quality oxide isolation, \n wherein said high quality oxide isolation has a leakage of less than one picoamp per micron at device power supply and 25\u00b0 C., \n wherein at least one of said plurality of third transistors comprise polysilicon, \n wherein one of said plurality of second transistors is self-aligned to at least one of said third transistors, \n wherein said memory cell comprises at least one of said plurality of third transistors, \n wherein at least one of said plurality of second transistors at least partially overlays at least a portion of said memory control circuits, and \n wherein at least one of said memory control circuits is designed to control said memory cell.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 94.0
- Lexical Diversity: 3.51111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15917629', '15913917', '15904377', '13251269', '13869963']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9187150500015454
- 35 USC 102 Novelty (BERT): 0.498388388942688
- Combined Prediction Score: 0.8766823838956597
- Mean Citation Score: 268.31646
- Max Citation Score: 290.28104
- Similarity Product: 259.8377558571148

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test