PATENT CLAIM ANALYSIS

Application Number: 16205474
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["365", "072000"]

Abstract:
A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.

Claim (Index 2):
The memory macro of  claim 1 , wherein the logic circuit comprises:\n a first NAND gate having a first terminal, a second terminal and a third terminal, the first terminal of the first NAND gate being configured to receive the first signal, the second terminal of the first NAND gate being configured to receive a first memory signal, and the third terminal of the first NAND gate being configured to output an inverted second signal; a second NAND gate having a first terminal, a second terminal and a third terminal, the first terminal of the second NAND gate being configured to receive the first signal, the second terminal of the second NAND gate being configured to receive a second memory signal, and the third terminal of the second NAND gate being configured to output an inverted fourth signal; a first inverter having a first terminal and a second terminal, the first terminal of the first inverter being coupled to the third terminal of the first NAND gate, and being configured to output the third signal; and a second inverter having a first terminal and a second terminal, the first terminal of the second inverter being coupled to the third terminal of the second NAND gate, and being configured to output the fourth signal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 4.05
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15140726', '13551387', '15798710', '16005121', '14805611']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7925115555959008
- 35 USC 102 Novelty (BERT): 0.4869785356116499
- Combined Prediction Score: 0.7619582535974757
- Mean Citation Score: 172.09567199999995
- Max Citation Score: 237.38506
- Similarity Product: 190.1188180902684

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test