PATENT CLAIM ANALYSIS

Application Number: 15918309
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["361", "056000"]

Abstract:
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.

Claim (Index 5):
The semiconductor device according to  claim 4 , wherein the protection circuit further comprises a fourth transistor which is coupled between the power wire and the ground wire in series with the first resistive element.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 90.0
- Lexical Diversity: 2.0
- Patent Class: 361.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14865418', '14243523', '15480000', '13480956', '11253635']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8464169273053679
- 35 USC 102 Novelty (BERT): 0.5177479886254667
- Combined Prediction Score: 0.8135500334373778
- Mean Citation Score: 218.766566
- Max Citation Score: 330.5323
- Similarity Product: 261.89060695616604

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test