PATENT CLAIM ANALYSIS

Application Number: 16023740
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["361", "774000"]

Abstract:
A printed circuit board (PCB) includes a plurality of layers and electronic components connected to its top surface. The PCB also includes a plurality of trace layers, each located at a respective depth within the layers of the PCB. A plurality of vias provide signal pathways for the trace layer. Upon their manufacture, the vias include a stub portion not necessary for the signal pathways and causing degradation of the integrity of these signal pathways. Embodiments mill the bottom of the PCB to form a variable-depth cavity. The different milling depths of the variable-depth cavity are selected to remove the stub portions of the plurality of vias and the dielectric material between the stubs. By configuring the PCB power planes as the topmost trace layers, decoupling capacitors may be located at the greatest depth of the variable-depth cavity, thus reducing the loop inductance in the power circuit of the PCB.

Claim (Index 5):
The PCB of  claim 1 , wherein a trace layer designated as a power plane is the closest of the plurality of trace layers to the top surface of the PCB.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 1.96386
- Patent Class: 361.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15019369', '13070858', '15861877', '15928042', '15903327']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8475936419640454
- 35 USC 102 Novelty (BERT): 0.4909504502922491
- Combined Prediction Score: 0.8119293227968658
- Mean Citation Score: 196.600368
- Max Citation Score: 224.51175
- Similarity Product: 159.0246420745254

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test