PATENT CLAIM ANALYSIS

Application Number: 15966032
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["438", "637000"]

Abstract:
Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

Claim (Index 10):
A method of forming an interconnect of an integrated circuit (IC), the method comprising:\n forming a first interlayer dielectric (ILD) layer over an interconnect layer, the interconnect layer including a conductive structure therein under an interconnect layer etch stop layer (ESL); forming an aluminum oxynitride (AlON) etch stop layer (ESL) over the first ILD layer, the AlON ESL having a thickness of less than 5 nanometers; forming a second interlayer dielectric (ILD) layer over the AlON ESL; forming a dual damascene (DD) hard mask over the second ILD layer, the DD hard mask including: a patterned wire trench hard mask layer over the second ILD layer, a mask barrier layer over the patterned wire trench hard mask layer, and a patterned via opening hard mask layer over the mask barrier layer; etching a preliminary via opening through the mask barrier layer, the patterned hard mask layer and the second ILD layer to the AlON ESL; removing the AlON ESL at a bottom of the preliminary via opening, creating a via ESL opening in the AlON ESL; removing the mask barrier layer, exposing the patterned wire trench hard mask layer; etching to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, wherein the via ESL opening in the AlON ESL defines the via opening in the first ILD layer as a chamferless via opening; removing any remaining interconnect layer ESL in the via opening to expose an upper surface of the conductive structure in the interconnect layer; and forming a unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.10959
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15912975', '10379757', '10963268', '14540367', '10246061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8710345480710345
- 35 USC 102 Novelty (BERT): 0.528402668080061
- Combined Prediction Score: 0.8367713600719372
- Mean Citation Score: 286.899104
- Max Citation Score: 356.33475
- Similarity Product: 269.39847368153926

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test