PATENT CLAIM ANALYSIS

Application Number: 15910117
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["345", "055000"]

Abstract:
The present disclosure provides a gate driving circuit and a display apparatus. The gate driving circuit comprises a plurality of cascaded shift registers, wherein the shift registers each comprise an input sub-circuit, an output sub-circuit, an output de-noising sub-circuit, a capacitor sub-circuit and a reset sub-circuit, wherein the output de-noising sub-circuit is electrically connected to a first reference voltage signal terminal, a second reference voltage signal terminal and an output signal terminal, and for each stage of shift register except for a first stage of shift register, the second reference voltage signal terminal is electrically connected to an input signal terminal of a stage of shift register immediately prior to the current stage of shift register.

Claim (Index 2):
The gate driving circuit according to  claim 1 , wherein\n the input sub-circuit is electrically connected to the input signal terminal and a first node and is configured to provide an input signal from the input signal terminal to the first node; the output sub-circuit is electrically connected to the first node, a clock signal terminal and the output signal terminal and is configured to provide a clock signal from the clock signal terminal to the output signal terminal under the control of a potential at the first node; the capacitor sub-circuit is electrically connected to the first node and the output signal terminal; the reset sub-circuit is electrically connected to a reset signal terminal, the first node and the first reference voltage signal terminal and is configured to provide a first reference voltage signal from the first reference voltage signal terminal to the first node under the control of a reset signal from the reset signal terminal; the output de-noising sub-circuit is configured to provide the first reference voltage signal from the first reference voltage signal terminal to the output signal terminal under the control of a second reference voltage signal from the second reference voltage signal terminal.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 2.68085
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15743617', '15508921', '15827553', '15761749', '15652474']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6956625547442694
- 35 USC 102 Novelty (BERT): 0.4995869903210762
- Combined Prediction Score: 0.67605499830195
- Mean Citation Score: 259.89851200000004
- Max Citation Score: 272.6986
- Similarity Product: 219.69832561745645

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test