PATENT CLAIM ANALYSIS

Application Number: 16047883
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-08
Patent Classification: ["326", "003000"]

Abstract:
A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

Claim (Index 17):
The method of  claim 16 , further comprising:\n providing a second negative SFQ pulse to the input end of the JTL to reset the input-side Josephson junction to a 0 superconducting phase, such that the second negative SFQ pulse propagates to the output end of the JTL to set to 2\u03c0 the superconducting phase of the output-side Josephson junction.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 95.0
- Lexical Diversity: 1.48529
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15887524', '15810954', '15886626', '15937418', '15810907']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7311554073782677
- 35 USC 102 Novelty (BERT): 0.6127347755715474
- Combined Prediction Score: 0.7193133441975956
- Mean Citation Score: 446.457114
- Max Citation Score: 667.6732
- Similarity Product: 494.1503650804042

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test