PATENT CLAIM ANALYSIS

Application Number: 16046453
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-06
Patent Classification: ["365", "201000"]

Abstract:
A memory device and a method are provided. The memory device includes a memory cell array; a peripheral circuit configured to store data in the memory cell array or to read data from the memory cell array; a test mode register set (TMRS) that stores a delay value; and a test circuit. In response to detecting a clock select signal received from outside the memory device, the test circuit generates an asynchronous signal from a clock received from the outside based on the delay value, and controls the peripheral circuit based on the asynchronous signal.

Claim (Index 21):
A memory device comprising:\n a memory cell array; and a test circuit comprising a test mode register that stores information for generating an asynchronous signal for controlling testing of the memory cell array, wherein the test circuit is configured to receive a clock and a clock select signal from outside the memory device, and in response to the clock select signal, generate, internally within the memory device, the asynchronous signal based on the clock and the information stored in the test mode register.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.05882
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11195897', '13071287', '10357862', '11845191', '11129150']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7938468278610354
- 35 USC 102 Novelty (BERT): 0.465101207063318
- Combined Prediction Score: 0.7609722657812636
- Mean Citation Score: 191.313342
- Max Citation Score: 195.52943
- Similarity Product: 156.0905433819294

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test