PATENT CLAIM ANALYSIS

Application Number: 15917124
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["370", "421000"]

Abstract:
A bus control device ( 401 a ) includes a storage ( 408 ) that stores a transmission order of data pieces transmitted from a first node ( 402 ) to each second node ( 403 ); a sorter ( 413 ) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer ( 409 ) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller ( 410 ) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

Claim (Index 9):
The bus control device according to  claim 1 , wherein each of the first node and the second nodes is either one of a bus master, a memory and an input/output device.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 2.34247
- Patent Class: 370.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14641197', '14641223', '14221619', '14246468', '14492181']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5703534631258586
- 35 USC 102 Novelty (BERT): 0.5570609477277263
- Combined Prediction Score: 0.5690242115860453
- Mean Citation Score: 259.13223600000003
- Max Citation Score: 457.43646
- Similarity Product: 321.8580959306073

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test