PATENT CLAIM ANALYSIS

Application Number: 15978497
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "782000"]

Abstract:
A semiconductor device ( 100 ) comprising a leadframe ( 120 ) having an assembly pad ( 121 ) in a first horizontal plane ( 180 ), the pad's first surface ( 121 a ) with a semiconductor chip ( 110 ) attached; further a plurality of leads ( 122 ) in a parallel second horizontal plane ( 190 ) offset from the first plane in the direction of the attached chip, the leads having a third surface ( 122 a ) with bonding wires, and an opposite fourth surface ( 122 b ); a package ( 140 ) encapsulating leadframe, chip, and wires, the package having a fifth surface ( 140 a ) parallel to the first and second planes; a plurality of recess holes ( 150 ) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder ( 160 ) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Claim (Index 10):
The device of  claim 1 , wherein the third lead surface includes the plane parallel to and below the plane along the first lead surface, and the fourth lead surface includes the plane parallel to and below the plane along the fourth lead surface.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.78788
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14453650', '14215896', '14683277', '13542827', '11051061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91251519290581
- 35 USC 102 Novelty (BERT): 0.5434943512665181
- Combined Prediction Score: 0.8756131087418808
- Mean Citation Score: 250.4113
- Max Citation Score: 375.82388
- Similarity Product: 214.5534039608431

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test