PATENT CLAIM ANALYSIS

Application Number: 15871381
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "096000"]

Abstract:
A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Claim (Index 13):
The method of  claim 9 , wherein the data latch is operated in the set state in response to the sensed output signal indicating the logic state of the data stored in the memory element corresponds to a programmed state.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 86.0
- Lexical Diversity: 2.19403
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15247352', '14192038', '14630766', '15450503', '15408942']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8324337463737951
- 35 USC 102 Novelty (BERT): 0.5472893718348589
- Combined Prediction Score: 0.8039193089199015
- Mean Citation Score: 283.00209200000006
- Max Citation Score: 435.5402
- Similarity Product: 301.254763214314

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test