PATENT CLAIM ANALYSIS

Application Number: 16133269
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["712", "222000"]

Abstract:
An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

Claim (Index 32):
The method of  claim 31 , wherein the storage is X bits and the third input operand is K bits of the storage.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 97.0
- Lexical Diversity: 1.44444
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13538523', '13996529', '15141786', '15257833', '13538499']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6314545483757081
- 35 USC 102 Novelty (BERT): 0.5492837907293275
- Combined Prediction Score: 0.6232374726110701
- Mean Citation Score: 386.8207880000001
- Max Citation Score: 442.9806
- Similarity Product: 255.82224069635868

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test