PATENT CLAIM ANALYSIS

Application Number: 15906890
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["257", "326000"]

Abstract:
A memory device comprises electrode layers stacked in a stacking direction. Semiconductor pillars penetrate the electrode layers in the stacking direction. First wirings are disposed above the plurality of electrode layers at a first level. Each first wiring is electrically connected to a semiconductor pillar. A second wiring is disposed above the plurality of electrode layers at the first level. The second wiring is insulated from semiconductor pillars. The second wiring and the first wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction. A width of the second wiring the second direction is equal to a width of each first wiring. A spacing distance between the second wiring and a nearest first wiring is greater than a spacing interval between adjacent first wirings.

Claim (Index 16):
The memory device according to  claim 11 , wherein the outermost first wiring in the plurality of first wirings is an active bit line wiring.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 2.58929
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15906423', '15855186', '12705231', '14687177', '13401113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9185799472605514
- 35 USC 102 Novelty (BERT): 0.4890088418510913
- Combined Prediction Score: 0.8756228367196053
- Mean Citation Score: 175.594106
- Max Citation Score: 190.95038
- Similarity Product: 131.8681998753571

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test