PATENT CLAIM ANALYSIS

Application Number: 15912463
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["711", "206000"]

Abstract:
Provided are an apparatus and method for allocating shared memory blocks to table entries to store in a memory device. A memory interface unit includes interface circuitry to connect to the blocks of the memory device. Requests are received to target addresses to access tables. For each request of the requests to a target address for a target table of the tables, the request is routed to a table block dedicated to the target table in response to the target address mapping to the table block and route the request to a shared memory block allocated to the target table in response to the target address mapping to the shared memory block allocated to the target table.

Claim (Index 24):
The method of  claim 17 , wherein a first table of the tables comprises leader state transitions and a second table of the tables stores a set of member state transitions for each leader state transition, wherein member state transitions for one of the leader state transitions differ from the leader state transitions by at least one character, wherein the leader and member state transitions are concurrently requested from the first and second tables.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.59574
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11136651', '11136652', '13767256', '15574938', '14460530']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5039241307516246
- 35 USC 102 Novelty (BERT): 0.4836360836838984
- Combined Prediction Score: 0.501895326044852
- Mean Citation Score: 129.28256919999998
- Max Citation Score: 133.49263
- Similarity Product: 83.93248410232304

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test