PATENT CLAIM ANALYSIS

Application Number: 16151139
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-08
Patent Classification: ["326", "093000"]

Abstract:
A sectioned mesh which includes multiple sections to distribute a clock signal to logic gates. Each section includes interconnected wires operable to deliver the clock signal to the logic gates. The interconnected wires in a same section are shorted together and the interconnected wires in different sections are not shorted. The sectioned mesh also includes clock input structure connecting to one or more contact points in an input section of the sectioned mesh. The sectioned mesh also includes multiple groups of repeater drivers to repower the clock signal. Different groups are in different sections, and each group in a respective section receives the clock signal from a neighboring section.

Claim (Index 14):
The method of  claim 11 , wherein the sections extend from only one side of the input section in a horizontal direction and the repeater drivers in each section are aligned in a vertical direction.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.14815
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11596968', '12987652', '14924542', '13649547', '14221139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6803676660469635
- 35 USC 102 Novelty (BERT): 0.4763083118647048
- Combined Prediction Score: 0.6599617306287376
- Mean Citation Score: 178.76270800000003
- Max Citation Score: 183.00813
- Similarity Product: 131.8603887301719

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test