PATENT CLAIM ANALYSIS

Application Number: 16048921
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

Claim (Index 7):
A semiconductor device, comprising:\n a first interlayer dielectric (ILD) layer disposed over a substrate; a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate, wherein the first metal wiring pattern includes a first lower portion and a first upper portion; a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern, wherein the second metal wiring pattern includes a second lower portion and a second upper portion, in a cross section along a second direction, which crosses the first direction and is in parallel with the substrate, a top of the second metal wiring pattern is fully covered by a first two-dimensional material layer, the first two-dimensional material layer is a single layer of two-dimensional material, and the first two-dimensional material layer is in direct contact with a surface of the second metal wiring pattern, wherein in the cross section, sides and bottom of the upper portion of the second metal wiring pattern are covered by a second two-dimensional material layer, in the cross section, a part of a top of the first metal wiring pattern is covered by a third two-dimensional material layer, and the second metal wiring pattern passes through the third two-dimensional material layer and is in direct contact with a surface of the first metal wiring pattern, and in the cross section, sides and bottom of the upper portion of the first metal wiring pattern are covered by a fourth two-dimensional material layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 1.88095
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15220078', '15484344', '14868377', '15816843', '15593479']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9043172725543602
- 35 USC 102 Novelty (BERT): 0.4593638797156584
- Combined Prediction Score: 0.8598219332704901
- Mean Citation Score: 142.91239319999997
- Max Citation Score: 212.98325
- Similarity Product: 205.62444782979787

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test