PATENT CLAIM ANALYSIS

Application Number: 16104382
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D 1 , between two vertical fin segments.

Claim (Index 20):
The vertical finFET of  claim 19 , wherein the bottom spacer is silicon oxide, the gate dielectric layer is a high-k dielectric material, and the top spacer is silicon oxide.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.41071
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15177362', '15178193', '15789620', '15177358', '16046273']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9461756643312922
- 35 USC 102 Novelty (BERT): 0.6277316131548698
- Combined Prediction Score: 0.91433125921365
- Mean Citation Score: 466.875316
- Max Citation Score: 581.73004
- Similarity Product: 553.2498720224906

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test