PATENT CLAIM ANALYSIS

Application Number: 16400434
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["716", "112000"]

Abstract:
Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified, responsive to the determination that the first chip layout within the tile area fails to comply with the one or more layout design rules, to bring non-compliant periphery chip regions into compliance. It is determined that the portion of the first chip layout within the tile area complies with the one or more design rules after modifying the first chip layout. A multi-chip wafer is fabricated that includes the chip layouts.

Claim (Index 13):
The system of  claim 10 , the one or more layout design rules include a shunt placement rule based on a determination of whether each transistor is within a threshold distance from a shunt.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 100.0
- Lexical Diversity: 2.43284
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15081226', '15073898', '15910132', '15597705', '15154525']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.394242814685473
- 35 USC 102 Novelty (BERT): 0.5268554656953961
- Combined Prediction Score: 0.4075040797864653
- Mean Citation Score: 301.27211
- Max Citation Score: 392.6258
- Similarity Product: 330.9260478370667

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test