PATENT CLAIM ANALYSIS

Application Number: 16173040
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["710", "105000"]

Abstract:
A system on chip includes a display serial interface (DSI) which includes a PHY protocol interface (PPI) used for communication between a DSI host controller and a D-PHY. The DSI host controller includes a register configured to store first indicator data indicating a PPI packetizing method and a lane distributor configured to determine a size of a symbol to be transmitted to the PPI and an order of first processing units to be included in the symbol based on the first indicator data.

Claim (Index 11):
A data processing system comprising:\n a lane distributor configured to:\n receive processing units in a data packet from a DSI host controller, \n determine a number of the processing units, transmission orders of the processing units, and a number of a plurality of lanes through which the processing units are to be transmitted, based on first indicator data, and \n packetize the processing units based on the determined transmission orders of the processing units; and \n a PHY interface circuit configured to receive the packetized processing units from the lane distributor through the plurality of lanes.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 1.71154
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14989823', '16120735', '15139441', '14713080', '11450899']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6516402966425551
- 35 USC 102 Novelty (BERT): 0.5785854522853776
- Combined Prediction Score: 0.6443348122068373
- Mean Citation Score: 239.939102
- Max Citation Score: 516.7654
- Similarity Product: 407.5939313030004

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test