PATENT CLAIM ANALYSIS

Application Number: 15956823
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "321000"]

Abstract:
According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

Claim (Index 2):
A nonvolatile semiconductor memory device, comprising:\n a plurality of first memory cells stacked in a first direction and electrically connected in series; a plurality of second memory cells stacked in the first direction and electrically connected in series, the plurality of second memory cells being provided beside the plurality of first memory cells; and a connection member extending in a second direction and being connected to one end of the plurality of first memory cells and one end of the plurality of second memory cells, the second direction being orthogonal to the first direction, the plurality of first memory cells including\n a first semiconductor body extending in the first direction, \n a plurality of first floating electrodes provided on a side surface of the first semiconductor body interposed a first insulating layer, the plurality of first floating electrodes being stacked in the first direction, and \n a plurality of first conductive layers stacked in the first direction, one of the first conductive layers being provided on a side surface of one of the first floating electrodes interposed a second insulating layer, \n the plurality of second memory cells including\n a second semiconductor body extending in the first direction and being provided beside the first semiconductor body, \n a plurality of second floating electrodes provided on a side surface of the second semiconductor body interposed a third insulating layer, the plurality of second floating electrodes being stacked in the first direction, and \n a plurality of second conductive layers stacked in the first direction, one of the second conductive layers being provided on a side surface of one of the second floating electrodes interposed a fourth insulating layer, and \n the connection member including metal silicide and being formed as a body different from the first semiconductor body and the second semiconductor body.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 91.0
- Lexical Diversity: 3.27083
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15014112', '13780150', '13864882', '12638480', '12708161']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9133794057507773
- 35 USC 102 Novelty (BERT): 0.5534626111246904
- Combined Prediction Score: 0.8773877262881686
- Mean Citation Score: 323.845924
- Max Citation Score: 413.232
- Similarity Product: 326.25513611984263

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test