PATENT CLAIM ANALYSIS

Application Number: 16059136
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "158000"]

Abstract:
Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

Claim (Index 36):
An apparatus, comprising:\n a delay locked loop configured to receive an input at a first end and generate a feedback clock signal at a second end based on the input, wherein the delay locked loop has a delay between the first end and a location within the delay locked loop; an input block coupled to the delay locked loop, wherein the input block is configured to output an input clock signal to the input of the delay locked loop, wherein the input block is configured to selectively omit at least one cycle of the input clock signal in response to a skip-control signal; a loop monitor coupled to the delay locked loop and the input block, wherein the loop monitor is configured to:\n receive the feedback clock signal; \n assert the skip-control signal; and \n determine a number of cycles of the clock signal in the delay of the delay locked loop based on detection of the at least one omitted clock cycle at the location within the delay locked loop.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.04839
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15583539', '12659057', '11588954', '11250600', '12615833']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7673867720085618
- 35 USC 102 Novelty (BERT): 0.5076488637998783
- Combined Prediction Score: 0.7414129811876935
- Mean Citation Score: 220.804588
- Max Citation Score: 312.15414
- Similarity Product: 279.74111667131064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test