PATENT CLAIM ANALYSIS

Application Number: 16061604
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["716", "106000"]

Abstract:
The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes. A simulator object is able to store and/or maintain simulation state by retrieving it from a sole manager object, and a logical construct object is able to retrieve its initial state from the simulator object on construction and save its state on destruction. Furthermore, logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.

Claim (Index 15):
The method according to  claim 10 , wherein the logical construct is:\n a clock signal; a reset signal; a register; a memory block; a wire, wherein a wire is a mechanism which enables a signal to be read before it is written; a tri-state signal; a module instantiation with an associated name; a module input signal; a module output signal; a module tri-state input and output signal; a sensitivity list; and/or a debugging element.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.93443
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10405573', '11315683', '12640601', '09418706', '11006093']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3689149665111014
- 35 USC 102 Novelty (BERT): 0.4797390423193083
- Combined Prediction Score: 0.3799973740919221
- Mean Citation Score: 200.800626
- Max Citation Score: 211.14864
- Similarity Product: 138.6865992179203

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test