PATENT CLAIM ANALYSIS

Application Number: 16153225
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "185240"]

Abstract:
Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

Claim (Index 18):
The method of  claim 17 , wherein the single page of data read from each associated erasure block on a selected die shares the same page address.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 1.81707
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15498595', '14871148', '15078151', '15585429', '13969049']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.794276250726571
- 35 USC 102 Novelty (BERT): 0.5353413222654554
- Combined Prediction Score: 0.7683827578804595
- Mean Citation Score: 272.340866
- Max Citation Score: 373.05783
- Similarity Product: 260.61097117445115

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test