PATENT CLAIM ANALYSIS

Application Number: 16161247
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-09
Patent Classification: ["365", "230060"]

Abstract:
A memory device includes a plurality of memory regions including memory cells coupled between a plurality of word lines and a plurality of bit lines, an address decoder suitable for decoding an address to generate a plurality of selection signals corresponding to the bit lines, and outputting the selection signals to a plurality of signal lines, and a plurality of selection circuits corresponding to the memory regions, respectively, and suitable for selecting the bit lines in response to the selection signals received through the signal lines, wherein at least one of the selection circuits is coupled to the signal lines in an arrangement different from remaining selection circuits.

Claim (Index 6):
The memory device of  claim 5 , wherein when a greatest common divisor of K and N is equal to or greater than 2, and an overlapping signal line occurs in the wrapping order, the skipped line number order restarts from a signal line having a line number less than the overlapping signal line by K+1.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 2.39583
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10937335', '14859635', '10506868', '12323583', '09469497']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8032162322976539
- 35 USC 102 Novelty (BERT): 0.5001298050080958
- Combined Prediction Score: 0.7729075895686982
- Mean Citation Score: 186.85515400000003
- Max Citation Score: 193.33708
- Similarity Product: 107.95993926700116

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test