PATENT CLAIM ANALYSIS

Application Number: 16057036
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["257", "206000"]

Abstract:
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

Claim (Index 1):
A complementary metal oxide semiconductor (CMOS) device including a plurality of p-type metal oxide semiconductor (PMOS) transistors each having a PMOS drain and a PMOS gate and a plurality of n-type metal oxide semiconductor (NMOS) transistors each having an NMOS drain and an NMOS gate, each PMOS gate and NMOS gate extending in a first direction, the CMOS device comprising:\n a first interconnect on an interconnect level connecting a first subset of the PMOS drains together, the first interconnect extending in a second direction perpendicular to the first direction; a second interconnect on the interconnect level connecting a second subset of the PMOS drains together, the second subset of the PMOS drains being different than the first subset of the PMOS drains, the first interconnect and the second interconnect being disconnected on the interconnect level; a third interconnect on the interconnect level connecting a first subset of the NMOS drains together, the third interconnect being disconnected from the first interconnect or from the second interconnect on the interconnect level; and a fourth interconnect on the interconnect level connecting a second subset of the NMOS drains together, the second subset of the NMOS drains being different than the first subset of the NMOS drains, the third interconnect and the fourth interconnect being disconnected on the interconnect level, wherein the first interconnect coupling the first subset of the PMOS drains together and the second interconnect coupling the second subset of the PMOS drains together on the interconnect level, and the third interconnect coupling the first subset of NMOS drains together and the fourth interconnect coupling the second subset of the NMOS drains together on the interconnect level are coupled together through at least one other interconnect level.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 4.41667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13975074', '15493008', '15927539', '13975185', '15393180']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9262588824482316
- 35 USC 102 Novelty (BERT): 0.5778429200959212
- Combined Prediction Score: 0.8914172862130006
- Mean Citation Score: 382.722248
- Max Citation Score: 428.4985
- Similarity Product: 424.18246183741087

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test