PATENT CLAIM ANALYSIS

Application Number: 15964487
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "329000"]

Abstract:
Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.

Claim (Index 4):
The method of  claim 3 , wherein the lateral direction and the another lateral direction lie in a same plane perpendicular to the vertical direction.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.45283
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15139937', '15138651', '15177358', '15290146', '15843318']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9288953811981534
- 35 USC 102 Novelty (BERT): 0.534075721019001
- Combined Prediction Score: 0.8894134151802381
- Mean Citation Score: 250.495738
- Max Citation Score: 368.68393
- Similarity Product: 367.1688666623211

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test