PATENT CLAIM ANALYSIS

Application Number: 16435887
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["438", "268000"]

Abstract:
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

Claim (Index 16):
The method of  claim 15 , wherein the top portion is displaced from the bottom portion by at least 5 nm.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 100.0
- Lexical Diversity: 1.75
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15882454', '15891126', '14452220', '15332910', '14222418']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9172030596015772
- 35 USC 102 Novelty (BERT): 0.5649113816877478
- Combined Prediction Score: 0.8819738918101945
- Mean Citation Score: 367.319006
- Max Citation Score: 460.03082
- Similarity Product: 354.6965800705445

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test