PATENT CLAIM ANALYSIS

Application Number: 15868683
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "369000"]

Abstract:
A complimentary metal-oxide-semiconductor (CMOS) device includes a wafer having a bulk semiconductor layer. A fin-type semiconductor device is formed on a first portion of the wafer. The CMOS devices also includes a nanosheet semiconductor device formed on a second portion of the wafer different from the first portion.

Claim (Index 11):
A method of fabricating a configuration of complimentary metal-oxide-semiconductor (CMOS) device, the method comprising:\n forming, on an upper surface of a bulk semiconductor layer of a semiconductor wafer, an alternating series of first semiconductor layers and second semiconductor layers stacked on top of one another, a lower-most first semiconductor layer formed directly on the bulk semiconductor layer and having a different doping concentration of than remaining first semiconductor layers; etching the alternating series of first semiconductor layers and second semiconductor layers to form a first sacrificial stack on the semiconductor wafer and a second sacrificial stack on the semiconductor wafer; selectively etching the remaining first semiconductor layers with respect to the second semiconductor layers and the lower-most first semiconductor layers layer to form a plurality of semiconductor nanosheets; epitaxially growing a semiconductor material from the first sacrificial semiconductor stack and subsequently removing the first sacrificial semiconductor stack to form a semiconductor fin; replacing the lower-most first semiconductor layers layer with a dielectric layer; and forming a first electrically conductive gate structure on the semiconductor fin to define a p-type field effect field transistor (PFET) on the semiconductor wafer, and forming a second electrically conductive gate structure on the plurality of semiconductor nanosheets to form an n-type filed effect transistor (NFET) on the semiconductor wafer.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 1.76667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15868742', '15342346', '15404469', '15339665', '15866851']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9121156352273156
- 35 USC 102 Novelty (BERT): 0.5128870186413945
- Combined Prediction Score: 0.8721927735687235
- Mean Citation Score: 286.816322
- Max Citation Score: 297.2113
- Similarity Product: 242.19098126064537

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test