PATENT CLAIM ANALYSIS

Application Number: 15986886
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "329000"]

Abstract:
Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.

Claim (Index 7):
The method of  claim 1  further comprising laterally trimming the first recess to the fin.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 93.0
- Lexical Diversity: 1.51282
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15918077', '13848203', '14750455', '15404466', '14729105']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303109199561738
- 35 USC 102 Novelty (BERT): 0.5260753330500983
- Combined Prediction Score: 0.8898873612655662
- Mean Citation Score: 323.995334
- Max Citation Score: 332.1764
- Similarity Product: 182.43422843065247

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test