PATENT CLAIM ANALYSIS

Application Number: 15864896
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "713000"]

Abstract:
In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

Claim (Index 27):
The method of  claim 23 , wherein forming the conductive feature comprises:\n plating a copper pillar on the dummy TSV.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 86.0
- Lexical Diversity: 2.64706
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15800349', '14470666', '14298548', '15720565', '15181212']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9237563176986552
- 35 USC 102 Novelty (BERT): 0.5231397089647871
- Combined Prediction Score: 0.8836946568252683
- Mean Citation Score: 229.23955
- Max Citation Score: 288.80988
- Similarity Product: 159.56365706962825

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test