PATENT CLAIM ANALYSIS

Application Number: 15945215
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "326000"]

Abstract:
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

Claim (Index 33):
A method of forming an integrated structure, comprising:\n forming vertically-stacked levels over a base; the base comprising a sacrificial material over a first conductively-doped semiconductor material; upper levels of the vertically-stacked levels being memory cell levels, and a lower level of the vertically-stacked levels being a select device level; forming a pair of openings extending through the memory cell levels, through the select device level, through the sacrificial material, and into the first conductively-doped semiconductor material; the openings being a first opening and a second opening; forming tunneling material, charge-storage material and charge-blocking material extending vertically along sidewalls of the first and second openings to narrow the first and second openings; the charge-storage material comprising silicon and nitrogen; forming channel material within the narrowed first and second openings; the channel material extending vertically along the memory cell levels, the select device level and the sacrificial material, and extending downwardly into the conductively-doped semiconductor material; a region of the channel material along the sacrificial material within the narrowed first opening being comprised by a first lower region, and a region of the channel material along the sacrificial material within the narrowed second opening being comprised by a second lower region; the first and second lower regions of the channel material having first and second sidewalls, respectively; the first and second lower regions of the channel material having first segments along the sacrificial material, and having lowest segments beneath the first segments and along the first conductively-doped semiconductor material; removing regions of the tunneling material, charge-storage material, and charge-blocking material along the first segments of the channel material to expose the first and second sidewalls along said first segments, and to form a void over the first conductively-doped semiconductor material; regions of the tunneling material, charge-storage material, and charge-blocking material along the lowest segments not being removed and remaining along the first conductively-doped semiconductor material; and forming a second conductively-doped semiconductor material within the void and directly against the exposed first and second sidewalls of the channel material; the second conductively-doped semiconductor material being over the regions of the tunneling material, charge-storage material, and charge-blocking material remaining along the first conductively-doped semiconductor material.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.7931
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15130803', '15651916', '15659482', '15176072', '15926427']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9176224436624436
- 35 USC 102 Novelty (BERT): 0.50132494474287
- Combined Prediction Score: 0.8759926937704863
- Mean Citation Score: 236.304954
- Max Citation Score: 304.54034
- Similarity Product: 295.8013591400516

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test