PATENT CLAIM ANALYSIS

Application Number: 15983125
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "751000"]

Abstract:
Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.

Claim (Index 16):
The semiconductor package of  claim 13 , the first conductive layer and the second conductive layer are formed by a patterning a conductive layer,\n wherein the conductive layer covers the lower semiconductor chip and the lower mold layer and fills the opening.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 93.0
- Lexical Diversity: 2.57447
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15235958', '14531994', '15856800', '14841736', '15245243']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9192067318300752
- 35 USC 102 Novelty (BERT): 0.5369964978402605
- Combined Prediction Score: 0.8809857084310938
- Mean Citation Score: 286.442348
- Max Citation Score: 357.1053
- Similarity Product: 285.761871142745

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test