PATENT CLAIM ANALYSIS

Application Number: 15869654
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["345", "030000"]

Abstract:
A display panel and a display device are provided. The display panel includes a substrate, the substrate is provided with a display region, a fan-out region, and a plurality of driving chips, a plurality of signal lines formed in the display region; a plurality of pixel regions formed in the display region, and coupled to the signal lines; a plurality of fan-out wires formed in the fan-out region, wherein one terminal of each of the fan-out wires is connected to the signal lines, the other terminal of each of the fan-out wires is connected to the driving chips; a connecting portion formed in the fan-out region; a plurality of connecting lines formed in the connecting portion, wherein each of the driving chips is connected by the connecting lines; wherein the plurality of the fan-out wires are arranged corresponding to a disposing position of the connecting portion.

Claim (Index 10):
The display panel according to  claim 1 , wherein the driving chips comprises first source electrode driving chips, second source electrode driving chips, first gate electrode driving chips and second gate electrode driving chips, wherein the first source electrode driving chips and the second source electrode driving chips are disposed adjacent to each other in the same side of a first edge of the display area, and the first gate electrode driving chips and the second gate electrode driving chips are disposed in both sides of the first edge, respectively;\n the fan-out region comprising a first fan-out region and a second fan-out region, the first fan-out region comprising a plurality of first fan-out wires connected to the first source electrode driving chips, the second fan-out region comprising a plurality of second fan-out wires connected to the second source electrode driving chips; the connecting portion comprising a first connecting portion and a second connecting portion formed in the first fan-out region, and a third connecting portion and a fourth connecting portion formed in the second fan-out region, wherein the first source electrode driving chips and the second source electrode driving chips are connected by the connecting lines in the first connecting portion and the third connecting portion, the first source electrode driving chips and the first gate electrode driving chips are connected by the connecting lines in the second connecting portion, the second source electrode driving chips and the second gate electrode driving chips are connected by the connecting lines in the fourth connecting portion; the first connecting portion and the third connecting portion disposed at an intermediate position of the first fan-out region, the plurality of first fan-out wires arranged corresponding to the position of the first connecting portion and the third connecting portion; and the second connecting portion and the fourth connecting portion disposed at an intermediate position of the second fan-out region, wherein the plurality of second fan-out wires are arranged corresponding to the position of the second connecting portion and the fourth connecting portion.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 3.57778
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14396052', '15075345', '14950976', '12176416', '14438697']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6502695148129946
- 35 USC 102 Novelty (BERT): 0.4825736817058974
- Combined Prediction Score: 0.6334999315022849
- Mean Citation Score: 208.693556
- Max Citation Score: 212.171
- Similarity Product: 160.71296751272678

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test