PATENT CLAIM ANALYSIS

Application Number: 16194018
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["257", "029000"]

Abstract:
Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

Claim (Index 1):
A method of fabricating a semiconductor structure, comprising:\n providing a substrate with a fin thereon, wherein the fin comprises first and second sidewalls and a top surface; depositing a first dielectric layer on the fin, wherein the first dielectric layer covers the first and second sidewalls and the top surface of the fin; depositing a two-dimensional (2-D) material layer on the first dielectric layer; depositing a second dielectric layer on the 2-D material layer; depositing an electrode layer on the second dielectric layer; and patterning the electrode layer and the second dielectric layer to form a gate stack having a length shorter than that of the 2-D material layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 98.0
- Lexical Diversity: 1.40909
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15615498', '14953481', '16004816', '14918737', '13530887']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91676391532924
- 35 USC 102 Novelty (BERT): 0.5064755368332905
- Combined Prediction Score: 0.8757350774796452
- Mean Citation Score: 210.877344
- Max Citation Score: 302.8908
- Similarity Product: 261.73472223129266

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test