PATENT CLAIM ANALYSIS

Application Number: 15871055
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "192000"]

Abstract:
A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

Claim (Index 10):
The semiconductor device of  claim 7 ,\n wherein the impurity providing layer includes a plurality of elements including at least one of carbon (C), boron (B), lanthanum (La), hafnium (Hf), zirconium (Zr), aluminum (Al) or yttrium (Y), and wherein the plurality of elements and the plurality of doping elements are the same in kind.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 86.0
- Lexical Diversity: 2.40385
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15466111', '13081776', '13796394', '14748575', '13920926']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9230792226745076
- 35 USC 102 Novelty (BERT): 0.4784346426882974
- Combined Prediction Score: 0.8786147646758866
- Mean Citation Score: 198.912112
- Max Citation Score: 200.08736
- Similarity Product: 157.0585052625656

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test