PATENT CLAIM ANALYSIS

Application Number: 16244352
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-10
Patent Classification: ["365", "185180"]

Abstract:
A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Claim (Index 1):
A system comprising:\n a processor; at least one voltage source; and a memory array; wherein:\n the processor is configured to provide control signals to the at least one voltage source and the memory array; \n the at least one voltage source is configured to generate a plurality of voltages, wherein the plurality of voltages comprises at least one voltage of at least 3.5V; and \n the memory array comprises:\n a first memory cell comprising a first transistor coupled to a second transistor, wherein the first transistor comprises a memory element; and \n a second memory cell comprising a third transistor coupled to a fourth transistor; \n wherein, in response to an initiation of a programming operation, the memory array receives at least one of the plurality voltages at each of a drain of the first transistor, a drain of the third transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the first transistor, and \n wherein receiving the voltages results in a change in one or more electrical characteristics of the memory element.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 99.0
- Lexical Diversity: 3.41379
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15271028', '14618815', '14316615', '15782137', '12975055']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7925933985646819
- 35 USC 102 Novelty (BERT): 0.4336679886137375
- Combined Prediction Score: 0.7567008575695875
- Mean Citation Score: 154.51771399999996
- Max Citation Score: 168.6856
- Similarity Product: 161.65840744085313

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test