PATENT CLAIM ANALYSIS

Application Number: 16217876
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "329000"]

Abstract:
A semiconductor device includes gate stacked structures surrounding channel layers, a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, and a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

Claim (Index 2):
The method of  claim 1 , further comprising, when the second material layers include a sacrificial material having an etch rate different from the first material layers:\n removing the second material layers through the second slit when the first material layers are supported by the fourth material layer; and filling regions from which the second material layers are removed with gate conductive materials.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 98.0
- Lexical Diversity: 1.45
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15638496', '14870164', '16033825', '14560638', '15007404']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916095331010103
- 35 USC 102 Novelty (BERT): 0.5228139319959444
- Combined Prediction Score: 0.8767671911086872
- Mean Citation Score: 242.669732
- Max Citation Score: 334.96136
- Similarity Product: 245.6360799171591

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test