PATENT CLAIM ANALYSIS

Application Number: 15962440
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "773000"]

Abstract:
A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region.

Claim (Index 5):
The method according to  claim 3 , wherein etching the second passivation layer to expose the conductive pad region comprises etching a portion of the first passivation layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 2.79487
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13369085', '14516492', '11641500', '15337328', '15800548']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9018791569095364
- 35 USC 102 Novelty (BERT): 0.4786399230382644
- Combined Prediction Score: 0.8595552335224091
- Mean Citation Score: 157.78441600000005
- Max Citation Score: 166.05403
- Similarity Product: 126.19908169809104

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test