PATENT CLAIM ANALYSIS

Application Number: 16238876
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "737000"]

Abstract:
In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Claim (Index 1):
A semiconductor device comprising:\n a first wiring substrate having a first obverse surface, a first reverse surface opposite the first obverse surface, a plurality of first wirings formed in the first wiring substrate, and a plurality of solder balls formed on the first reverse surface; a second wiring substrate as an interposer having a second obverse surface, a second reverse surface opposite the second obverse surface and a first wiring layer arranged closer to the second obverse surface than the second reverse surface; the second wiring substrate disposed on the first obverse surface of the first wiring substrate such that the second reverse surface faces the first obverse surface of the first writing substrate; a first semiconductor chip having a first main surface, a second rear surface opposite the first main surface and a plurality of first bump electrodes formed on the first main surface; the first semiconductor chip mounted on the second obverse surface of the second wiring substrate such that the first main surface faces the second obverse surface of the second wiring substrate via a first underfill material; a second semiconductor chip having a second main surface, a second rear surface opposite the second main surface and a plurality of second bump electrodes formed on the second main surface; and the second semiconductor chip mounted side by side with the first semiconductor chip on the second obverse surface of the second wiring substrate such that the second main surface faces the second obverse surface of the second wiring substrate via a second underfill material, wherein the first semiconductor chip includes a plurality of memory chips which are laminated with each other via a third underfill material, wherein, in a cross section view, a thickness of the first semiconductor chip is larger than a thickness of the second wiring substrate in a thickness direction of the second wiring substrate, and wherein in the cross section view, the thickness of the second wiring substrate is larger than a thickness of each of the memory chips in the thickness direction.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.28261
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15714712', '15354484', '14606425', '14455336', '14108960']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.93210701337328
- 35 USC 102 Novelty (BERT): 0.5269559021666265
- Combined Prediction Score: 0.8915919022526146
- Mean Citation Score: 336.997674
- Max Citation Score: 360.9273
- Similarity Product: 337.97720581576823

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test