PATENT CLAIM ANALYSIS

Application Number: 15909589
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["714", "755000"]

Abstract:
A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.

Claim (Index 7):
The memory system according to  claim 6 ,\n wherein the internal code in-error-bit estimation unit further includes\n one or more second parity inspection units that perform parity inspection of the internal code on the bit sequence which is the first result of decoding that is received by the data input unit, \n a syndrome register in which one or more syndrome values that are obtained as a result of each parity inspection by the second parity inspection unit, and \n a syndrome counter that calculates a sum of the syndrome values which are retained in the syndrome register, for each bit in the bit sequence that is the first result of decoding, \n wherein the in-error-bit estimation unit estimates that a bit, for which the sum of the syndrome values which are calculated by the syndrome counter exceeds a predetermined value, is the in-error bit, and wherein the first error level calculation unit records the sum of the syndrome values that are obtained by the parity inspection to which the in-error bit is subject, as the error level, for each of the in-error bits that are estimated.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 2.78571
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13679970', '12153121', '13547288', '13529390', '12379746']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3174542395512283
- 35 USC 102 Novelty (BERT): 0.4773321387736165
- Combined Prediction Score: 0.3334420294734672
- Mean Citation Score: 179.27520399999997
- Max Citation Score: 181.89594
- Similarity Product: 129.9861069585085

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test