PATENT CLAIM ANALYSIS

Application Number: 16012453
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["375", "356000"]

Abstract:
A semiconductor apparatus may include a synchronization circuit, and a phase detection circuit. The synchronization circuit may be configured to, based on an operation mode of the semiconductor apparatus, divide a first clock signal to generate first and second divided clock signals or divide a phase-locked clock signal to generate first and second divided clock signals. The phase detection circuit may be configured to use, based on the operation mode of the semiconductor apparatus, either the first and second clock signals created from dividing the first clock signal or the first and second clock signals created from dividing the phase-locked clock signal, to compare either the first divided clock signal or the second divided clock signal with a second clock signal to generate a phase detection signal.

Claim (Index 11):
The method according to  claim 10 , wherein the first clock signal has higher frequency than the second clock signal, and the first and second divided clock signals has lower frequencies than the first clock signal.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 94.0
- Lexical Diversity: 3.31707
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14845425', '15453408', '13944345', '15258672', '15812420']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5117589885732579
- 35 USC 102 Novelty (BERT): 0.4915145829742026
- Combined Prediction Score: 0.5097345480133524
- Mean Citation Score: 208.415252
- Max Citation Score: 217.94884
- Similarity Product: 157.00514275127887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test