PATENT CLAIM ANALYSIS

Application Number: 16101038
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-06
Patent Classification: ["365", "185030"]

Abstract:
A memory controller controls an operation of a semiconductor memory device including a plurality of memory cells at a request of a host. The memory controller includes a data conversion unit. The data conversion unit converts first data from the host by comparing the first data with second data programmed previously.

Claim (Index 23):
A memory system comprising:\n a memory device including a memory cell array coupled to word lines and bit lines respectively in row and column directions; and a controller configured to: generate randomized data by randomizing original data; generate currently converted data by selectively inverting the randomized data based on bit-similarity between the randomized data and previously converted data stored in the memory cell array coupled to one or more adjacent word lines; generate a flag bit indicating the currently converted data as one between inverted and non-inverted versions of the randomized data; and control the memory device to store the currently converted data and the flag bit into the memory cell array on a word line basis.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 96.0
- Lexical Diversity: 1.6875
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15703175', '13176035', '14657711', '12146121', '13469847']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.79295722373097
- 35 USC 102 Novelty (BERT): 0.4738234070681544
- Combined Prediction Score: 0.7610438420646884
- Mean Citation Score: 203.03369400000005
- Max Citation Score: 218.41309
- Similarity Product: 173.0243696883202

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test