PATENT CLAIM ANALYSIS

Application Number: 15948016
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "347000"]

Abstract:
The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs.

Claim (Index 19):
A method, comprising:\n selecting at least one of lateral position and lateral shape of a contact element for a source region of a transistor element so as to provide lateral overlap of said contact element and an isolation region adjacent to said source region; and forming said contact element on the basis of said lateral overlap so as to extend through a buried insulating layer and to a doped semiconductor region formed below said buried insulating layer and connectable to a reference potential.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 1.5303
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15647403', '15706048', '15622497', '15439444', '13404759']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9193547219571552
- 35 USC 102 Novelty (BERT): 0.4920478055797085
- Combined Prediction Score: 0.8766240303194104
- Mean Citation Score: 238.112018
- Max Citation Score: 250.25142
- Similarity Product: 197.6564144738209

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test