PATENT CLAIM ANALYSIS

Application Number: 15869092
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["365", "063000"]

Abstract:
A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array, and a memory controller is provided. The memory cell array includes a plurality of memory cells. The memory cells are configured to store data. Each of the memory cells is coupled to the corresponding word line and the corresponding bit line. The memory controller is configured to perform a read operation to the memory cell array. The memory controller performs a pre-charge operation to part or all of the bit lines when the memory controller enables the word lines. In addition, an operating method of a memory storage apparatus is also provided.

Claim (Index 20):
The operating method of the memory storage apparatus as claimed in  claim 12 , wherein the word lines are enabled in a first decoding period, a sector signal is decoded in a second decoding period, and the pre-charge operation is performed to part of the bit lines in the first decoding period and part of the second decoding period.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 2.54167
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12455337', '13399986', '15343332', '15213030', '14798795']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8112210338738289
- 35 USC 102 Novelty (BERT): 0.4778163108373225
- Combined Prediction Score: 0.7778805615701783
- Mean Citation Score: 192.324692
- Max Citation Score: 195.81645
- Similarity Product: 141.4374151334345

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test