PATENT CLAIM ANALYSIS

Application Number: 16006314
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["257", "004000"]

Abstract:
A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.

Claim (Index 11):
A memory device comprising:\n a first conductive line extending on a substrate along a first direction; a pair of second conductive lines extending on the first conductive line along a second direction intersecting with the first direction; a pair of memory cell structures, which are at intersections between the first conductive line and the pair of second conductive lines; a first select device layer and a second select device layer on the pair of memory cell structures, respectively; an insulation film interposed between the first select device layer and the second select device layer; a first one of the pair of memory cell structures comprising a first resistive memory layer; a second one of the pair of memory cell structures comprising a second resistive memory layer; a first insulation pattern interposed between the first resistive memory layer and the second resistive memory layer; and a first electrode layer, which is shared by the pair of memory cell structures, and completely covers bottom surfaces of the first resistive memory layer and the second resistive memory layer; wherein first included angles between sidewalls of the first resistive memory layer and the second select device layer contacting the first insulation pattern and a horizontal plane parallel to a surface of the substrate are acute angles, and wherein second included angles between sidewalls of the first select device layer and the second select device layer contacting the insulation film and the horizontal plane are obtuse angles.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 94.0
- Lexical Diversity: 3.2
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15663065', '15867951', '14736525', '15864388', '14531813']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9051503939843965
- 35 USC 102 Novelty (BERT): 0.4941006013007956
- Combined Prediction Score: 0.8640454147160362
- Mean Citation Score: 238.334948
- Max Citation Score: 248.89384
- Similarity Product: 208.27268375660407

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test