PATENT CLAIM ANALYSIS

Application Number: 15920251
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["375", "355000"]

Abstract:
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

Claim (Index 9):
The circuit of  claim 7 , wherein the second phase interpolator control signal generated during the clock cycle is based upon the next phase interpolator code if a boundary crossing in a positive direction is detected.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 90.0
- Lexical Diversity: 2.35714
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14989323', '14235242', '14798340', '14409165', '13397303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5192775139921707
- 35 USC 102 Novelty (BERT): 0.5007281822862703
- Combined Prediction Score: 0.5174225808215807
- Mean Citation Score: 229.511208
- Max Citation Score: 248.10484
- Similarity Product: 176.66645774266

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test