PATENT CLAIM ANALYSIS

Application Number: 16396937
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Claim (Index 1):
An integrated circuit (IC) comprising:\n a semiconductor substrate including a memory cell region, a high-voltage high-\u03ba metal gate transistor region, and a low-voltage high-\u03ba metal gate transistor region, wherein a boundary region that includes an isolation structure separates the memory cell region from the high-voltage high-\u03ba metal gate transistor region; a pair of split gate flash memory cells comprising first and second individual source/drain regions and a common source/drain region disposed between the first and second individual source/drain regions, a first select gate and a first memory gate disposed between the first individual source/drain region and the common source/drain region, and a second select gate and a second memory gate disposed between the common source/drain region and the second individual source/drain region; a high-voltage high-\u03ba metal gate transistor, which comprises a high-voltage metal gate, disposed over the high-voltage high-\u03ba metal gate transistor region; and a low-voltage high-\u03ba metal gate transistor, which comprises a low-voltage metal gate, disposed over the low-voltage high-\u03ba metal gate transistor region; and wherein upper surfaces of the first and second memory gates are co-planar or level with upper surfaces of the first and second select gates, are co-planar or level with an upper surface of the high-voltage metal gate, and are co-planar or level with an upper surface of the low-voltage metal gate.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 100.0
- Lexical Diversity: 1.64286
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15582889', '14324369', '14296496', '14547251', '14580454']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914263496263614
- 35 USC 102 Novelty (BERT): 0.5018341712961862
- Combined Prediction Score: 0.8730205637668713
- Mean Citation Score: 213.67021
- Max Citation Score: 261.62045
- Similarity Product: 249.5763337124884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test