PATENT CLAIM ANALYSIS

Application Number: 15880455
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "737000"]

Abstract:
An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

Claim (Index 6):
The IC package of  claim 5 , wherein at least one metal layer in the first die or at least one metal layer in the second die is coupled to a ground potential and located between the digital base band logic and the analog base band logic to reduce interference between signals in the digital base band logic or the analog base band logic.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 2.15686
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14040223', '09961767', '12512313', '14435677', '15346512']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9162053910492916
- 35 USC 102 Novelty (BERT): 0.4986884233545325
- Combined Prediction Score: 0.8744536942798157
- Mean Citation Score: 163.316214
- Max Citation Score: 168.52696
- Similarity Product: 99.86150054878236

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test