PATENT CLAIM ANALYSIS

Application Number: 15921056
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "392000"]

Abstract:
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.

Claim (Index 8):
A manufacturing method of a semiconductor device, comprising:\n forming an element separation layer on a semiconductor substrate; forming a first well layer by implanting impurities of a first conductivity type into a digital circuit forming area of the semiconductor substrate; forming a second well layer by implanting impurities of the first conductivity type into an analog circuit forming area of the semiconductor substrate, which is separated from the digital circuit forming area by the element separation layer; forming a non-doped film by selectively growing the non-doped film on a surface of the semiconductor substrate in the analog circuit forming area; forming gate insulating films on a surface of the semiconductor substrate in the digital circuit forming area and a surface of the non-doped film in the analog circuit forming area; forming a first gate electrode on a surface of the gate insulating film in the digital circuit forming area and forming a second gate electrode on a surface of the gate insulating film in the analog circuit forming area; forming a digital side second conductivity type impurity layer and an analog side second conductivity type impurity layer by implanting impurities of a second conductivity type into the first well layer and the non-doped film with a mean range shallower than or equal to thickness of the non-doped film; forming sidewalls made of insulating films on side surfaces of respective ones of the first gate electrode and the second gate electrode; forming a first source region and a first drain region in the digital side second conductivity type impurity layer and forming a second source region and a second drain region in the analog side second conductivity type impurity layer by implanting impurities of the second conductivity type into the digital side second conductivity type impurity layer and the analog side second conductivity type impurity layer using the first gate electrode, the second gate electrode, and the sidewalls as masks; and forming silicide films on surfaces of the first source region, the first drain region, and the first gate electrode and the second source region, the second drain region, and the second gate electrode.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.45902
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12219019', '13075625', '10403122', '11882355', '12963270']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9307839042227036
- 35 USC 102 Novelty (BERT): 0.5139426617282729
- Combined Prediction Score: 0.8890997799732606
- Mean Citation Score: 321.176508
- Max Citation Score: 328.9029
- Similarity Product: 294.4689525296509

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test