PATENT CLAIM ANALYSIS

Application Number: 16041160
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["706", "015000"]

Abstract:
A compression coding apparatus for artificial neural network, including memory interface unit, instruction cache, controller unit and computing unit, wherein the computing unit is configured to perform corresponding operation to data from the memory interface unit according to instructions of controller unit; the computing unit mainly performs three steps operation: step one is to multiply input neuron by weight data; step two is to perform adder tree computing and add the weighted output neuron obtained in step one level-by-level via adder tree, or add bias to output neuron to get biased output neuron; step three is to perform activation function operation to get final output neuron. The present disclosure also provides a method for compression coding of multi-layer neural network.

Claim (Index 6):
The neural network processor of  claim 1 , wherein the floating-point number converter is further configured to\n convert the first input neuron data to second input neuron data of the second bit length; and convert the first output neuron data to second output neuron data of the second bit length.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 1.87143
- Patent Class: 706.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['09890816', '15178137', '16039567', '16041497', '11953671']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3461458002962302
- 35 USC 102 Novelty (BERT): 0.4674128647784056
- Combined Prediction Score: 0.3582725067444477
- Mean Citation Score: 164.91772199999997
- Max Citation Score: 165.59361
- Similarity Product: 133.41490315793214

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test