PATENT CLAIM ANALYSIS

Application Number: 15868120
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "139000"]

Abstract:
In mesa regions between adjacent trenches disposed in an n − -type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p + -type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n + -type emitter region, and is electrically isolated from first and second gate electrodes and the floating p + -type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p + -type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.

Claim (Index 1):
A method of manufacturing a semiconductor device, comprising:\n forming a trench to a predetermined depth from a first principal surface of a first semiconductor layer of a first conductivity type; forming a first semiconductor region of a second conductivity type in a surface layer of the first principal surface of the first semiconductor layer at a depth shallower than the trench, the first semiconductor region of the second conductivity type contacting the trench; forming a second semiconductor region of the second conductivity type in the surface layer of the first principal surface of the first semiconductor layer, the second semiconductor region contacting the trench and separated from the first semiconductor region of the second conductivity type by the trench; forming a gate insulating film on the first principal surface of the first semiconductor layer and along an inner wall of the trench; forming an electrode layer on the gate insulating film, so as to be embedded inside the trench; selectively removing the electrode layer to leave a first portion embedded inside the trench as a first gate electrode and a second portion covering a portion of the second semiconductor region as a second gate electrode; forming a third semiconductor region selectively in the first semiconductor region after selectively removing the electrode layer; forming an interlayer insulating film on the first principal surface of the first semiconductor layer, covering the second semiconductor region, the first gate electrode, and the second gate electrode; selectively removing the interlayer insulating film and the gate insulating film so as to expose the first semiconductor region and the third semiconductor region; and forming a first electrode contacting the first semiconductor region and the third semiconductor region, after selectively removing the interlayer insulating film and the gate insulating film.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.31667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15250146', '14824027', '15583982', '14822791', '15774109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9155220368241818
- 35 USC 102 Novelty (BERT): 0.572113820647621
- Combined Prediction Score: 0.8811812152065257
- Mean Citation Score: 351.249768
- Max Citation Score: 449.5983
- Similarity Product: 406.38221470363135

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test