PATENT CLAIM ANALYSIS

Application Number: 16143627
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["361", "748000"]

Abstract:
A printed wiring board includes a first build-up layer including first insulating layer, conductor layer and via conductor, a second build-up layer formed on the first build-up layer and including second insulating layer, conductor layer and via conductor, and a third build-up layer formed on the second build-up layer and including third insulating layer, conductor layer and via conductor. The first via conductor has first via conductor diameter at interface between the first conductor layer and first via conductor, the second via conductor has second via conductor diameter at interface between the second conductor layer and second via conductor, and the third via conductor has third via conductor diameter at interface between the third conductor layer and third via conductor such that the first via conductor diameter is larger than the second via conductor diameter and that the second via conductor diameter is larger than the third via conductor diameter.

Claim (Index 1):
A printed wiring board, comprising\n a first build-up layer comprising a first resin insulating layer, a first conductor layer formed on the first resin insulating layer, and a first via conductor penetrating through the first resin insulating layer and connecting to the first conductor layer; a second build-up layer formed on the first build-up layer and comprising a second resin insulating layer, a second conductor layer formed on the second resin insulating layer, and a second via conductor penetrating through the second resin insulating layer and connecting to the second conductor layer; and a third build-up layer formed on the second build-up layer and comprising a third resin insulating layer, a third conductor layer formed on the third resin insulating layer, and a third via conductor penetrating through the third resin insulating layer and connecting to the third conductor layer, wherein the first via conductor has a first via conductor diameter at an interface between the first conductor layer and the first via conductor, the second via conductor has a second via conductor diameter at an interface between the second conductor layer and the second via conductor, and the third via conductor has a third via conductor diameter at an interface between the third conductor layer and the third via conductor such that the first via conductor diameter is larger than the second via conductor diameter and that the second via conductor diameter is larger than the third via conductor diameter.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 4.96875
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14857074', '14920974', '15581253', '14700313', '15040129']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8468280085088099
- 35 USC 102 Novelty (BERT): 0.4803768125888956
- Combined Prediction Score: 0.8101828889168184
- Mean Citation Score: 244.903306
- Max Citation Score: 256.69
- Similarity Product: 229.01774524331088

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test