PATENT CLAIM ANALYSIS

Application Number: 16299395
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["257", "371000"]

Abstract:
A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

Claim (Index 9):
The method according to  claim 6 , further comprising:\n forming p-type silicide regions on the heavily p-type doped regions, respectively, and n-type silicide regions on the heavily n-type doped regions, respectively, by the silicide process.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 3.3871
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15679346', '11965024', '10753632', '11725404', '11741551']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9297252661249138
- 35 USC 102 Novelty (BERT): 0.529013682545763
- Combined Prediction Score: 0.8896541077669987
- Mean Citation Score: 297.556616
- Max Citation Score: 345.356
- Similarity Product: 218.1722262539864

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test