PATENT CLAIM ANALYSIS

Application Number: 16046453
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-06
Patent Classification: ["365", "201000"]

Abstract:
A memory device and a method are provided. The memory device includes a memory cell array; a peripheral circuit configured to store data in the memory cell array or to read data from the memory cell array; a test mode register set (TMRS) that stores a delay value; and a test circuit. In response to detecting a clock select signal received from outside the memory device, the test circuit generates an asynchronous signal from a clock received from the outside based on the delay value, and controls the peripheral circuit based on the asynchronous signal.

Claim (Index 24):
The memory device of  claim 22 , wherein the test circuit is configured to:\n generate the asynchronous signal delayed by the delay value from a time at which a rising edge of the clock is detected, after detecting the clock select signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.05882
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11195897', '13071287', '10357862', '11845191', '11129150']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8110058331724854
- 35 USC 102 Novelty (BERT): 0.477832174500468
- Combined Prediction Score: 0.7776884673052836
- Mean Citation Score: 191.313342
- Max Citation Score: 195.52943
- Similarity Product: 141.14324106295288

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test