PATENT CLAIM ANALYSIS

Application Number: 16123266
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["327", "333000"]

Abstract:
According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.

Claim (Index 9):
The level shift circuit according to  claim 1 , wherein\n the potential adjusting circuit is a pull-up circuit electrically connected to the second node and the fifth node.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 3.70732
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15694556', '11199017', '12877748', '14633027', '11044030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.775004311202823
- 35 USC 102 Novelty (BERT): 0.4884864535130093
- Combined Prediction Score: 0.7463525254338417
- Mean Citation Score: 169.919638
- Max Citation Score: 179.87349
- Similarity Product: 115.90301503727316

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test