PATENT CLAIM ANALYSIS

Application Number: 16333206
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-08
Patent Classification: ["323", "271000"]

Abstract:
A voltage reducing circuit comprises a power switch circuit portion comprising a high-side and low-side field-effect-transistors connected at a switch node. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion comprising an inductor connected to the switch node is arranged to provide an output voltage. A timer determines a falltime duration required for the output voltage to fall to a threshold value. A controller switches the voltage reducing circuit between a first mode of operation in which a periodic pulse width modulated drive signal is applied to the high-side and low-side field-effect-transistors; and a second mode of operation in which a pulse is applied to the high-side and low-side field-effect-transistors only if the output voltage reaches the threshold value.

Claim (Index 1):
A voltage reducing circuit comprising:\n a power switch circuit portion comprising a high-side field-effect-transistor and a low-side field-effect-transistor arranged in series such that the drain terminals of each of said high-side and low-side transistors are connected at a switch node, the power switch circuit portion having an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled, and an off-state wherein the high-side transistor is disabled and the low-side transistor is enabled; an input voltage connected across said high-side and low-side transistors; an energy storage circuit portion comprising an inductor, said energy storage circuit portion being connected to the switch node and arranged to provide an output voltage; a timer arranged to determine a falltime duration required for the output voltage to fall from an initial value associated with the on-state to a threshold value; and a controller arranged to switch the voltage reducing circuit between a first mode of operation in which a periodic pulse width modulated drive signal is applied to the high-side and low-side field-effect-transistors; and a second mode of operation in which a pulse is applied to the high-side and low-side field-effect-transistors only if the output voltage reaches the threshold value; wherein the controller is arranged to:\n compare the falltime duration to a threshold duration; \n switch the voltage reducing circuit from the second mode to the first mode only if the falltime duration is less than the threshold duration; and \n carry out a test of the voltage reducing circuit, wherein the test comprises switching the voltage reducing circuit from the first mode to the second mode; comparing the falltime duration to a threshold duration; and switching the voltage reducing circuit back to the first mode only if the falltime duration is less than the threshold duration.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 99.0
- Lexical Diversity: 2.11429
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15190095', '15716265', '14926555', '15915205', '12827394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6846387442406928
- 35 USC 102 Novelty (BERT): 0.4786863993004125
- Combined Prediction Score: 0.6640435097466648
- Mean Citation Score: 190.42269
- Max Citation Score: 192.98204
- Similarity Product: 146.9086513750529

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test