PATENT CLAIM ANALYSIS

Application Number: 16120821
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["711", "202000"]

Abstract:
A memory system includes N core dies (N: an integer greater than one) stacked in a vertical direction and including N respective memory circuits having a same structure, a control circuit configured to supply N write data to the N respective memory circuits, an address generating circuit configured to generate a single common address as write addresses at which the N write data are to be stored in the N respective memory circuits, and an address conversion circuit configured to convert the single common address to generate N addresses which are different for the N respective memory circuits and to supply the N addresses as write addresses to the N respective memory circuits.

Claim (Index 2):
The memory system as claimed in  claim 1 , wherein The N write data includes information bits and check bits generated based on the information bits, the check bits including check bits generated with respect to data that is obtained by consolidating information bits corresponding to at least two write data among the N write data.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 97.0
- Lexical Diversity: 2.26415
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15143865', '14569466', '15794105', '15585429', '12342297']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5232062858240187
- 35 USC 102 Novelty (BERT): 0.4798930779637041
- Combined Prediction Score: 0.5188749650379872
- Mean Citation Score: 152.37189199999997
- Max Citation Score: 160.23221
- Similarity Product: 109.6411431718862

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test