PATENT CLAIM ANALYSIS

Application Number: 15948737
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "185170"]

Abstract:
A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.

Claim (Index 15):
A method of making a memory device, comprising:\n forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or subsequently replaced with, electrically conductive layers; forming a first vertical NAND string through the alternating stack, the first vertical NAND string comprising a first drain region and first memory cell charge storage transistors in a series connection with a first drain select transistor and a second drain select transistor; forming a second vertical NAND string through the alternating stack, the second vertical NAND string comprising a second drain region and second memory cell charge storage transistors in a series connection with a third drain select transistor and a fourth drain select transistor, wherein at least one first drain-select-level electrically conductive layer among the electrically conductive layers is formed as a common gate electrode for the first drain select transistor and the third drain select transistor, and at least one second drain-select-level electrically conductive layer among the electrically conductive layers is formed as a common gate electrode for the second drain select transistor and the fourth drain select transistor; adjusting a threshold voltage for the first drain select transistor by ion implantation such that the first drain select transistor has a higher threshold voltage than the third drain select transistor; forming a bit line electrically connected to the first and the second drain regions; and adjusting a threshold voltage for the fourth drain select transistor by electrical charge injection such that the fourth drain select transistor has a higher threshold voltage than the third drain select transistor.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.09589
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15078555', '15850073', '15704286', '15496359', '15628495']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8317296329473958
- 35 USC 102 Novelty (BERT): 0.5722976867426649
- Combined Prediction Score: 0.8057864383269226
- Mean Citation Score: 380.482124
- Max Citation Score: 493.9241
- Similarity Product: 427.6914885203839

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test