PATENT CLAIM ANALYSIS

Application Number: 15914435
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "506000"]

Abstract:
A method of manufacturing a semiconductor device includes: forming an isolation region comprising a dielectric material on a substrate; forming a recess in the isolation region, wherein a thickness of the isolation region is reduced but greater than zero in the recess; forming a fill layer or layer stack including at least one of a semiconductor or metal on the isolation region and which conforms to the recess; forming a dishing prevention layer or layer stack on the fill layer or layer stack and which conforms to the recess; planarizing the dishing prevention layer or layer stack and the fill layer or layer stack to confine the dishing prevention layer or layer stack and the fill layer or layer stack to the recess, wherein the planarizing stops on the isolation region outside the recess; and forming one or more electrical contacts to the fill layer or layer stack confined to the recess.

Claim (Index 2):
The method of  claim 1 , further comprising:\n forming one or more contact openings which extend through the dishing prevention layer or layer stack and to the fill layer or layer stack in the recess.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.92727
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15448873', '11861614', '13348018', '15822724', '13548237']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9112822202200992
- 35 USC 102 Novelty (BERT): 0.5019112296158643
- Combined Prediction Score: 0.8703451211596757
- Mean Citation Score: 191.568334
- Max Citation Score: 197.64906
- Similarity Product: 116.43553311895607

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test