PATENT CLAIM ANALYSIS

Application Number: 15947411
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "288000"]

Abstract:
A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Claim (Index 13):
A method for fabricating a semiconductor device, comprising:\n forming a first portion of a dielectric material on interfacial layers formed around channels of a first gate stack of a first gate-all-around field-effect transistor (GAA FET) device and on interfacial layers formed around channels of a second gate stack of a second GAA FET device, the first portion of the dielectric material being formed during a first deposition process; performing a first anneal process after forming the first portion of the dielectric material; forming first and second sacrificial layers within the first and second gate stacks, respectively; forming a first metal oxide layer on each of the first and second sacrificial layers; forming a first protective layer on each of the first metal oxide layers; removing the first protective layers and first sacrificial layer along with the first metal oxide layer formed on the first sacrificial layer; forming a second metal oxide layer on the first portion of the dielectric material of the first GAA FET device and on the first metal oxide layer of the second GAA FET device; forming second protective layers on the second metal oxide layers; forming layers including amorphous silicon (a-Si) on the second protective layers; performing a second anneal process after forming the layers including a-Si to achieve a threshold voltage (Vt) shift based on a thickness of the first portion of the dielectric material; removing all layers from the first GAA FET device and the second GAA FET device up to the first portion of the dielectric material; and forming a second portion of the dielectric material on the first portion of the dielectric material during a second deposition process to complete the dielectric material formation on the interfacial layers.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.44681
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15262206', '15367650', '13761476', '15642690', '13971974']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9034251645127882
- 35 USC 102 Novelty (BERT): 0.4969048722406125
- Combined Prediction Score: 0.8627731352855706
- Mean Citation Score: 229.11706400000003
- Max Citation Score: 235.66905
- Similarity Product: 180.07035607087613

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test