PATENT CLAIM ANALYSIS

Application Number: 15914202
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "316000"]

Abstract:
A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.

Claim (Index 17):
The method according to  claim 16 , wherein the semiconductor memory device is a SONOS memory device and the charge trapping layer is a silicon oxynitride or silicon nitride layer forming part of an ONO stack, wherein the method further comprises:\n forming the top oxide layer of the ONO stack by re-oxidizing part of the silicon oxynitride or silicon nitride layer of the stack by a low-temperature plasma oxidation process.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 1.63333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14670800', '10849689', '14595316', '15343387', '15252315']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916078226611885
- 35 USC 102 Novelty (BERT): 0.4926868740453305
- Combined Prediction Score: 0.8737390913552295
- Mean Citation Score: 161.16618200000005
- Max Citation Score: 163.65706
- Similarity Product: 102.15542722091315

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test