PATENT CLAIM ANALYSIS

Application Number: 16161247
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-09
Patent Classification: ["365", "230060"]

Abstract:
A memory device includes a plurality of memory regions including memory cells coupled between a plurality of word lines and a plurality of bit lines, an address decoder suitable for decoding an address to generate a plurality of selection signals corresponding to the bit lines, and outputting the selection signals to a plurality of signal lines, and a plurality of selection circuits corresponding to the memory regions, respectively, and suitable for selecting the bit lines in response to the selection signals received through the signal lines, wherein at least one of the selection circuits is coupled to the signal lines in an arrangement different from remaining selection circuits.

Claim (Index 7):
The memory device of  claim 3 , wherein when the first and second selection transistors included in the remaining selection circuits receive the first and second selection signals, respectively, the first and second selection transistors included in the at least one of the selection circuits receive the first and (K+1) th  selection signals, respectively, where K is a natural number greater than 1 and equal to or less than N/2\u22121.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 2.39583
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10937335', '14859635', '10506868', '12323583', '09469497']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.805896715447421
- 35 USC 102 Novelty (BERT): 0.4833398333371195
- Combined Prediction Score: 0.7736410272363909
- Mean Citation Score: 186.85515400000003
- Max Citation Score: 193.33708
- Similarity Product: 131.3666540698743

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test