PATENT CLAIM ANALYSIS

Application Number: 15965362
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["375", "344000"]

Abstract:
A clock synchronization method, a receiver, a transmitter, and a clock synchronization system, where the method includes obtaining a common reference clock signal, determining B t  according to the common reference clock signal and Mr d (t−1), where B t = mod  [ ∑ n = 0 t - 1   Mr d  ( n ) , 2 p ] , determining that Mr d (t−1) is a target Mr d  when C t  obtained by means of calculation according to Mr d (t−1) is less than or equal to a threshold, where C t =B t −A t , A t  is included in a residual time stamp (RTS) packet received by a receiver last time from the transmitter, and A t = mod  [ ∑ n = 0 t   M d  ( n ) , 2 p ] , performing frequency division on the common reference clock signal using the target Mr d  as a frequency dividing coefficient to obtain a first clock signal, and performing frequency multiplication processing on the first clock signal to obtain a service clock signal. Hence, random phase offset may be avoided.

Claim (Index 7):
The method of  claim 1 , wherein the RTS packet further comprises the P.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 91.0
- Lexical Diversity: 2.42697
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10246408', '13027885', '10246399', '10759101', '10182186']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4885499888908193
- 35 USC 102 Novelty (BERT): 0.5117505697557946
- Combined Prediction Score: 0.4908700469773169
- Mean Citation Score: 171.99452
- Max Citation Score: 177.05733
- Similarity Product: 92.35060358127774

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test