PATENT CLAIM ANALYSIS

Application Number: 16396429
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "401000"]

Abstract:
First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

Claim (Index 19):
The semiconductor device of  claim 16 , wherein the second gate is located between the first gate and the third gate.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 100.0
- Lexical Diversity: 3.53333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15642559', '15079436', '12567227', '14083533', '15627875']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921941667493518
- 35 USC 102 Novelty (BERT): 0.4934295227850498
- Combined Prediction Score: 0.8790904530226711
- Mean Citation Score: 172.784894
- Max Citation Score: 227.48003
- Similarity Product: 179.75431181191087

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test