PATENT CLAIM ANALYSIS

Application Number: 15933291
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["365", "189050"]

Abstract:
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Claim (Index 14):
The device of  claim 13 , wherein the control circuitry includes transistors arranged and switched to provide control signals along the control lines to achieve a timing sequence of Kout and KDLL characterized by: in the first (B 1 ) data path: providing a KDLL 1  (K 1 shot from DLL/PLL circuit) pulse to latch cycle (N\u22121) data from node B 1 _Kout 1  to Q as 1st part of output DDR data, (N\u22121)a, aligned to the rising edge of K at cycle (N+1); as KDLL 1  pulse is completed, providing a Kout 1  pulse to latch cycle (N) data from SA output B 1  to node B 1 _Kout 1 ; in the second (B 2 ) data path: providing a KDLL 2  (Kb 1 shot from DLL/PLL circuit) pulse to latch cycle (N\u22121) data from node B 2 _Kout 2  to Q as 2nd part of output DDR data, (N\u22121)b, aligned to the rising edge of Kb at the 2nd half of cycle (N+1); providing a Kout 22  pulse with the same timing as KDLL 1 , being a half cycle phase shifted before KDLL 2 , to latch cycle (N\u22121) data from node B 2 _Kout 1  to node B 2 _Kout 2 ; and as Kout 22  is completed, providing a Kout 1  pulse to latch cycle (N) data from SA output B 2  to node B 2 _Kout 1 .

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.30769
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15377981', '15159452', '14203416', '15182117', '15182109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8228278344858091
- 35 USC 102 Novelty (BERT): 0.5606256684991457
- Combined Prediction Score: 0.7966076178871428
- Mean Citation Score: 374.1944
- Max Citation Score: 488.11862
- Similarity Product: 318.59194269367816

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test