PATENT CLAIM ANALYSIS

Application Number: 15867180
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "124000"]

Abstract:
The present disclosure illustrates to a serially-connected transistor device including a lead line frame including a carrier board and an electrode pin set, and the carrier board including a first board and a second board, and the electrode pin set including a first pin electrically connected to the first board, and a second pin, a third pin and a fourth pin; and a die unit including a first die and a second die electrically connected to the first board and the second board, respectively, so that two transistors can be electrically connected in series in the serially-connected transistor device to increase reverse voltage. As a result, the serially-connected transistor device of the present disclosure can be produced by automation die bonding and wire bonding manner, so as to achieve the effect of automated production, high yield, low cost, and better product consistency and reliability.

Claim (Index 8):
The serially-connected transistor device according to  claim 7 , wherein a first die and a second die of a die unit are selected from two dies located on the same wafer and adjacent to each other.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.39394
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15823085', '10301200', '15552409', '14457965', '15291284']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9173042585443116
- 35 USC 102 Novelty (BERT): 0.4722623335391274
- Combined Prediction Score: 0.8728000660437931
- Mean Citation Score: 165.15748
- Max Citation Score: 178.3012
- Similarity Product: 139.2808721379757

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test