PATENT CLAIM ANALYSIS

Application Number: 15897472
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["708", "209000"]

Abstract:
Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Claim (Index 1):
A computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in at least one arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n\u00d7P\u00d7Q+m\u00d7R\u00d7S, where n and m are natural numbers, the method comprising the calculation steps for obtaining a result of the operation:\n generating, by a right shifter of the arithmetic unit, a shifted high part (B\u2032 HIGH ) of the addend B by performing a right shift of the high part (B HIGH ) of the addend B by n bits; generating, by a first adder of the arithmetic unit connected to an output of a multiplier and the right shifter; a shifted first intermediate result by generating the multiplication product P\u00d7Q and adding the shifted high part B\u2032 HIGH ; generating, by a left shifter of the arithmetic unit, a first intermediate result by performing a left shift of the shifted first intermediate result by n bits; generating, by the right shifter of the arithmetic unit, shifted low part (B\u2032 LOW ) of the addend B by performing a right shift of the low part (B LOW ) of the addend B by m bits; generating, by the left shifter, a shifted second intermediate result by generating the multiplication product R\u00d7S and adding the shifted low part B\u2032 LOW ; generating, by a second adder connected to an output of the left shifter; a second intermediate result by performing a left shift of the shifted second intermediate result by m bits; determining, by the multiplier of the arithmetic unit, the accumulated sum as the result of the multiply-add operations by adding the first intermediate result to the second intermediate result; generating the shifted first intermediate result and the shifted second intermediate result in parallel steps; and wherein the natural numbers n and m being in the range of {1, 2}; wherein the addend B is initialized with zero for starting the multiply-add operations; wherein a guard bit logic path of the arithmetic unit is used for rounding an output of the first adder, and when m equals to 2, the shifted second intermediate result reuses part of the guard bit logic path; and wherein the preceding steps are performed on at least two binary arithmetic units.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.98214
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15649406', '15856255', '15406910', '15810033', '15646543']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4301317882840675
- 35 USC 102 Novelty (BERT): 0.5491739594635319
- Combined Prediction Score: 0.442036005402014
- Mean Citation Score: 314.59034799999995
- Max Citation Score: 382.06284
- Similarity Product: 376.7192896029925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test