PATENT CLAIM ANALYSIS

Application Number: 16180181
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-07
Patent Classification: ["712", "223000"]

Abstract:
Hardware units and methods for performing matrix multiplication via a multi-stage pipeline wherein the storage elements associated with one or more stages of the pipeline are clock gated based on the data elements and/or portions thereof that known to have a zero value (or can be treated as having a zero value). In some cases, the storage elements may be clock gated on a per data element basis based on whether the data element has a zero value (or can be treated as having a zero value). In other cases, the storage elements may be clock gated on a partial element basis based on the bit width of the data elements. For example, if bit width of the data elements is less than a maximum bit width for the data elements then a portion of the bits related to that data element can be treated as having a zero value and a portion of the storage elements associated with that data element may not be clocked. In yet other cases the storage elements may be clock gated on both a per element and a partial element basis.

Claim (Index 16):
A method of clock gating storage elements in a hardware unit for performing matrix multiplication, the hardware unit comprising a plurality of multipliers each configured to multiply data elements to output a multiplication data element, and a plurality of adders that form an adder tree to produce a sum of the multiplication data elements by adding data elements from a multiplier or an adder, wherein at least one multiplier and/or at least one adder is preceded by a storage element for each bit of each input data element, the method comprising;\n receiving information indicating whether each data element input to the at least one multiplier and/or the at least one adder can be treated as having a zero value, and/or, indicating whether a portion of each data element input to the at least one multiplier and/or the at least one adder can be treated as having a zero value; and in response to receiving information that indicates that a data element or portion of a data element can be treated as having a zero value, clock gating all or a portion of the storage elements corresponding to that data element.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 98.0
- Lexical Diversity: 2.65333
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13664689', '11749224', '13785528', '10435976', '12417013']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.598744818837959
- 35 USC 102 Novelty (BERT): 0.4764434683305722
- Combined Prediction Score: 0.5865146837872204
- Mean Citation Score: 210.794676
- Max Citation Score: 213.49867000000003
- Similarity Product: 166.5693981701148

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test