PATENT CLAIM ANALYSIS

Application Number: 16050240
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["707", "705000"]

Abstract:
In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Claim (Index 40):
An apparatus, comprising:\n a computer platform with an operating system (OS) to incorporate a performance and power management (PPM) interface; physical memory available to the OS, the OS to manage power states of the memory through the PPM interface; and firmware to build a first table and a second table for the PPM interface, wherein each of the first table and the second table is to store a same Memory Power Node ID (Identification) associated with a memory power node; wherein the memory power node comprises a first memory address range and a second memory address range, such that the first and second memory address ranges are non-contiguous; wherein the first table is to store information to identify the first memory address range; and wherein the second table is to store information to identify the second memory address range.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.31579
- Patent Class: 707.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13977635', '13683748', '13977625', '13977593', '15396726']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.1861615298613039
- 35 USC 102 Novelty (BERT): 0.5133602839803825
- Combined Prediction Score: 0.2188814052732118
- Mean Citation Score: 240.312764
- Max Citation Score: 313.29358
- Similarity Product: 264.82417462832217

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test