PATENT CLAIM ANALYSIS

Application Number: 16021306
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "185120"]

Abstract:
Memory devices having selectively electrically connected data lines with no intervening memory cells.

Claim (Index 13):
The memory device of  claim 12 , wherein the first transistor selectively electrically connects the plurality of page buffers in parallel to the first data line and the second transistor selectively electrically connects the plurality of page buffers in parallel to the second data line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15019175', '16021250', '15191786', '15692565', '11228189']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.809717214849099
- 35 USC 102 Novelty (BERT): 0.5073009529088656
- Combined Prediction Score: 0.7794755886550757
- Mean Citation Score: 234.661602
- Max Citation Score: 305.80945
- Similarity Product: 244.89558746463064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test