PATENT CLAIM ANALYSIS

Application Number: 16255269
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["333", "032000"]

Abstract:
In one embodiment, an impedance matching network includes at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC. Each switch includes a first terminal operably coupled to the corresponding discrete capacitor, a second terminal, and a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor. A tuning inductor is coupled parallel to the switching circuit. A value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit.

Claim (Index 30):
A method of fabricating a semiconductor, the method comprising:\n placing a substrate in a plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate; energizing plasma within the plasma chamber by coupling RF power from an RF source into the plasma chamber to perform a deposition or etching; and while energizing the plasma, carrying out an impedance match by an impedance matching network coupled between a plasma chamber and an RF source, wherein the impedance matching network comprises:\n an RF input configured to operably couple to the RF source; \n an RF output configured to operably couple to the plasma chamber; and \n at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises:\n a first terminal operably coupled to the corresponding discrete capacitor; \n a second terminal; \n a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor; and \n a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit; \n \n wherein for each switch, switching the switching transistor ON and OFF causes the corresponding discrete capacitor to be switched in and out.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 99.0
- Lexical Diversity: 2.06897
- Patent Class: 333.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16211961', '14669568', '15637271', '14936978', '15667951']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8934895528675993
- 35 USC 102 Novelty (BERT): 0.5458408000146067
- Combined Prediction Score: 0.8587246775823001
- Mean Citation Score: 356.3085680000001
- Max Citation Score: 406.35043
- Similarity Product: 394.3867282988739

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test