PATENT CLAIM ANALYSIS

Application Number: 16042927
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["326", "101000"]

Abstract:
A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.

Claim (Index 1):
A semiconductor structure, comprising:\n a vertical transport logic circuit cell comprising a first logic gate and at least a second logic gate positioned in a substantially side-by-side configuration, the first logic gate comprising at least one input terminal and at least one output terminal; the second logic gate comprising at least one input terminal and at least one output terminal; wherein one of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 3.27027
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15046863', '15464696', '10648474', '12338632', '11090116']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6530574656365166
- 35 USC 102 Novelty (BERT): 0.471873530395913
- Combined Prediction Score: 0.6349390721124563
- Mean Citation Score: 181.869966
- Max Citation Score: 208.79659
- Similarity Product: 166.0872417010808

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test