PATENT CLAIM ANALYSIS

Application Number: 15889017
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "741000"]

Abstract:
A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Claim (Index 29):
A process for forming an integrated circuit device, the process operative on an integrated circuit chip having electrically conductive lands on a first surface, the first surface coated with a catalytic adhesive thereby forming a second surface above the first surface, said second surface having a reduced density of catalytic particles in a region extending from said second surface to an exclusion depth below said second surface compared to other regions of the catalytic adhesive, the process comprising:\n applying a catalytic adhesive to an integrated circuit chip; curing the catalytic adhesive; forming apertures into the catalytic adhesive in locations corresponding to integrated circuit lands, said apertures thereby exposing said catalytic particles of said catalytic adhesive and said integrated circuit lands; forming channels in the catalytic laminate to a depth below the exclusion depth and leading to said apertures and also to optional connection regions on said second surface; performing an electroless plating operation until said channels and apertures are in electrical contact with said integrated circuit lands and said optional connection regions.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 88.0
- Lexical Diversity: 2.08929
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15635201', '15878398', '15603326', '15240133', '09957401']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9116055567084816
- 35 USC 102 Novelty (BERT): 0.515772979264123
- Combined Prediction Score: 0.8720222989640458
- Mean Citation Score: 267.567402
- Max Citation Score: 295.43475
- Similarity Product: 222.6730328049213

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test