PATENT CLAIM ANALYSIS

Application Number: 15985136
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-02
Patent Classification: ["375", "316000"]

Abstract:
In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.

Claim (Index 15):
The method of  claim 10  further comprising:\n responsive to applying the first jitter signal at the first frequency and the first amplitude to the DCO control signal, measuring, based on the DCO clock signal, vertical margin of the receiver component; \n responsive to determining the vertical margin is greater than zero, generating a second jitter signal with a second amplitude that is greater than the first amplitude; \n responsive to determining the vertical margin is less than zero and the first frequency is not greater than a maximum frequency, generating a third jitter signal with a second frequency that is greater than the first frequency; and \n responsive to determining the vertical margin is less than zero and the first frequency is greater than the maximum frequency, plotting a Jitter Tolerance Eye (JTE) for on-chip jitter tolerance testing.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 93.0
- Lexical Diversity: 2.16071
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15979219', '14070249', '13621783', '13865843', '12529320']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4588424731257176
- 35 USC 102 Novelty (BERT): 0.4789198474166843
- Combined Prediction Score: 0.4608502105548143
- Mean Citation Score: 167.467376
- Max Citation Score: 198.71089
- Similarity Product: 151.30306404581071

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test