PATENT CLAIM ANALYSIS

Application Number: 15918753
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "013000"]

Abstract:
According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first metal pillar, a second metal pillar, and an insulating layer. The semiconductor layer includes a first surface, a second surface, and a light emitting layer. The first metal pillar is electrically connected to the second surface. The first metal pillar includes first and second metal layers. The first metal layer is provided between the second surface and at least a part of the second metal layer. The second metal pillar is arranged side by side with the first metal pillar, and electrically connected to the second surface. The second metal pillar includes third and fourth metal layers. The third metal layer is provided between the second surface and at least a part of the fourth metal layer. The insulating layer is provided between the first and second metal pillars.

Claim (Index 2):
A method for manufacturing a semiconductor light emitting device, comprising:\n forming a semiconductor member on a substrate, the semiconductor member including a first semiconductor layer having a first conductivity type, a light emitting layer, and a second semiconductor layer having a second conductivity type, the second semiconductor layer and a part of the first semiconductor layer being exposed on an upper surface of the semiconductor member; forming a first metal layer on the part of the first semiconductor layer and forming a second metal layer on the second semiconductor layer, the first metal layer being connected to the part of the first semiconductor layer, and the second metal layer being connected to the second semiconductor layer; forming a third metal layer on the first metal layer and forming a fourth metal layer on the second metal layer, the third metal layer being connected to the first metal layer, and the fourth metal layer being connected to the second metal layer; forming a first insulating layer covering a first pillar and a second pillar, the first pillar including the first metal layer and the third metal layer, and the second pillar including the second metal layer and the fourth metal layer; exposing a first surface of the semiconductor member by removing the substrate; and exposing the third metal layer and the fourth metal layer by grinding the first insulating layer.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 4.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15597226', '14842162', '13707001', '13153554', '13826935']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9207005882619308
- 35 USC 102 Novelty (BERT): 0.4862981441998899
- Combined Prediction Score: 0.8772603438557267
- Mean Citation Score: 216.0307
- Max Citation Score: 241.92091
- Similarity Product: 203.8235652327627

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test