PATENT CLAIM ANALYSIS

Application Number: 16201266
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["438", "268000"]

Abstract:
A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Claim (Index 6):
The device according to  claim 1 , wherein a height of the gate structure is in a range of 150 \u212b to 200 \u212b.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.51111
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15830742', '15363273', '15725867', '15356439', '15455603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8402403070454396
- 35 USC 102 Novelty (BERT): 0.5200065272106253
- Combined Prediction Score: 0.8082169290619583
- Mean Citation Score: 190.907856
- Max Citation Score: 226.88423
- Similarity Product: 127.98909216363607

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test