PATENT CLAIM ANALYSIS

Application Number: 16012715
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "230060"]

Abstract:
Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.

Claim (Index 2):
The apparatus of  claim 1 , wherein the shifter further comprises a first multiplexer, the first multiplexer comprising a first input end, a second input end, and a first output end, and the first multiplexer being inserted between the third register and the fourth register such that the first input end of the first multiplexer is coupled to the output node of the first register, the second input end of the first multiplexer is coupled to the output node of the third register and the first output end of the first multiplexer is coupled to the input node of the fourth register.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 1.11111
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11594807', '15063229', '12585428', '14698550', '11896788']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7843839225635261
- 35 USC 102 Novelty (BERT): 0.4736217733188184
- Combined Prediction Score: 0.7533077076390553
- Mean Citation Score: 158.75661200000005
- Max Citation Score: 165.16328
- Similarity Product: 112.43358574483872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test