PATENT CLAIM ANALYSIS

Application Number: 16040862
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-06
Patent Classification: ["257", "784000"]

Abstract:
A chip package structure includes a substrate, a die, a plurality of warpage retainers, and an encapsulant. The substrate has a surface, on which the die is provided. The warpage retainers are provided at at least one corner of the substrate. The encapsulant covers the surface of the substrate, the die and the warpage retainers.

Claim (Index 11):
The chip package structure according to  claim 1 , wherein a ratio of a total area of the plurality of warpage retainers to an area of the surface is greater than 4%.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 95.0
- Lexical Diversity: 2.06452
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15611766', '13647375', '14598053', '13937040', '11766523']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9168219279509476
- 35 USC 102 Novelty (BERT): 0.4921951731968513
- Combined Prediction Score: 0.8743592524755379
- Mean Citation Score: 149.02187199999997
- Max Citation Score: 151.39825
- Similarity Product: 92.28110331603884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test