PATENT CLAIM ANALYSIS

Application Number: 15913414
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "288000"]

Abstract:
A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Claim (Index 12):
The semiconductor device of  claim 10 , wherein a bottom surface of the first semiconductor alloy layer is non-coplanar with a bottom surface of the second semiconductor alloy layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 2.12121
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15613778', '11714416', '10710012', '10726472', '10738716']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9242932208240972
- 35 USC 102 Novelty (BERT): 0.4937043539739196
- Combined Prediction Score: 0.8812343341390794
- Mean Citation Score: 214.06667400000003
- Max Citation Score: 226.35646
- Similarity Product: 164.41944060046558

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test