PATENT CLAIM ANALYSIS

Application Number: 15871452
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["714", "033000"]

Abstract:
Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

Claim (Index 15):
A computer program product for testing a data coherency algorithm of a multi-processor environment, wherein a simulated multi-processor environment containing a private cache hierarchy and simulation drivers for other components of the multi-processor environment is provided, the computer program product comprising:\n a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:\n implementing a reference model, the reference model operating on a cache line and keeping a set of timestamps for the cache line, the set of timestamps comprising a construction date representing a first global timestamp based on new data arriving at the private cache hierarchy, and an expiration date representing a second global timestamp based on the private cache hierarchy being hit by a cross-invalidation; \n implementing a core observed timestamp; \n implementing interface events that monitor at least one selected from a group consisting of:\n a fetch return from the simulated multi-processor environment to update the construction date; \n a fetch return from an L1 cache to a processor core to update the core observed timestamp; \n a cross-invalidate from the simulated multi-processor environment to update the expiration date; \n a transaction start instruction being executed by the processor core to update a transactional execution flag and clear a transactional footprint, the transactional footprint maintaining one or more addresses of one or more cache lines used by the processor core; and \n a transaction end instruction being executed by the processor core to perform checking; and \n \n reporting an error based on detecting a transaction end event and finding a cache line in the transactional footprint with an expiration date that is older than or equal to a core observed time.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 1.91139
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15010088', '15197534', '12328242', '14829773', '14037958']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2725082854985203
- 35 USC 102 Novelty (BERT): 0.5486776848549563
- Combined Prediction Score: 0.300125225434164
- Mean Citation Score: 286.594624
- Max Citation Score: 408.71185
- Similarity Product: 339.510226417321

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test