PATENT CLAIM ANALYSIS

Application Number: 16051886
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "324000"]

Abstract:
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.

Claim (Index 10):
The method of  claim 7 , wherein forming the slots comprises dividing at least some of the individual access lines into four distinct portions.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.83636
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14942573', '15666064', '14877997', '15068329', '14679488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.915822893054352
- 35 USC 102 Novelty (BERT): 0.5326376134725203
- Combined Prediction Score: 0.8775043650961689
- Mean Citation Score: 271.167746
- Max Citation Score: 336.53683
- Similarity Product: 239.54161297959928

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test