PATENT CLAIM ANALYSIS

Application Number: 15991871
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["341", "161000"]

Abstract:
The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

Claim (Index 6):
The ADC of  claim 1 , wherein the sequence instructions includes one or more bit decision (BIT) instructions to store one or more results of the comparator as one or more bits of the digital value.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.35938
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15793839', '15832503', '15825838', '14949423', '15278519']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.602130975460919
- 35 USC 102 Novelty (BERT): 0.5048856351917927
- Combined Prediction Score: 0.5924064414340064
- Mean Citation Score: 216.209852
- Max Citation Score: 297.1654
- Similarity Product: 295.9335530670046

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test