PATENT CLAIM ANALYSIS

Application Number: 15942614
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["375", "295000"]

Abstract:
The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

Claim (Index 6):
The circuit of  claim 2 , wherein the cyclic filter is a tap delay line, and configured to perform cyclic convolution of the error signal and filter coefficients associated with the cyclic filter.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 3.18182
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15426464', '13710120', '13443398', '12253635', '13478526']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4517900118421357
- 35 USC 102 Novelty (BERT): 0.5548480634855508
- Combined Prediction Score: 0.4620958170064771
- Mean Citation Score: 235.071714
- Max Citation Score: 402.86295
- Similarity Product: 342.5871010743677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test