PATENT CLAIM ANALYSIS

Application Number: 15917168
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "329000"]

Abstract:
An SGT is formed in Si pillars. The SGT includes WSi 2  layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

Claim (Index 1):
A semiconductor device including an SGT, comprising:\n a first semiconductor pillar that stands on a substrate in a direction vertical to a plane of the substrate; a first gate insulating layer that surrounds the first semiconductor pillar; a first gate conductor layer that surrounds the first gate insulating layer; a first impurity region that is positioned below the gate conductor layer in the vertical direction and is connected to a portion inside the first semiconductor pillar or to a side surface of the first semiconductor pillar; a first conductive layer that surrounds an entire periphery of the first impurity region in plan view; a second conductive layer that is partly connected to a periphery of the first conductive layer in plan view and extends in a direction horizontal to the plane of the substrate; a third conductive layer that surrounds an entire periphery of the first gate conductor layer in plan view; and a fourth conductive layer that is partly connected to a periphery of the third conductive layer in plan view, extends in a direction horizontal to the plane of the substrate, and partly overlaps the second conductive layer or does not overlap the second conductive layer in plan view, wherein at least one of the first conductive layer and the third conductive layer has an equal width in plan view.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15655168', '14806053', '15584466', '14689640', '15360488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92372213973217
- 35 USC 102 Novelty (BERT): 0.546373782368544
- Combined Prediction Score: 0.8859873039958075
- Mean Citation Score: 379.74567
- Max Citation Score: 392.4889
- Similarity Product: 334.68286279191966

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test