PATENT CLAIM ANALYSIS

Application Number: 15909987
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["365", "227000"]

Abstract:
In a semiconductor device according to related art, there is a problem that it is impossible to increase an operation speed when a power supply noise is suppressed. According to one embodiment, a semiconductor device includes a first power supply line, a second power supply line that is branched off from a branching point on the first power supply line, an internal circuit configured to receive power from the second power supply line, and a clock generation circuit configured to supply an operation clock to the internal circuit, in which, when a voltage difference between a determination threshold voltage VCC 0  acquired from a position on the first power supply line that is closer to a power supply source than the branching point is and a monitor voltage VCC 1  acquired from the second power supply line exceeds a predetermined voltage, the semiconductor device changes a timing of an edge of the operation clock until that the voltage difference between the monitor voltage VCC 1  and the determination threshold voltage VCC 0  returns to a predetermined recovery possible voltage.

Claim (Index 6):
The semiconductor device according to  claim 1 , wherein\n the internal circuit comprises a first internal circuit and a second internal circuit that operate in operation clocks different from each other, the clock generation circuit outputs a first operation clock to be supplied to the first internal circuit and a second operation clock to be supplied to the second internal circuit, and the clock generation circuit makes the phase of the first operation clock different from the phase of the second operation clock to output the first operation clock and the second operation clock in a period in which the power supply fluctuation detection signal is in the enable state, and makes the phase of the first operation clock match the phase of the second operation clock to output the first operation clock and the second operation clock in a period in which the power supply fluctuation detection signal is in the disable state.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.625
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13303153', '11036393', '13064237', '11313963', '14918905']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8098078093931321
- 35 USC 102 Novelty (BERT): 0.4648768223388221
- Combined Prediction Score: 0.7753147106877012
- Mean Citation Score: 186.59851200000003
- Max Citation Score: 191.96275
- Similarity Product: 155.25688289532062

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test