PATENT CLAIM ANALYSIS

Application Number: 15950193
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["365", "148000"]

Abstract:
A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.

Claim (Index 1):
A nonvolatile memory, comprising:\n a first memory unit comprising a first bipolar-variable-resistance transistor and a first control transistor which are electrically connected to each other, wherein the first bipolar-variable-resistance transistor is electrically connected to a word-line selecting driving circuit, the first control transistor is electrically connected to a control-line selecting driving circuit, and the first bipolar-variable-resistance transistor is configured to receive a first current flow from a bit-line selecting driving circuit through the first control transistor when the first control transistor is driven by the control-line selecting driving circuit; a second memory unit comprising a second bipolar-variable-resistance transistor and a second control transistor which are electrically connected to each other, wherein the second bipolar-variable-resistance transistor is electrically connected to the word-line selecting driving circuit, the second control transistor is electrically connected to the control-line selecting driving circuit, and the second bipolar-variable-resistance transistor is configured to receive a second current flow from the bit-line selecting driving circuit through the second control transistor when the second control transistor is driven by the control-line selecting driving circuit; and an isolation transistor coupled between the first and second memory units and configured to electrically isolate the first and second memory units from each other.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 91.0
- Lexical Diversity: 2.21154
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12273225', '11238381', '14807899', '13440633', '14119936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8098963141697171
- 35 USC 102 Novelty (BERT): 0.4730477808959905
- Combined Prediction Score: 0.7762114608423445
- Mean Citation Score: 216.167218
- Max Citation Score: 223.64581
- Similarity Product: 180.9149203135592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test