PATENT CLAIM ANALYSIS

Application Number: 15884725
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["257", "295000"]

Abstract:
A memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.

Claim (Index 11):
A memory array comprising:\n a plurality of bit lines disposed in parallel along a first axis; a plurality of source lines disposed in parallel along the first axis; a plurality of word lines disposed in parallel substantially perpendicular to the first axis; and a plurality of memory elements, each memory element comprising a vertical ferroelectric transistor disposed between a corresponding one of the bit lines and a corresponding one of the source lines, and each memory element coupled to a corresponding one of the word lines wherein:\n each vertical ferroelectric transistor comprises two separate and distinct gate electrodes; and \n each vertical ferroelectric transistor comprises a long axis in a first direction, and the gate electrodes each comprise a long axis in a second direction substantially perpendicular to the first direction.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 86.0
- Lexical Diversity: 1.25
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14075010', '13897037', '10453441', '14542213', '12987302']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9130339435243188
- 35 USC 102 Novelty (BERT): 0.4647149479057029
- Combined Prediction Score: 0.8682020439624571
- Mean Citation Score: 158.940444
- Max Citation Score: 172.31046
- Similarity Product: 138.72311912979126

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test