PATENT CLAIM ANALYSIS

Application Number: 15888260
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["333", "014000"]

Abstract:
Nonlinear bandwidth compression circuitry is provided. In examples discussed herein, nonlinear bandwidth compression circuitry can be configured to modify predefined amplitude(s) of a predefined voltage waveform to generate modified amplitude(s) of a modified voltage waveform that is never less than the predefined amplitude(s) of the predefined voltage waveform. Thus, by providing the nonlinear bandwidth compression circuitry in an envelope tracking (ET) system to perform bandwidth compression, signal distortion(s) resulted from the bandwidth compression can be corrected (e.g., via digital pre-distortion). As such, the ET system can amplify a radio frequency (RF) signal having a signal modulation bandwidth exceeding a voltage modulation bandwidth limitation of the ET system, without degrading spectral performance of the RF signal.

Claim (Index 8):
The nonlinear bandwidth compression circuitry of  claim 7  wherein:\n the one or more input interfaces comprises a first input interface, one or more intermediate input interfaces succeeding to the first input interface, and a last input interface succeeding to the one or more intermediate input interfaces; \n the one or more delay circuits comprise a first delay circuit, one or more intermediate delay circuits succeeding to the first delay circuit, and\n a last delay circuit succeeding to the one or more intermediate delay circuits, wherein: \n a respective input end of the first delay circuit is coupled to the input node; \n a respective input end of each of the one or more intermediate delay circuits and the last delay circuit is coupled to a respective output end of a preceding delay circuit among the one or more delay circuits; and \n a respective output end of the last delay circuit is coupled to the reference node; \n \n the one or more combiners comprise a first combiner, one or more intermediate combiners succeeding to the first combiner, and a last combiner succeeding to the one or more intermediate combiners, wherein:\n the first combiner is coupled between the respective input end of the first delay circuit and the first input interface; \n the one or more intermediate combiners are coupled between respective input nodes of the one or more intermediate delay circuits and the one or more intermediate input interfaces, respectively; and \n the last combiner is coupled between a respective input interface of the last delay circuit and the last input interface.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 2.13433
- Patent Class: 333.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15888300', '15792909', '15728202', '13408819', '15459449']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8405308466912116
- 35 USC 102 Novelty (BERT): 0.5611001743904774
- Combined Prediction Score: 0.8125877794611382
- Mean Citation Score: 257.91555800000003
- Max Citation Score: 452.32242
- Similarity Product: 321.1024016020989

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test