PATENT CLAIM ANALYSIS

Application Number: 16167903
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "231000"]

Abstract:
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Claim (Index 7):
An integrated circuit having a NMOS transistor and a PMOS transistor, comprising:\n a NMOS gate of the NMOS transistor that crosses opposite NMOS edges of a NMOS active area and extends past a first of the opposite NMOS edges nearest the PMOS transistor a first distance; and a PMOS gate of the PMOS transistor that crosses opposite edges of a PMOS active area and extends past a first edge of the opposite PMOS edges nearest the NMOS transistor a second distance, wherein the first distance is greater than the second distance.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 1.66667
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14576659', '15409842', '14584348', '11849798', '13288664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.863361439404757
- 35 USC 102 Novelty (BERT): 0.5116251579779592
- Combined Prediction Score: 0.8281878112620772
- Mean Citation Score: 255.28350200000008
- Max Citation Score: 318.36716
- Similarity Product: 279.9100331924105

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test