PATENT CLAIM ANALYSIS

Application Number: 16112402
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "103000"]

Abstract:
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Claim (Index 4):
The memory array of  claim 1 , wherein the memory cells are read only memory (ROM) cells.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 96.0
- Lexical Diversity: 3.05405
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15709498', '15050678', '12820342', '11013429', '11219827']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8209886940570007
- 35 USC 102 Novelty (BERT): 0.4777411293639206
- Combined Prediction Score: 0.7866639375876927
- Mean Citation Score: 202.704468
- Max Citation Score: 263.63324
- Similarity Product: 260.5978747500181

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test