PATENT CLAIM ANALYSIS

Application Number: 16010694
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "401000"]

Abstract:
A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

Claim (Index 17):
A method of fabricating a semiconductor device for use with one or more field-effect transistor (FinFET) devices, the method comprising:\n forming a shallow trench isolation (STI) structure within a semiconductor substrate from a shallow trench of first insulating material, the STI structure comprising,\n a first STI layer disposed in the substrate, \n a second STI layer disposed above the first STI layer and within the substrate, the second STI layer comprising, a first lower layer disposed above the first STI layer, a first vertical layer disposed along a first vertical sidewall of the substrate, and a second vertical layer disposed along a second vertical sidewall of the substrate, \n a third STI layer disposed above the first lower layer of the second STI layer, wherein the third STI layer is disposed within the substrate and extends above a surface of the substrate, and \n a fourth STI layer disposed above the third STI layer and located above the surface of the substrate; and \n forming a field effect transistor (FET) disposed on the semiconductor substrate and having a first gate structure, an epitaxial first source/drain (S/D) region, and an epitaxial second S/D region, wherein the epitaxial first S/D region is disposed adjacent to the STI structure.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 94.0
- Lexical Diversity: 2.30986
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15665183', '15076762', '14512282', '10733378', '15480340']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9194299898323564
- 35 USC 102 Novelty (BERT): 0.5150692114507973
- Combined Prediction Score: 0.8789939119942005
- Mean Citation Score: 237.786226
- Max Citation Score: 328.1339
- Similarity Product: 289.773317165786

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test