PATENT CLAIM ANALYSIS

Application Number: 16042170
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.

Claim (Index 13):
The integrated circuit of  claim 12  wherein:\n the output power-down circuitry includes a latch or flip/flop.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.75
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15975037', '15978235', '15239958', '16009656', '15996430']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7145543642615158
- 35 USC 102 Novelty (BERT): 0.5383989736489047
- Combined Prediction Score: 0.6969388252002546
- Mean Citation Score: 364.025478
- Max Citation Score: 387.6765
- Similarity Product: 251.00850962492825

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test