PATENT CLAIM ANALYSIS

Application Number: 15947075
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "154000"]

Abstract:
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Claim (Index 8):
The multi-port memory circuit according to  claim 5 , further comprising:\n first and second word drivers that drive the first and second word lines respectively; first and second clock generators; first and second clock selectors; and first, second and third clock terminals, wherein the first clock selector selects one clock signal from a first clock signal that is input through the first clock terminal and a third clock signal that is input through the third clock terminal and supplies the clock signal so selected to the first clock generator, wherein the second clock selector selects one clock signal from a second clock signal that is input through the second clock terminal and the third clock signal and supplies the clock signal so selected to the second clock generator, wherein the first clock generator supplies a first word line activation pulse that gives a timing that the first word line is activated to the first word driver, wherein the second clock generator supplies a second word line activation pulse that gives a timing that the second word line is activated to the second word driver, wherein in the first operation mode, the first clock selector selects and supplies the first clock signal to the first clock generator, and the second clock selector selects and supplies the second clock signal to the second clock generator, wherein in the second operation mode, the first clock selector selects and supplies the third clock signal to the first generator and the second clock selector selects and supplies the third clock signal to the second clock generator respectively, and the second clock generator generates a second word line activation pulse that gives a timing that the second word line is activated earlier than a timing that the first clock generator activates the first word line and that the second word line is deactivated later than a timing that the first clock generator deactivates the first word line and supplies the pulse so generated to the second word driver.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.40426
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15281947', '15606562', '15885449', '14504994', '13750328']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8192299941807852
- 35 USC 102 Novelty (BERT): 0.5822306132091754
- Combined Prediction Score: 0.7955300560836243
- Mean Citation Score: 330.520802
- Max Citation Score: 501.18726
- Similarity Product: 453.7990418409992

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test