PATENT CLAIM ANALYSIS

Application Number: 15781253
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["349", "043000"]

Abstract:
A plurality of TFTs provided in a peripheral circuit region of an active matrix substrate of an embodiment includes a TFT ( 10 A) in which, when viewed in a direction perpendicular to a substrate ( 11 A), the length in the channel width direction of an oxide semiconductor layer ( 14 A), WAos, is smaller than the length in the channel width direction of a gate electrode ( 12 A), WAg, the length in the channel width direction of a source electrode region ( 15 AR) in which the source electrode ( 15 A) is in contact with the oxide semiconductor layer ( 14 A), WAs, is smaller than the length in the channel width direction of the oxide semiconductor layer ( 14 A), WAos, and the drain electrode ( 16 A) is in contact with the oxide semiconductor layer ( 14 A) in a plurality of drain electrode regions ( 16 AR) arranged in the channel width direction, and the overall length in the channel width direction of the plurality of drain electrode regions ( 16 AR), WAd, is smaller than the length in the channel width direction of the oxide semiconductor layer ( 14 A), WAos.

Claim (Index 1):
An active matrix substrate including an active region and a peripheral circuit region provided outside the active region,\n the active matrix substrate comprising a substrate and a plurality of TFTs supported by the substrate, wherein the plurality of TFTs include a plurality of first TFTs provided in the active region and a plurality of second TFTs provided in the peripheral circuit region,\n the plurality of second TFTs include a third TFT, \n the third TFT includes a gate electrode, an oxide semiconductor layer, a gate insulating layer interposed between the gate electrode and the oxide semiconductor layer, and source and drain electrodes connected with the oxide semiconductor layer, \n when viewed in a direction perpendicular to the substrate, \n where a direction in which a source-drain current flows through the oxide semiconductor layer is referred to as a channel length direction, and a direction which is generally perpendicular to the channel length direction is referred to as a channel width direction, \n a length in the channel width direction of the oxide semiconductor layer is smaller than a length in the channel width direction of the gate electrode, \n a length in the channel width direction of a source electrode region in which the source electrode is in contact with the oxide semiconductor layer is smaller than the length in the channel width direction of the oxide semiconductor layer, and \n the drain electrode is in contact with the oxide semiconductor layer in a plurality of drain electrode regions arranged in the channel width direction, and an overall length in the channel width direction of the plurality of drain electrode regions is smaller than the length in the channel width direction of the oxide semiconductor layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 3.91379
- Patent Class: 349.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15117507', '15482959', '16081455', '14370804', '14438687']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8572087527131185
- 35 USC 102 Novelty (BERT): 0.520190513915413
- Combined Prediction Score: 0.823506928833348
- Mean Citation Score: 308.6735480000001
- Max Citation Score: 342.65692
- Similarity Product: 273.0764642014122

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test