PATENT CLAIM ANALYSIS

Application Number: 15972216
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-10
Patent Classification: ["257", "296000"]

Abstract:
The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.

Claim (Index 16):
The method of  claim 8 , wherein the etching step comprises soaking in a dilute hydrofluoric acid (DHF) solution.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.08824
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14792979', '13796449', '12944896', '10708530', '12330282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8967148729201826
- 35 USC 102 Novelty (BERT): 0.506124659130838
- Combined Prediction Score: 0.8576558515412481
- Mean Citation Score: 141.0078
- Max Citation Score: 151.8289
- Similarity Product: 87.08495663918256

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test