PATENT CLAIM ANALYSIS

Application Number: 16023702
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-08
Patent Classification: ["257", "043000"]

Abstract:
A manufacturing method for a thin-film transistor array substrate is disclosed. The method includes: providing a base substrate; depositing a first metal layer on the base substrate, and patterning to form a gate electrode and a first storage electrode; depositing a gate insulation layer, wherein the gate insulation layer covers the gate electrode and the first storage electrode; depositing a metal oxide semiconductor layer, and patterning to form a metal oxide active layer; depositing a second insulation layer, and patterning to form an etching barrier layer; depositing a second metal layer, and pattering to form a source electrode, a drain electrode and a second storage electrode, wherein the first storage electrode and the second storage electrode are two electrodes of a storage capacitor; depositing a third insulation layer, and patterning to form a passivation layer; and depositing a third metal layer, and patterning to form a pixel electrode.

Claim (Index 9):
A thin-film transistor array substrate, comprising:\n a base substrate; a gate electrode formed on the base substrate; a first storage electrode formed on the base substrate; a gate insulation layer covering gate electrode and the first storage electrode; a metal oxide active layer formed on the gate insulation layer, and the metal oxide active layer is disposed corresponding to the metal oxide active layer; an etching barrier layer formed on the metal oxide active layer and the gate insulation layer, and a portion of the etching barrier layer corresponding to the first storage electrode is provided with a storage through hole; a source electrode and a drain electrode electrically connected to the metal oxide active layer through the etching barrier layer; a second storage electrode located in the storage through hole, wherein the first storage capacitor, the gate insulation layer and the second storage electrode form a storage capacitor; a passivation layer covers the etching barrier layer, the source electrode, the drain electrode and the second storage electrode; and a pixel electrode formed on the passivation layer, and the pixel electrode is electrically connected to the drain electrode.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 3.15094
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14769891', '14771526', '14436995', '15121928', '13100883']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9255398255110426
- 35 USC 102 Novelty (BERT): 0.5090510872230183
- Combined Prediction Score: 0.8838909516822402
- Mean Citation Score: 288.570784
- Max Citation Score: 304.3339
- Similarity Product: 244.46696652405265

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test