PATENT CLAIM ANALYSIS

Application Number: 16102748
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "296000"]

Abstract:
A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

Claim (Index 11):
The layout structure of semiconductor structure of  claim 5 , wherein said first tooth portion and said second tooth portion are in pair and have same length in one said active regions, and adjacent said pairs of said first tooth portion and said second tooth portion have different lengths.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 96.0
- Lexical Diversity: 2.23529
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15465580', '15479271', '12494243', '13595497', '15479290']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9229081062979316
- 35 USC 102 Novelty (BERT): 0.522657490308235
- Combined Prediction Score: 0.882883044698962
- Mean Citation Score: 220.648092
- Max Citation Score: 317.1949
- Similarity Product: 213.61949745530487

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test