PATENT CLAIM ANALYSIS

Application Number: 15916585
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "149000"]

Abstract:
Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET; a control circuit configured to supply a first electric potential on a second terminal of the capacitor, a second electric potential on the gate of the TFET and a third electric potential on a second electrode of the TFET, such that:          when the stored potential is low, the TFET is reverse biased with a conduction current obtained by band-to-band tunneling with a value higher than a capacitor leakage current; when the stored potential is high, the TFET is reverse biased with an OFF state current value less than the capacitor leakage current.

Claim (Index 1):
Memory latch comprising at least:\n a first tunnel field effect transistor TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the first TFET corresponding to the source or the drain of the first TFET and configured to store a bit such that the low and high values of the electric potential of the storage node are representative of the value of the stored bit; a control circuit configured to supply a first electric potential on a virtual ground line, a second electric potential on a word line connected to the gate of the first TFET and a third electric potential on a bit line; wherein, n a first configuration, a second terminal of the capacitor is connected to the virtual ground line, the first electrode of the first TFET corresponds to its source when the first TFET is n-type or to its drain when the first TFET is p-type, a second electrode of the first TFET corresponding to its drain when the first electrode corresponds to the source or to its source when the first electrode corresponds to the drain, is connected to the bit line, or in a second configuration, a second terminal of the capacitor is connected to the bit line, the first electrode of the first TFET corresponds to its drain when the first TFET is n-type or to its source when the first TFET is p-type, a second electrode of the first TFET, corresponding to its source when the first electrode corresponds to the drain or to its drain when the first electrode corresponds to the source, is connected to the bit line; and wherein the control circuit is configured to provide, during a retention of a bit stored in the storage node, the first, second and third electric potentials with values such that: when the stored bit has a first value, a first bias voltage applied between the source and the drain of the first TFET has an absolute value less than that of a second bias voltage applied between the first and second terminals of the capacitor, and the first TFET is reverse biased such that a conduction current obtained by band-to-band tunneling in the first TFET has a value higher than a leakage current of the capacitor; when the stored bit has a second value different than the first value, the first bias voltage has an absolute value greater than that of the second bias voltage and the first TFET is reverse biased such that an OFF state current obtained in the first TFET has a value less than the leakage current of the capacitor.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.38182
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15452783', '15454405', '14882611', '15694841', '13006109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.766849357350227
- 35 USC 102 Novelty (BERT): 0.5061892516138805
- Combined Prediction Score: 0.7407833467765923
- Mean Citation Score: 240.292258
- Max Citation Score: 288.76407
- Similarity Product: 221.79762348486184

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test