PATENT CLAIM ANALYSIS

Application Number: 16179405
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["341", "143000"]

Abstract:
The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.

Claim (Index 15):
The converting circuit of  claim 14 , wherein the rate converter is coupled between the analog-to-digital converter and the sigma-delta modulator; the rate converter receives the first digital signal, and the first digital signal has a first bit rate; the rate converter converts the first digital signal into a third digital signal having a second bit rate, and the sigma-delta modulator receives the third digital signal and generates the second digital signal having the second bit rate.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 98.0
- Lexical Diversity: 2.63043
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11807504', '11865036', '11323671', '16117402', '12819096']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6267804785477397
- 35 USC 102 Novelty (BERT): 0.5054338153580281
- Combined Prediction Score: 0.6146458122287686
- Mean Citation Score: 254.510062
- Max Citation Score: 258.07498
- Similarity Product: 193.4749694241536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test