PATENT CLAIM ANALYSIS

Application Number: 15907212
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["365", "051000"]

Abstract:
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Claim (Index 21):
The DRAM die according to  claim 19 , wherein:\n the aggregated data is transferred as groups of alternating data bursts.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 88.0
- Lexical Diversity: 3.2381
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13908973', '14954976', '14023970', '15333001', '14683080']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8048190466773458
- 35 USC 102 Novelty (BERT): 0.5049584366865593
- Combined Prediction Score: 0.7748329856782672
- Mean Citation Score: 202.27174400000004
- Max Citation Score: 243.4669
- Similarity Product: 143.84624929974677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test