PATENT CLAIM ANALYSIS

Application Number: 15869349
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "329000"]

Abstract:
Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

Claim (Index 17):
The method of  claim 16  wherein the sacrificial layer is completely removed to form the cavity by an etching process that selectively removes the sacrificial layer relative to the substrate and the semiconductor fin.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15676300', '15586621', '15800563', '15427403', '15694109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9300025395775248
- 35 USC 102 Novelty (BERT): 0.5194758571728323
- Combined Prediction Score: 0.8889498713370555
- Mean Citation Score: 264.099646
- Max Citation Score: 318.81198
- Similarity Product: 246.539676944797

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test