PATENT CLAIM ANALYSIS

Application Number: 16006505
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["711", "105000"]

Abstract:
Embodiment of this disclosure provides a hierarchical structure of ordering points. In some embodiments, the hierarchical structure includes a single primary ordering point (POP) and at least one (or more) auxiliary order point (AOP) of a processing device. In one implementation, the processing device includes one or more cores; and a coherency circuit, operatively coupled to the cores. The processing device is to receive a plurality of memory access requests to be ordered by a first ordering point of the processing device. The processing device determines whether to stop the first ordering point based on a system event. Responsive to determining that the first ordering point is stopped, a second ordering point of the processing device is identified. Thereupon, a memory access request of the plurality of memory access requests is provided to the second ordering point.

Claim (Index 17):
The system of  claim 15 , wherein the processing device is further to:\n detect that the one or more cores are shutdown in accordance with the system event.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 94.0
- Lexical Diversity: 2.26087
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14612861', '12485579', '13785908', '11026676', '14669248']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5097211715954717
- 35 USC 102 Novelty (BERT): 0.4800851913033688
- Combined Prediction Score: 0.5067575735662615
- Mean Citation Score: 130.303292
- Max Citation Score: 135.85373
- Similarity Product: 88.39376717712045

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test