PATENT CLAIM ANALYSIS

Application Number: 15939721
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "040000"]

Abstract:
Provided are a method of fabricating a 3-dimensional transistor sensor and the sensor and a sensor array thereof. The method of fabricating the 3-dimensional transistor sensor includes forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer and forming a 3-dimensional silicon fin by etching the silicon layer, forming a source area and a source electrode at one end of the silicon fin, forming a drain area and a drain electrode at the other end the silicon fin, and forming a gate area at a center of the silicon fin, surrounding three surfaces of a gate with a gate insulating layer, forming a sensing gate layer configured to surround a portion of the gate insulating layer, and sealing an upper portion of the gate insulating layer excluding the sensing gate layer.

Claim (Index 4):
The method of  claim 1 , wherein the sensing gate layer is formed by removing a portion of the gate insulating layer, which is in contact with the drain or the source side.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 2.97959
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12195302', '10313887', '10825872', '11924903', '11157077']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927019420106382
- 35 USC 102 Novelty (BERT): 0.49870649596297
- Combined Prediction Score: 0.8841881276920407
- Mean Citation Score: 204.632696
- Max Citation Score: 214.26042
- Similarity Product: 140.4362103615582

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test