PATENT CLAIM ANALYSIS

Application Number: 16139858
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["712", "205000"]

Abstract:
A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

Claim (Index 3):
The processing device of  claim 2 , wherein the arbiter is further configured to select the selected memory address based at least partially on how many memory access credits are presently assigned to the interface, the number of memory access credits assigned to the interface indicating how many memory access requests the interface is permitted to submit to the memory.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 97.0
- Lexical Diversity: 1.625
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15384580', '15384487', '16126680', '15204243', '15971875']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5927898286402002
- 35 USC 102 Novelty (BERT): 0.5361690063903045
- Combined Prediction Score: 0.5871277464152107
- Mean Citation Score: 295.847396
- Max Citation Score: 365.7779
- Similarity Product: 283.03338514533635

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test