PATENT CLAIM ANALYSIS

Application Number: 15918581
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "153000"]

Abstract:
The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 μm from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

Claim (Index 10):
A method for manufacturing a turn-off power semiconductor device, the method comprising the following steps:\n providing a semiconductor wafer having a first main side and a second main side opposite to the first main side and a third main side corresponding to the first main side and a fourth main side corresponding to the second main side, the semiconductor wafer comprising in the order from the third main side to the fourth main side: (a) a first semiconductor layer of the second conductivity type which forms the base layer in the final turn-off power semiconductor device; and (b) a second semiconductor layer of the first conductivity type, which forms the drift layer in the final turn-off power semiconductor device, forming a plurality of semiconductor regions of the first conductivity type within the first semiconductor layer by selectively applying a first conductivity type first dopant into the first semiconductor layer from the third main side of the semiconductor wafer, wherein the plurality of semiconductor regions form the cathode regions of a plurality of thyristor cells in the final turn-off power semiconductor device;\n wherein each of the plurality of thyristor cells comprising in the order from the first main side to the second main side: \n (a) the cathode region of a first conductivity type; (b) a base layer of the second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region; (c) the drift layer of the first conductivity type forming a second p-n junction with the base layer; and (d) an anode layer of the second conductivity type separated from the base layer by the drift layer, wherein each thyristor cell comprises: a gate electrode which is arranged lateral to the cathode region and forms an ohmic contact with the base layer; a cathode electrode arranged on the first main side and forming an ohmic contact with the cathode region; and an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer, increasing the doping concentration in a plurality of well regions within the first semiconductor layer by selectively applying a second conductivity type second dopant into the first semiconductor layer from, the third main side of the semiconductor wafer, wherein the well regions are separated from the plurality of semiconductor regions and wherein the well regions form the gate well regions in the final turn-off power semiconductor device; selectively forming a first metallization layer to form the cathode electrodes of the plurality of thyristor cells; selectively forming a second metallization layer to form the gate electrodes of the plurality of thyristor cells; applying a first conductivity type third dopant in a region adjacent ot the third main side to partially compensate the second conductivity type doping of the first semiconductor layer at least in a region located between the cathode regions and the gate well regions of the plurality of thyristor cells in the final turn-off power semiconductor device; wherein interfaces between the cathode regions and the cathode electrodes and interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar; wherein the base layer includes a gate well region extending from its contact with the gate electrode to a depth (d w ) which is at least half of a depth (d C ) of the cathode region; wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 \u03bcm from the cathode region; and wherein the base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.8172
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15078602', '12007890', '15290377', '14748774', '13530727']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926333859755031
- 35 USC 102 Novelty (BERT): 0.5243569541711504
- Combined Prediction Score: 0.886136169196643
- Mean Citation Score: 304.38334999999995
- Max Citation Score: 350.34708
- Similarity Product: 296.3051985963106

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test