PATENT CLAIM ANALYSIS

Application Number: 16417827
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["375", "355000"]

Abstract:
A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

Claim (Index 7):
A radio frequency (RF) sampling receiver, comprising:\n a RF sampling analog-to-digital converter (ADC) configured to sample an RF signal at a sampling rate to form a sampled signal; a clock generator coupled to the RF sampling ADC and configured to generate a root clock signal at the sampling rate for use by the RF sampling ADC in sampling the RF signal; a clock divider configured to divide the root clock signal according to delay modulated clock division to form a modulated divided clock signal; and digital logic coupled to the RF sampling ADC and the clock divider and configured to process the sampled signal at a frequency of the modulated divided clock signal.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 100.0
- Lexical Diversity: 1.97143
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15906000', '15273764', '16167488', '13363410', '14490952']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4499879596472417
- 35 USC 102 Novelty (BERT): 0.5137803611340361
- Combined Prediction Score: 0.4563671997959212
- Mean Citation Score: 189.37786
- Max Citation Score: 327.92758
- Similarity Product: 324.17306571515803

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test