PATENT CLAIM ANALYSIS

Application Number: 15761497
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.

Claim (Index 18):
A method for driving the shift register according to  claim 4 , comprising:\n during a first display period displaying a first image frame:\n in a charging phase of the first display period, providing an active signal to the first input terminal and providing an inactive signal to the clock signal terminal, to electrically connect the first input terminal to the first pull-up node, and to electrically connect the clock signal terminal to the signal output terminal, \n in an output phase of the first display period, providing an active signal to the clock signal terminal and providing an inactive signal to the first input terminal, to float the first pull-up node, and to electrically connect the signal output terminal to the clock signal terminal, and \n in a reset phase of the first display period, providing an active signal to the reset terminal, to electrically connect the first pull-up node, the second pull-up node, and the signal output terminal to the inactive signal terminal; and \n during a second display period displaying a second image frame:\n in a charging phase of the second display period, providing an active signal to the second input terminal and providing an inactive signal to the clock signal terminal, to electrically connect the second input terminal to the second pull-up node, and to electrically connect the clock signal terminal to the signal output terminal, \n in an output phase of the second display period, providing an active signal to the clock signal terminal and providing an inactive signal to the second input terminal, to float the second pull-up node, and to electrically connect the signal output terminal to the clock signal terminal, and \n in a reset phase of the second display period, providing an active signal to the reset terminal, to electrically connect the first pull-up node, the second pull-up node, and the signal output terminal to the inactive signal terminal.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 4.09677
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15740121', '15518389', '15541622', '15542365', '15541426']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6916072502348746
- 35 USC 102 Novelty (BERT): 0.5165637276472823
- Combined Prediction Score: 0.6741028979761153
- Mean Citation Score: 313.09041400000007
- Max Citation Score: 322.13254
- Similarity Product: 237.4183216995692

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test