PATENT CLAIM ANALYSIS

Application Number: 15927366
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["174", "262000"]

Abstract:
This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

Claim (Index 2):
The electronic package of  claim 1 , wherein the first electrically conductive layer, the second electrically conductive layer, and the metal layer form a via, wherein the via has a substantially non-circular profile.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.14815
- Patent Class: 174.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13717048', '14456606', '15056794', '13717185', '15611428']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8228088667978984
- 35 USC 102 Novelty (BERT): 0.4810158894494553
- Combined Prediction Score: 0.7886295690630541
- Mean Citation Score: 122.882263
- Max Citation Score: 152.24052
- Similarity Product: 103.22062926438332

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test