PATENT CLAIM ANALYSIS

Application Number: 15879610
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Claim (Index 1):
A semiconductor device comprising:\n a wiring substrate; an interposer mounted on a first surface of the wiring substrate; a first semiconductor component having a first main surface, a plurality of first electrodes disposed on the first main surface, and a component mounted on the interposer; a second semiconductor component having a second main surface, a plurality of second electrodes formed on the second main surface and mounted on the interposer, the second semiconductor component controlling the first semiconductor component; and a plurality of external terminals formed on a second surface of the wiring substrate, which is opposite to the first surface, wherein the interposer includes a base member made of a semiconductor material as a base material and a plurality of wiring layers arranged on a main surface of the base member, wherein the first semiconductor component and the second semiconductor component are electrically connected to each other via the plurality of wiring layers, wherein the plurality of wiring layers include a first wiring layer, a second wiring layer spaced farther away from the main surf ace of the base member than the first wiring layer, a third wiring layer spaced farther away from the main surf ace of the base member than the second wiring layer, and a fourth wiring layer spaced farther away from the main surface of the base member than the third wiring layer, wherein a plurality of first electrode pads and a plurality of second electrode pads are formed in the fourth wiring layer of the interposer, wherein the plurality of first electrodes of the first semiconductor component are electrically connected with the plurality of first electrode pads of interposer, wherein the plurality of second electrodes of the second semiconductor component are electrically connected with the plurality of second electrode pads of interposer, wherein, in a first region of the interposer which, in plan view, is sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a plurality of reference potential wirings in the third layer, the plurality of reference potential wirings constituting a part of a transmission path of a reference potential, is higher than a ratio of a plurality of reference potential wirings in the first wiring layer, wherein, in the first region of the interposer in plan view, a plurality of signal wirings are formed in the second wiring layer, and wherein the first semiconductor component and the second semiconductor component are arranged next to each other.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.63636
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15515465', '15549107', '14967463', '15721784', '16063280']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9240325820947852
- 35 USC 102 Novelty (BERT): 0.5519882243163071
- Combined Prediction Score: 0.8868281463169374
- Mean Citation Score: 312.84803
- Max Citation Score: 412.42133
- Similarity Product: 398.8057261798906

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test