PATENT CLAIM ANALYSIS

Application Number: 16431012
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["257", "040000"]

Abstract:
An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

Claim (Index 1):
A three-terminal apparatus, comprising:\n a field-effect transistor (FET) comprising:\n a first layer comprising silicon having a first type of carrier as its majority carrier; \n a gate comprising a second layer formed on the first layer, the second layer comprising intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer, the third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier, and a conductive layer formed on the third layer; and \n drain and source terminals, each of the drain and source terminals comprising a fourth layer formed on the first layer, the fourth layer comprising crystalline hydrogenated silicon having the first type of carrier as its majority carrier, and a conductive layer formed on the fourth layer; and \n a set of one or more serially-connected diodes, each diode having first and second terminals, wherein the first terminal of a first diode in the set of one or more serially-connected diodes is connected to the source terminal of the FET; wherein the gate terminal of the FET forms a first terminal of the three-terminal apparatus, the drain terminal of the FET forms a second terminal of the three-terminal apparatus, and the second terminal of a last diode in the set of one or more serially-connected diodes forms a third terminal of the three-terminal apparatus; and wherein a subthreshold swing of the apparatus is higher than a subthreshold swing of the FET by a factor proportional to a sum of ideality factors of the set of one or more serially-connected diodes.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 100.0
- Lexical Diversity: 3.47826
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15346546', '15346462', '14226285', '10762627', '14717344']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8906811668394181
- 35 USC 102 Novelty (BERT): 0.5498339648547887
- Combined Prediction Score: 0.8565964466409552
- Mean Citation Score: 214.859312
- Max Citation Score: 390.35638
- Similarity Product: 367.9004161146212

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test