PATENT CLAIM ANALYSIS

Application Number: 15924100
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185020"]

Abstract:
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

Claim (Index 50):
The non-volatile memory device of  claim 29 , further comprising:\n a control gate decoder comprising transistors only of the PMOS type.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 90.0
- Lexical Diversity: 1.7931
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15158460', '15479235', '15238681', '15467174', '14875533']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8656077319926222
- 35 USC 102 Novelty (BERT): 0.6003105667222295
- Combined Prediction Score: 0.8390780154655829
- Mean Citation Score: 518.533778
- Max Citation Score: 647.1237
- Similarity Product: 467.5804089230061

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test