PATENT CLAIM ANALYSIS

Application Number: 15971079
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["716", "052000"]

Abstract:
A method of manufacturing an IC includes detecting connectivity between polygons from layout data of the IC and extracting a layout netlist, by performing a DRC on the layout data. The DRC includes loading a rule file including a DRC syntax. The method includes performing INS verification on the extracted layout netlist and schematic data of the IC to generate LVS result data. The method includes manufacturing the IC according to a layout based on the layout data and the LVS result data.

Claim (Index 8):
The computer-implemented method of  claim 7 , wherein the DRC syntax is DRC loop syntax configured to check connectivity for each of the plurality of layers and for each of the plurality of polygons.

Metadata:
- Claim Count in Document: 83.0
- Percentile: 93.0
- Lexical Diversity: 2.14634
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13470653', '15407535', '13717118', '10132776', '14482296']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4161706319956642
- 35 USC 102 Novelty (BERT): 0.5151717920929452
- Combined Prediction Score: 0.4260707480053923
- Mean Citation Score: 316.528448
- Max Citation Score: 367.08426
- Similarity Product: 250.83257620650528

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test