PATENT CLAIM ANALYSIS

Application Number: 16106658
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["375", "375000"]

Abstract:
A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Claim (Index 5):
The clock generation circuit of  claim 1 , wherein the clock generation unit includes:\n a first clock generation unit suitable for generating the first clock by dividing a reference clock by 2 and generating the first inversion clock by inverting the first clock; and a second clock generation unit suitable for generating the second clock by dividing a reference inversion clock, which has an opposite phase to the reference clock, by 2 and generating the second inversion clock by inverting the second clock.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 96.0
- Lexical Diversity: 2.71053
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14793451', '15869167', '13845181', '13444271', '12379019']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4632063567778766
- 35 USC 102 Novelty (BERT): 0.5703211681104225
- Combined Prediction Score: 0.4739178379111312
- Mean Citation Score: 266.166648
- Max Citation Score: 430.5481
- Similarity Product: 417.8839076676905

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test