PATENT CLAIM ANALYSIS

Application Number: 15862041
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["714", "719000"]

Abstract:
An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Claim (Index 15):
The diagnostic method for a semiconductor device, according to  claim 14 ,\n wherein the first step, the second step, and the third step are executed by a BIST (Built In Self Test) circuit included in the semiconductor device.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.10417
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15658734', '10699223', '10805227', '10739123', '10271533']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3288485199024009
- 35 USC 102 Novelty (BERT): 0.4948214905735643
- Combined Prediction Score: 0.3454458169695172
- Mean Citation Score: 223.031606
- Max Citation Score: 266.2719
- Similarity Product: 210.507660719204

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test