PATENT CLAIM ANALYSIS

Application Number: 15992112
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["711", "114000"]

Abstract:
An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Claim (Index 31):
A method of operation within an integrated-circuit buffer component having internal data conductors configurably coupled between a control-side data signaling interface and first and second memory-side data signaling interfaces, the first memory-side data signaling interface having twice as many input/output (I/O) transceivers as the second memory-side data signaling interface, the method comprising:\n in a first memory system configuration in which the first memory-side data signaling interface is coupled to a memory module having a first interface width and the second memory-Application side data signaling interface is not connected to a memory module, coupling all the internal data conductors exclusively to the I/O transceivers of the first memory-side data signaling interface such that data received from a memory control component via the control-side data signaling interface is conveyed via the internal data conductors exclusively to the first memory-side data signaling interface, and data to be transmitted to the memory control component via the control-side data signaling interface is received via the internal data conductors exclusively from the first memory-side data signaling interface ; and in a second memory system configuration in which the first and second memory-side data signaling interfaces are coupled to respective memory modules each having an interface width less than the first interface width, coupling a first half of the internal data conductors exclusively to the I/O transceivers of the second memory-side data signaling interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first memory-side data signaling interface.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 1.33333
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15458166', '14874324', '13499029', '15793029', '11460582']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4647706265714143
- 35 USC 102 Novelty (BERT): 0.4980312397481775
- Combined Prediction Score: 0.4680966878890906
- Mean Citation Score: 203.302042
- Max Citation Score: 279.7678
- Similarity Product: 258.2653775344968

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test