PATENT CLAIM ANALYSIS

Application Number: 15954078
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["710", "315000"]

Abstract:
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Claim (Index 7):
The integrated circuit of  claim 6 , wherein the universal interface block further comprises:\n a first clock tree network configured to distribute the first input-output clock signal to the first group of input-output modules; a second clock tree network configured to distribute the second input-output clock signal to the second group of input-output modules; a first phase detector configured to receive the first input-output clock signal, to receive a first core fabric clock signal that is fed back from ends of the first clock tree network, and to generate a first control signal for adjusting the first delay locked loop circuit; and a second phase detector configured to receive the second input-output clock signal, to receive a second core fabric clock signal that is fed back from ends of the second clock tree network, and to generate a second control signal for adjusting the second delay locked loop circuit.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 91.0
- Lexical Diversity: 1.73913
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14960175', '14692133', '15799816', '15429018', '10326695']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6664038699086846
- 35 USC 102 Novelty (BERT): 0.5536638802602565
- Combined Prediction Score: 0.6551298709438418
- Mean Citation Score: 265.832208
- Max Citation Score: 434.16278
- Similarity Product: 290.70248861309886

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test