PATENT CLAIM ANALYSIS

Application Number: 16049267
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["375", "260000"]

Abstract:
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Claim (Index 1):
A data processing apparatus operable to map input symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols, the data processing apparatus comprising\n an interleaver operable to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, an address generator operable to generate the set of addresses, an address being generated for each of the input symbols for mapping the input data symbol on to one of the sub-carrier signals, the address generator comprising a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately eight thousand, the linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R i \u2032[11]=R i-1 \u2032[0]\u2295R i-1 \u2032[1]\u2295R i-1 \u2032[4]\u2295R i-1 \u2032[6], and the permutation code forms, with an additional bit, a thirteen bit address, characterised in that the permutation circuit is arranged to change the permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 1.85294
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13363467', '15080733', '13364640', '13398506', '12256746']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5662288590003122
- 35 USC 102 Novelty (BERT): 0.5503878065759511
- Combined Prediction Score: 0.5646447537578761
- Mean Citation Score: 399.140248
- Max Citation Score: 403.93262
- Similarity Product: 400.75729833034273

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test