PATENT CLAIM ANALYSIS

Application Number: 16294834
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["330", "279000"]

Abstract:
The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

Claim (Index 1):
A variable-gain amplifier device comprising:\n an equalizer section comprising:\n a first transistor and a second transistor, the first transistor comprising a first gate terminal coupled to a first input signal and a first drain terminal coupled to a first output node, the second transistor comprising a second gate terminal coupled to a second input signal and a second drain terminal coupled to a second output node; \n a first common mode resistor coupled to the first output node; \n a second common mode resistor coupled to the second output node and the first common mode resistor; \n a common node configured between the first common mode resistor and the second common mode resistor, the common node is characterized by a common mode voltage; \n an amplifier section comprising:\n a third transistor and a fourth transistor, the third transistor comprising a third gate terminal coupled to the first output node and a third drain node coupled to a third output node, the fourth transistor comprising a fourth gate terminal coupled to the second output node and a fourth drain terminal coupled to a third output node; and \n a fifth transistor comprising a fifth gate terminal coupled to a control voltage and the common node between the first common mode resistor and the second common resistor, the fifth transistor being characterized by a resistance value configured between the third transistor and the fourth transistor, the resistance value based on the control voltage and the common node voltage.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 99.0
- Lexical Diversity: 1.75385
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15597074', '16215864', '16271413', '15272828', '15701072']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7563988764477565
- 35 USC 102 Novelty (BERT): 0.5604104446338729
- Combined Prediction Score: 0.7368000332663682
- Mean Citation Score: 290.413398
- Max Citation Score: 410.9473
- Similarity Product: 386.4264292560935

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test