PATENT CLAIM ANALYSIS

Application Number: 15923195
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["330", "296000"]

Abstract:
A single-stage amplifier circuit includes first and second transistors (e.g., BJTs or FETs) connected in parallel between the amplifier's input and output nodes. The first and second transistors are configured differently using known fabrication techniques such that a (first) cutoff frequency of the first transistor is at least 1.5 times greater than a (second) cutoff frequency of the second transistor, and such that a ratio of the respective cutoff frequencies produces a significant cancellation of second derivative transconductance (Gm″) in the amplifier output signal, whereby the amplifier achieves significantly improved IIP 3 . Alternatively, the amplifier is configured using MOSFETs having respective different channel lengths to achieve the desired cutoff frequency ratio. An exemplary communication circuit includes a low-noise amplifier having two NPN BJTs that are fabricated using different collector doping concentrations, different emitter doping concentrations, or different base region widths in order to achieve the desired cutoff frequency ratio.

Claim (Index 13):
An amplifier circuit for generating an amplified output signal on an output node in response to an unamplified input signal received at an input node, the amplifier circuit comprising:\n a first transistor having a first control terminal coupled to the input node and a first output terminal coupled to the output node, the first transistor being operably configured to have a first cutoff frequency; a second transistor having a second control terminal coupled to the input node and a second output terminal coupled to the output node, the second transistor being operably configured to have a second cutoff frequency; and at least one of a first bias network circuit coupled between a first emitter terminal of the first transistor and the second voltage source, and a second bias network circuit coupled between a second emitter terminal of the second transistor and the second voltage source, wherein the first and second transistors are configured such that the first cutoff frequency is at least 1.5 times greater than the second cutoff frequency.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 1.90909
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14882470', '14375127', '15916411', '11156851', '10307200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7435833875222589
- 35 USC 102 Novelty (BERT): 0.4729676550913682
- Combined Prediction Score: 0.7165218142791699
- Mean Citation Score: 200.29550200000003
- Max Citation Score: 210.74498
- Similarity Product: 193.02589783595084

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test