PATENT CLAIM ANALYSIS

Application Number: 16258679
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "392000"]

Abstract:
A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Claim (Index 4):
The method of forming a transistor with dual spacers according to  claim 1 , wherein the gate dielectric layer protrudes from the gate electrode, and the gate dielectric layer comprises a first part and a second part, wherein the first part is right below the second inner spacer, and the second part is uncovered by the second inner spacer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 99.0
- Lexical Diversity: 2.90476
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15846150', '13850887', '14659576', '11329623', '13728948']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9260503871727594
- 35 USC 102 Novelty (BERT): 0.5109070421911832
- Combined Prediction Score: 0.8845360526746019
- Mean Citation Score: 221.240878
- Max Citation Score: 308.36023
- Similarity Product: 273.03425901278143

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test