PATENT CLAIM ANALYSIS

Application Number: 15966236
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-09
Patent Classification: ["257", "760000"]

Abstract:
A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

Claim (Index 2):
The integrated circuit of  claim 1 , wherein the vias are further formed by etching lines based on the lithographic pattern.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.89655
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15198962', '14314945', '15198827', '13748159', '14231448']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9228946015375245
- 35 USC 102 Novelty (BERT): 0.5088701305017194
- Combined Prediction Score: 0.8814921544339439
- Mean Citation Score: 196.597126
- Max Citation Score: 298.95013
- Similarity Product: 250.86541272571088

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test