PATENT CLAIM ANALYSIS

Application Number: 15765266
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["709", "213000"]

Abstract:
Processing apparatus in the form of a parallel processing configuration having a plurality of processors and at least one shared memory that is shared between the processors. Each processor is operated at a clock speed that is lower than the clock speed of the memory.

Claim (Index 6):
Processing apparatus as claimed in  claim 5  wherein each processor is arranged to complete instructions at an average rate of one instruction per processor clock cycle even when the instructions require read or write access to a plurality of items of data.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 1.56667
- Patent Class: 709.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12147332', '11850761', '09909507', '11531387', '12781314']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2318259536251519
- 35 USC 102 Novelty (BERT): 0.4736443861347224
- Combined Prediction Score: 0.256007796876109
- Mean Citation Score: 132.88912
- Max Citation Score: 142.53603
- Similarity Product: 102.7985805257249

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test