PATENT CLAIM ANALYSIS

Application Number: 15756039
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-05
Patent Classification: ["714", "755000"]

Abstract:
Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Claim (Index 8):
The electronic system of  claim 7 , wherein the local memory is synchronous dynamic random-access memory (SDRAM).

Metadata:
- Claim Count in Document: 26.0
- Percentile: 88.0
- Lexical Diversity: 1.6875
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14775848', '14091757', '13930600', '14126310', '14493956']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3200341259432216
- 35 USC 102 Novelty (BERT): 0.5025806027122781
- Combined Prediction Score: 0.3382887736201272
- Mean Citation Score: 208.140884
- Max Citation Score: 257.7803
- Similarity Product: 173.4602463838041

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test