PATENT CLAIM ANALYSIS

Application Number: 15910929
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Claim (Index 1):
A semiconductor device, comprising:\n a shallow trench isolation (STI) layer on a substrate; an interlayer dielectric (ILD) layer on the STI layer, the ILD layer corresponding to a gate cut region; and a filling on the STI layer on both sides of the ILD layer including both sides of the ILD layer corresponding to an isolation cut region, wherein and the gate cut region and the isolation cut region intersect each other at a junction, and wherein the ILD layer is continuous through the junction.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 1.36364
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15271867', '15841942', '14639159', '15859775', '13041134']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9150160321988536
- 35 USC 102 Novelty (BERT): 0.5209376689362241
- Combined Prediction Score: 0.8756081958725909
- Mean Citation Score: 203.485026
- Max Citation Score: 326.3773
- Similarity Product: 253.23231676450368

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test