PATENT CLAIM ANALYSIS

Application Number: 16271226
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "401000"]

Abstract:
Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

Claim (Index 11):
The semiconductor device of  claim 2 , wherein the semiconductor structure is a nanowire disposed above the semiconductor substrate.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 99.0
- Lexical Diversity: 2.20755
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15527288', '15743575', '14780218', '13622974', '15266819']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922431632952232
- 35 USC 102 Novelty (BERT): 0.5054925347383509
- Combined Prediction Score: 0.8807377231308438
- Mean Citation Score: 217.339186
- Max Citation Score: 291.17807
- Similarity Product: 245.58854015406368

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test