PATENT CLAIM ANALYSIS

Application Number: 16081012
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "195000"]

Abstract:
A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Claim (Index 6):
The heterostructure semiconductor device of  claim 2  wherein the resistance value is determined to substantially dampen oscillations of the current flowing in the power transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 2.38596
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14539086', '13780192', '15448724', '15700087', '15587276']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9055118108097006
- 35 USC 102 Novelty (BERT): 0.4906417649682362
- Combined Prediction Score: 0.8640248062255541
- Mean Citation Score: 178.48176999999995
- Max Citation Score: 189.03392
- Similarity Product: 136.66877304597855

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test