PATENT CLAIM ANALYSIS

Application Number: 15935345
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["708", "204000"]

Abstract:
A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2 ew-1 −1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw−1−s y ) to generate a shift value s v  of sw bits given by s v =(B−E)+(iw−1−s y ), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2 ew-1 −1, iw−1−s y )+min(2 ew-1 −2, fw)]≤k≤sw, where s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

Claim (Index 18):
A non-transitory computer readable storage medium having stored thereon a computer readable description of a binary logic circuit for converting a number in floating point format having an exponent E, an exponent bias B=2 ew-1 \u22121, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the binary logic circuit, the binary logic circuit comprising:\n an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw\u22121\u2212s y ) to generate a shift value s v  of sw bits given by s v =(B\u2212E)+(iw\u22121\u2212s y ), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; and a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2 ew-1 \u22121, iw\u22121\u2212s y )+min(2 ew-1 2, fw)]\u2264k\u2264sw, where s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

Metadata:
- Claim Count in Document: 46.0
- Percentile: 90.0
- Lexical Diversity: 2.21782
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15935313', '11740711', '11840323', '13284125', '10329765']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4159895153711819
- 35 USC 102 Novelty (BERT): 0.7124268286580898
- Combined Prediction Score: 0.4456332466998727
- Mean Citation Score: 412.455188
- Max Citation Score: 785.0961
- Similarity Product: 722.7442588423489

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test