PATENT CLAIM ANALYSIS

Application Number: 15889415
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["716", "112000"]

Abstract:
Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

Claim (Index 18):
The computer program product of  claim 16 , wherein the modeling includes varying a depth-of-focus to measure a critical dimension of a known structure;\n determining a reference curve for the known structure; measuring a critical dimension of the one or more structures of the design; and comparing the measured critical dimension of the one or more structures to the determined reference curve for the known structure.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.37209
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11187609', '14892880', '11540453', '14873120', '15445042']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.292970026254589
- 35 USC 102 Novelty (BERT): 0.4349987749625476
- Combined Prediction Score: 0.3071729011253849
- Mean Citation Score: 126.055605
- Max Citation Score: 128.23523
- Similarity Product: 106.8632929486728

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test