PATENT CLAIM ANALYSIS

Application Number: 16245276
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "043000"]

Abstract:
An array substrate includes a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack. The active layer includes a source transfer portion and a drain transfer portion separated from the source transfer portion and a channel integrally connected to the source transfer portion and the drain transfer portion. Contact resistances between the source transfer portion, the drain transfer portion and the channel are reduced, and interface defects of the channel are reduced, so that through the source transfer portion and the drain transfer portion, an on-state current of a thin film transistor is increased and an off-state current is reduced so that is the on/off ratio is raised to improve the performance of the array substrate.

Claim (Index 5):
The array substrate according to  claim 1 , wherein the predetermined material comprises an oxide semiconductor.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 99.0
- Lexical Diversity: 2.48148
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15125176', '10875559', '15740606', '15112195', '10608085']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921602957482214
- 35 USC 102 Novelty (BERT): 0.5052464349915422
- Combined Prediction Score: 0.8799673052331468
- Mean Citation Score: 209.49064600000003
- Max Citation Score: 263.85764
- Similarity Product: 190.7739307643796

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test