PATENT CLAIM ANALYSIS

Application Number: 16411924
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "192000"]

Abstract:
Method and structure of forming a vertical FET. The method includes depositing a bottom source-drain layer over a substrate; depositing a first heterostructure layer over the bottom source-drain layer; depositing a channel layer over the first heterostructure layer; depositing a second heterostructure layer over the channel layer; forming a first fin having a hard mask; recessing the first and the second heterostructure layers to narrow them; filling gaps with an inner spacer; laterally trimming the channel layer to a narrower width; depositing a bottom outer spacer over the bottom source-drain layer; depositing a high-k layer on the bottom outer spacer, the first fin, and the hard mask; and depositing a metal gate layer over the high-k and top outer spacer to produce the vertical FET. Forming another structure by recessing the metal gate layer below the second inner spacer.

Claim (Index 11):
A vertical field-effect transistor (FET) structure comprising:\n a substrate of a first type; a highly doped bottom source-drain layer disposed on the substrate of the first type; a dielectric bottom outer spacer disposed on the highly doped bottom source-drain layer; a recessed first heterostructure layer disposed on the highly doped bottom source-drain layer; a channel layer disposed on the recessed first heterostructure layer; a recessed second heterostructure layer disposed on the channel layer; a first dielectric inner spacer disposed between the dielectric bottom outer spacer and the recessed first heterostructure layer; a fin including the recessed first and the second heterostructure layers and the channel layer; a high-k dielectric layer disposed on the bottom outer spacer and the channel layer; a dielectric top outer spacer disposed on top of the high-k dielectric layer; a second dielectric inner spacer disposed between the dielectric top outer spacer and the recessed second heterostructure layer; a metal gate layer disposed on top of the high-k dielectric layer and directionally recessed below the second dielectric inner spacer; and a top source-drain epitaxial layer of a second type disposed on the first fin, the dielectric top inner spacer, and the dielectric top outer spacer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.8
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15611981', '15786047', '15163049', '15935468', '16233825']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9286642064727664
- 35 USC 102 Novelty (BERT): 0.5968111617136452
- Combined Prediction Score: 0.8954789019968543
- Mean Citation Score: 376.172636
- Max Citation Score: 527.9611
- Similarity Product: 450.5716280043245

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test