PATENT CLAIM ANALYSIS

Application Number: 16000271
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["716", "113000"]

Abstract:
The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.

Claim (Index 2):
The IC of  claim 1 , further comprising a multilayer metallization on top of a semiconductor wafer, wherein the row of the sink cells, the first and the second driver cell are comprised in the semiconductor wafer, the multilayer metallization comprising at least two metallization layers, the first interconnect line being comprised in one of the metallization layers, the second interconnect line being comprised in another one of the metallization layers being above the one of the metallization layers in the multilayer metallization.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 2.475
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14941508', '16000341', '15016476', '15197423', '12123769']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3663091221012118
- 35 USC 102 Novelty (BERT): 0.4937821358534405
- Combined Prediction Score: 0.3790564234764347
- Mean Citation Score: 236.230354
- Max Citation Score: 327.85333
- Similarity Product: 325.94712691313623

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test