PATENT CLAIM ANALYSIS

Application Number: 16290346
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-08
Patent Classification: ["710", "310000"]

Abstract:
A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

Claim (Index 4):
The memory module of  claim 2 , wherein the buffer component comprises a slot register to store a first value indicative of a first number of slots in a memory system in which the memory module resides, wherein the buffer component is to determine the subset of the plurality of secondary CS signals based on the primary CS signal and the first value.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 99.0
- Lexical Diversity: 2.01667
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15101870', '14538524', '15024454', '14578078', '14869294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7199240948456123
- 35 USC 102 Novelty (BERT): 0.5724230947238174
- Combined Prediction Score: 0.7051739948334328
- Mean Citation Score: 377.5441
- Max Citation Score: 485.71692
- Similarity Product: 407.1937148690344

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test