PATENT CLAIM ANALYSIS

Application Number: 16235956
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["326", "038000"]

Abstract:
The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.

Claim (Index 2):
The programmable logic device of  claim 1 , wherein the second die comprises second timing circuitry coupled to the bridge circuitry and comprising a second phase difference detector and a second delay element.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 98.0
- Lexical Diversity: 1.37838
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16236062', '14882065', '16146849', '15392225', '15338074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6478277343504624
- 35 USC 102 Novelty (BERT): 0.4688472590942222
- Combined Prediction Score: 0.6299296868248383
- Mean Citation Score: 165.987802
- Max Citation Score: 189.29652
- Similarity Product: 146.08859135547638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test