PATENT CLAIM ANALYSIS

Application Number: 15951894
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["323", "313000"]

Abstract:
A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

Claim (Index 3):
The common mode reference circuit of  claim 1 , including a resistive circuit element coupled between a drain region of the PFET of the first NFET/PFET pair and a gate region of the first YET of the output stage; and a capacitor coupled to the resistive circuit element and coupled between the gate region of the first FET of the output stage and the series connection from the first FET to the second FET.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 2.54348
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11623185', '13727580', '10905436', '14541713', '10926934']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7570755198385065
- 35 USC 102 Novelty (BERT): 0.4970884775155199
- Combined Prediction Score: 0.731076815606208
- Mean Citation Score: 232.33304
- Max Citation Score: 253.8
- Similarity Product: 181.6271044850349

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test