PATENT CLAIM ANALYSIS

Application Number: 15978682
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["365", "189050"]

Abstract:
The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.

Claim (Index 7):
The detecting circuit of  claim 5 , wherein when the delay-locked loop module operates at a high frequency, the delay-locked loop module is enabled to adjust the phase of the clock signal after receiving a phase delay or a phase advance.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 3.71429
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10983504', '13102938', '12392495', '15133068', '11481518']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7794650134877709
- 35 USC 102 Novelty (BERT): 0.4811620466218501
- Combined Prediction Score: 0.7496347168011788
- Mean Citation Score: 196.940412
- Max Citation Score: 203.7917
- Similarity Product: 156.8779411366105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test