PATENT CLAIM ANALYSIS

Application Number: 15958332
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["361", "783000"]

Abstract:
A printed wiring board includes a core laminate including insulating layers and conductor layers, a first build-up layer formed on first surface of the laminate and including first interlayer resin and conductor layers, and a second build-up layer formed on second surface of the core laminate on the opposite side and including second interlayer resin and conductor layers. The conductor layers in the laminate include first and second conductor layers such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the laminate, and the first interlayer resin layer has thickness greater than thickness of the second interlayer resin layer.

Claim (Index 17):
A method for manufacturing a printed wiring board according to  claim 16 , wherein the forming of the core laminate includes forming the first conductor layer on the support plate such that the first conductor layer has a pattern, forming on the first conductor layer one of the insulating layers and a metal foil, forming a plurality of via holes through the one of the insulating layers and the metal foil, forming a seed layer on the metal foil such that the seed layer is formed in the via holes, forming a plating resist film such that the plating resist film has a pattern, applying electroplating on the seed layer on the metal foil and in the via holes exposed by the pattern of the plating resist film such that an electroplating film is formed on the seed layer on the metal foil and in the via holes exposed by the pattern of the plating resist film, removing the plating resist film from the seed layer, and removing the seed layer and the metal foil exposed by the removing of the plating resist film such that one of the conductor layers having a conductor pattern is formed for the core laminate.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 91.0
- Lexical Diversity: 3.27273
- Patent Class: 361.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14700313', '14857074', '15793084', '14886544', '15581253']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8809169247408853
- 35 USC 102 Novelty (BERT): 0.5503637277411176
- Combined Prediction Score: 0.8478616050409086
- Mean Citation Score: 364.05341800000014
- Max Citation Score: 435.12634
- Similarity Product: 338.27770198202614

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test