PATENT CLAIM ANALYSIS

Application Number: 15944069
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "459000"]

Abstract:
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

Claim (Index 15):
An apparatus comprising:\n a first semiconductor chip having a first substrate and one or more first dielectric layers on a first surface of the first substrate, a first conductive feature being in the one or more first dielectric layers, the first conductive feature having a first surface facing toward the first substrate; a second semiconductor chip having a second substrate and one or more second dielectric layers on a first surface of the second substrate, a second conductive feature being in the one or more second dielectric layers, the first semiconductor chip being bonded to the second semiconductor chip such that the one or more first dielectric layers and the one or more second dielectric layers are interposed between the first substrate and the second substrate; a first liner extending from a second surface of the first substrate and into the one or more first dielectric layers; a second liner over the first liner, the second liner extending from the second surface of the first substrate to the second conductive feature, the second liner contacting the first conductive feature; a conductive plug over the second liner, the conductive plug extending from the second surface of the first substrate to the second conductive feature; and a dielectric layer on the second surface of the first substrate, the conductive plug being interposed between the first surface of the first conductive feature and the dielectric layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 1.82456
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15076115', '14020370', '14135153', '15231419', '14316125']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.896740274618498
- 35 USC 102 Novelty (BERT): 0.4624527409918635
- Combined Prediction Score: 0.8533115212558345
- Mean Citation Score: 174.126504
- Max Citation Score: 198.29048
- Similarity Product: 185.72399887192245

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test