PATENT CLAIM ANALYSIS

Application Number: 15953588
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["709", "208000"]

Abstract:
A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Claim (Index 12):
The method of  claim 11 , further comprising mapping each of the plurality of USB host ports on the DAC master computer to a memory segment of the mass storage on each of the plurality of disjoint node computers.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 91.0
- Lexical Diversity: 1.80645
- Patent Class: 709.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14743752', '12180971', '10338441', '15750528', '15721871']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.1928033450632945
- 35 USC 102 Novelty (BERT): 0.5366418440363003
- Combined Prediction Score: 0.227187194960595
- Mean Citation Score: 188.06977
- Max Citation Score: 368.4682
- Similarity Product: 268.14102781207555

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test