PATENT CLAIM ANALYSIS

Application Number: 15864498
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["345", "204000"]

Abstract:
Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An n th  (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n−1) th  shift register located on a same side as the n th  pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an n th  shift register of the shift registers located on an opposite side of the n th  pull-up transistor; and a second end, coupled to an n th  gate line of the pixel array and used to drive the n th  gate line.

Claim (Index 8):
The image display panel according to  claim 6 , wherein a driving transistor of each shift register outputs a scanning signal.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.7619
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15351457', '15798011', '15522368', '12643963', '15311386']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6947531442143612
- 35 USC 102 Novelty (BERT): 0.5123630949413207
- Combined Prediction Score: 0.6765141392870572
- Mean Citation Score: 262.02422
- Max Citation Score: 277.50348
- Similarity Product: 181.43468931541443

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test