PATENT CLAIM ANALYSIS

Application Number: 15907390
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["365", "194000"]

Abstract:
A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface,

Claim (Index 17):
The method of  claim 14  further comprising receiving at least one configuration parameter, wherein the programmable delay is a function of the received at least one configuration parameter.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 88.0
- Lexical Diversity: 2.7963
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14664580', '15262462', '14691051', '14573379', '14270293']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8050117450768954
- 35 USC 102 Novelty (BERT): 0.5147557931630903
- Combined Prediction Score: 0.775986149885515
- Mean Citation Score: 263.41992200000004
- Max Citation Score: 321.64487
- Similarity Product: 203.3059280470085

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test