PATENT CLAIM ANALYSIS

Application Number: 15912486
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["712", "002000"]

Abstract:
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

Claim (Index 1):
A system comprising:\n a system memory; and a processor coupled to the system memory over a memory interface, the processor comprising a plurality of simultaneous multi-threading (SMT) cores coupled over an interconnect to simultaneously execute multiple threads, each of the SMT cores including a Level 1 instruction cache and a Level 1 data cache; a Level 2 (L2) cache and a Level 3 cache shared by at least two of the cores; at least one of the cores comprising:\n an instruction fetch circuit to fetch instructions from a memory subsystem; \n a decoder to decode the instructions; \n a source register to store a plurality of 64-bit packed data elements; \n a destination register to store a plurality of packed data elements; \n execution circuitry to execute a vector leading zero count instruction to generate plurality of count values indicating a number of consecutive zeroes in each of the 64-bit packed data elements starting at a most significant bit position in each of the 64-bit packed data elements, the execution circuitry to store each count value in a packed data element location in the destination vector register corresponding to one of the 64-bit packed data elements.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.42857
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15912498', '15912468', '15790987', '13731008', '15188817']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6205657373918583
- 35 USC 102 Novelty (BERT): 0.5954759770561187
- Combined Prediction Score: 0.6180567613582844
- Mean Citation Score: 441.901764
- Max Citation Score: 508.9396
- Similarity Product: 479.20373743124014

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test