PATENT CLAIM ANALYSIS

Application Number: 15916193
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["711", "149000"]

Abstract:
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Claim (Index 13):
A dynamic random access memory (DRAM) device, comprising:\n memory arrays; for each one of said memory arrays, a command link for receiving data access commands respective to the one of said memory arrays from a memory controller and data links for exchanging corresponding data with the memory controller; for each one of said memory arrays, circuitry to control performance of data access commands received via the respective command link independent of whether another of said memory arrays is subject to an outstanding data access command from the memory controller; and circuitry to implement a selected one of two mode settings, including\n a first setting corresponding to a mode in which, for each one of said memory arrays, each of the corresponding data links is to be used for exchanging data in association with the data access commands respective to the one of said memory arrays, and \n a second setting corresponding to a mode in which, for each one of said memory arrays, only one-half of the corresponding data links are to be used to exchange data in association with the data access commands respective to the one of said memory arrays; \n wherein the selected one of said two mode settings is to be determined by reading at least one input pin, and wherein the circuitry to implement is to configure each of said memory arrays to data using a same column size but with double addressable row depth when the selected one of said two mode settings is the second setting, relative to when the selected one of said two mode settings is the first setting.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 90.0
- Lexical Diversity: 2.04918
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15169331', '14305799', '12820973', '14449610', '12627769']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5024487530895857
- 35 USC 102 Novelty (BERT): 0.4871015641117502
- Combined Prediction Score: 0.5009140341918021
- Mean Citation Score: 217.57258199999995
- Max Citation Score: 248.19466
- Similarity Product: 201.8442789597237

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test