PATENT CLAIM ANALYSIS

Application Number: 16018073
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.

Claim (Index 11):
The method of forming a semiconductor structure having a metal gate according to  claim 6 , wherein the method of forming the dielectric layer having the recess on the substrate comprises:\n forming a dummy gate on the substrate; depositing the bottom part on the substrate beside the dummy gate by a flowable chemical vapor deposition process; depositing the top part on the bottom part beside the dummy gate by a high density plasma deposition process; and removing the dummy gate.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 94.0
- Lexical Diversity: 1.90698
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14048131', '13075443', '15928325', '14052924', '15822724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9209459051595456
- 35 USC 102 Novelty (BERT): 0.4802445477764009
- Combined Prediction Score: 0.8768757694212311
- Mean Citation Score: 183.191146
- Max Citation Score: 183.48534
- Similarity Product: 134.9926602427268

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test