PATENT CLAIM ANALYSIS

Application Number: 15901881
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["365", "185110"]

Abstract:
A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.

Claim (Index 5):
The semiconductor storage device according to  claim 4 , wherein the first command follows an input of a first column address and the second command follows an input of a second column address that is the same as the first column address.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 88.0
- Lexical Diversity: 3.15217
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14013833', '15411225', '15405098', '14014252', '15439912']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7865806401011215
- 35 USC 102 Novelty (BERT): 0.4982243482550723
- Combined Prediction Score: 0.7577450109165166
- Mean Citation Score: 222.74659000000003
- Max Citation Score: 225.74733
- Similarity Product: 153.19777902248742

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test