PATENT CLAIM ANALYSIS

Application Number: 15901749
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["716", "119000"]

Abstract:
Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation. An annotated netlist is developed for the plurality of the transistors interconnects endpoints identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation.

Claim (Index 27):
A non-transitory computer readable medium having stored thereon a plurality of instructions which when executed by a processor aids development of an integrated circuit fabrication process when provided with a layout of a circuit design, the circuit design including at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design, the plurality of instructions comprising instructions that cause the processor to:\n identify, from the layout, locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout; synthesize by simulation of the fabrication process under test, a three-dimensional circuit representation fabricated in accordance with the layout of the circuit design, the three-dimensional circuit representation including at least the interconnects provided in the layout of the circuit design and the locations of the plurality of interconnect endpoints identified from the layout; estimate, from the three-dimensional circuit representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect; estimate, from the three-dimensional circuit representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design; develop an annotated netlist that includes the plurality of the transistors identified from the layout and the plurality of the interconnects identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation; and write the annotated netlist into a storage device in conjunction with the parasitic resistance values and parasitic capacitance values for use by a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test.

Metadata:
- Claim Count in Document: 107.0
- Percentile: 88.0
- Lexical Diversity: 2.28169
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15227863', '13527096', '12893870', '12704048', '13850120']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3206969991022557
- 35 USC 102 Novelty (BERT): 0.4845732323844685
- Combined Prediction Score: 0.337084622430477
- Mean Citation Score: 238.422276
- Max Citation Score: 242.59665
- Similarity Product: 175.52684935025275

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test