PATENT CLAIM ANALYSIS

Application Number: 16042424
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "324000"]

Abstract:
According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.

Claim (Index 11):
A manufacturing method of a semiconductor device, the method comprising:\n forming a stacked body above a semiconductor substrate, the stacked body including first films and second films, which are different from each other in etching rate and are alternately stacked; forming a first slit in the stacked body, as penetrating some layers from an uppermost layer of the first films; embedding a third film into the slit; etching the stacked body through a mask layer including hole patterns formed therein in a row direction and a column direction, thereby forming memory holes penetrating the stacked body; embedding columnar bodies respectively into the memory holes; forming a second slit in the stacked body, as penetrating all layers of the first films and the second films; making an etchant infiltrate into the stacked body through the second slit, thereby removing the first films, while leaving the columnar bodies, the second films, and the third film in the stacked body; and making a source material infiltrate into gap spaces formed by removing the first films, thereby embedding fourth films respectively into the gap spaces, wherein the memory holes include a first memory hole, a second memory hole, and a third memory hole sequentially arrayed side by side in a first direction between the first slit and the second slit, wherein the memory holes are not arranged at a position of the first slit, and wherein a first distance between the first memory hole and the second memory hole is larger than a second distance between the second memory hole and the third memory hole.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 95.0
- Lexical Diversity: 1.75862
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15257613', '14844250', '14965159', '15267924', '15213537']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8969849815330645
- 35 USC 102 Novelty (BERT): 0.5034925750381125
- Combined Prediction Score: 0.8576357408835693
- Mean Citation Score: 205.90059
- Max Citation Score: 267.39197
- Similarity Product: 218.04703255834224

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test