PATENT CLAIM ANALYSIS

Application Number: 15863090
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "401000"]

Abstract:
A memory circuit layout design includes first, second, third, and fourth memory cell regions abutting one another and corresponding to respective first, second, third, and fourth memory cells of the memory circuit. A first oxide diffusion (OD) layout pattern corresponds to a first active structure for forming the first and second memory cells, extends along a first direction, and has a shared source portion overlapping the first and second memory cell regions. A second OD layout pattern corresponds to a second active structure for forming the third and fourth memory cells, extends along the first direction, and has a shared source portion overlapping the third and fourth memory cell regions. A first conductive layout pattern corresponds to a first conductive structure under a lowest via plug layer of the memory circuit, extends along a second direction, and overlaps the shared source portions of the first and second OD layout patterns.

Claim (Index 15):
A layout design for fabricating a memory circuit, the layout design comprising:\n a first memory cell region corresponding to a first memory cell of the memory circuit; a second memory cell region corresponding to a second memory cell of the memory circuit; a third memory cell region corresponding to a third memory cell of the memory circuit; a fourth memory cell region corresponding to a fourth memory cell of the memory circuit, the first, second, third, and fourth memory cell regions abutting one another; a first gate layout pattern corresponding to a gate structure of the first memory cell and a gate structure of the third memory cell, the first gate layout pattern extending along a first direction; a second gate layout pattern corresponding to a gate structure of the second memory cell and a gate structure of the fourth memory cell, the second gate layout pattern extending along the first direction; and a first conductive layout pattern corresponding to a first conductive structure, wherein the first conductive structure is under a lowest via plug layer of the memory circuit, the first conductive layout pattern extends along the first direction between the first gate layout pattern and the second gate layout pattern, and the first conductive layout pattern overlaps the first memory cell region, the second memory cell region, the third memory cell region, and the fourth memory cell region.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 86.0
- Lexical Diversity: 3.16981
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14995413', '14688321', '14330684', '15606621', '13965648']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907746503972894
- 35 USC 102 Novelty (BERT): 0.4929596461593976
- Combined Prediction Score: 0.8662678181915445
- Mean Citation Score: 168.812378
- Max Citation Score: 176.13162
- Similarity Product: 109.93810035737516

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test