PATENT CLAIM ANALYSIS

Application Number: 15755687
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["257", "072000"]

Abstract:
The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.

Claim (Index 6):
The array substrate according to  claim 4 , wherein the array substrate is configured in any one of the following manners:\n the insulating layer is located between the conductive pattern layer and an active layer of the array substrate; the array substrate comprises a gate insulating layer disposed between the conductive pattern layer and an active layer of the array substrate, a source/drain pattern layer disposed above the active layer and a passivation layer disposed on the source/drain pattern layer, the insulating layer comprises the gate insulating layer and the passivation layer, and the common electrode layer is disposed on the passivation layer; the array substrate comprises a gate insulating layer disposed between the conductive pattern layer and the active layer of the array substrate, a source/drain pattern layer disposed above the active layer and a planarization layer disposed on the source/drain pattern layer, the insulating layer comprises the gate insulating layer and the planarization layer, and the common electrode layer is disposed on the planarization layer; the array substrate comprises a gate insulating layer disposed between the conductive pattern layer and an active layer of the array substrate, a source/drain pattern layer disposed above the active layer, a passivation layer disposed on the source/drain pattern layer, and a planarization layer disposed above the passivation layer, the insulating layer comprises the gate insulating layer, the passivation layer, and the planarization layer, and the common electrode layer is disposed on the planarization layer; an active layer of the array substrate is disposed under the conductive pattern layer, the insulating layer is disposed above the conductive pattern layer, the array substrate further comprises a source/drain pattern layer disposed above the insulating layer, and the common electrode layer is disposed on the insulating layer; an active layer of the array substrate is disposed under the conductive pattern layer, the array substrate further comprises an interlayer insulating layer disposed above the conductive pattern layer, a source/drain pattern layer disposed on the interlayer insulating layer, a passivation layer disposed on the source/drain pattern layer, the common electrode layer is disposed on the passivation layer, and the insulating layer comprises the passivation layer and the interlayer insulating layer; an active layer of the array substrate is disposed under the conductive pattern layer, the array substrate further comprises an interlayer insulating layer disposed above the conductive pattern layer, a source/drain pattern layer disposed on the interlayer insulating layer, and a planarization layer disposed on the source/drain pattern layer, the common electrode layer is disposed on the planarization layer, and the insulating layer comprises the planarization layer and the interlayer insulating layer; an active layer of the array substrate is disposed under the conductive pattern layer, the array substrate further comprises an interlayer insulating layer disposed above the conductive pattern layer, a source/drain pattern layer disposed on the interlayer insulating layer, a passivation layer disposed on the source/drain pattern layer and a planarization layer disposed on the passivation layer, the common electrode layer is disposed on the planarization layer, and the insulating layer comprises the interlayer insulating layer, the passivation layer, and the planarization layer.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 88.0
- Lexical Diversity: 2.75439
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14436563', '14134058', '14432025', '15576837', '15064378']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.931226968197905
- 35 USC 102 Novelty (BERT): 0.5088074098110308
- Combined Prediction Score: 0.8889850123592176
- Mean Citation Score: 267.86939
- Max Citation Score: 273.13358
- Similarity Product: 190.2901727187109

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test