PATENT CLAIM ANALYSIS

Application Number: 16368485
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["345", "213000"]

Abstract:
A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Claim (Index 8):
The semiconductor device according to  claim 7 , wherein:\n the comparator circuit includes\n first conductivity-type first to Nth differential pairs for generating first to Nth pairs of currents each of which corresponds to the difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the first to Nth pairs of currents into a fifth common wire and flowing the other of each of the first to Nth pairs of currents into a sixth common wire, \n at least one first current supply connected to a fifth power supply terminal at one end, the at least one first current supply driving one or a plurality of the first to Nth differential pairs in common, \n a first pair of load elements connected between the third power supply terminal and the fifth and sixth common wires, \n second conductivity-type (N+1)th to (2N)th differential pairs for generating (N+1)th to (2N)th pairs of currents each of which corresponds to the difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the (N+1)th to (2N)th pairs of currents into a seventh common wire and flowing the other of each of the (N+1)th to (2N)th pairs of currents into an eighth common wire, \n at least one second current supply connected to a sixth power supply terminal at one end, the at least one second current supply driving one or a plurality of the (N+1)th to (2N)th differential pairs in common, and \n a second pair of load elements connected between the fourth power supply terminal and the seventh and eighth common wires; \n one of a pair of connection points between the seventh and eighth common wires and the second pair of load elements is connected to the control terminal of the first current control transistor through the first output terminal; one of a pair of connection points between the third and fourth common wires and the first pair of load elements is connected to the control terminal of the second current control transistor through the second output terminal; the other of the pair of connection points between the third and fourth common wires and the first pair of load elements is connected to the control terminal of the third current control transistor through the third output terminal; and the other of the pair of connection points between the seventh and eighth common wires and the second pair of load elements is connected to the control terminal of the fourth current control transistor through the fourth output terminal.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 99.0
- Lexical Diversity: 1.85714
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15442107', '13155023', '13029888', '15818628', '16243249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.689262779032282
- 35 USC 102 Novelty (BERT): 0.6134529232637
- Combined Prediction Score: 0.6816817934554238
- Mean Citation Score: 296.590204
- Max Citation Score: 540.95166
- Similarity Product: 520.1233385092055

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test