PATENT CLAIM ANALYSIS

Application Number: 15944811
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["331", "057000"]

Abstract:
The present utility model relates to an ultra-low voltage two-stage ring voltage-controlled oscillator applied to a chip circuit. The oscillator includes two-stage delay units. The oscillator includes two delay units that are connected end-to-end, and adjusts a working frequency by adjusting delay time of the delay unit. The delay unit includes PMOS transistors M 1 , M 2 , M 3 , and M 4 , NMOS transistors M 5 , M 6 , M 7 , and M 8 , and a load capacitor C L . The two-stage ring voltage-controlled oscillator of the present utility model uses a substrate feed forward bias structure, reduces a threshold voltage of a transistor, reduces a supply voltage, reduces power consumption, has a large tuning range, and is particularly suitable for a system that works at a low supply voltage.

Claim (Index 2):
The ultra-low voltage two-stage ring voltage-controlled oscillator according to  claim 1 , wherein substrates of the PMOS transistors M 2  and M 4  are grounded, substrates of the PMOS transistors M 1  and M 3  are connected to a control voltage Vc, gate electrodes of the PMOS transistors M 1  and M 3  are grounded, source electrodes of the PMOS transistors M 1  and M 3  are connected to a VDD, and drain electrodes of the PMOS transistors M 1  and M 3  are connected to gate electrodes and drain electrodes of the PMOS transistors M 2  and M 4 ; the NMOS transistor M 5  and the NMOS transistor M 6  are used as non-inverting and inverting differential input ends of the delay unit respectively, source electrodes and drain electrodes of the NMOS transistor M 7  and the NMOS transistor M 8  are connected to source electrodes and drain electrodes of the NMOS transistor M 5  and the NMOS transistor M 6  respectively, a gate electrode of the NMOS transistor M 7  is connected to the drain electrode of the NMOS transistor M 6 , and a gate electrode of the NMOS transistor M 8  is connected to the drain electrode of the NMOS transistor M 5 ; the drain electrode of the NMOS transistor M 5  is used as an inverting output end, the drain electrode of the NMOS transistor M 6  is used as a non-inverting output end, and the output ends are connected to the load capacitor C L ; and substrate ends of the NMOS transistors are connected to a bias voltage V B .

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.92208
- Patent Class: 331.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14651340', '11093619', '10880893', '10616326', '11360522']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.785165529726631
- 35 USC 102 Novelty (BERT): 0.4870073014081982
- Combined Prediction Score: 0.7553497068947876
- Mean Citation Score: 213.455224
- Max Citation Score: 221.22932000000003
- Similarity Product: 168.7742119881201

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test