PATENT CLAIM ANALYSIS

Application Number: 15990611
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "324000"]

Abstract:
A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.

Claim (Index 3):
The device according to  claim 1 ,\n wherein at least one of said first memory cells is self-aligned to at least one of said third memory cells.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 3.75
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15761426', '15333138', '15911071', '15344562', '15727592']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.929575052563246
- 35 USC 102 Novelty (BERT): 0.5369985463232396
- Combined Prediction Score: 0.8903174019392455
- Mean Citation Score: 302.632014
- Max Citation Score: 379.37946
- Similarity Product: 282.01661694989207

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test