PATENT CLAIM ANALYSIS

Application Number: 16215719
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["710", "109000"]

Abstract:
The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

Claim (Index 15):
A method, comprising:\n determining a change in an operation state of at least one of a number of serialization/deserialization (SERDES) components that has been operating on a logic die, wherein the number of SERDES components are located on a number of respective link interface controllers that are configured to control a number of respective input/output (I/O) links; and responsive to determining the change in the operation state of the at least one of the number of SERDES components, placing the at least one of the number of SERDES components in an inactive state.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 98.0
- Lexical Diversity: 1.85714
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15170183', '14718649', '12329982', '12359039', '14821005']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6245284969070533
- 35 USC 102 Novelty (BERT): 0.5074884297617477
- Combined Prediction Score: 0.6128244901925227
- Mean Citation Score: 144.6154
- Max Citation Score: 260.16675
- Similarity Product: 174.28173602025208

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test