PATENT CLAIM ANALYSIS

Application Number: 16209520
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "185180"]

Abstract:
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Claim (Index 11):
The method of performing a reading operation in a nonvolatile semiconductor memory device according to  claim 8 , wherein\n the first operation further includes setting the source line voltage of the source line to a positive value.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 2.96078
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15263518', '15915129', '13749029', '13246004', '14088744']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8357254106628994
- 35 USC 102 Novelty (BERT): 0.5452531504318073
- Combined Prediction Score: 0.8066781846397901
- Mean Citation Score: 395.541526
- Max Citation Score: 406.444
- Similarity Product: 332.023285964489

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test