PATENT CLAIM ANALYSIS

Application Number: 15900696
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "737000"]

Abstract:
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Claim (Index 33):
The method of  claim 32 , wherein the providing the first metal bump including the solder resistant coating that covers the first portion of the first metal bump and leaves the second portion of the first metal bump uncovered comprises positioning the solder resistant coating to cover an outer portion of a surface of the first metal bump and to cover sidewalls of the first metal bump, while leaving a central portion of the surface of the first metal bump exposed.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 88.0
- Lexical Diversity: 1.85714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13977658', '12969451', '13313747', '11330107', '15803008']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9269587800969192
- 35 USC 102 Novelty (BERT): 0.4912470025358464
- Combined Prediction Score: 0.8833876023408118
- Mean Citation Score: 157.34882
- Max Citation Score: 227.88513
- Similarity Product: 173.50877332115292

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test