PATENT CLAIM ANALYSIS

Application Number: 16101438
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["438", "199000"]

Abstract:
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel.

Claim (Index 1):
A 3D semiconductor device, the device comprising:\n a first single crystal layer comprising a plurality of first transistors; at least one first metal layer interconnecting said plurality of first transistors,\n wherein said interconnecting comprises forming memory peripheral circuits; \n a plurality of second transistors underlying said first single crystal layer; a second metal layer overlaying said plurality of second transistors; a first memory cell underlying said memory peripheral circuits; a second memory cell underlying said first memory cell; a staircase structure underlying said first single crystal layer; and a non-volatile NAND memory,\n wherein said first memory cell comprises at least one of said second transistors, \n wherein said memory peripheral circuits control at least said first memory cell, \n wherein at least one of said second transistors comprises a source, channel and drain, \n wherein said source, said channel and said drain have the same dopant type, \n wherein said non-volatile NAND memory comprises said first memory cell, \n wherein at least one of said second transistors comprises a polysilicon channel, \n wherein said non-volatile NAND memory comprises a memory array structure, \n wherein said memory array structure comprises wordlines and bitlines, said bitlines are orthogonally oriented to said wordlines, \n wherein said wordlines and bitlines are adapted to function as memory control lines, \n wherein said wordlines and bitlines are connected to said memory peripheral circuits, and \n wherein said connected to comprises said staircase structure.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 96.0
- Lexical Diversity: 3.6
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15950169', '16004404', '16024911', '15990684', '15904377']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8803005931768294
- 35 USC 102 Novelty (BERT): 0.5277437890705933
- Combined Prediction Score: 0.8450449127662059
- Mean Citation Score: 336.533492
- Max Citation Score: 364.4499
- Similarity Product: 337.10679927173857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test