PATENT CLAIM ANALYSIS

Application Number: 16040791
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["363", "098000"]

Abstract:
Inverter circuit operation for managing power factor changes is provided. Various modes of switch timing may be employed near zero-voltage crossings. Inverter switch timing may change during a cycle such that one timing strategy is employed approaching or leaving a zero-voltage crossing while another timing strategy is employed at other times of the cycle.

Claim (Index 9):
A system comprising:\n an inverter circuit with two or more switches, the inverter circuit configured to receive a dc input voltage and output an alternating output voltage; and a gate controller configured to send gate command signals to one or more of the switches in the inverter circuit for purposes of converting the dc input voltage to the alternating output voltage,\n wherein the gate controller is also configured to send gate command signals when a non-unity power factor exists for the system, that create three different output current rate changes during a single current cycle, the current rate changes having durations of T 1 , T 2 , and T 3 , and \n wherein the cumulative absolute sum of T 1  plus T 2  are equal to or less than the duration of T 3 .

Metadata:
- Claim Count in Document: 25.0
- Percentile: 95.0
- Lexical Diversity: 1.425
- Patent Class: 363.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15395911', '11688083', '15209958', '12960208', '11045821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8053398918673166
- 35 USC 102 Novelty (BERT): 0.5074254559433464
- Combined Prediction Score: 0.7755484482749196
- Mean Citation Score: 203.469372
- Max Citation Score: 310.33914
- Similarity Product: 257.23196784455536

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test