PATENT CLAIM ANALYSIS

Application Number: 16296025
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["365", "193000"]

Abstract:
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Claim (Index 19):
The apparatus of  claim 18 , wherein the DQS delay element is configured such that at least one loop of the one or more loops associated with the one or more read data capture calibration results is for one adjustment of the delay of the DQS delay element, and a DQS delay element delay tap setting of the DQS delay element is determined using at least one of the one or more pre-determined calibration data patterns.

Metadata:
- Claim Count in Document: 140.0
- Percentile: 99.0
- Lexical Diversity: 2.11475
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16049693', '15996365', '15926902', '15722209', '13172740']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8693341788050251
- 35 USC 102 Novelty (BERT): 0.657507899980707
- Combined Prediction Score: 0.8481515509225933
- Mean Citation Score: 610.763472
- Max Citation Score: 639.74554
- Similarity Product: 634.0408693462896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test