PATENT CLAIM ANALYSIS

Application Number: 16374126
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-10
Patent Classification: ["718", "100000"]

Abstract:
Disclosed is a data accelerated processing system including a processing device, a storage device, an interface device and a control device. The processing device is configured to realize accelerated operation processing of data. The storage device is electrically connected to the processing device for storing the data sent by a server. The interface device is electrically connected to the processing device for data transmission between the processing device and the server. The control device is configured to regulate the status of the processing device. During an operation process, a large number of operating tasks in the server may be transmitted to the processing device for operating through the interface device, and large amounts of buffered data may be stored in the storage device. The data accelerated processing system improves data reading speed and operation efficiency through the cooperation of the processing device, the storage device and the interface device.

Claim (Index 18):
The data accelerated processing system of  claim 1 ,\n wherein each of the one or more processors includes a primary processing circuit, one or more branch processing circuits, and a plurality of secondary processing circuits, wherein the primary processing circuit is configured to divide input data into a plurality of data blocks, wherein the input data includes input neuron data and weight data, wherein the primary processing circuit is configured to\n determine the input neuron data as broadcast data, \n determine the weight data as distribution data, \n divide distribution data into the data blocks, \n send at least one of the data blocks, the broadcast data, and at least one of a plurality of operation instructions to the one or more branch processing circuits, \n wherein the one or more branch processing circuits are configured to forward the data blocks, the broadcast data, and the plurality of operation instructions between the primary processing circuit and the plurality of secondary processing circuits, wherein the secondary processing circuits are configured to process the received data blocks and the broadcast data according to the operation instructions to obtain intermediate results and to transmit the intermediate results to the one or more branch processing circuits, and wherein the primary processing circuit is configured to process the intermediate results to obtain the result of the operation instructions.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 100.0
- Lexical Diversity: 3.03774
- Patent Class: 718.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15094939', '14725811', '15201175', '15700018', '15144734']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4283712604356469
- 35 USC 102 Novelty (BERT): 0.516463055474673
- Combined Prediction Score: 0.4371804399395495
- Mean Citation Score: 148.094162
- Max Citation Score: 149.59808
- Similarity Product: 90.25217023029327

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test