PATENT CLAIM ANALYSIS

Application Number: 15871586
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "619000"]

Abstract:
A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

Claim (Index 12):
The method of  claim 7 , wherein the first stencil includes a notch disposed over the edge support ring.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 86.0
- Lexical Diversity: 3.20833
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15240568', '13195636', '12794612', '12036000', '13434660']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9313125684780996
- 35 USC 102 Novelty (BERT): 0.575734303665112
- Combined Prediction Score: 0.8957547419968008
- Mean Citation Score: 291.355606
- Max Citation Score: 499.7683
- Similarity Product: 370.3372749739528

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test