PATENT CLAIM ANALYSIS

Application Number: 15914135
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "347000"]

Abstract:
Systems and methods for forming a low contact resistance nanowire transistor are described. The transistor includes a gate formed over a substrate including a gate conductor. Gate spacers are formed on sides of the gate. At least one semiconductor nanowire is formed through the gate such that the at least one semiconductor nanowire extends through the gate conductor and the gate spacers and into source and drain regions grown from surfaces of the at least one semiconductor nanowire adjacent to sides of the gate to increase the surface area of the source drain region contacting the semiconductor nanowire.

Claim (Index 13):
The method as recited in  claim 10 , wherein the oxide fill include germanium oxide (GeO 2 ) and the first nanowires include silicon germanium (SiGe).

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 1.96154
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14754751', '14948509', '15821041', '15198622', '15180314']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9276043370335768
- 35 USC 102 Novelty (BERT): 0.5353866347206926
- Combined Prediction Score: 0.8883825668022883
- Mean Citation Score: 339.614576
- Max Citation Score: 352.64972
- Similarity Product: 263.0947440644884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test