PATENT CLAIM ANALYSIS

Application Number: 16026271
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["330", "277000"]

Abstract:
Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.

Claim (Index 15):
The amplifier system of  claim 17 , wherein both of the first and second semiconductor dies are coupled to a substrate that forms a portion of a first package.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 95.0
- Lexical Diversity: 2.85455
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15846162', '15379789', '15804268', '14797275', '15913896']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7689224657428717
- 35 USC 102 Novelty (BERT): 0.4991811362551721
- Combined Prediction Score: 0.7419483327941018
- Mean Citation Score: 217.082734
- Max Citation Score: 240.19934
- Similarity Product: 193.4859445739281

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test