PATENT CLAIM ANALYSIS

Application Number: 15952308
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["257", "296000"]

Abstract:
Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

Claim (Index 5):
The semiconductor memory device of  claim 1 , wherein the gate line structure further comprises capping insulating patterns in the first trench portions on the top surface of the gate electrode.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 2.41667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13349714', '14089356', '14159940', '15059673', '14978155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.929923052811131
- 35 USC 102 Novelty (BERT): 0.5014674688955197
- Combined Prediction Score: 0.8870774944195698
- Mean Citation Score: 253.128034
- Max Citation Score: 262.8075
- Similarity Product: 197.8345590618253

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test