PATENT CLAIM ANALYSIS

Application Number: 15909404
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["365", "185030"]

Abstract:
A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.

Claim (Index 14):
The semiconductor memory device according to  claim 13 , wherein\n each of the sense amplifier units further includes a transistor having one end connected to a bit line and another end connected to a power supply line and a control signal generated by the controller is input to a gate of the transistor, the controller is configured to, during the verification operation: set a voltage of the control signal to a first voltage when determining data stored in the corresponding memory cell based on the first verification voltage and the second verification voltage, between the determination of data based on the first verification voltage and the determination of data based on the second verification voltage, temporarily set the voltage of the control signal to be higher than the first voltage by a kick voltage amount, and mirror the verification result stored in the first latch circuit of the sense amplifier unit corresponding to the first memory cell in the second latch circuit and the third latch circuit, while the control signal is temporarily set higher by the kick voltage amount between the determination of data based on the first verification voltage and the determination of data based on the second verification voltage.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.51282
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15405098', '15690256', '15908449', '15195560', '14630505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.793593580587044
- 35 USC 102 Novelty (BERT): 0.5045791353897204
- Combined Prediction Score: 0.7646921360673116
- Mean Citation Score: 251.253478
- Max Citation Score: 284.98608
- Similarity Product: 229.09295553849225

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test