PATENT CLAIM ANALYSIS

Application Number: 15986079
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "351000"]

Abstract:
Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.

Claim (Index 11):
The integrated chip of  claim 9 , further comprising first and second source/drain regions at opposite ends of the respective first and second nanosheet channel layers.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 93.0
- Lexical Diversity: 2.91111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15057439', '15626734', '15398232', '15470352', '15847894']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9358713504064144
- 35 USC 102 Novelty (BERT): 0.565286874549524
- Combined Prediction Score: 0.8988129028207253
- Mean Citation Score: 389.854998
- Max Citation Score: 480.51694
- Similarity Product: 355.24643756036164

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test