PATENT CLAIM ANALYSIS

Application Number: 16021822
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Claim (Index 3):
The semiconductor structure according to  claim 2 , wherein:\n the metal fill is maintained separated from the gate electrode of the first gate to keep the first gate electrically separated from the contact and from the conductive metal trenches.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 2.58621
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14870534', '15597871', '16016477', '11228741', '10383231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9287327840811022
- 35 USC 102 Novelty (BERT): 0.5320032602380751
- Combined Prediction Score: 0.8890598316967995
- Mean Citation Score: 277.25392200000005
- Max Citation Score: 353.4396
- Similarity Product: 313.0399746057987

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test