PATENT CLAIM ANALYSIS

Application Number: 16003950
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["712", "215000"]

Abstract:
Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where each load/store slice includes a load miss queue and a load reorder queue, includes: receiving, at a load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; and if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction.

Claim (Index 19):
The apparatus of  claim 18 , wherein propagating the data for the previous load instruction to the results bus without accessing the data cache for the cache line is in dependence upon determining that the previous load instruction is the oldest load instruction among the multiple entries.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.50943
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15077015', '15135685', '15180838', '15219638', '15997863']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6110289914272145
- 35 USC 102 Novelty (BERT): 0.5568826075094324
- Combined Prediction Score: 0.6056143530354363
- Mean Citation Score: 325.77904
- Max Citation Score: 430.5251
- Similarity Product: 338.1654265912414

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test