PATENT CLAIM ANALYSIS

Application Number: 16371174
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-07
Patent Classification: ["375", "240020"]

Abstract:
Power consumption of a decoder is reduced. The decoder includes an FPGA. The FPGA performs at least one processing to decode the data. In the case where the data has first resolution, an input data signal of the FPGA is a binary signal and a clock frequency of the FPGA is a first frequency. In the case where the resolution of the data is lower than the first resolution, the input data signal of the FPGA is a pulse signal and the FPGA operates at a second frequency which is lower than the first frequency. The FPGA operates at the first clock frequency in the case of decoding 8K data and the FPGA operates at the second clock frequency in the case of decoding 4K or 2K data.

Claim (Index 2):
The display device according to  claim 1 ,\n wherein the second signals are used when the display device displays image for a 8k broadcast, and wherein the binary data signal is used when the display device displays image for a 4K broadcast or a 2K broadcast.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 100.0
- Lexical Diversity: 2.95652
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15083716', '15729191', '15876724', '15729169', '15210068']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4886188330629178
- 35 USC 102 Novelty (BERT): 0.4965907855176905
- Combined Prediction Score: 0.4894160283083951
- Mean Citation Score: 203.097034
- Max Citation Score: 208.0487
- Similarity Product: 138.26432041400074

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test