PATENT CLAIM ANALYSIS

Application Number: 15913286
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-12
Patent Classification: ["257", "318000"]

Abstract:
Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

Claim (Index 10):
A method for forming a hybrid electrically erasable programmable read only memory (EEPROM) cell, the method comprising:\n forming a programming region having a programmable capacitor disposed on a substrate, wherein forming the programming region comprises:\n forming a floating gate having a first polysilicon layer, the floating gate having first and second opposing surfaces; \n disposing an oxide-nitride-oxide (ONO) layer over the first surface of the floating gate, the ONO layer having first and second opposing surfaces; and \n forming a control gate having a second polysilicon layer, the control gate formed over the first surface of the ONO layer to form a hybrid EEPROM comprising a single polysilicon layer and a double polysilicon EEPROM, the single polysilicon EEPROM comprising the first polysilicon layer and the double polysilicon EEPROM comprising the first and second polysilicon layers; and \n coupling a drain region to the programming region through a liner region, wherein the drain region is configured to operate as a drain node or a read node for the hybrid EEPROM cell.

Metadata:
- Claim Count in Document: 63.0
- Percentile: 90.0
- Lexical Diversity: 2.65
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15624886', '11502129', '10842008', '10983443', '14277784']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9172174993134496
- 35 USC 102 Novelty (BERT): 0.5270885591502595
- Combined Prediction Score: 0.8782046052971305
- Mean Citation Score: 232.29606400000003
- Max Citation Score: 357.55338
- Similarity Product: 351.7345650995922

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test