PATENT CLAIM ANALYSIS

Application Number: 15871478
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "324000"]

Abstract:
A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.

Claim (Index 4):
The vertical memory device of  claim 1 , wherein the first one of the conductive pads is a lower one of the steps than the second one of the conductive pads.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.19697
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15295034', '14790724', '14682567', '15001877', '14965532']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9255918075794866
- 35 USC 102 Novelty (BERT): 0.5019926383078258
- Combined Prediction Score: 0.8832318906523204
- Mean Citation Score: 226.049328
- Max Citation Score: 242.20572
- Similarity Product: 166.75657066991332

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test