PATENT CLAIM ANALYSIS

Application Number: 16077176
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "347000"]

Abstract:
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Claim (Index 11):
The multilayer structure of  claim 1  wherein the polycrystalline silicon comprising grains having a plurality of crystal orientations comprise at least two orientations selected from the group consisting of (111), (100), and (110).

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 1.12903
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15435428', '15984586', '15526798', '16077142', '15828534']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9271050687907568
- 35 USC 102 Novelty (BERT): 0.5652393010141128
- Combined Prediction Score: 0.8909184920130925
- Mean Citation Score: 410.202564
- Max Citation Score: 431.36313
- Similarity Product: 409.866805579446

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test