PATENT CLAIM ANALYSIS

Application Number: 16048304
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["716", "112000"]

Abstract:
Identifying and resolving issues with placement of plated through vias in voltage divider regions of a printed circuit board (“PCB”) layout. Search parameters indicate an area of the PCB layout to be analyzed, and vias meeting the search parameters are evaluated for placement issues. Upon detecting a placement issue for a via, a solution is determined that addresses and resolves the placement issue of the via. The resolution in an embodiment includes modifying an adjacent power shape, modifying a region between shapes, and/or modifying via placement to minimize risks that include potential shorting, partially-connected vias, and/or poor plated barrel adhesion.

Claim (Index 11):
The computer-implemented method according to  claim 1 , wherein the predetermined set of resolutions comprises:\n determining whether the voltage boundary can be adjusted without causing any net of the PCB layout to cross the voltage boundary, and if so, then selecting, as the resolution, an adjusting of the voltage boundary to fully connect a particular via identified as having a placement issue to the voltage shape and an adjusting of the voltage shape; determining that the voltage boundary cannot be adjusted without causing any net of the PCB layout to cross a voltage boundary, but that a particular one of the any net can be moved without causing the particular net to cross the voltage boundary, and then selecting, as the resolution, a moving of the particular net to a different location that does not cross the voltage boundary, an adjusting of the voltage shape, and an adjusting of the voltage boundary to fully connect the particular via to the voltage shape; determining that the voltage boundary cannot be adjusted without causing any of one or more net of the PCB layout to cross a voltage boundary and that at least a particular one of the one or more net cannot be moved without causing the particular net to cross the voltage boundary, but that a width of the voltage boundary can be reduced around the particular via, and then selecting, as the resolution, a voiding of the voltage boundary around the particular via that causes the particular via to be fully connected to the voltage shape; and determining that the voltage boundary cannot be adjusted without causing any of one or more net of the PCB layout to cross a voltage boundary and that at least a particular one of the one or more net cannot be moved without causing the particular net to cross the voltage boundary and that a width of the voltage boundary cannot be reduced around the particular via, and that the particular via is not critical to the PCB layout and then selecting, as the resolution, a deletion of the particular via from the PCB layout or a disconnecting of the particular via from a layer of the PCB layout on which the particular via is located.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 95.0
- Lexical Diversity: 1.60563
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15597496', '15666900', '11696659', '15813233', '15139653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3281576485116433
- 35 USC 102 Novelty (BERT): 0.4573616690467451
- Combined Prediction Score: 0.3410780505651535
- Mean Citation Score: 113.568706
- Max Citation Score: 118.478645
- Similarity Product: 78.95818905546489

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test