PATENT CLAIM ANALYSIS

Application Number: 15997725
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "296000"]

Abstract:
Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

Claim (Index 2):
A nonvolatile memory device, comprising:\n a substrate having a cell region and a peripheral circuit region; a memory cell string including a plurality of vertical memory cells formed in the cell region and a plurality of channel holes formed to penetrate the vertical memory cells in a first direction vertical to an upper surface of the substrate; an insulating layer formed in the peripheral circuit region on the substrate at substantially same level as an upper surface of the memory cell string; and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, wherein the plurality of capacitor electrodes are spaced apart from each other in a direction parallel to the upper surface of the substrate, and are spaced apart from the substrate and have a pitch that is substantially the same as a pitch of the plurality of channel holes.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 2.58333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15589528', '14702038', '12264490', '09756864', '14731764']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9158999872109786
- 35 USC 102 Novelty (BERT): 0.5181684749999551
- Combined Prediction Score: 0.8761268359898763
- Mean Citation Score: 258.41226800000004
- Max Citation Score: 337.76587
- Similarity Product: 313.80946418871764

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test