PATENT CLAIM ANALYSIS

Application Number: 15925617
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189090"]

Abstract:
A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2 n-1  bytes, n being a number of registers included in the linear feedback shift register circuit.

Claim (Index 8):
The semiconductor memory device according to  claim 2 , wherein\n the value set in the linear feedback shift register circuit is equal to the selected initial value.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.10938
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14722751', '12341108', '12350398', '13446155', '13616168']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7581848553234796
- 35 USC 102 Novelty (BERT): 0.4851779534294221
- Combined Prediction Score: 0.7308841651340738
- Mean Citation Score: 141.48500399999998
- Max Citation Score: 150.0143
- Similarity Product: 97.43743713511228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test