PATENT CLAIM ANALYSIS

Application Number: 16057113
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["365", "154000"]

Abstract:
A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Claim (Index 9):
A static random access memory circuit in a semiconductor device comprising:\n a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells; a plurality of I/O circuits; and an operating control circuit coupled to a precharge circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.74545
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14634743', '15181175', '15619821', '15894757', '14942861']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8241973350976358
- 35 USC 102 Novelty (BERT): 0.5016102129568262
- Combined Prediction Score: 0.7919386228835548
- Mean Citation Score: 317.228008
- Max Citation Score: 317.2352
- Similarity Product: 292.07663773193366

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test