PATENT CLAIM ANALYSIS

Application Number: 16036908
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-03
Patent Classification: ["257", "368000"]

Abstract:
A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.

Claim (Index 2):
The semiconductor memory device according to  claim 1 , wherein the top surface of the gate capping layer and a top surface of the first spacer structure are coplanar.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 4.35135
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15413466', '15060174', '13241716', '15884399', '14738421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9246350345096704
- 35 USC 102 Novelty (BERT): 0.49166970339373
- Combined Prediction Score: 0.8813385013980763
- Mean Citation Score: 213.246324
- Max Citation Score: 221.65514
- Similarity Product: 162.23029020212172

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test