PATENT CLAIM ANALYSIS

Application Number: 15989556
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "774000"]

Abstract:
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure is in the first and second IC dies and extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure. The plurality of TSV coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

Claim (Index 28):
The 3D IC according to  claim 21 , wherein the first lower conductive ring and the second lower conductive ring are concentric to one another.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.72414
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15383419', '15954772', '15665495', '12618412', '15216815']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9255170558295968
- 35 USC 102 Novelty (BERT): 0.5104437967590421
- Combined Prediction Score: 0.8840097299225413
- Mean Citation Score: 237.237586
- Max Citation Score: 275.49405
- Similarity Product: 190.20608522896168

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test