PATENT CLAIM ANALYSIS

Application Number: 16183389
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "314000"]

Abstract:
A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

Claim (Index 1):
A semiconductor memory device comprising:\n a memory cell array formed on a semiconductor substrate and configured to have a memory unit obtained by connecting a plurality of first selection transistors, a plurality of memory transistors, and a plurality of second selection transistors in series, when three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array having a plurality of first conductive layers to be control gates of the plurality of first selection transistors, a plurality of second conductive layers to be control gates of the plurality of memory transistors, and a plurality of third conductive layers to be control gates of the plurality of second selection transistors, which are laminated in the third direction, ends of the plurality of first conductive layers corresponding to control gates of the first selection transistors being formed such that at least one end of one first conductive layer extends farther in the first direction than a corresponding end of another first conductive layer disposed directly above the one first conductive layer, ends of the plurality of third conductive layers corresponding to control gates of the second selection transistors being formed such that at least one end of one third conductive layer extends farther in the first direction than a corresponding end of another third conductive layer disposed directly above the one third conductive layer, ends of the plurality of second conductive layers corresponding to control gates of the memory transistors being formed such that at least two ends of one second conductive layer extend farther respectively in the first direction and the second direction than corresponding ends of another second conductive layer disposed directly above the one second conductive layer, and the first direction and the second direction are parallel with the semiconductor substrate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.85455
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14849743', '13600936', '12694690', '16120412', '12718353']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8929625459168228
- 35 USC 102 Novelty (BERT): 0.4957130603199132
- Combined Prediction Score: 0.8532375973571319
- Mean Citation Score: 189.654384
- Max Citation Score: 279.90088
- Similarity Product: 277.8058463003158

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test