PATENT CLAIM ANALYSIS

Application Number: 15863983
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["375", "371000"]

Abstract:
A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Claim (Index 15):
The CDR circuit according to  claim 14 , wherein the decision and voting circuit comprises:\n a plurality of early or late decision circuits, wherein, each of the early or late decision circuit receives consecutive two of the plurality of rising edge sampled data and one falling edge sampled data therebetween and generates an initial early or late information; and a plurality of voting stages, coupled to the early or late decision circuits in series, each voting stage operating a majority voting operation on received early or late information to generate early or late information to be outputted, wherein the last voting stage of the plurality of voting stages generates the final early or late information.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 1.84906
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13833321', '13235628', '15602239', '14145493', '13081941']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5222430419142322
- 35 USC 102 Novelty (BERT): 0.520879670195924
- Combined Prediction Score: 0.5221067047424014
- Mean Citation Score: 242.94647
- Max Citation Score: 264.6696
- Similarity Product: 138.53939777283668

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test