PATENT CLAIM ANALYSIS

Application Number: 15918919
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["345", "212000"]

Abstract:
A half-power buffer and/or amplifier is disclosed. The half-power buffer and/or amplifier includes an amplifying unit including first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and a first output node configured to connect the first and second transistors and to output a voltage over a first voltage range between the first and third voltages, a second output buffer unit including third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and a second output node configured to connect the third and fourth transistors and to output a voltage over a second voltage range between the second and third voltages, and a first charge share switch unit connected between the gate of the second transistor and the first voltage source, and configured to perform a charge share and/or equalization operation.

Claim (Index 1):
A half-power buffer and/or amplifier comprising:\n an amplifying unit configured to amplify a differential input signal, the amplifying unit comprising first to fourth nodes configured to output first to fourth amplified outputs; a first output buffer unit comprising (i) first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and (ii) a first output node configured to connect the first and second transistors, the first and second transistors having gates connected to corresponding ones of the first and second nodes, respectively, the first output node being configured to output a voltage over a first voltage range between the first voltage and the third voltage; a second output buffer unit comprising (i) third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and (ii) a second output node configured to connect the third and fourth transistors, the third and fourth transistors having gates connected to corresponding ones of the third and fourth nodes, respectively, the second output node being configured to output a voltage over a second voltage range between the second voltage and the third voltage; and a first charge share switch unit connected between the gate of the second transistor and the first voltage source, and configured to control the second transistor and/or equilibrate a voltage at the first output node with the third voltage in response to a first control signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.55556
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14820182', '15884037', '14565939', '14734385', '12028856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.655426871731139
- 35 USC 102 Novelty (BERT): 0.47731876689101
- Combined Prediction Score: 0.6376160612471262
- Mean Citation Score: 222.942412
- Max Citation Score: 241.1423
- Similarity Product: 216.69594269216657

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test