PATENT CLAIM ANALYSIS

Application Number: 15869349
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "329000"]

Abstract:
Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

Claim (Index 12):
The method of  claim 1  wherein the sacrificial layer has a top surface, and the support structure is arranged over the top surface of the sacrificial layer.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15676300', '15586621', '15800563', '15427403', '15694109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.929773804832063
- 35 USC 102 Novelty (BERT): 0.5296081044985324
- Combined Prediction Score: 0.8897572347987099
- Mean Citation Score: 264.099646
- Max Citation Score: 318.81198
- Similarity Product: 168.0441879134345

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test