PATENT CLAIM ANALYSIS

Application Number: 15922682
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "288000"]

Abstract:
The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Claim (Index 3):
The method of  claim 1 , further comprising forming a leveling dielectric layer over the second dielectric layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.8
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12756662', '14187896', '12487894', '14083533', '10707757']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9071730137920284
- 35 USC 102 Novelty (BERT): 0.4749599582434848
- Combined Prediction Score: 0.8639517082371742
- Mean Citation Score: 160.829368
- Max Citation Score: 168.1732
- Similarity Product: 122.39427170562745

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test