PATENT CLAIM ANALYSIS

Application Number: 15983627
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "329000"]

Abstract:
Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.

Claim (Index 1):
A structure comprising:\n a first active device region; a second active device region; and a storage element including a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a first bottom source/drain region centrally arranged in the first active device region and a fin projecting from the first bottom source/drain region, a first pull-down (PD) vertical-transport field-effect transistor (VTFET) with a fin projecting from the first active device region and aligned lengthwise in a first row with the fin of the first PU VTFET, a second pull-up (PU) vertical-transport field-effect transistor (VTFET) with a second bottom source/drain region centrally arranged in the first second active device region and a fin projecting from the second bottom source/drain region, and a second pull-down (PD) vertical-transport field-effect transistor (VTFET) with a fin projecting from the second active device region and aligned lengthwise in a second row with the fin of the second PU VTFET, wherein the first bottom source/drain region of the first PU VTFET in the first active device region is aligned with the second bottom source/drain region of the second PU VTFET in the second active device region such that the first bottom source/drain region and the second bottom source/drain region are laterally arranged between the first PD VTFET and the second PD VTFET.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.91071
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15634227', '12823860', '15878711', '12823907', '15599581']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9206481400772428
- 35 USC 102 Novelty (BERT): 0.4972472835205831
- Combined Prediction Score: 0.8783080544215769
- Mean Citation Score: 250.98119
- Max Citation Score: 259.20392000000004
- Similarity Product: 197.456043843379

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test