PATENT CLAIM ANALYSIS

Application Number: 16030590
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "145000"]

Abstract:
Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

Claim (Index 10):
The method of  claim 9 , further comprising:\n selecting the memory cell for the read operation, wherein the memory cell is in electronic communication with the digit line, and wherein charging the capacitor is based at least in part on selecting the memory cell for the read operation.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.26087
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15246249', '15844154', '15377767', '15067838', '15151065']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8191895151831677
- 35 USC 102 Novelty (BERT): 0.5156215641102571
- Combined Prediction Score: 0.7888327200758767
- Mean Citation Score: 270.968836
- Max Citation Score: 333.63522
- Similarity Product: 245.824761777842

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test