PATENT CLAIM ANALYSIS

Application Number: 16109857
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "296000"]

Abstract:
Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Claim (Index 3):
A semiconductor device comprising:\n a first circuit comprising a first transistor and a second transistor; and a second circuit comprising a capacitor, wherein the first transistor and the second transistor are n-channel type transistors, wherein one of a source and a drain of the first transistor is electrically connected to an output terminal of the first circuit, wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein an electrode of the capacitor is electrically connected to a gate of the second transistor, wherein the first circuit is configured to output a first potential from the first wiring to the output terminal of the first circuit through the first transistor by a bootstrap operation, wherein a second potential is supplied to the second wiring, wherein the second circuit is configured to output a third potential to the gate of the second transistor when the first potential is output to the output terminal of the first circuit, wherein the first potential is higher than the second potential, and wherein the third potential is lower than the second potential.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 96.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14790309', '15350712', '13468135', '14250623', '14339948']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9258863358068306
- 35 USC 102 Novelty (BERT): 0.5138172640128502
- Combined Prediction Score: 0.8846794286274325
- Mean Citation Score: 354.404852
- Max Citation Score: 382.0933
- Similarity Product: 333.2886321014822

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test