PATENT CLAIM ANALYSIS

Application Number: 15769558
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["712", "222000"]

Abstract:
Processing circuitry supports a first type of vector arithmetic instruction specifying at least a first input vector. When at least one exceptional condition is detected for an arithmetic operation performed for a first active data element of the first input vector in a predetermined sequence, the processing circuitry performs at least one response action. When the at least one exceptional condition is detected for a given active data element other than the first active data element in the predetermined sequence, the processing circuitry suppresses the at least one response action and stores elements identifying information identifying which data element is the given active data element which triggered the exceptional condition. This can be useful for reducing the amount of hardware resource for tracking the occurrence of the exceptional conditions and/or supporting speculative execution of vector instructions.

Claim (Index 12):
The apparatus according to  claim 1 , wherein the first active data element in the predetermined sequence comprises a least significant active data element of the first input vector.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 91.0
- Lexical Diversity: 2.21875
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15759914', '15078149', '14564708', '09860777', '16081147']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5944989081939225
- 35 USC 102 Novelty (BERT): 0.5087313849880264
- Combined Prediction Score: 0.5859221558733329
- Mean Citation Score: 211.691232
- Max Citation Score: 319.0050700000001
- Similarity Product: 297.41980719118067

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test