PATENT CLAIM ANALYSIS

Application Number: 16364239
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["327", "225000"]

Abstract:
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Claim (Index 14):
The ADC of  claim 13 , wherein the pair of cross-coupled capacitors include:\n a first capacitor that includes a first terminal and a second terminal; and a second capacitor that includes a third terminal and a fourth terminal; the first terminal connected to an input of the first inverter, the third terminal connected to an input of the second inverter, the second terminal connected to an output of the second inverter, and the fourth terminal connected to an output of the first inverter.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 99.0
- Lexical Diversity: 2.20513
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15945165', '15884813', '15883623', '16211259', '15864090']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7813059674707606
- 35 USC 102 Novelty (BERT): 0.5653625894160946
- Combined Prediction Score: 0.7597116296652942
- Mean Citation Score: 267.002016
- Max Citation Score: 466.54208
- Similarity Product: 367.68573614425657

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test