PATENT CLAIM ANALYSIS

Application Number: 16260142
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "185030"]

Abstract:
A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Claim (Index 2):
The method of  claim 1 , wherein the plurality of data blocks are realized by triple-level cells (TLCs), and the blocks supports eight plurality of program threshold voltage intervals.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 99.0
- Lexical Diversity: 3.16327
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15985718', '15643501', '14596236', '15235128', '14983566']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.810887602849365
- 35 USC 102 Novelty (BERT): 0.54309322512922
- Combined Prediction Score: 0.7841081650773505
- Mean Citation Score: 325.956756
- Max Citation Score: 390.00815
- Similarity Product: 387.8604710905671

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test