PATENT CLAIM ANALYSIS

Application Number: 16045175
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "288000"]

Abstract:
A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer

Claim (Index 16):
The device of  claim 8  further comprising an additional inter-layer dielectric, with the gate stack and the gate spacer in the additional inter-layer dielectric, wherein a top surface of the additional inter-layer dielectric is further in contact with the dielectric layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.34694
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15429894', '15610981', '15225304', '15221123', '15490439']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919362071743018
- 35 USC 102 Novelty (BERT): 0.5062921157890096
- Combined Prediction Score: 0.8780550761476172
- Mean Citation Score: 244.1919
- Max Citation Score: 280.35114
- Similarity Product: 205.4851315403724

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test