PATENT CLAIM ANALYSIS

Application Number: 16228428
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["365", "185170"]

Abstract:
Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described.

Claim (Index 16):
A method comprising:\n erasing information, during a first stage of an operation, from memory cells of a memory cell string, the memory cells of the string located in different levels of a device; determining, during a second stage of an operation, whether a state of a selected memory cell of the memory cells is within a target value range; and applying a negative voltage to the body of the memory cell string during a time interval between the first and second stages, wherein erasing, determining, and applying are performed by a memory device.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 98.0
- Lexical Diversity: 1.95918
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13437547', '14581631', '15849299', '16125280', '13707067']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7906764215247644
- 35 USC 102 Novelty (BERT): 0.4786408074431217
- Combined Prediction Score: 0.7594728601166001
- Mean Citation Score: 203.56637
- Max Citation Score: 238.43922
- Similarity Product: 193.76299071616887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test