PATENT CLAIM ANALYSIS

Application Number: 15935363
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["257", "565000"]

Abstract:
In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Claim (Index 12):
An integrated circuit (IC) comprising:\n a first IC region comprising,\n an emitter region disposed within a semiconductor substrate; \n a ring-shaped base region disposed within the semiconductor substrate and laterally surrounding the emitter region; \n a ring-shaped collector region disposed within the semiconductor substrate and laterally surrounding the ring-shaped base region; \n a pre-metal dielectric layer disposed over an upper surface of the semiconductor substrate, and separating the upper surface of the semiconductor substrate from a lowermost metal interconnect layer; and \n a plurality of dishing prevention columns arranged over the emitter region and within the pre-metal dielectric layer, wherein the plurality of dishing prevention columns each comprise a dummy gate that is conductive and electrically floating; \n a second IC region comprising,\n a semiconductor device having a pair of source/drain regions disposed within the semiconductor substrate, wherein the source/drain regions are spaced apart; and \n a gate stack disposed over the semiconductor substrate and arranged between the source/drain regions, wherein the gate stack comprises a first gate oxide layer separating a gate electrode from the semiconductor substrate.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.36842
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13538220', '12455509', '12471091', '14808040', '14178383']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9115311670700113
- 35 USC 102 Novelty (BERT): 0.4789320366486306
- Combined Prediction Score: 0.8682712540278732
- Mean Citation Score: 177.390986
- Max Citation Score: 194.3664
- Similarity Product: 148.27341353359222

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test