PATENT CLAIM ANALYSIS

Application Number: 16023584
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["365", "200000"]

Abstract:
A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Claim (Index 12):
The semiconductor memory device of  claim 10 , wherein the fuse information circuit comprises:\n a fuse table configured to store first row addresses of word-lines in the first cell region, second row addresses of word-lines in the second cell region, the fuse information and spare row addresses corresponding to the second row addresses respectively; and a sensing circuit configured to output the spare row address corresponding to the row address of the access address when the fuse information of the row addresses of the access address has a first logic level.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12320892', '14030066', '13008431', '10657790', '12320891']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8310432536951783
- 35 USC 102 Novelty (BERT): 0.4999742505041892
- Combined Prediction Score: 0.7979363533760794
- Mean Citation Score: 271.242584
- Max Citation Score: 280.63547
- Similarity Product: 207.88024346269248

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test