PATENT CLAIM ANALYSIS

Application Number: 15993583
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["711", "122000"]

Abstract:
Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.

Claim (Index 37):
The system of  claim 36 , wherein the operations further comprise:\n indicating in a dispatch table having an entry for each memory access category of the memory access categories, at least one processing unit assigned to process tasks assigned to the memory access category and a processor chip including the at least one processing unit assigned to the memory access category.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 93.0
- Lexical Diversity: 2.20968
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15264406', '15264382', '15431637', '15269640', '12629325']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5188714982148037
- 35 USC 102 Novelty (BERT): 0.535347512614139
- Combined Prediction Score: 0.5205190996547373
- Mean Citation Score: 238.337544
- Max Citation Score: 372.83075
- Similarity Product: 248.7044422466159

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test