PATENT CLAIM ANALYSIS

Application Number: 15904346
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["257", "306000"]

Abstract:
This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Claim (Index 13):
A manufacturing method of a semiconductor device having a first capacitive element and a second capacitive element, comprising the steps of:\n (a) providing a substrate having a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a semiconductor layer formed over the first insulating layer; (b) forming a first active region and a second active region that are surrounded in plan view by a second insulating layer that penetrates through the semiconductor layer and the first insulating layer to reach the semiconductor substrate; (c) forming a semiconductor region in the semiconductor substrate so as to include the first active region and the second active region; (d) removing the semiconductor layer and the first insulating layer in the second active region; and (e) in the first active region, forming a first conductor layer over the semiconductor layer via a third insulating layer, wherein the first capacitive element is comprised of the semiconductor layer, the third insulating layer, and the first conductor layer, wherein the second capacitive element is comprised of the semiconductor region, the first insulating layer, and the semiconductor layer, and wherein each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 3.52632
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15212331', '14860700', '15266914', '15239193', '14869988']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9211187303086502
- 35 USC 102 Novelty (BERT): 0.4924442203079594
- Combined Prediction Score: 0.8782512793085812
- Mean Citation Score: 247.054064
- Max Citation Score: 278.07376
- Similarity Product: 254.02338279197696

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test