PATENT CLAIM ANALYSIS

Application Number: 15862366
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "459000"]

Abstract:
It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.

Claim (Index 4):
The semiconductor device according to  claim 3  wherein said contact area is alloyed by carrying out a thermal treatment in order to electrically connect said through-silicon via made of copper to said line made of aluminum.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.22535
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13587317', '15057375', '12133828', '12913020', '13681348']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9251974498700628
- 35 USC 102 Novelty (BERT): 0.5192119941143273
- Combined Prediction Score: 0.8845989042944892
- Mean Citation Score: 212.03886
- Max Citation Score: 305.9002
- Similarity Product: 208.9221508493065

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test