PATENT CLAIM ANALYSIS

Application Number: 15875651
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "194000"]

Abstract:
Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.

Claim (Index 11):
The memory device of  claim 6 , wherein the multiplexer is configured to select the first copy of the IWS when write leveling is not enabled, and to select the second copy of the IWS when write leveling is enabled and a write preamble length for a write falls in the second set of write preamble lengths.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 86.0
- Lexical Diversity: 2.04839
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15680006', '15790896', '15826236', '13768858', '15658276']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.807589786339929
- 35 USC 102 Novelty (BERT): 0.4864376430469019
- Combined Prediction Score: 0.7754745720106263
- Mean Citation Score: 195.556582
- Max Citation Score: 221.09663
- Similarity Product: 157.58922307536244

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test