PATENT CLAIM ANALYSIS

Application Number: 16185028
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["708", "497000"]

Abstract:
A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

Claim (Index 13):
A computer program product for rounding a decimal floating point number to a lesser precision in a computer processor, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computer processor to cause the computer processor to perform a method comprising:\n a) executing, by the computer processor operating in emulation mode, a decimal floating point instruction to perform a decimal floating point operation utilizing a round-for-reround mode, the executing comprising: fetching from computer processor storage, by the computer processor, a decimal floating point operand having a first number of bits representing a first decimal number, the first decimal number having a first number of decimal digits of precision; performing in the round-for-reround mode, by the computer processor, the decimal floating point operation on the decimal floating point operand to produce an intermediate result, the intermediate result consisting of a high order portion and a to-be-discarded low order portion, the high order portion consisting of a second number of bits representing a second decimal number, the second decimal number having a least significant decimal digit, the low order portion having a third number of bits; based on the to-be-discarded low order portion representing a greater-than-0 decimal value, causing the least significant decimal digit to not have a 0 value by setting the least significant bit of the high order portion to 1, wherein the least significant decimal digit having a 0 decimal value indicates the second decimal number is exact; and storing in computer processor storage, by the computer processor, the high order portion as a final result of the executed decimal floating point operation; and b) subsequent to executing the decimal floating point instruction, executing, by the computer processor operating in emulation mode, a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to a designated decimal rounding precision of a plurality of decimal rounding precisions, the executing the decimal reround instruction comprising: fetching from computer processor storage, by the computer processor, the stored final result of the executed decimal floating point operation, the fetched final result having the second number of bits representing the second number of decimal digits; determining a decimal reround instruction specified second rounding precision of the plurality of rounding precisions, the second rounding precision having at least 2 fewer decimal digits than the first number of decimal digits; rounding, by the computer processor, the fetched final result to a rounded result, the rounded result representing a decimal number having the at least 2 fewer decimal digits than the first number of decimal digits; and storing in computer processor storage, by the processor, the rounded final result as a result of the execution of the decimal reround instruction.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.03371
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15852180', '15470692', '11680894', '14943254', '13848885']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.605074002061232
- 35 USC 102 Novelty (BERT): 0.6532548854552146
- Combined Prediction Score: 0.6098920904006302
- Mean Citation Score: 622.4171200000002
- Max Citation Score: 631.75775
- Similarity Product: 612.3438286067843

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test