PATENT CLAIM ANALYSIS

Application Number: 16014020
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "760000"]

Abstract:
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Claim (Index 2):
The apparatus of  claim 1 , further comprising a semi-conformal cap on top of the first dielectric layer and the plurality of metal lines.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 94.0
- Lexical Diversity: 2.40426
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15229470', '14721440', '13964772', '14721460', '15992685']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9126871499483036
- 35 USC 102 Novelty (BERT): 0.5373696426605318
- Combined Prediction Score: 0.8751553992195265
- Mean Citation Score: 237.263012
- Max Citation Score: 381.16522
- Similarity Product: 313.46356479872105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test