PATENT CLAIM ANALYSIS

Application Number: 15987919
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["438", "197000"]

Abstract:
A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.

Claim (Index 14):
The manufacturing method of the semiconductor memory device according to  claim 12 , wherein the contact structure includes a non-metal conductive material.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 2.65455
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14869987', '15892387', '15355032', '14811814', '14023481']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8753370592668227
- 35 USC 102 Novelty (BERT): 0.5105424739908823
- Combined Prediction Score: 0.8388576007392287
- Mean Citation Score: 232.928636
- Max Citation Score: 243.13094
- Similarity Product: 147.72204869965677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test