PATENT CLAIM ANALYSIS

Application Number: 15951426
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "189020"]

Abstract:
The present disclosure relates to a structure including a column multiplexor circuit with a plurality of bit line groups to perform a read operation of data using half of a plurality of column selection signals in the column multiplexor circuit, and each of the bit line groups comprises a reference bit line column, a plurality of transistors, and a plurality of bit lines.

Claim (Index 21):
The method of  claim 16 , wherein each of the first bit line group, the second bit line group, the third bit line group, and the fourth bit line group includes a plurality of bit lines and a corresponding plurality of transistors, and each of the first reference bit line column, the second reference bit line column, the third reference bit line column, and the fourth reference bit line column is connected to the corresponding plurality of transistors.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 91.0
- Lexical Diversity: 1.91429
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10694761', '11830077', '12398155', '12965504', '13827815']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7638949129802832
- 35 USC 102 Novelty (BERT): 0.4859087912792233
- Combined Prediction Score: 0.7360963008101773
- Mean Citation Score: 157.03747600000003
- Max Citation Score: 167.35801999999995
- Similarity Product: 111.9110676512718

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test