PATENT CLAIM ANALYSIS

Application Number: 15917369
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "295000"]

Abstract:
A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. The ferroelectric layers may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The ferroelectric layers may be polarized by different electric fields.

Claim (Index 10):
A method of manufacturing a ferroelectric memory device, the method comprising:\n implanting impurities into a semiconductor substrate; etching the semiconductor substrate to form a recess for defining a source and a drain in the semiconductor substrate; forming a first ferroelectric pattern over a sidewall of the recess; forming a second ferroelectric pattern over the first ferroelectric pattern to fill the recess; and forming a gate over the first and second ferroelectric patterns.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15183232', '10776394', '15246081', '14812245', '11384689']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8957442283626607
- 35 USC 102 Novelty (BERT): 0.492456665697458
- Combined Prediction Score: 0.8554154720961404
- Mean Citation Score: 194.85802
- Max Citation Score: 248.39906
- Similarity Product: 213.7683061889064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test