PATENT CLAIM ANALYSIS

Application Number: 15896015
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "230060"]

Abstract:
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

Claim (Index 20):
The method of  claim 18 , wherein the integrated circuit is a memory fault detector that provides a security feature for detecting laser attacks imposed on the memory circuitry.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.74419
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15238551', '15789715', '14796744', '15477516', '15357691']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.806051439628254
- 35 USC 102 Novelty (BERT): 0.4883348114906222
- Combined Prediction Score: 0.7742797768144909
- Mean Citation Score: 194.005106
- Max Citation Score: 202.49379
- Similarity Product: 133.48324511003136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test