PATENT CLAIM ANALYSIS

Application Number: 16134599
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["327", "156000"]

Abstract:
The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal of the processing core and comprising a frequency locked loop having: a digitally controlled oscillator configured to generate the variable frequency clock signal; and a controller ( 614 ) configured to generate a digital control signal (C_FREQ), wherein the controller is configured to implement a frequency transition of the variable frequency clock signal from a first frequency to a second lower frequency by generating: a first value of the digital control signal (C_FREQ) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency lower than the second frequency; and further values of the digital control signal (C_FREQ).

Claim (Index 1):
A circuit comprising:\n a voltage generator ( 106 ) adapted to generate a variable supply voltage V_CORE) for powering a processing core ( 102 ); a frequency generator ( 108 ) adapted to generate a variable frequency clock signal (CLK_CORE) of the processing core, wherein the frequency generator comprises a frequency locked loop ( 400 ) comprising: a digitally controlled oscillator ( 402 ) configured to generate the variable frequency clock signal (CLK_CORE); and a controller ( 614 ) configured to generate a digital control signal (C_FREQ) for controlling the, digitally controlled oscillator ( 402 ) based on the product of a frequency error signal (F_ERR) and a gain, wherein the controller is configured to implement a frequency transition of the variable frequency clock signal (CLK_CORE) from a first frequency (F_H) to a second frequency (F_T) lower than the first frequency by generating: a first value of the digital control signal (C_FREQ) based on a first value of the gain applied to a first value of the frequency error signal (F_ERR) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency (F_L) lower than the second frequency (F_T); and further values of the digital control signal (C_FREQ) based on one or more further gain values different to and tower than the first value of the gain, wherein the controller ( 614 ) is configured to apply said further gain values selected such that the second frequency (F_T) is not exceeded by the variable frequency clock signal.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.55932
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14406973', '15751615', '15370796', '16050762', '14566847']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7594735635366385
- 35 USC 102 Novelty (BERT): 0.4791307905790998
- Combined Prediction Score: 0.7314392862408847
- Mean Citation Score: 183.13238
- Max Citation Score: 189.94608
- Similarity Product: 134.73330235865592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test