PATENT CLAIM ANALYSIS

Application Number: 15996365
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-09
Patent Classification: ["365", "193000"]

Abstract:
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.

Claim (Index 22):
The DDR memory controller of  claim 2 , wherein the DDR memory controller is configured such that at least one of:\n at least one of the communicative couplings is a direct communicative coupling without a component therebetween; at least one of the communicative couplings is an indirect communicative coupling with at least one a component therebetween; the self-configuring logic circuit is configured to be responsive to the first core domain register; the self-configuring logic circuit is configured to be responsive to the second core domain register; the self-configuring logic circuit is configured to be responsive to the first core domain register and the second core domain register; the core_clock delay element is configured to generate the capture clock by deriving the capture clock using phase information derived from the DQS signal; the read data path is configured to receive the data DQ signal that is driven by the DDR memory; the read data path is configured to receive the signal derived from the DQ signal; the first core domain register is configured to be responsive to the DQ signal; the first core domain register is configured to be responsive to the signal derived from the DQ signal; the first core domain register is configured to be clocked by the capture clock; the first core domain register is configured to be clocked by the clock derived from the capture clock; the second core domain register is configured to be clocked by the core_clock; the second core domain register is configured to be clocked by the clock derived from the core_clock; the self-configuring logic circuit is configured to be responsive to the first core domain register; the self-configuring logic circuit is configured to be responsive to the signal derived from the first core domain register; the self-configuring logic circuit is configured to be responsive to the second core domain register; the self-configuring logic circuit is configured to be responsive to the signal derived from the second core domain register; the one or more pre-determined calibration data patterns are written to the DDR memory; the one or more pre-determined calibration data patterns are read from the DDR memory; the first core domain register is configured to be clocked based solely on the capture clock; the first core domain register is configured to be clocked based directly on the capture clock; the first core domain register is configured to be clocked based indirectly on the capture clock; the first core domain register is configured to be clocked based, at least in part, on the capture clock, by being based, at least in part, on a timing of the capture clock; the first core domain register is configured to be clocked based, at least in part, on the capture clock, by being clocked based, at least in part, on a timing of active edges of the capture clock; the first core domain register is configured to be clocked based, at least in part, on the capture clock, by being clocked based, at least in part, on active edges of the capture clock; the second core domain register is configured to be clocked based solely on the core_clock; the second core domain register is configured to be clocked based directly on the core_clock; the second core domain register is configured to be clocked based indirectly on the core_clock; the second core domain register is configured to be clocked based, at least in part, on the core_clock, by being based, at least in part, on a timing of the core_clock; the second core domain register is configured to be clocked based, at least in part, on the core_clock, by being clocked based, at least in part, on a timing of active edges of the core_clock; the second core domain register is configured to be clocked based, at least in part, on the core_clock, by being clocked based, at least in part, on active edges of the core clock; or the setting of the delay of the core_clock delay element is repeated.

Metadata:
- Claim Count in Document: 80.0
- Percentile: 94.0
- Lexical Diversity: 2.90625
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15722209', '15926902', '13172740', '12157081', '14752903']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8796071998332422
- 35 USC 102 Novelty (BERT): 0.6025637465939538
- Combined Prediction Score: 0.8519028545093134
- Mean Citation Score: 610.6998120000002
- Max Citation Score: 622.7399
- Similarity Product: 455.9828285931409

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test