PATENT CLAIM ANALYSIS

Application Number: 15859726
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["370", "411000"]

Abstract:
Systems and methods to automatically generate various multi-stage pyramid network based fabrics, applicable to including Field programmable gate arrays, are disclosed. Significantly optimized multi-stage pyramid networks either partially connected or fully connected, useful in wide target applications, with VLSI layouts (or floor plans) substantially using horizontal and vertical links to route signals between inlet and outlet links of large scale sub-integrated circuit blocks and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks, (for example in an FPGA where the sub-integrated circuit blocks are Lookup Tables, or memory blocks, or DSP blocks) are disclosed. The optimized multi-stage networks in each block employ a plurality of slices of rings of stages of switches with different size multiplexer having inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side, or from right-hand side, or from both left-hand side and right-hand side, or through any incoming and outgoing links of any stage. The VLSI layouts exhibit spatial locality so that sub-integrated circuit blocks that are spatially nearer are connected with shorter hop wires. Fabrics are generated iteratively either manually or automatically by changing different parameters including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers which may be in any switch, connections between stages of rings which may be between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

Claim (Index 3):
The two-dimensional layout of  claim 2 , wherein said all horizontal cross links between switches in any two corresponding said succeeding stages are substantially of equal length and said vertical cross links between switches in any two corresponding said succeeding stages are substantially of equal length in the entire said two-dimensional layout.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 2.37584
- Patent Class: 370.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14329876', '14199168', '15140470', '15331855', '14522599']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6340354073168191
- 35 USC 102 Novelty (BERT): 0.6177952430100901
- Combined Prediction Score: 0.6324113908861462
- Mean Citation Score: 494.5352959999999
- Max Citation Score: 556.9894
- Similarity Product: 517.5305439317466

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test