PATENT CLAIM ANALYSIS

Application Number: 15897424
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

Claim (Index 1):
A semiconductor device comprising:\n a fifth second-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first second-conductivity-type semiconductor layer, a first body region, a second second-conductivity-type semiconductor layer, a first first-conductivity-type semiconductor layer, a second body region, and a second first-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; a first output terminal connected to the second second-conductivity-type semiconductor layer and the first first-conductivity-type semiconductor layer; a third pillar-shaped semiconductor layer which is formed above the semiconductor substrate and in which a fifth first-conductivity-type semiconductor layer, a fifth body region, and a sixth first-conductivity-type semiconductor layer are formed from the substrate side in that order; a fifth gate insulating film formed around the fifth body region; a fifth gate formed around the fifth gate insulating film; a second pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a third second-conductivity-type semiconductor layer, a third body region, a fourth second-conductivity-type semiconductor layer, a third first-conductivity-type semiconductor layer, a fourth body region, and a fourth first-conductivity-type semiconductor layer are formed from the substrate side in that order; a third gate insulating film formed around the third body region; a third gate formed around the third gate insulating film; a fourth gate insulating film formed around the fourth body region; a fourth gate formed around the fourth gate insulating film; a second output terminal connected to the fourth second-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; a fourth pillar-shaped semiconductor layer which is formed above the semiconductor substrate and in which a seventh first-conductivity-type semiconductor layer, a sixth body region, and an eighth first-conductivity-type semiconductor layer are formed from the substrate side in that order; a sixth gate insulating film formed around the sixth body region; and a sixth gate formed around the sixth gate insulating film, wherein the fifth first-conductivity-type semiconductor layer is connected to the second output terminal, the seventh first-conductivity-type semiconductor layer is connected to the first output terminal, the first gate, the second gate, and the second output terminal are connected to one another, and the third gate, the fourth gate, and the first output terminal are connected to one another.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 88.0
- Lexical Diversity: 3.08333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14743500', '14743612', '14744588', '15680724', '14743570']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9305035830941554
- 35 USC 102 Novelty (BERT): 0.5299016967691462
- Combined Prediction Score: 0.8904433944616544
- Mean Citation Score: 333.219598
- Max Citation Score: 365.38226
- Similarity Product: 288.8882897462404

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test