PATENT CLAIM ANALYSIS

Application Number: 15889928
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["365", "193000"]

Abstract:
When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.

Claim (Index 9):
The semiconductor device according to  claim 2 ,\n wherein during the second adjustment period, the control circuit writes externally supplied normal data to the memory device as the write data.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 88.0
- Lexical Diversity: 2.18868
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15360404', '14369501', '12596535', '11505328', '13272856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8031654739893767
- 35 USC 102 Novelty (BERT): 0.4638436850150225
- Combined Prediction Score: 0.7692332950919413
- Mean Citation Score: 168.60554
- Max Citation Score: 172.85379
- Similarity Product: 133.57889990307748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test