PATENT CLAIM ANALYSIS

Application Number: 16016879
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "427000"]

Abstract:
A FET driving circuit includes: two inputs for inputting a DC voltage; two outputs respectively connected to gate and source electrodes of a FET; a switch; a resonant capacitance connected between both ends of the switch; and an LC resonance circuit connected between the inputs and both ends of the switch. When the two inputs are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low to a high-frequency side, first to fourth resonant frequencies. The first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is around double the switching frequency, the fourth resonant frequency is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.

Claim (Index 11):
The FET driving circuit according to  claim 9 ,\n wherein a biasing circuit that applies a DC bias to the driving voltage is connected across the two output terminals.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 2.37313
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16017121', '16012099', '15790354', '15481109', '12470192']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7836794270911732
- 35 USC 102 Novelty (BERT): 0.5447690561144305
- Combined Prediction Score: 0.759788389993499
- Mean Citation Score: 314.345928
- Max Citation Score: 394.03265
- Similarity Product: 308.02599116626976

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test