PATENT CLAIM ANALYSIS

Application Number: 15749107
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "072000"]

Abstract:
The present invention provides an FFS type TFT array substrate and a manufacturing method thereof. The manufacturing method for an FFS type TFT array substrate of the present invention comprises that a gate electrode, a scanning line, a common electrode, and a common electrode line are formed in one photomask process. Comparing with the conventional art, the present invention simplifies the manufacturing process, with fewer photomasks, and a shorter processing time, therefore, the production cost is low. The fabrication process of the FFS type TFT array substrate of the present invention is simple, has low production cost and excellent electrical performance.

Claim (Index 7):
A fringe field switching (FFS) type thin film transistor (TFT) array substrate, comprising:\n a base substrate; a gate electrode, a scanning line, a common electrode, and a common electrode line being disposed on the base substrate; wherein the gate electrode is connected with the scanning line, and the common electrode is connected with the common electrode line; a gate insulating layer being disposed on the gate electrode, the scanning line, the common electrode, the common electrode line and the base substrate; an active layer being disposed on the gate insulating layer and corresponding onto the gate electrode; a source electrode and a drain electrode being disposed on the active layer and the gate insulating layer, and a data line being disposed on the gate insulating layer; wherein, the source electrode and the drain electrode are respectively in contact with the active layer; the data line is connected with the source electrode; a passivation layer being disposed on the source electrode, the drain electrode, the data line, the active layer, and the gate insulating layer; a first through hole being disposed on the passivation layer and corresponding onto the drain electrode; a pixel electrode being disposed on the passivation layer; wherein the pixel electrode is connected with the drain electrode via the first through hole located on the passivation layer; or a passivation layer being disposed on the source electrode, the drain electrode, the data line, the active layer, and the gate insulating layer, and a planer layer being disposed on the passivation layer, a second through hole being disposed on the passivation layer and the planer layer and corresponding onto the drain electrode; a pixel electrode being disposed on the planer layer; wherein the pixel electrode is connected with the drain electrode via the second through hole located on the passivation layer and the planer layer; wherein the gate electrode and the scanning line have a dual-layer structure comprising a layer of a first material and a second layer of a second material disposed on a top of the layer of the first material layer, and common electrode and the common electrode line have a single-layer structure comprising a layer of the first material.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.11111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15748631', '12836028', '11309805', '14759255', '13499353']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9238722954556722
- 35 USC 102 Novelty (BERT): 0.5204729290991795
- Combined Prediction Score: 0.8835323588200229
- Mean Citation Score: 289.330888
- Max Citation Score: 342.436
- Similarity Product: 306.7921921818256

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test