PATENT CLAIM ANALYSIS

Application Number: 15896991
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["607", "059000"]

Abstract:
Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Claim (Index 5):
The implantable stimulator device of  claim 4 , wherein the control circuitry is configured to provide the amplitude and percentages for a sub-phase from the first register to the stimulation circuitry in parallel.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 2.59016
- Patent Class: 607.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14858554', '15289809', '13847676', '14636380', '15696031']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.739790306806491
- 35 USC 102 Novelty (BERT): 0.548238126551281
- Combined Prediction Score: 0.7206350887809702
- Mean Citation Score: 404.620282
- Max Citation Score: 438.22583
- Similarity Product: 350.99835886026136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test