PATENT CLAIM ANALYSIS

Application Number: 16232144
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["174", "262000"]

Abstract:
A printed wiring board includes a core substrate, and a build-up layer formed on the substrate. The substrate includes core material, third conductor layer, fourth conductor layer, and through-hole conductors. The build-up layer is formed on the core material and third conductor layer and includes insulating layers, first conductor layers, and via conductors. The build-up layer has central area and outer peripheral area such that the via conductors include central area via conductors and outer peripheral area via conductors, diameter of central area via conductor is smaller than diameter of outer peripheral area via conductor, the outermost first conductor layer includes first pads to mount first electronic component and second pads to mount second electronic component, the first and second pads are connected to each other via the central via conductors, and the lowermost insulating layer does not have the via conductors in the central area of the build-up layer.

Claim (Index 18):
The printed wiring board according to  claim 2 , wherein the first electronic component is a logic IC, and the second electronic component is a memory.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 98.0
- Lexical Diversity: 2.92857
- Patent Class: 174.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16167850', '14857074', '14920974', '15581253', '16166392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8631328699179964
- 35 USC 102 Novelty (BERT): 0.5032402800089234
- Combined Prediction Score: 0.8271436109270891
- Mean Citation Score: 259.940976
- Max Citation Score: 271.45184
- Similarity Product: 197.6561391397857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test