PATENT CLAIM ANALYSIS

Application Number: 15889521
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["711", "216000"]

Abstract:
Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Claim (Index 1):
A computer-implemented method comprising:\n detecting a first set of hash functions and a first bit array corresponding to elements of a cache; detecting a first instruction to add a new element to the cache; modifying the first bit array based on the new element, wherein modifying the first bit array comprises modifying bit values corresponding to a hash value detected from the first set of hash functions applied to the new element; processing a first invalidation operation using the first bit array; generating a second bit array and a second set of hash functions, while processing additional instructions with the first bit array; deleting the first bit array and the first set of hash functions in response to detecting the second bit array and the second set of hash functions have been generated; processing a second invalidation operation using the second set of hash functions and the second bit array; deleting the second bit array and the second set of hash functions responsive to processing the second invalidation operation with the second bit array; detecting at least one element to remove from the first bit array; preventing bits from being set based on the at least one element during the generation of the second bit array; designating the first bit array as an active array for invalidation operations until the second bit array is generated; wherein: the first bit array and the second bit array are Bloom filters; wherein designation of the active array alternates between the first bit array and the second bit array; the second set of hash functions differs from the first set of hash functions; and the cache comprises an address translation cache and the invalidation operations correspond to invalidated memory pages in which a virtual memory address does not exist for an actual memory address.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.52727
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15653776', '15841890', '13729361', '12708376', '15021133']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4690325742029338
- 35 USC 102 Novelty (BERT): 0.5011827000800794
- Combined Prediction Score: 0.4722475867906484
- Mean Citation Score: 219.067548
- Max Citation Score: 296.11343
- Similarity Product: 293.1358313204485

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test