PATENT CLAIM ANALYSIS

Application Number: 16220441
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["438", "067000"]

Abstract:
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Claim (Index 15):
A method comprising:\n providing a first semiconductor element comprising a first substrate, a first inter-level dielectric (ILD) layer over the first substrate, a first interconnection feature in the first ILD layer, and a conductive plug in the first ILD layer; providing a second semiconductor element comprising a second substrate, a second inter-level dielectric (ILD) layer over the second substrate, and a second interconnection feature in the second ILD layer, wherein the first semiconductor element is disposed over the second semiconductor element; forming a substrate trench in the first substrate to expose the first ILD layer; forming a deep-interconnection-trench (DIT) pattern mask in the substrate trench; etching the exposed first ILD layer and the second ILD layer through the DIT pattern mask to form a first DIT that exposed a portion of the second interconnection feature; etching the DIT pattern mask to form a second DIT, the second DIT having an upper portion and the first DIT as a lower portion; and forming a conductive deep plug within the second DIT to couple the first and second semiconductor elements.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.31111
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15864979', '15167390', '13898641', '13937055', '15886812']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8395661203405966
- 35 USC 102 Novelty (BERT): 0.5172718498817033
- Combined Prediction Score: 0.8073366932947073
- Mean Citation Score: 252.699474
- Max Citation Score: 318.8047200000001
- Similarity Product: 295.0996700239707

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test