PATENT CLAIM ANALYSIS

Application Number: 15981928
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["257", "330000"]

Abstract:
A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

Claim (Index 15):
The device of  claim 11 , wherein at its bottommost portion the memory layer only extends vertically in a direction perpendicular to a plane coinciding with the top surface of the substrate or each half of the bottommost portion of the memory layer, on opposite sides of a vertical plane passing through an axial center of the memory layer, has an L-shaped cross section, and\n the upper channel extends conformally alongside the bottommost portion of the memory layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 93.0
- Lexical Diversity: 2.14545
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15514239', '15639733', '14831449', '14725476', '13800872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9293381901563296
- 35 USC 102 Novelty (BERT): 0.5026856099453778
- Combined Prediction Score: 0.8866729321352346
- Mean Citation Score: 250.361496
- Max Citation Score: 260.1696
- Similarity Product: 189.9028470703125

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test