PATENT CLAIM ANALYSIS

Application Number: 15924043
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "148000"]

Abstract:
A memory device is disclosed. The memory device includes a bottom contact. The memory device also includes a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure, where a first contact formed at an interface between the bottom contact and the memory layer is ohmic, and where a second contact formed at an interface between the memory layer and the top electrode is ohmic.

Claim (Index 19):
The method of  claim 15 , wherein the memory device further comprises a bottom barrier between the electrically conductive oxide layer and the bottom contact, wherein a second contact formed at an interface between the electrically conductive oxide layer and the bottom barrier is ohmic, and wherein the method further comprises causing the first current to be conducted through the bottom barrier.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.81081
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15924014', '15923992', '15204215', '11789344', '12556771']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8097373045333367
- 35 USC 102 Novelty (BERT): 0.5120561150810015
- Combined Prediction Score: 0.7799691855881031
- Mean Citation Score: 234.273512
- Max Citation Score: 327.71222
- Similarity Product: 274.7308195700466

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test