PATENT CLAIM ANALYSIS

Application Number: 15981505
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "369000"]

Abstract:
A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.

Claim (Index 14):
The method of  claim 13 , wherein forming a gate stack structure comprises:\n forming a gate dielectric material layer covering the first separation region, a portion of the first semiconductor column above the first separation region, and a portion of the second semiconductor column above the first separation region; forming a P-type work function regulation material layer and a N-type work function regulation material layer, wherein the P-type work function regulation material layer is on the first semiconductor column and a portion of the gate dielectric material layer on a first portion of the first separation region, and the N-type work function regulation material layer is on the second semiconductor column and a portion of the gate dielectric material layer on a second portion of the first separation region; forming a gate material layer on the P-type work function regulation material layer and the N-type work function regulation material layer; conducting an etch-back process on the gate material layer to expose the gate dielectric material layer and the P-type work function regulation material layer on an upper portion of the first semiconductor column, and to expose the gate dielectric material layer and the N-type work function regulation material layer on an upper portion of the second semiconductor column; removing the gate dielectric material layer and the P-type work function regulation material layer on the upper portion of the first semiconductor column to expose the upper portion of the first semiconductor column; and removing the gate dielectric material layer and the N-type work function regulation material layer on the upper portion of the second semiconductor column to expose the upper portion of the second semiconductor column, wherein the remaining gate dielectric material layer becomes the gate dielectric layer, the remaining P-type work function regulation material layer becomes the P-type work function regulation layer, the remaining N-type work function regulation material layer becomes the N-type work function regulation layer, and the remaining gate material layer becomes the gate.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 2.60938
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15916729', '14165930', '14621440', '14271909', '15455203']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9183877617656812
- 35 USC 102 Novelty (BERT): 0.4774258947254463
- Combined Prediction Score: 0.8742915750616577
- Mean Citation Score: 164.915688
- Max Citation Score: 173.95296000000005
- Similarity Product: 128.25168776733403

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test