PATENT CLAIM ANALYSIS

Application Number: 16431012
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["257", "040000"]

Abstract:
An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

Claim (Index 8):
The apparatus as set forth in  claim 1 , wherein the first type of carrier is an electron and the second type of carrier is a hole.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 100.0
- Lexical Diversity: 3.47826
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15346546', '15346462', '14226285', '10762627', '14717344']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9015032913616003
- 35 USC 102 Novelty (BERT): 0.5527348261601881
- Combined Prediction Score: 0.8666264448414591
- Mean Citation Score: 214.859312
- Max Citation Score: 390.35638
- Similarity Product: 385.1661751386583

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test