PATENT CLAIM ANALYSIS

Application Number: 15868484
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "316000"]

Abstract:
An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

Claim (Index 6):
The transistor of  claim 1 , wherein the first insulating layer includes a first portion having a first thickness and a second portion having a second thickness that is smaller than the first thickness.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 1.425
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12812533', '14883364', '12374793', '12374795', '14181427']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9176577770283136
- 35 USC 102 Novelty (BERT): 0.5355333202042095
- Combined Prediction Score: 0.8794453313459034
- Mean Citation Score: 279.755196
- Max Citation Score: 355.38553
- Similarity Product: 311.8714124250055

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test