PATENT CLAIM ANALYSIS

Application Number: 16159498
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-07
Patent Classification: ["341", "120000"]

Abstract:
A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V d  having a first input, a second input, and an output; a first plurality of capacitors C p [0 :n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C n [0 :n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V d  and the digital output port.

Claim (Index 26):
The successive approximation register analog-to-digital converter of  claim 19  wherein the set of bits are divided into a plurality of collapsible bit groupings with each collapsible bit grouping implemented by a subset of capacitors from the first plurality of capacitors and the second plurality of capacitors.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.46296
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15799812', '14932798', '15391573', '15052452', '13085920']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6552773813402794
- 35 USC 102 Novelty (BERT): 0.591304666418211
- Combined Prediction Score: 0.6488801098480725
- Mean Citation Score: 442.3388059999999
- Max Citation Score: 531.8103
- Similarity Product: 385.2014358131647

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test