PATENT CLAIM ANALYSIS

Application Number: 16174180
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["365", "191000"]

Abstract:
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

Claim (Index 17):
The memory device of  claim 13 , wherein the register values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 3.16
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15665304', '15394009', '15081745', '14613270', '12519908']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8589970657314853
- 35 USC 102 Novelty (BERT): 0.559987788093088
- Combined Prediction Score: 0.8290961379676456
- Mean Citation Score: 341.2453000000001
- Max Citation Score: 384.30798
- Similarity Product: 313.35135115819213

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test