PATENT CLAIM ANALYSIS

Application Number: 15922186
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "390000"]

Abstract:
Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

Claim (Index 8):
The device as claimed in  claim 1 , wherein top surfaces of the peripheral gate stacks are positioned between a top surface of the lower electrode and a bottom surface of the lowermost one of the upper electrodes.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 2.78846
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15642829', '15661280', '15426081', '15251510', '15805560']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.934654575303876
- 35 USC 102 Novelty (BERT): 0.5509486097623434
- Combined Prediction Score: 0.8962839787497228
- Mean Citation Score: 324.4903240000001
- Max Citation Score: 427.91818
- Similarity Product: 309.8188229325748

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test