PATENT CLAIM ANALYSIS

Application Number: 15865892
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "185170"]

Abstract:
A method of operating a three-dimensional memory device includes applying a target string bias voltage to a selected drain select gate electrode which partially surrounds a row of memory stack structures that directly contact a drain select isolation structure, and applying a neighboring string bias voltage that has a greater magnitude than the target string bias voltage to an unselected drain select gate electrode that contacts the drain select level isolation structure.

Claim (Index 8):
The method of  claim 2 , wherein the three-dimensional memory device further comprises:\n drain regions contacting a top end of a respective one of the vertical semiconductor channels; and bit lines that are electrically shorted to a respective subset of the drain regions such that each bit line is electrically shorted to only one drain region per each neighboring pair of groups, and each bit line is electrically shorted to more than one drain region in each memory block.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 86.0
- Lexical Diversity: 1.68182
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15850073', '15818146', '15818061', '15628495', '15704286']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8134604120614437
- 35 USC 102 Novelty (BERT): 0.5246157395316746
- Combined Prediction Score: 0.7845759448084668
- Mean Citation Score: 322.257094
- Max Citation Score: 343.7213700000001
- Similarity Product: 268.97124215929995

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test