PATENT CLAIM ANALYSIS

Application Number: 16021550
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["257", "324000"]

Abstract:
Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

Claim (Index 18):
The method of  claim 16 , wherein forming the components includes providing the dielectric layers with low-k dielectric material.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 1.65517
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14835648', '10884337', '15612245', '14998194', '14852429']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9204186338188156
- 35 USC 102 Novelty (BERT): 0.4773461654275005
- Combined Prediction Score: 0.876111386979684
- Mean Citation Score: 161.58973799999995
- Max Citation Score: 173.71893
- Similarity Product: 127.70553315119147

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test