PATENT CLAIM ANALYSIS

Application Number: 15924600
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["327", "270000"]

Abstract:
An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.

Claim (Index 8):
The input buffer circuit according to  claim 7 , wherein the second delay matching circuit includes one pair of unit delay circuits,\n wherein each of the unit delay circuits includes:\n a second inverter configured to invert the second input signal; \n a first resistor coupled to an output terminal of the second inverter; and \n a plurality of second capacitors coupled in parallel to an output terminal of the second resistor.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 3.12766
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15499238', '11649805', '15351910', '12205668', '12208978']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7951698703209731
- 35 USC 102 Novelty (BERT): 0.5059882907781015
- Combined Prediction Score: 0.7662517123666859
- Mean Citation Score: 207.297928
- Max Citation Score: 306.9387200000001
- Similarity Product: 267.9460212201501

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test