PATENT CLAIM ANALYSIS

Application Number: 15904292
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "230020"]

Abstract:
Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

Claim (Index 14):
An integrated circuit, comprising:\n memory circuitry having multiple banks of bitcells, wherein each bank of bitcells has columns of bitcells that represent bits, wherein each bank of bitcells has a first column of bitcells that represents a nearest bit of the bits, and wherein each bank of bitcells has a last column of bitcells that represents a farthest bit of the bits; multiple local input/output (IO) circuits, wherein each local IO circuit includes sense amplifier circuitry coupled to corresponding banks of the multiple banks of bitcells to assist with accessing data in the memory circuitry; a global IO multiplexer circuit having multiple multiplexer circuits coupled to outputs of corresponding sense amplifiers of the multiple local IO circuits; a global control circuit coupled to the multiple multiplexer circuits of the global IO multiplexer circuit, wherein the last column of bitcells of an upper bank is farther away from the global control circuit than the first column of bitcells such that the farthest bit of the bits is farther away from the global control circuit than the nearest bit of the bits; first bypass circuitry coupled to the sense amplifier circuitry at the farthest bit of the farthest bank to receive an output signal from the sense amplifier circuitry and provide an output data signal based on the output signal from the sense amplifier circuitry; and second bypass circuitry coupled to the global IO multiplexer circuit at the nearest bit.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 88.0
- Lexical Diversity: 2.70588
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15891212', '15789715', '15256200', '15477516', '15490352']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.744106249097215
- 35 USC 102 Novelty (BERT): 0.4892430081963749
- Combined Prediction Score: 0.718619925007131
- Mean Citation Score: 171.0528
- Max Citation Score: 210.76051
- Similarity Product: 149.48036605064215

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test