PATENT CLAIM ANALYSIS

Application Number: 15744829
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["345", "055000"]

Abstract:
The invention discloses a pixel internal compensation circuit and riving method. The pixel internal compensation circuit comprises: first TFT (T 1 ), with gate connected to third control signal (SCAN 3 ), source and drain connected to data voltage (Vdata) and first node (A); second TFT (T 2 ), with gate connected to first node (A), source and drain connected to second node (B) and high voltage power source (OVDD); third TFT (T 3 ), with gate connected to first control signal (SCAN 1 ), source and drain connected to first node (A) and reference voltage (Vref); fourth TFT (T 4 ), with gate connected to second control signal (SCAN 2 ), source and drain connected to second node (B) and initial voltage (Vini); capacitor C 1 , with two ends connected to first node (A) and second node (B); OLED, with anode connected to second node (B), and cathode connected to low voltage power source (OVSS). The invention provides a corresponding driving method. The invention uses parallel driving mode to effectively increase sensing time of threshold voltage compensation to improve compensation effect.

Claim (Index 11):
A pixel internal compensation circuit, which comprises:\n a first thin film transistor (TFT), having a gate connected to a third control signal, a source and a drain connected respectively to a data voltage and a first node; a second TFT, having a gate connected to the first node, a source and a drain connected respectively to a second node and a high voltage power source; a third TFT, having a gate connected to a first control signal, a source and a drain connected respectively to the first node and a reference voltage; a fourth TFT, having a gate connected to a second control signal, a source and a drain connected respectively to the second node and an initial voltage; a capacitor, having two ends connected respectively to the first node and the second node; an OLED, having an anode connected to the second node, and a cathode connected to a low voltage power source; wherein the initial voltage being less than activation voltage of the OLED, and the difference between reference voltage and initial voltage (reference voltage\u2212initial voltage) being greater than threshold voltage of the second TFT; wherein the first control signal, the second control signal, and the third control signal having timing sequence configured for a reset phase, a sensing phase, a data write-in phase, and a light-emitting phase; wherein in the reset phase, the first control signal beings at high voltage, the second control signal being at high voltage, and the third control signal being at low voltage; wherein in the sensing phase, the first control signal being at high voltage, the second control signal being at low voltage, and the third control signal being at low voltage; wherein in the data write-in phase, the first control signal being at low voltage, the second control signal being at low voltage, and the third control signal being at high voltage.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 86.0
- Lexical Diversity: 3.23288
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15505097', '15328494', '15328497', '15328493', '15744073']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7000209068424427
- 35 USC 102 Novelty (BERT): 0.5098367264846081
- Combined Prediction Score: 0.6810024888066593
- Mean Citation Score: 275.267004
- Max Citation Score: 294.5731
- Similarity Product: 224.07487075517184

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test