PATENT CLAIM ANALYSIS

Application Number: 15926274
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["716", "119000"]

Abstract:
A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.

Claim (Index 7):
The method as recited in  claim 6 , wherein the fabricating step includes fabricating the assist features using a directed self-assembly process.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 1.48387
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15206789', '14185491', '14750742', '14586268', '11863577']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2965863392193987
- 35 USC 102 Novelty (BERT): 0.5159522082273011
- Combined Prediction Score: 0.318522926120189
- Mean Citation Score: 178.98501399999995
- Max Citation Score: 350.71848
- Similarity Product: 339.48175257648467

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test