PATENT CLAIM ANALYSIS

Application Number: 15864330
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "347000"]

Abstract:
Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.

Claim (Index 8):
The semiconductor device of  claim 1 , wherein the substrate comprises on its upper portion a fin-shaped active pattern including a first region under the gate electrode and second regions on the opposite sides of the gate electrode,\n the channel semiconductor patterns are disposed on the first region, and the bottom surfaces of the source/drain regions are lower than a bottom surface of a lowermost one of the channel semiconductor patterns and higher than top surfaces of the second regions.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 86.0
- Lexical Diversity: 1.93333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14989485', '15786864', '15724874', '15133424', '15245549']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9223309197469578
- 35 USC 102 Novelty (BERT): 0.5102371019590233
- Combined Prediction Score: 0.8811215379681644
- Mean Citation Score: 290.0187640000001
- Max Citation Score: 293.60925
- Similarity Product: 256.42961326168466

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test