PATENT CLAIM ANALYSIS

Application Number: 16181130
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Claim (Index 8):
The semiconductor device of  claim 1 , further comprising a conductive pad formed on the semiconductor substrate, wherein the conductive pad is partially covered by the passivation layer, and the conductive pad is electrically connected to the landing pad conductive element of the interconnect structure and the conductive pad has a direct interface with a surface of the landing pad conductive element.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.825
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13313811', '15477717', '13272540', '14058466', '13370895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9015983380011614
- 35 USC 102 Novelty (BERT): 0.4873973602450226
- Combined Prediction Score: 0.8601782402255476
- Mean Citation Score: 220.99029
- Max Citation Score: 258.40744
- Similarity Product: 247.4936128267432

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test