PATENT CLAIM ANALYSIS

Application Number: 15983405
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "330000"]

Abstract:
A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

Claim (Index 4):
The semiconductor device of  claim 1 , wherein a bottom surface of the gate contact has a stepped profile at a boundary between the first portion and the second portion.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.8
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15821230', '15055666', '15082820', '15956006', '15405420']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9356890856136302
- 35 USC 102 Novelty (BERT): 0.509826272900659
- Combined Prediction Score: 0.893102804342333
- Mean Citation Score: 303.195534
- Max Citation Score: 312.60876
- Similarity Product: 279.315358830042

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test