PATENT CLAIM ANALYSIS

Application Number: 16294411
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["257", "099000"]

Abstract:
A LED chip including a first semiconductor layer; an active layer; a second semiconductor layer; a plurality of indentations, wherein each indentation extends downward to reach and expose the first semiconductor layer, wherein each indentation includes a bottom part and two side surfaces in a cross sectional view; an exposing area exposing the first semiconductor layer at a side of the LED chip; a first metal layer disposed on the second semiconductor layer and electrically connecting to the first semiconductor layer; and a first insulating layer formed between the first metal layer and the second semiconductor layer to isolate the first metal layer from the second semiconductor layer; wherein the first metal layer continuously extends to the plurality of indentations, covers the bottom part, the two side surfaces of each indentation and a top surface of the second semiconductor layer around the two side surfaces and contacts the exposing area; and wherein the first metal layer includes a plurality of recesses corresponding to the plurality of indentations.

Claim (Index 1):
A light-emitting diode (LED) chip, comprising:\n a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; a plurality of indentations, wherein each indentation extends downward to reach the first semiconductor layer and exposes the first semiconductor layer, wherein each indentation comprises a bottom part and two side surfaces in a cross sectional view; an exposing area exposing the first semiconductor layer at a side of the LED chip; a first metal layer disposed on the second semiconductor layer and electrically connecting to the first semiconductor layer; and a first insulating layer formed on the second semiconductor layer and between the first metal layer and the second semiconductor layer to isolate the first metal layer from the second semiconductor layer; wherein the first metal layer continuously extends to the plurality of indentations, covers the bottom part, the two side surfaces of each indentation and a top surface of the second semiconductor layer around the two side surfaces and contacts the exposing area; and wherein the first metal layer comprises a plurality of recesses corresponding to the plurality of indentations.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 99.0
- Lexical Diversity: 3.10345
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14826646', '13715120', '15078488', '12422027', '14752413']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8980801140219405
- 35 USC 102 Novelty (BERT): 0.4810277592993327
- Combined Prediction Score: 0.8563748785496798
- Mean Citation Score: 195.220586
- Max Citation Score: 240.61946
- Similarity Product: 226.3929046461153

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test