PATENT CLAIM ANALYSIS

Application Number: 16225094
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["345", "212000"]

Abstract:
A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.

Claim (Index 2):
The shift register circuit according to  claim 1 , wherein an output signal of a subsequent stage is input to a control electrode of the third transistor of each of the shift register basic circuits.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 98.0
- Lexical Diversity: 3.47727
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14805134', '15361785', '16106835', '15830061', '13356700']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7380996353736216
- 35 USC 102 Novelty (BERT): 0.5402892074469141
- Combined Prediction Score: 0.7183185925809509
- Mean Citation Score: 384.496642
- Max Citation Score: 390.28928
- Similarity Product: 340.42608713081364

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test