PATENT CLAIM ANALYSIS

Application Number: 15952609
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "154000"]

Abstract:
Systems, circuits, and chips for hardening a latch/flip-flop circuit against soft errors caused by alpha and neutron radiation are provided. As an example, a latch/flip-flop circuit including a switch to selectively couple a capacitor to first and second storage nodes during a hold phase is disclosed.

Claim (Index 4):
The circuit of  claim 1 , wherein the first transmission gate couples the capacitor between the output of the first logic element and the output of the second logic element during a hold phase of the circuit.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 91.0
- Lexical Diversity: 1.30769
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12895078', '12620042', '13479319', '12165578', '14446501']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7921208335653197
- 35 USC 102 Novelty (BERT): 0.4601298495516336
- Combined Prediction Score: 0.7589217351639511
- Mean Citation Score: 134.61721200000002
- Max Citation Score: 139.42738
- Similarity Product: 102.66172502803089

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test