PATENT CLAIM ANALYSIS

Application Number: 16144286
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Claim (Index 8):
An integrated chip, comprising:\n a first source/drain region disposed in a substrate; a second source/drain region disposed in the substrate and spaced apart from the first source/drain region; a common source/drain region disposed in the substrate and spaced between the first source/drain region and the second source drain region, wherein a plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region, the second source/drain region, and the common source/drain region; a select gate electrode extending over a first channel region in the substrate between the first source/drain region and the common source/drain region, the select gate electrode being separated from the first channel region by way of one or more select gate dielectric layers; a control gate electrode extending over a second channel region in the substrate between the common source/drain region and the second source/drain region, the control gate electrode being separated from the second channel region by way of a charge trapping dielectric structure, the charge trapping dielectric structure comprising a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer; and wherein the second channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 97.0
- Lexical Diversity: 2.39683
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15365156', '14865179', '14645993', '14779938', '14983682']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9204468123472052
- 35 USC 102 Novelty (BERT): 0.5107427472862212
- Combined Prediction Score: 0.8794764058411069
- Mean Citation Score: 234.062562
- Max Citation Score: 295.94983
- Similarity Product: 218.3109309908521

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test