PATENT CLAIM ANALYSIS

Application Number: 16157108
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "738000"]

Abstract:
A method of manufacturing a chip package structure comprising: disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface; forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface; forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars; forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars; and removing the first carrier.

Claim (Index 10):
The manufacturing method of the chip package structure as claimed in  claim 9 , further comprising:\n disposing a sub chip package on the first solder balls, wherein the sub chip package is electrically connected to the first solder balls, wherein the method of forming the sub chip package comprises:\n disposing the second semiconductor component on a second carrier, wherein the second semiconductor component comprises a second active surface and a plurality of second pads disposed on the second active surface; \n forming a plurality of second conductive pillars on the second pads, wherein each of the second conductive pillars is a solid cylinder; \n forming a plurality of through pillars on the second carrier, wherein the through pillars surround the second semiconductor component; \n forming a second encapsulant to encapsulate the second semiconductor component, the second conductive pillars and the through pillars, wherein the second encapsulant exposes an upper surface of each of the second conductive pillars and an upper surface of each of the through pillars; \n forming a second redistribution layer on the second encapsulant, wherein the second redistribution layer is electrically connected to the second conductive pillars and the through pillars; \n forming a plurality of second solder balls on the second redistribution layer; and \n removing the second carrier.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 3.18367
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15599477', '15455143', '15911183', '14960962', '15936444']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9243155265352042
- 35 USC 102 Novelty (BERT): 0.5337561775448801
- Combined Prediction Score: 0.8852595916361718
- Mean Citation Score: 293.764876
- Max Citation Score: 374.7112
- Similarity Product: 294.6623756574631

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test