PATENT CLAIM ANALYSIS

Application Number: 15954617
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["365", "189150"]

Abstract:
A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.

Claim (Index 4):
The word line decoder circuit as recited in  claim 2 , wherein the read mode comprises a first read period and a second read period, the word line decoder receives the first power in the first read period, and the word line decoder receives the third power in the second read period.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 91.0
- Lexical Diversity: 2.97619
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11502016', '15871124', '11316256', '11640388', '10409120']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8127135249937316
- 35 USC 102 Novelty (BERT): 0.4779950852016625
- Combined Prediction Score: 0.7792416810145247
- Mean Citation Score: 205.044618
- Max Citation Score: 208.31276
- Similarity Product: 156.13972105881453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test