PATENT CLAIM ANALYSIS

Application Number: 16035566
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "329000"]

Abstract:
Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low R DS(ON) , and is acceptable and suitable for manufacture at semiconductor fabrication. plants that cannot or typically do not make superjunction MOSFETs.

Claim (Index 31):
A die structure comprising:\n a substrate semiconductor layer of a first conductivity type; a first epitaxial semiconductor layer disposed on the substrate; a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure; a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer; an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, and wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer; and an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 95.0
- Lexical Diversity: 1.81609
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15815391', '15284488', '13684203', '14444953', '13594837']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9097201778670018
- 35 USC 102 Novelty (BERT): 0.5570866809725057
- Combined Prediction Score: 0.8744568281775522
- Mean Citation Score: 306.527468
- Max Citation Score: 416.86343
- Similarity Product: 354.7730215638626

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test