PATENT CLAIM ANALYSIS

Application Number: 15918431
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["324", "750300"]

Abstract:
To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.

Claim (Index 1):
A semiconductor device, comprising:\n a test pattern generator configured to generate a test pattern; a circuit under test configured to output, in response to the supply of the test pattern from the test pattern generator, a test result in accordance with the test pattern, an output response analyzer configured to compare an expected value to the test result; and a plurality of test control circuits configured to control the test pattern generator and the output response analyzer; the semiconductor device having:\n a first test mode in which a first test control circuit of the plurality of test control circuits controls the test pattern generator and the output response analyzer to cause the test pattern to be supplied to a test control circuit of the plurality of test control circuits other than the first test control circuit, to thereby perform a test; and \n a second test mode in which a second test control circuit different from the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern to be supplied to the first test control circuit, to thereby perform a test.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.96
- Patent Class: 324.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11188159', '13327847', '15508168', '10516583', '13062937']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5456792893919756
- 35 USC 102 Novelty (BERT): 0.4731738613177155
- Combined Prediction Score: 0.5384287465845496
- Mean Citation Score: 160.007132
- Max Citation Score: 179.1672
- Similarity Product: 128.3852887192726

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test