PATENT CLAIM ANALYSIS

Application Number: 15900479
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "401000"]

Abstract:
High-mobility semiconductor fins are formed on an insulator layer using techniques allowing precise control of fin heights. Lattice-matched fins are grown epitaxially on sidewalls of an essentially defect-free portion of a semiconductor template. The fins are formed within laterally extending trenches in a top dielectric layer, the thickness of which determines fin height. The trenches extend orthogonally to the template. Epitaxial overgrowth above the top dielectric layer is removed by planarization. The fin template and top dielectric layer are removed, leaving sets of parallel fins on the insulator layer. The fin template can be replaced by an isolation region for electrically isolating sets of fins.

Claim (Index 15):
A monolithic structure, comprising:\n a semiconductor substrate; a dielectric layer on the substrate, the dielectric layer including a top surface; a first set of parallel semiconductor fins extending vertically from the top surface of the dielectric layer, each of the semiconductor fins within the first set having an inner end portion; a second set of parallel semiconductor fins extending vertically from the dielectric layer, each of the parallel semiconductor fins within the second set having an inner end portion; a trench extending vertically through the dielectric layer down to the semiconductor substrate; and an isolation region comprising electrically insulating material and extending orthogonally with respect to the first and second sets of parallel semiconductor fins, the isolation region including a first portion extending beneath the top surface of the dielectric layer and into the trench and a second portion extending above the top surface of the dielectric layer, the second portion of the isolation region having a first sidewall adjoining the inner end portions of the first set of parallel semiconductor fins and a second sidewall adjoining the inner end portions of the second set of parallel semiconductor fins.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 88.0
- Lexical Diversity: 1.80952
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14961372', '14962401', '15344272', '15344256', '15818674']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.911049835686412
- 35 USC 102 Novelty (BERT): 0.5057231096669105
- Combined Prediction Score: 0.8705171630844619
- Mean Citation Score: 278.293254
- Max Citation Score: 284.78265
- Similarity Product: 243.97255027902423

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test