PATENT CLAIM ANALYSIS

Application Number: 15773549
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "043000"]

Abstract:
Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a fmfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Claim (Index 25):
The semiconductor device of  claim 24 , wherein the source contact and the drain contact completely encircle the surfaces of the IGZO nanowire.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 93.0
- Lexical Diversity: 2.25373
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15748842', '14757875', '14242907', '14135534', '14739233']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9236134132069856
- 35 USC 102 Novelty (BERT): 0.5079696115516353
- Combined Prediction Score: 0.8820490330414507
- Mean Citation Score: 218.27495600000003
- Max Citation Score: 249.85681
- Similarity Product: 161.97472163205686

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test