PATENT CLAIM ANALYSIS

Application Number: 15945418
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "458000"]

Abstract:
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.

Claim (Index 11):
The IC package of  claim 9 , wherein the semiconductor die is a silicon die.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 91.0
- Lexical Diversity: 2.22535
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14872910', '14885202', '15795915', '14851652', '14885243']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8594914308090222
- 35 USC 102 Novelty (BERT): 0.5617313866698314
- Combined Prediction Score: 0.8297154263951032
- Mean Citation Score: 214.571524
- Max Citation Score: 342.18915
- Similarity Product: 229.92420329305529

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test