PATENT CLAIM ANALYSIS

Application Number: 16008234
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-09
Patent Classification: ["365", "185290"]

Abstract:
An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

Claim (Index 18):
The electronic device of  claim 11 , wherein the pair of program/erase nodes comprise an erase gate and a word line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.81159
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15922571', '11593398', '15921858', '14546294', '11230078']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8155504883976558
- 35 USC 102 Novelty (BERT): 0.4879280938813164
- Combined Prediction Score: 0.7827882489460218
- Mean Citation Score: 220.384282
- Max Citation Score: 239.74597000000003
- Similarity Product: 178.81315197612645

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test