PATENT CLAIM ANALYSIS

Application Number: 15903396
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["713", "323000"]

Abstract:
Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Claim (Index 6):
The method of  claim 1 , further comprising determining assignments for the plurality of power domain assignments for hardware elements of the NoC based on determining correct power domain assignment for the hardware elements of the NoC, such that the power domain assignments satisfy the power specification, ensuring uninterrupted traffic flow in each of a plurality of power profiles and meet optimization rules.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 1.96154
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15701305', '15903462', '15903427', '14495689', '14738487']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4959651586127788
- 35 USC 102 Novelty (BERT): 0.5545052177726391
- Combined Prediction Score: 0.5018191645287648
- Mean Citation Score: 406.961678
- Max Citation Score: 466.18918
- Similarity Product: 315.5939241428924

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test