PATENT CLAIM ANALYSIS

Application Number: 15760681
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "154000"]

Abstract:
The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell ( 100 ). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Claim (Index 1):
A memory connected to a first supply voltage, the memory comprising:\n a plurality of memory cells arranged in a matrix having rows and columns; a plurality of wordlines, each wordline, WL, comprising a row of the plurality of memory cells; a plurality of bitline pairs wherein each bitline pair comprising: a column of the plurality of memory cells; a read bitline, RBL, arranged for reading of the memory cells of the bitline pair; and a write bitline, WBL, arranged for writing to the memory cells of the bitline pair; each memory cell comprising a static random access memory, SRAM, bitcell comprising:\n two cross-coupled inverters; \n a single write access transistor arranged to supply data from the WBL comprising the memory cell to the SRAM bitcell, wherein the single write access transistor being arranged to be activated using a write word line, WWL, signal; and \n a first read access transistor and a second read access transistor arranged to feed data from the SRAM bitcell, and wherein the second read access transistor being arranged to be activated using a read word line, RWL, signal, and wherein the first read access transistor arranged to translate data stored by the two cross-coupled inverters; \n wherein the bitcell is connected to an inverter arranged to connect the first read access transistor to a-ground during read operation of the memory cell and to connect the first read access transistor to the first supply voltage otherwise, wherein each WL of the plurality of wordlines being connected to a first and a second decoder, wherein the first decoder being arranged to decode a read address and to output the RWL signal to select a WL for reading data of the SRAM bitcells comprised in the memory cells of the WL, whereby the selected WL will supply read data through to the read data access transistors of the memory cells of the selected WL; and the second decoder being arranged to decode a write address and to output the WWL signal to select a WL for writing data to the SRAM bitcell comprised in the memory cells of the selected WL, whereby the selected WL will be supplied with data to the write access transistors of the memory cells of the selected WL.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 1.4
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15096563', '14976065', '15096434', '13539577', '11614231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8020672429385096
- 35 USC 102 Novelty (BERT): 0.4880227675161998
- Combined Prediction Score: 0.7706627953962787
- Mean Citation Score: 231.226824
- Max Citation Score: 238.97003
- Similarity Product: 171.48251195459903

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test