PATENT CLAIM ANALYSIS

Application Number: 15947992
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["365", "201000"]

Abstract:
A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.

Claim (Index 10):
A semiconductor device comprising:\n a memory cell array with a plurality of memory cells arranged in a matrix, wherein the memory cell array comprises: a first memory cell column included in the memory cell array and comprised of a first memory cell; and a second memory cell column included in the memory cell array and comprised of a second memory cell arranged at the same row as the first memory cell and adjoining the first memory cell, wherein the memory cell array further comprises: a first input/output circuit electrically coupled to the first memory cell column and to perform data input/output to the first memory cell; a second input/output circuit electrically coupled to the second memory cell column and to perform data input/output to the second memory cell; and an interface control circuit electrically coupled to the first input/output circuit and the second input/output circuit, wherein the interface control circuit comprises: a test address signal line; and a selection circuit electrically coupled to the test address signal line, wherein the first input/output circuit and the second input/output circuit are arranged between the interface control circuit and the memory cell array, wherein, in a normal mode, the first input/output circuit and the second input/output circuit perform data input/output respectively to the first memory cell and the second memory cell so as to perform data input/output every row to the memory cells, and in a test mode, a test address is inputted to the selection circuit via the test address signal line, and wherein, according to the test address, the selection circuit selects one of an input-output of the test data of the first memory cell using the first input/output circuit and an input-output of the test data of the second memory cell using the second input/output circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.67797
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['09691115', '10829949', '09793612', '10229035', '11165273']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8009671239411681
- 35 USC 102 Novelty (BERT): 0.4808059218166964
- Combined Prediction Score: 0.7689510037287209
- Mean Citation Score: 230.983572
- Max Citation Score: 244.99893
- Similarity Product: 198.3812441921997

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test