PATENT CLAIM ANALYSIS

Application Number: 15919250
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185050"]

Abstract:
A memory device includes first and second electrode layers, first and second semiconductor pillars, an interconnect, and a first connecting conductor. The first and second electrode layers are stacked in a first direction. The second electrode layers are positioned in the first direction when viewed from the first electrode layers. The first semiconductor pillar extends in the first direction through the first electrode layers. The second semiconductor pillar extends in the first direction through the second electrode layers. The interconnect is provided between the first and second electrode layers, and is electrically connected to the first and second semiconductor pillars. The first connecting conductor extends in the first direction, is connected to one of the first electrode layers and one of the second electrode layers. The first connecting conductor extends in the first direction, and crosses at least one of the second electrode layers.

Claim (Index 9):
The device according to  claim 8 , wherein\n the first electrode layers each include a first region, a first end portion, and a second region, the first region crossing the first semiconductor pillar, the first end portion being separated from the first region, and the second region linking the first region and the first end portion, the first electrode layers each have a first recess between the first region and the first end portion, the second region being recessed in a direction crossing the first direction at the first recess, the second electrode layers each include a third region, a second end portion, and a fourth region, the third region crossing the second semiconductor pillar, the second end portion being separated from the third region, and the fourth region linking the third region and the second end portion, the second electrode layers each have a second recess between the third region and the second end portion, the fourth region being recessed in a direction crossing the first direction at the second recess, the third connecting conductor extends in the first direction, passes through the first recesses of the first electrode layers other than the first electrode layer positioned at the end in the first direction, and passes through the second recesses of the second electrode layers, and the fourth connecting conductor extends in the first direction, passes through the first recesses of the first electrode layers, and passes through the second recesses of the second electrode layers other than the second electrode layer positioned at the end in the first direction.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 3.7619
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15907984', '15855186', '15906890', '15906423', '15700402']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8093676858787545
- 35 USC 102 Novelty (BERT): 0.4858897343799797
- Combined Prediction Score: 0.777019890728877
- Mean Citation Score: 203.045632
- Max Citation Score: 224.01086
- Similarity Product: 162.28582740683913

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test