PATENT CLAIM ANALYSIS

Application Number: 16059792
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["710", "308000"]

Abstract:
The present disclosure provides a technique of suppressing competition of processes in a semiconductor device employing a multilayer bus configuration. A semiconductor device employing a multilayer bus configuration includes a control device controlling an access from each of bus maters to each memory, and a storage device for storing a corresponding relation between identification information identifying a storage region included in each memory and a group to which the storage region belongs. On the basis of an instruction of assuring a storage region including designation of a group, with reference to a corresponding relation between a group designated by an instruction and identification information from the corresponding relation stored in the storage device, the control device specifies one or more storage regions belonging to the designated group, assures the storage region used by a bus master on the basis of the use state of the specified storage region, and outputs information for accessing the assured storage region to the bus master corresponding to the instruction.

Claim (Index 9):
A semiconductor device comprising:\n a plurality of bus masters; a plurality of buses which are coupled to the bus masters, respectively; a plurality of memories each of which is coupled to at least any of the plurality of buses; a control device for controlling an access from each of the bus maters to any of the plurality of memories via the bus coupled to the bus master; and a storage device for storing a corresponding relation between identification information identifying each of the memories and a group to which the memory belongs, wherein the control device detects a use state of each of the memories, on the basis of an instruction of assuring a storage region used by any of the plurality of bus masters from the plurality of memories, with reference to a corresponding relation between a group designated by the instruction and the identification information from the corresponding relation, specifies one or more memories belonging to the designated group from the plurality of memories, assures the storage region to be used from the specified one or more memories on the basis of the detected use state, and outputs information for accessing the assured storage region to the bus master corresponding to the instruction.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 96.0
- Lexical Diversity: 2.36986
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11213795', '11493904', '11569753', '13680268', '12109894']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6096729185445866
- 35 USC 102 Novelty (BERT): 0.4632502023424441
- Combined Prediction Score: 0.5950306469243725
- Mean Citation Score: 146.132638
- Max Citation Score: 160.73238
- Similarity Product: 128.96520339049815

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test