PATENT CLAIM ANALYSIS

Application Number: 15960847
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["327", "211000"]

Abstract:
A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.

Claim (Index 12):
A flip-flop circuit comprising:\n a first latch circuit comprising:\n a power supply node; \n a first input node; \n a second input node; \n a first output node; \n a second output node; \n a first switching device coupled between the first output node and the second output node, the first switching device being configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal; \n a first transistor having a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node; \n a second transistor having a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node; and \n a second switching device coupled between the common node and the power supply node, the second switching device being configured to be turned on in response to the second state of the clock signal and to be turned off in response to the first state of the clock signal; and \n a second latch circuit comprising:\n a third input node coupled with the first output node; \n a fourth input node coupled with the second output node; \n a third output node; \n a fourth output node; and \n a third switching device coupled between the third output node and the fourth output node, the third switching device being configured to be turned on in response to the second state of the clock signal and to be turned off in response to the first state of the clock signal.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 3.7561
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14630941', '13951306', '15443504', '14539407', '11226564']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7575532758214302
- 35 USC 102 Novelty (BERT): 0.469393240081741
- Combined Prediction Score: 0.7287372722474613
- Mean Citation Score: 175.969804
- Max Citation Score: 237.16963
- Similarity Product: 220.64232716728333

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test