PATENT CLAIM ANALYSIS

Application Number: 16049790
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["257", "737000"]

Abstract:
Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape.

Claim (Index 12):
The microelectronic package structure of  claim 11  wherein the solder bumps attached to each of the individual ones of the first plurality of interconnect structures are directly attached to interconnect structures disposed on the board.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 95.0
- Lexical Diversity: 2.675
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15635555', '14067809', '15720480', '14748496', '14621936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9155584080289256
- 35 USC 102 Novelty (BERT): 0.4637033135844189
- Combined Prediction Score: 0.870372898584475
- Mean Citation Score: 139.66476199999997
- Max Citation Score: 146.74916000000005
- Similarity Product: 113.14728012982847

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test