PATENT CLAIM ANALYSIS

Application Number: 16041013
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "774000"]

Abstract:
An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Claim (Index 2):
The method of  claim 1 , further including plugging the at least one second via opening with a high-pressure TEOS plug prior to the step of filling the plurality of first via openings.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 95.0
- Lexical Diversity: 2.61404
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13962349', '15601406', '13477586', '14206756', '15441783']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9187066991876576
- 35 USC 102 Novelty (BERT): 0.5283371620138645
- Combined Prediction Score: 0.8796697454702782
- Mean Citation Score: 218.303
- Max Citation Score: 288.1009
- Similarity Product: 156.63710493560438

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test