PATENT CLAIM ANALYSIS

Application Number: 15869023
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "341000"]

Abstract:
In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Claim (Index 15):
The manufacturing method for semiconductor devices according to  claim 14 , further comprising the step of:\n (e) forming a source electrode to be coupled with the source region.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.04167
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14965899', '14826075', '15355469', '16300348', '15640375']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9040625092724304
- 35 USC 102 Novelty (BERT): 0.5164661030597637
- Combined Prediction Score: 0.8653028686511638
- Mean Citation Score: 241.404856
- Max Citation Score: 303.7593700000001
- Similarity Product: 207.6605720316637

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test