PATENT CLAIM ANALYSIS

Application Number: 16355740
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["257", "774000"]

Abstract:
Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs.

Claim (Index 1):
A system for stacking Integrated Circuits vertically to create a three dimensional chip package, said system comprising:\n one or more silicon die; one or more redistribution layers; one or more through silicon via; one or more contact pads; a dielectric substrate; high speed serial circuits; wherein said one or more silicon die contain said high speed serial circuits; wherein said high speed serial circuits are staggered on said one or more silicon die; wherein said one or more silicon die are stacked vertically on top of each other in such a way that said high speed serial circuits of said one or more stacked silicon die do not block each other; wherein one or more fiducials are used to optically align said one or more silicon die that are stacked vertically on top of each other; wherein said one or more through silicon via are placed in said high speed serial circuits; wherein said one or more distribution layer is placed between two of said one or more silicon die; wherein said one or more silicon die along with said one or more redistribution layer are stacked on top of said dielectric substrate; wherein said one or more contact pads are placed on said dielectric substrate; wherein said one or more distribution layers are used to interconnect said one or more through silicon via belonging to said two of said one or more silicon die or to interconnect said one or more through silicon via to said one or more contact pads.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 99.0
- Lexical Diversity: 1.4
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12205875', '13192217', '13456968', '12889615', '13304968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9153969587402776
- 35 USC 102 Novelty (BERT): 0.5540058755682307
- Combined Prediction Score: 0.8792578504230729
- Mean Citation Score: 266.39407600000004
- Max Citation Score: 415.04346
- Similarity Product: 400.3765864024401

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test