PATENT CLAIM ANALYSIS

Application Number: 16150224
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["708", "620000"]

Abstract:
A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.

Claim (Index 2):
A system comprising:\n a memory storing a first plurality of multiplier operands and a second plurality of multiplicand operands; a processor coupled to the memory to receive the first plurality of multiplier operands and the second plurality of multiplicand operands and to multiply each one of the first plurality of multiplier operands with every one of the second plurality of multiplicand operands, the processor including an array of circuit tiles arranged in rows and columns, each circuit tiles in the array including:\n a multiplier circuit coupled to receive one multiplier operand and one multiplicand operand and provide a multiplication result; \n an adder circuit coupled to the multiplier circuit to receive the multiplication result, add it to any previous multiplication result stored in an accumulator circuit and provide a sum; and \n the accumulator circuit coupled to the adder circuit to store the sum as an accumulation result.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 97.0
- Lexical Diversity: 1.18182
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15224176', '11497496', '09854853', '14748956', '10996103']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4648311881557713
- 35 USC 102 Novelty (BERT): 0.5813085740426979
- Combined Prediction Score: 0.476478926744464
- Mean Citation Score: 314.47214
- Max Citation Score: 499.39554
- Similarity Product: 387.9974180598342

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test