PATENT CLAIM ANALYSIS

Application Number: 15945822
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "296000"]

Abstract:
A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.

Claim (Index 11):
A method for manufacturing a semiconductor device, comprising:\n provided a substrate; forming a well region in the substrate; forming a first isolation region and a second isolation region in the substrate, wherein the first isolation region is adjacent to the second isolation region; forming a dielectric layer on the well region between the first isolation region and the second isolation region, wherein the dielectric layer does not overlap the first isolation region and the second isolation region; forming a conductive layer on the dielectric layer; forming a first doped region in the well region and between the first isolation region and the second isolation region; forming an insulating layer on the dielectric layer, the first isolation region, the second isolation region, and the first doped region; forming a first contact via in the insulating layer and on an overlapping area between the dielectric layer and the conductive layer, wherein the first contact via is electrically connected to the conductive layer; and forming a second contact via in the insulating layer, wherein the second contact via is electrically connected to the doped region, wherein the well region and the first doped region have the same conductivity type.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 4.35135
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12101608', '15066374', '12342609', '13596704', '15645686']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916542144647467
- 35 USC 102 Novelty (BERT): 0.4733972564430562
- Combined Prediction Score: 0.872227655827026
- Mean Citation Score: 201.487418
- Max Citation Score: 205.41959
- Similarity Product: 168.29371872511032

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test