PATENT CLAIM ANALYSIS

Application Number: 16191763
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-11
Patent Classification: ["323", "315000"]

Abstract:
A bias current circuit which includes: a main unit including first PMOS and NMOS transistors constituting a first current path, and second PMOS and NMOS transistors constituting a second current path together with a first resistor; an output unit; and a supply voltage adapting unit including a third MOS transistor, a pull-up current source and a pull-down current source. The third MOS transistor is connected between a first node to which gates of the first and second PMOS transistors are connected and a second node to which drains of the second NMOS and PMOS transistors are connected. The pull-up current source is mirrored to the first PMOS transistor and configured to provide a current equal to a current provided by the pull-down current source. The bias current circuit has an operating voltage range encompassing low-voltage band such that it is operable at high and low voltages.

Claim (Index 1):
A bias current circuit comprising a bias current main unit, an output unit and a supply voltage adapting unit,\n the bias current main unit comprising a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first resistor, the first and second PMOS transistors having gates both connected to a first node, the first and second PMOS transistors being mirrored to each other, the first and second PMOS transistors having sources both connected to a supply voltage, the first NMOS transistor having a drain connected to a drain of the first PMOS transistor and a source that is grounded, the second NMOS transistor having a drain connected, along with a drain of the second PMOS transistor, to a second node and a source connected to a first end of the first resistor, a second end of the first resistor being grounded, the first NMOS transistor and the first PMOS transistor constituting a first current path, the first resistor, the second NMOS transistor and the second PMOS transistor constituting a second current path, the output unit mirrored to the first PMOS transistor and configured to output a bias current, the supply voltage adapting unit comprising a third MOS transistor, a pull-up current source and a pull-down current source, the third MOS transistor having a first terminal connected to the first node, a second terminal connected to the second node and a third terminal which is a gate and is connected to an electric potential that maintains the third MOS transistor in an ON state, the pull-up current source mirrored to the first PMOS transistor, the pull-down current source configured to provide a current that is equal in magnitude to a current provided by the pull-up current source, the pull-up current source connected to the second node, the pull-down current source connected to the first node, wherein the current from the pull-up current source is entirely fed into the third MOS transistor via the second node due to the current provided by the pull-up current source being equal in magnitude to the current provided by the pull-down current source.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 98.0
- Lexical Diversity: 2.31343
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15817830', '10948524', '10402472', '14840257', '11636876']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7518235346121851
- 35 USC 102 Novelty (BERT): 0.4864631003949073
- Combined Prediction Score: 0.7252874911904573
- Mean Citation Score: 261.664708
- Max Citation Score: 267.82306
- Similarity Product: 230.1529872337687

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test