PATENT CLAIM ANALYSIS

Application Number: 15966775
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["714", "011000"]

Abstract:
A redundant computer system utilizing comparison diagnostics and voting techniques includes a plurality of redundant channels. Each pair of the processors receives/obtains process information from I/O modules via dual redundant sensors (DRS). The processors execute an application program, whereby output module is utilized for comparing output data of the two processors. Output module receives output data from neighboring modules, if there is a deviation or other disparity in the output data. Each pair of processors, a voter and an improper sequence detector component disables the output module, if a majority of signals vote that output module fails. In addition, the system uses 2-of-3 voting, the system remains operational in the presence of up two transient or hard failures.

Claim (Index 3):
A redundant computer system comprising:\n a first channel, and a second channel, each channel comprising:\n a primary processor; \n a secondary processor, wherein said primary processor is in operative communication with said secondary processor; said primary and secondary processor operate in parallel redundancy; \n said primary processor in the first channel and said primary processor in the second channel are in operative communication with each other; \n said secondary processor in the first channel and said secondary processor in the second channel are in operative communication with each other; \n an input module includes in each channel a first and a second interface to provide operative communication of said input module with said primary and secondary processor, said input module can be digital or analog module; \n said input module in each channel is in operative communication with a first and a second section of a dual redundant sensor (DRS) for each controlled point that deliver an input data to said input module; \n means in said input module for calculating a deviation between values of said input data produced by said first and in second section of the DRS for each controlled point to indicate whether said deviation is within predetermined limits or not; \n said primary processor and said secondary processor in each channel receive said input data for synchronously execute an application program and for transfer an output data as a result of said application program execution to an output module via a first and a second interface; said output module can be digital or analog; \n said output module in each channel includes an output controller, said voter and improper sequence components, a logic circuit and a voting network; said output module can be digital or analog; \n said voter component is in operative communication with said PPM and said SPM, said ISD component is in operative communication with said voter component and with said output controller; \n said comparison diagnostic in said primary processor (PPM) and said secondary processor (SPM) in each channel for monitoring condition of said output module, said diagnostic includes a voter component and includes an improper sequence detector (ISD) component; \n said comparison diagnostic allows the system for disabling said output module if at least two elements among the PPM, the SPM, and the ISD vote that the output controller fails; \n means in said improper sequence detector that verify absence or presence a fault in timetable and verify consistency of program operations in an output module, said output module in operative communication with said primary processor and said secondary processor and with said ISD component; \n said output controller connected via a read only bus with a neighboring output controller for receiving/sending said output data from/to said neighboring output controller; \n means in said output controller for activating a disparity signal on input of said logic circuit for some controlled points if the associated primary and secondary processor produce said output data that are different due to occurrence of transient faults, or due to said deviation that is out of said predetermined limits for said controlled points; \n said disparity signal is activated as a result of an Exclusive NOR (XNOR) operation between single-bit output data that said output controller receives from the associated PPM and SPM; \n the primary processor and the secondary processor in each channel use said input data for synchronously execute an application program and for transfer an output data as a result of said application program execution to said output controller in said output module; \n said logic circuit and voting network perform a logic operation with said output data to provide 2-of-2 voting among output data produced by said first and second channel of the system, said voting network includes a fault recovery valve for each controlled point to provide no single point of failure of said voting network; \n said voting networks includes plurality switches in series, said switches in said first and second channels connected in parallel to provide output of the system; \n the system performs said 2-of-2 voting even though only two PPM or two SPM are operational; the system, thereby, continues to be operational in the presence of any two faults in said PPM and said SPM; \n said output controller connected via a read only buses with neighboring output controller for receiving/sending said output data from/to said neighboring output controller; \n said output controller excludes an own output data from inputs of said logic circuit and uses output data receiving from the neighboring output controller, the system then performs the 1-of-2 voting instead of 2-of-2 voting if said disparity signal activates in said output controller for some controlled points; \n the system, thereby, continues operate in the presence of said disparity in one channel, the system may perform a safe shutdown for the process, if said disparity occurs in first and second channel concurrently; \n said logic circuit is in operative communication with said output controller and in operative communication with said voting network, which contains multiple switches in series for each controlled points, said switches in said first and second channels connected in parallel; \n said logic circuit in said first channel provides outputs of the associated voting network as a product of said output data received from said output controller in said first channel and a sum of said output data receiving from output controllers in said first and second channel; \n said logic circuit in said second channel provides outputs of the associated voting network as a product of said output data received from said output controller in said second channel and a sum of said output data receiving from output controllers in said second and first channel.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.67089
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12316966', '10899667', '11923534', '10758977', '11389349']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2463857865797165
- 35 USC 102 Novelty (BERT): 0.5094847349115208
- Combined Prediction Score: 0.272695681412897
- Mean Citation Score: 185.776398
- Max Citation Score: 281.1801
- Similarity Product: 205.541565466404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test