PATENT CLAIM ANALYSIS

Application Number: 16102317
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["438", "183000"]

Abstract:
A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.

Claim (Index 9):
A semiconductor device, comprising:\n a first structure comprising a first gate structure disposed over a substrate, a first spacer element abutting the first gate structure, a first strained recess region over a recessed portion in the substrate adjacent the first gate structure; and a second structure comprising a second gate structure disposed over the substrate, a second spacer element abutting the second gate structure and a second strained recess region over a recessed portion in the substrate adjacent the second gate structure, wherein: the first gate structure includes a first gate dielectric region disposed over the substrate and underlying a first gate electrode, the second gate structure includes a second gate dielectric region disposed over the substrate and underlying a second gate electrode, a first spacer dielectric region disposed over the substrate and underlying the first spacer element, a second spacer dielectric region disposed over the substrate and underlying the second spacer element, and a height of the second gate dielectric region is the same as a height of the second spacer dielectric region.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 96.0
- Lexical Diversity: 3.16
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14809158', '15449582', '15068409', '15699643', '15846887']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8508026643634815
- 35 USC 102 Novelty (BERT): 0.476078066329647
- Combined Prediction Score: 0.8133302045600981
- Mean Citation Score: 184.429322
- Max Citation Score: 227.11765
- Similarity Product: 198.35895846745672

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test