PATENT CLAIM ANALYSIS

Application Number: 15900327
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-12
Patent Classification: ["711", "151000"]

Abstract:
The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Claim (Index 44):
The computer readable medium as defined in  claim 43 , wherein the instructions, when executed, further cause the one or more processor to report a clash condition when the sum of authorization bits is greater than 1.

Metadata:
- Claim Count in Document: 89.0
- Percentile: 88.0
- Lexical Diversity: 2.13725
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14082396', '14082645', '14458014', '14458052', '15900368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5403274024400164
- 35 USC 102 Novelty (BERT): 0.5502906119595844
- Combined Prediction Score: 0.5413237233919732
- Mean Citation Score: 257.677034
- Max Citation Score: 413.95746
- Similarity Product: 233.63740017923

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test