PATENT CLAIM ANALYSIS

Application Number: 16169796
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["257", "774000"]

Abstract:
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Claim (Index 10):
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:\n (a) forming a first-level interconnect over the main surface of a semiconductor substrate; (b) forming a first interlayer insulating film over the first-level interconnect; (b) forming, in the first interlayer insulating film, a first via hole for connecting to the first-level interconnect; (d) forming a first interconnect trench in the first interlayer insulating film in a region including a region in which the first via hole has been formed; (e) filling a metal film in the first interconnect trench and first via hole to form a second-level interconnect; (f) forming, over the second-level interconnect, a second interlayer insulating film having a first insulating film; (g) forming, in the second interlayer insulating film, a second via hole for connecting to the second-level interconnect; (h) forming a second interconnect trench in the second interlayer insulating film in a region including a region in which the second via hole has been formed; and (i) filling a metal film in the second interconnect trench and second via hole, thereby forming a third-level interconnect, wherein the second interlayer insulating film is thicker than the first interlayer insulating film, wherein in the step (h), the second interconnect trench is formed by using the first insulating film as an etching stopper film, and wherein in the step (d), the first interconnect trench is formed without using an etching stopper film.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 1.76786
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11453882', '12141195', '13081332', '13525195', '12141172']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.935001488597484
- 35 USC 102 Novelty (BERT): 0.6012838547707196
- Combined Prediction Score: 0.9016297252148076
- Mean Citation Score: 486.80999
- Max Citation Score: 509.54678
- Similarity Product: 492.6501019457818

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test