PATENT CLAIM ANALYSIS

Application Number: 15939292
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["257", "774000"]

Abstract:
A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

Claim (Index 9):
A method of manufacturing a package structure, comprising:\n forming a first redistribution circuit structure on a carrier; disposing at least one semiconductor die on a first side of the first redistribution circuit structure; forming through vias on the first side of the first redistribution circuit structure and aside of the at least one semiconductor die, wherein the through vias are electrically connected to the first redistribution circuit structure; encapsulating the at least one semiconductor die and the through vias in an insulating encapsulation; forming a second redistribution circuit structure on the insulating encapsulation, wherein the second redistribution circuit structure is electrically connected to the at least one semiconductor die and the through vias; and forming first antenna elements on a second side of the first redistribution circuit structure, the first antenna elements being mechanically separated and spaced apart from each other and each comprising an insulator and a metallic pattern disposed thereon, wherein edges of the first antenna elements are aside of edges of the at least one semiconductor die along a direction perpendicular to a stacking direction of the first redistribution circuit structure and the insulating encapsulation, and the second side is opposite to the first side.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.77083
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15652249', '15854736', '15696192', '15794006', '15202541']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91300780818246
- 35 USC 102 Novelty (BERT): 0.4794785583819632
- Combined Prediction Score: 0.8696548832024102
- Mean Citation Score: 190.057256
- Max Citation Score: 202.1296
- Similarity Product: 154.7567038820267

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test