PATENT CLAIM ANALYSIS

Application Number: 16232144
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["174", "262000"]

Abstract:
A printed wiring board includes a core substrate, and a build-up layer formed on the substrate. The substrate includes core material, third conductor layer, fourth conductor layer, and through-hole conductors. The build-up layer is formed on the core material and third conductor layer and includes insulating layers, first conductor layers, and via conductors. The build-up layer has central area and outer peripheral area such that the via conductors include central area via conductors and outer peripheral area via conductors, diameter of central area via conductor is smaller than diameter of outer peripheral area via conductor, the outermost first conductor layer includes first pads to mount first electronic component and second pads to mount second electronic component, the first and second pads are connected to each other via the central via conductors, and the lowermost insulating layer does not have the via conductors in the central area of the build-up layer.

Claim (Index 1):
A printed wiring board, comprising:\n a core substrate; and a first build-up layer formed on the core substrate, wherein the core substrate includes a core material, a third conductor layer formed on a first surface of the core material, a fourth conductor layer formed on a second surface of the core material on an opposite side with respect to the first surface, and a plurality of through-hole conductors penetrating through the core material and connecting the third conductor layer and the fourth conductor layer, the first build-up layer is formed on the first surface of the core material and the third conductor layer and includes a plurality of first resin insulating layers, a plurality of first conductor layers formed on the first resin insulating layers respectively, and a plurality of first via conductors penetrating through the first resin insulating layers and connecting the first conductor layers, and the first build-up layer has a central area and an outer peripheral area surrounding the central area formed such that the plurality of first via conductors includes a plurality of central area first via conductors formed in the central area and a plurality of outer peripheral area first via conductors formed in the outer peripheral area, that a diameter of each of the central area first via conductors is smaller than a diameter of each of the outer peripheral area first via conductors, that the plurality of first resin insulating layers includes a lowermost first resin insulating layer covering the first surface of the core material and the third conductor layer and includes an outermost first resin insulating layer, that the plurality of first conductor layers includes an outermost first conductor layer formed on the outermost first resin insulating layer and including a plurality of first pads positioned to mount a first electronic component to the first build-up layer and a plurality of second pads positioned to mount a second electronic component to the first build-up layer, that the first and second pads are connected to each other via the central area first via conductors, and that the lowermost first resin insulating layer does not have the first via conductors formed in the central area of the first build-up layer.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 98.0
- Lexical Diversity: 2.92857
- Patent Class: 174.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16167850', '14857074', '14920974', '15581253', '16166392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8495537897803269
- 35 USC 102 Novelty (BERT): 0.4903344427772821
- Combined Prediction Score: 0.8136318550800226
- Mean Citation Score: 259.940976
- Max Citation Score: 271.45184
- Similarity Product: 234.55534867229463

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test