PATENT CLAIM ANALYSIS

Application Number: 15951029
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["326", "039000"]

Abstract:
A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

Claim (Index 5):
The timer block of  claim 3 , further comprising a data selector that is configured to select the programmable time delay or the preset time delay.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 91.0
- Lexical Diversity: 2.26562
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15656978', '15673142', '15656954', '15656982', '15921201']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6580817819928851
- 35 USC 102 Novelty (BERT): 0.5378869153123189
- Combined Prediction Score: 0.6460622953248285
- Mean Citation Score: 307.91959400000013
- Max Citation Score: 388.6186
- Similarity Product: 264.6529010416627

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test