PATENT CLAIM ANALYSIS

Application Number: 16155482
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["341", "118000"]

Abstract:
In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes.

Claim (Index 4):
The system of  claim 1 , wherein the one or more control circuits are configured to apply adjustments during active operation of the DAC.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.50794
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15700383', '15949395', '15130617', '15130636', '15633157']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6016570219035635
- 35 USC 102 Novelty (BERT): 0.5384328308023597
- Combined Prediction Score: 0.5953346027934432
- Mean Citation Score: 299.635592
- Max Citation Score: 349.7041
- Similarity Product: 311.86333936040404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test