PATENT CLAIM ANALYSIS

Application Number: 16042498
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["438", "197000"]

Abstract:
Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

Claim (Index 4):
The field effect transistor of  claim 1 , wherein the internal spacers each comprises a crescent shape.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 1.77778
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15493441', '15007920', '15045759', '16042388', '15847894']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8932572199385495
- 35 USC 102 Novelty (BERT): 0.5417811376552268
- Combined Prediction Score: 0.8581096117102173
- Mean Citation Score: 334.2591240000001
- Max Citation Score: 386.74112
- Similarity Product: 369.7330283662415

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test