PATENT CLAIM ANALYSIS

Application Number: 15944565
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["363", "021030"]

Abstract:
An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the T D(L-H)  optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the T D(H-L)  optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the T DM  optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

Claim (Index 16):
The apparatus of  claim 15 , wherein the first timing circuit comprises:\n a current subtraction circuit configured to output a current difference between a pre-set current I th(Tz)  and a current I VSL  corresponding to the present input voltage, a summing resistor having a resistance value of R SUM  and coupled to a voltage supply V r  and to receive the current difference from the current subtraction circuit, a transistor having a gate connected to receive a voltage based on a comparison between a set voltage V SET  and a voltage across a set resistance R SET , wherein the voltage across the set resistance is based on a transistor current flowing through the resistance, a capacitor having a capacitance C r  coupled to receive a current equivalent to the transistor current, and wherein the first timing circuit is configured to modify the first dead time by providing an output T D(H-L)  according to the piece-wise linear function defined as: If \ue89e \ue89e I VSL > I th \ue8a0 ( Tz ) , T D \ue8a0 ( H - L ) = T SET If \ue89e \ue89e I VSL < I th \ue8a0 ( Tz ) , T D \ue8a0 ( H - L ) = V r + R sum \ue8a0 ( I th \ue8a0 ( Tz ) - I VSL ) V SET / R SET \ue89e C r where , T SET \ue89e \ue89e programed \ue89e \ue89e by \ue89e \ue89e R SET = V SET \ue89e T SET C r \ue89e V r .

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.73864
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15334170', '15334173', '15715818', '15662301', '12417780']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8290925187487409
- 35 USC 102 Novelty (BERT): 0.4917695290744115
- Combined Prediction Score: 0.795360219781308
- Mean Citation Score: 213.516146
- Max Citation Score: 234.92357
- Similarity Product: 172.2323402603114

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test