PATENT CLAIM ANALYSIS

Application Number: 16072301
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["257", "421000"]

Abstract:
An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

Claim (Index 12):
The non-volatile memory device of  claim 10 , wherein a thickness of the buffer layer is between 3 angstroms and 10 angstroms.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 95.0
- Lexical Diversity: 1.97403
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15755437', '15707491', '15157783', '11752157', '15656398']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9236644681413912
- 35 USC 102 Novelty (BERT): 0.5001399405309821
- Combined Prediction Score: 0.8813120153803504
- Mean Citation Score: 198.902784
- Max Citation Score: 203.99107
- Similarity Product: 127.21576302176356

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test