PATENT CLAIM ANALYSIS

Application Number: 16012037
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-06
Patent Classification: ["257", "676000"]

Abstract:
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; first metal bumps disposed on the connection pads; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first metal bumps and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a first blocking structure disposed on walls of the recess portion to surround side surfaces of the semiconductor chip.

Claim (Index 1):
A fan-out semiconductor package comprising:\n a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; first metal bumps disposed on the connection pads of the semiconductor chip; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first metal bumps and filling at least portions of the recess portion; a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other; and a first blocking structure disposed on walls of the recess portion to surround side surfaces of the semiconductor chip.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 94.0
- Lexical Diversity: 2.61667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15981651', '15986302', '15988647', '15978727', '15988541']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9392191847403452
- 35 USC 102 Novelty (BERT): 0.530996949311119
- Combined Prediction Score: 0.8983969611974225
- Mean Citation Score: 360.8616
- Max Citation Score: 367.49445
- Similarity Product: 348.83744142369034

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test