PATENT CLAIM ANALYSIS

Application Number: 15873005
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["709", "200000"]

Abstract:
Method and systems using stateful encryption for non-bypassable FPGA configuration including receiving, at an FPGA, FPGA-configuration data comprising a cryptographic state to initialize a cryptographic state of the FPGA, and decrypting, at the FPGA, the FPGA-configuration data, wherein decrypting the FPGA-configuration data yields at least a second cryptographic state and decrypted FPGA-configuration data. Embodiments can include receiving, at the FPGA, a challenge message, processing, at the FPGA, the challenge message to yield at least a third cryptographic state and a response, and transmitting the response from the FPGA.

Claim (Index 7):
The system of  claim 6  further comprising a memory arranged to store the FPGA-configuration data.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.37209
- Patent Class: 709.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12861586', '13967400', '15630476', '09747759', '14015443']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2824833021560031
- 35 USC 102 Novelty (BERT): 0.5351115322993193
- Combined Prediction Score: 0.3077461251703348
- Mean Citation Score: 263.20596
- Max Citation Score: 378.15103
- Similarity Product: 263.93526932686984

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test