PATENT CLAIM ANALYSIS

Application Number: 16049724
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["714", "758000"]

Abstract:
This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

Claim (Index 28):
The apparatus of  claim 12 , wherein the magnitude state of a check node stored in one or more memory units of the check node processor includes only the lowest two magnitudes among the magnitudes of all its incoming messages along with their respective edge indices.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 95.0
- Lexical Diversity: 1.47692
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14499284', '14950659', '14826161', '15686361', '11003940']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.387881985107217
- 35 USC 102 Novelty (BERT): 0.5153466653269855
- Combined Prediction Score: 0.4006284531291939
- Mean Citation Score: 306.18703399999987
- Max Citation Score: 315.19638
- Similarity Product: 213.5783904260731

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test