PATENT CLAIM ANALYSIS

Application Number: 16029649
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["174", "252000"]

Abstract:
A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.

Claim (Index 3):
The ceramic module as claimed in  claim 1 , wherein both the conductive circuit layer and the heat dissipation layer are made of an electroplated copper material, and the thickness of the heat dissipation layer is greater than the thickness of the conductive circuit layer.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 1.74576
- Patent Class: 174.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15797549', '13796489', '13024083', '15777582', '10852315']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8235165459840258
- 35 USC 102 Novelty (BERT): 0.5007766242417093
- Combined Prediction Score: 0.7912425538097941
- Mean Citation Score: 199.042048
- Max Citation Score: 205.37613
- Similarity Product: 135.09525924220918

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test