PATENT CLAIM ANALYSIS

Application Number: 15934886
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["711", "003000"]

Abstract:
A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Claim (Index 1):
A data access system comprising:\n a storage system, wherein the storage system includes:\n a main memory, and \n a cache module comprising a final level of cache (FLC) controller and a cache, wherein the cache of the cache module is configured as a final level of cache to be accessed by the FLC controller prior to the FLC controller accessing the main memory; and \n a processor coupled to one or more levels of cache, wherein the one or more levels of cache coupled to the processor are separate from the final level of cache, and wherein\n the processor is configured to generate, in response to data required by the processor not being cached in the one or more levels of cache coupled to the processor, a physical address corresponding to a physical location to be accessed in the storage system in order to retrieve the data required by the processor, \n the FLC controller is configured to generate a virtual address based on the physical address of the physical location to be accessed in the storage system, wherein the virtual address corresponds to i) a physical location within the final level of cache, or ii) a physical location within the main memory where the data required by the processor is stored, and \n the cache module is configured to cause, in response to determining the virtual address does not correspond to the physical location within the final level of cache, the data required by the processor to be retrieved from the physical location within the main memory.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 3.03846
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15454306', '14710988', '14937330', '15137611', '14519826']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5579082454553157
- 35 USC 102 Novelty (BERT): 0.567350768426641
- Combined Prediction Score: 0.5588524977524483
- Mean Citation Score: 370.484644
- Max Citation Score: 440.59894
- Similarity Product: 407.0115621825969

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test