PATENT CLAIM ANALYSIS

Application Number: 15899187
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["365", "189050"]

Abstract:
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Claim (Index 36):
A method of operating a system, the method comprising:\n receiving instructions at a memory device from a host; and executing the instructions on the memory device, wherein executing the instructions comprises performing a logical AND operation by:\n performing a first operation phase that includes:\n activating a first access line of the array, the first access line coupled to a first memory cell storing a data value corresponding to a first input of the logical AND operation; \n activating a first latch of sensing circuitry coupled to a sense line to which the first memory cell is coupled in order to latch the data value therein; \n activating a second latch of the sensing circuitry to copy the data value latched in the first latch to the second latch; and \n \n performing a second operation phase that includes:\n activating a second access line to which a second memory cell is coupled, the second memory cell storing a data value corresponding to a second input of the logical AND operation; \n while the second access line is activated, activating the first latch; and \n \n wherein subsequent to activating the first latch while the second access line is activated, the second latch stores an accumulated result of the logical AND operation.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.30909
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15439681', '15051112', '13962399', '14538399', '13784219']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8013283448931026
- 35 USC 102 Novelty (BERT): 0.5111657706443065
- Combined Prediction Score: 0.772312087468223
- Mean Citation Score: 307.544638
- Max Citation Score: 317.213
- Similarity Product: 261.16966996836663

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test