PATENT CLAIM ANALYSIS

Application Number: 16039422
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["718", "104000"]

Abstract:
Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.

Claim (Index 11):
A system comprising:\n a host; and a hardware accelerator device communicatively coupled to the host; wherein the hardware accelerator device comprises an integrated circuit configured, using a Hardware Description Language (HDL), to perform one or more functions;\n wherein the integrated circuit is configured to: \n execute a first acceleration task assigned by the host to be executed on the hardware accelerator device; \n detect status information of the first acceleration task before termination of the first acceleration task; and \n provide the detected status information to the host before termination of the first acceleration task; \n wherein the host comprises one or more processor cores configured to:\n receive from the hardware accelerator device, the status information of the first acceleration task, wherein the status information of the first acceleration task is received before termination of the first acceleration task, the status information indicating at least one of a cache miss/hit rate of the first acceleration task or a latency of data fetch by the first acceleration task; \n prepare for a second acceleration task during execution of the first acceleration task and before termination of the first acceleration task, the second acceleration task to be executed by the hardware accelerator device; and \n provide the preparation for the second acceleration task to the hardware accelerator device for executing the second acceleration task; \n wherein the integrated circuit of the hardware accelerator device is configured to execute the second acceleration task based on the preparation for the second acceleration task.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 1.92
- Patent Class: 718.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15098475', '15023694', '15471372', '15859372', '15222823']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4140546952452132
- 35 USC 102 Novelty (BERT): 0.5119086897293263
- Combined Prediction Score: 0.4238400946936245
- Mean Citation Score: 174.54751399999995
- Max Citation Score: 279.79724
- Similarity Product: 278.0687800726748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test