PATENT CLAIM ANALYSIS

Application Number: 16045956
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "185170"]

Abstract:
A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Claim (Index 8):
A memory system comprising:\n a nonvolatile semiconductor memory device comprising:\n first to n-th (n is an integer of 2 or more) strings, each of the first to n-th strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; \n a bit line electrically connected to the first to n-th strings; \n first to n-th select gate lines, the k-th (k is an integer that satisfies 7\u2264k\u2264n) select gate line electrically connected to a gate of the select transistor of the k-th string; \n a first word line electrically connected to gates of the first memory cells of the first to n-th strings; \n a second word line electrically connected to gates of the second memory cells of the first to n-th strings, \n a third word line electrically connected to gates of the third memory cells of the first to n-th strings; and \n a fourth word line electrically connected to gates of the fourth memory cells of the first to n-th strings, and \n a controller configured to perform first to n-th write processes and to perform (n+1)-th to 2n-th write processes after the first to n-th write processes, wherein the controller performs the (i+1)-th (i is an integer that satisfies 1\u2264i\u2264(n\u22121)) write process after the i-th write process, the controller performs the (j+1)-th (j is an integer that satisfies (n+1)\u2264j\u2264(2n\u22121)) write process after the j-th write process, the k-th write process includes writing data in the first memory cell of the k-th string and writing data in the second memory cell of the k-th string after the writing in the first memory cell of the k-th string, and the (n+k)-th write process includes writing data in the third memory cell of the k-th string and writing data in the fourth memory cell of the k-th string after the writing in the third memory cell of the k-th string.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 95.0
- Lexical Diversity: 2.85366
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15230857', '14200641', '13779427', '14847086', '14833719']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7647330871875689
- 35 USC 102 Novelty (BERT): 0.5074821078296001
- Combined Prediction Score: 0.739007989251772
- Mean Citation Score: 238.338484
- Max Citation Score: 317.62735
- Similarity Product: 305.4606960555792

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test