PATENT CLAIM ANALYSIS

Application Number: 16169480
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["710", "022000"]

Abstract:
A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

Claim (Index 10):
The memory management circuit of  claim 9 , wherein the second circuit is configured to write the second buffer to a source of the second buffer using the bit manipulation using the mask information.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 1.6
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11080376', '11132070', '11626414', '12205386', '13791345']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6925829856079385
- 35 USC 102 Novelty (BERT): 0.4849446921614682
- Combined Prediction Score: 0.6718191562632916
- Mean Citation Score: 165.02706
- Max Citation Score: 171.05841
- Similarity Product: 111.43871979018688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test