PATENT CLAIM ANALYSIS

Application Number: 16119676
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "369000"]

Abstract:
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

Claim (Index 1):
A semiconductor chip, comprising:\n gate electrode features formed within a region of the semiconductor chip, the gate electrode features positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein all gate gridlines extend in the y-direction, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature in the region having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature positioned thereon, wherein at least one gate electrode feature within the region forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature within the region forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type; at least six contact structures formed within the region of the semiconductor chip, wherein at least six gate electrode features within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six gate contact structures, each of the at least six gate contact structures having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in an x-direction, each of the at least six gate contact structures positioned and sized to overlap both edges of the top surface of the gate electrode feature to which it is in physical and electrical contact; and a first-metal layer formed above top surfaces of the gate electrode features within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate electrode features, the first-metal layer separated from the top surfaces of the gate electrode features by at least one insulator material, wherein the first-metal layer includes first-metal structures positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, wherein all first-metal gridlines extend in the x-direction, wherein at least eight of the at least eight first-metal gridlines have at least one first-metal structure positioned thereon, each first-metal structure in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner on an associated first-metal gridline, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein some diffusion regions within the region of the semiconductor chip are physically and electrically contacted by at least one diffusion contact structure, each diffusion contact structure within the region positioned in a substantially centered manner along an associated diffusion contact gridline of a diffusion contact grid, the diffusion contact grid having a diffusion contact gridline-to-diffusion contact gridline spacing measured in the x-direction equal to the gate pitch.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.93478
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16119727', '16119794', '15688187', '15696728', '15696651']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9352375925108356
- 35 USC 102 Novelty (BERT): 0.5845326726313732
- Combined Prediction Score: 0.9001671005228893
- Mean Citation Score: 451.083808
- Max Citation Score: 471.4597
- Similarity Product: 469.5484820055245

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test