PATENT CLAIM ANALYSIS

Application Number: 16125857
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "324000"]

Abstract:
The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

Claim (Index 8):
The semiconductor substrate according to  claim 7 ,\n wherein, in the second region, a second semiconductor region is formed in the first semiconductor region, wherein the first plugs are electrically coupled to the second semiconductor region, thereby feeding electric potential to the first semiconductor region.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.2963
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14921445', '14466092', '13964576', '15792009', '15429512']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9253500309333474
- 35 USC 102 Novelty (BERT): 0.5263639236409958
- Combined Prediction Score: 0.8854514202041123
- Mean Citation Score: 320.3718520000001
- Max Citation Score: 324.4517
- Similarity Product: 247.93518903869392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test