PATENT CLAIM ANALYSIS

Application Number: 16131575
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["365", "158000"]

Abstract:
A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.

Claim (Index 4):
The resistive memory device of  claim 3 , wherein the output circuit comprises an XOR gate configured to receive the comparison signal and the section selection signal and output the output signal.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 97.0
- Lexical Diversity: 3.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16037109', '15408942', '16130358', '12135241', '15388419']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8193833955047986
- 35 USC 102 Novelty (BERT): 0.5002512063019117
- Combined Prediction Score: 0.7874701765845099
- Mean Citation Score: 240.57957399999995
- Max Citation Score: 268.98364
- Similarity Product: 188.6034104842901

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test