PATENT CLAIM ANALYSIS

Application Number: 15990750
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["361", "776000"]

Abstract:
A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

Claim (Index 3):
A semiconductor device according to  claim 1 , wherein a solder resist film covering therewith an interconnect on the main surface of the wiring substrate is disposed on the side inner than the wire connecting portion of the first bond.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.4
- Patent Class: 361.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11606027', '14820282', '15041858', '11759290', '14329833']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.837660595906144
- 35 USC 102 Novelty (BERT): 0.525375795310158
- Combined Prediction Score: 0.8064321158465454
- Mean Citation Score: 271.12569599999995
- Max Citation Score: 343.3540000000001
- Similarity Product: 315.785670865059

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test