PATENT CLAIM ANALYSIS

Application Number: 15885468
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "256000"]

Abstract:
A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

Claim (Index 7):
The integrated circuit structure of  claim 6 , wherein the first upper end portion of the insulating layer is substantially co-planar with the first upper end portion of the dielectric layer, and wherein the second upper end portion of the insulating layer is substantially co-planar with the second upper end portion of the dielectric layer.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 86.0
- Lexical Diversity: 2.97727
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15409065', '15122796', '14779936', '15859354', '15487636']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9057552671996348
- 35 USC 102 Novelty (BERT): 0.491707509326603
- Combined Prediction Score: 0.8643504914123316
- Mean Citation Score: 190.813414
- Max Citation Score: 249.06691
- Similarity Product: 223.01916965091408

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test