PATENT CLAIM ANALYSIS

Application Number: 15910152
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["323", "271000"]

Abstract:
A regulator amplifier circuit of an embodiment includes a differential amplifier circuit, an nMOS transistor, and a pMOS transistor. The differential amplifier circuit includes a differential circuit and a transistor. The differential circuit includes a differential MOS transistor circuit, and the transistor includes a gate voltage controlled by the differential circuit. The nMOS transistor includes a drain connected to a drain on minus side of the differential MOS transistor, and a gate connected to a source of the transistor. The nMOS transistor operates in a weak inversion region. The pMOS transistor includes a source connected to a source of the AMOS transistor, and a drain connected to a voltage lower than a source voltage of the nMOS transistor. The pMOS transistor operates in the weak inversion region.

Claim (Index 1):
A regulator amplifier circuit, comprising:\n a differential amplifier circuit that includes a differential circuit and a third nMOS transistor, and is configured to cause a source potential of the third nMOS transistor to be fed back to minus side of a differential MOS transistor circuit, the differential circuit including the differential MOS transistor circuit, a first current mirror circuit, and a first constant current circuit, the differential MOS transistor circuit including first and second nMOS transistors, the first current mirror circuit being connected to each drain of the first and second nMOS transistors, the first constant current circuit being connected to a common source of the first and second nMOS transistors, and the third nMOS transistor including a gate voltage controlled by the differential circuit; a fourth nMOS transistor including a drain connected to a drain on plus side of the differential MOS transistor circuit, and a source connected to a source of the third nMOS transistor, the fourth nMOS transistor operating in a weak inversion region; a second constant current circuit connected to the fourth nMOS transistor to cause a source voltage of the fourth nMOS transistor to be equal to or substantially equal to a gate voltage on the plus side of the differential MOS transistor circuit; a fifth nMOS transistor including a drain connected to a drain on the minus side of the differential MOS transistor circuit, and a gate connected to the source of the third nMOS transistor, the fifth nMOS transistor operating in the weak inversion region; and a first pMOS transistor including a source connected to a source of the fifth nMOS transistor, and a drain connected to a voltage lower than a source voltage of the fifth nMOS transistor, the first pMOS transistor operating in the weak inversion region.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 3.65789
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13064935', '11195263', '13038163', '12822832', '12754860']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7329280661487121
- 35 USC 102 Novelty (BERT): 0.4683976365249167
- Combined Prediction Score: 0.7064750231863326
- Mean Citation Score: 211.082544
- Max Citation Score: 214.70003
- Similarity Product: 181.0032704545212

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test