PATENT CLAIM ANALYSIS

Application Number: 15878121
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "185170"]

Abstract:
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Claim (Index 26):
The apparatus of  claim 21 , further comprising:\n a first global control line coupled to the selected access line; and a second global control line coupled to the non-selected access line, wherein the controller is configured to cause the first global control line and the second global control line to be discharged to a potential different than the equalization potential discharge of the selected one of the access lines and the non-selected one of the access lines to the equalization potential.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 1.875
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15692512', '15164400', '14813711', '13774522', '13245587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7620011655099045
- 35 USC 102 Novelty (BERT): 0.4946645207284488
- Combined Prediction Score: 0.7352675010317589
- Mean Citation Score: 223.94029800000004
- Max Citation Score: 275.64645
- Similarity Product: 239.3475149463952

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test