PATENT CLAIM ANALYSIS

Application Number: 16058896
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["375", "233000"]

Abstract:
A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Claim (Index 12):
The two-stage decision feedback equalizer of  claim 11 , wherein the third flip flop has a clock input configured to receive a third phase of the second clock, the third phase of the second clock having a rising edge following each rising edge of the first phase of the second clock by one quarter cycle of the second clock.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 96.0
- Lexical Diversity: 2.18182
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11111403', '10638386', '10823252', '10880959', '10967459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5268179090067414
- 35 USC 102 Novelty (BERT): 0.4963590489169254
- Combined Prediction Score: 0.5237720229977598
- Mean Citation Score: 240.210546
- Max Citation Score: 253.70706
- Similarity Product: 195.8858679955566

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test