PATENT CLAIM ANALYSIS

Application Number: 16179899
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-10
Patent Classification: ["717", "158000"]

Abstract:
A method for generating code for multiple hardware platforms from a common high-level source is disclosed. The method apparatus includes a language specification, JavaVerilog, that contains the information necessary to automatically generate efficient Java, C, and SystemVerilog code for various hardware platforms. The method also includes a code generator to automatically translate the JavaVerilog code into the components necessary to configure and control the execution on the desired hardware platform. The method further defines the protocol for configuring and controlling peripheral hardware objects, such as those on a Field Programmable Gate Array (FPGA) accelerator board.

Claim (Index 1):
A method for developing a processing algorithm on multiple hardware platforms from a common high-level code source, the method comprising:\n reading a source file conforming to the JavaVerilog language syntax defining the processing algorithm, wherein: the JavaVerilog language syntax conforms to Java 1.6 with the addition of SystemVerilog data types and SystemVerilog bit manipulation syntax; reading configuration files defining data types, math functions, and optimization preferences; producing a pure Java implementation for execution on a JVM; producing a pure C implementation for execution on a CPU; producing a pure C implementation for controlling an accelerator platform; and producing a pure SystemVerilog implementation for execution on an FPGA accelerator platform, wherein: the SystemVerilog implementation includes object instantiation and initialization, control flow sequencing, math function implementation, instruction pipelining, loop unrolling, and clock doubling.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.58209
- Patent Class: 717.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11877599', '10753262', '13214083', '15688196', '11865596']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3172852376633277
- 35 USC 102 Novelty (BERT): 0.4659449201036496
- Combined Prediction Score: 0.3321512059073599
- Mean Citation Score: 63.3828156
- Max Citation Score: 66.46358000000001
- Similarity Product: 46.151051013230095

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test