PATENT CLAIM ANALYSIS

Application Number: 16157772
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["330", "280000"]

Abstract:
An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

Claim (Index 16):
The method according to  claim 10 , wherein:\n the amplifier includes at least two transistors; a first one of the one or more inductors is connected to an emitter of a first one of the at least two transistors; and a second one of the one or more inductors is connected to an emitter of a second one of the at least two transistors.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 97.0
- Lexical Diversity: 1.77778
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15706924', '15278822', '14880974', '10920526', '13372648']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7699496130178937
- 35 USC 102 Novelty (BERT): 0.5657471496257804
- Combined Prediction Score: 0.7495293666786823
- Mean Citation Score: 271.56972399999995
- Max Citation Score: 428.4086
- Similarity Product: 351.7101737461328

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test