PATENT CLAIM ANALYSIS

Application Number: 15867613
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "659000"]

Abstract:
A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Claim (Index 19):
The manufacturing method as claimed in  claim 17 , wherein in the step of forming the through hole further comprises steps of forming a scribe opening through the first encapsulant, wherein the through hole is disposed between the scribe line opening and the chip packages.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 1.98182
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15867577', '15383560', '15455143', '15630940', '15361073']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9217222496425368
- 35 USC 102 Novelty (BERT): 0.5143475798702334
- Combined Prediction Score: 0.8809847826653064
- Mean Citation Score: 216.22650200000004
- Max Citation Score: 292.66626
- Similarity Product: 207.74607834935543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test