PATENT CLAIM ANALYSIS

Application Number: 15948143
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["438", "653000"]

Abstract:
Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.

Claim (Index 16):
A method comprising:\n pulsing a reducing agent, wherein the reducing agent is boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing; and pulsing a Mo-containing precursor, wherein the Mo-containing precursor is reduced by the reducing agent or a product thereof to form a multi-component tungsten-containing film containing one or more of B, Si, and Ge on the substrate.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 1.63265
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15040561', '12538770', '11265531', '11963698', '15816268']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8569471805056397
- 35 USC 102 Novelty (BERT): 0.4788345314789582
- Combined Prediction Score: 0.8191359156029716
- Mean Citation Score: 194.72888
- Max Citation Score: 197.84758
- Similarity Product: 147.98299010939118

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test