PATENT CLAIM ANALYSIS

Application Number: 16101645
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["365", "185170"]

Abstract:
According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.

Claim (Index 13):
The semiconductor memory device according to  claim 11 , wherein the circuit measures the first time upon programming second data into the first memory cell, and determines whether or not the programming has been completed on the basis of the measured first time.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 96.0
- Lexical Diversity: 2.83636
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11737154', '15439912', '13537317', '10920161', '15921165']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7696217803953752
- 35 USC 102 Novelty (BERT): 0.4864234072292415
- Combined Prediction Score: 0.7413019430787618
- Mean Citation Score: 174.644778
- Max Citation Score: 178.02173
- Similarity Product: 121.14026987169504

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test