PATENT CLAIM ANALYSIS

Application Number: 16043286
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["438", "300000"]

Abstract:
A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

Claim (Index 17):
The semiconductor device of  claim 16  further comprising an isolation feature disposed within the substrate, wherein the second semiconductor layer further has a side surface that extends to the isolation feature.

Metadata:
- Claim Count in Document: 46.0
- Percentile: 95.0
- Lexical Diversity: 2.73585
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15475826', '15700468', '14460438', '13902322', '15357782']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8468627233208696
- 35 USC 102 Novelty (BERT): 0.476256332267444
- Combined Prediction Score: 0.8098020842155271
- Mean Citation Score: 167.980752
- Max Citation Score: 191.5676
- Similarity Product: 147.60725551147462

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test