PATENT CLAIM ANALYSIS

Application Number: 16183136
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["714", "752000"]

Abstract:
Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM IC's and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.

Claim (Index 5):
A method, comprising:\n sequentially receiving groups of N original data bits at a logic device, the logic device having circuitry to implement one or more logic functions including an encoder, the logic device further having at least one circuit selectable from a group of circuits consisting of command decoder, for interpreting a write command and enabling the encoder, and queuing circuitry for a plurality of memory devices, redundancy circuitry for determining faulty memory addresses in the plurality of memory devices and rerouting around such faulty addresses to functioning ones of the plurality of memory devices, and address decode circuitry for the plurality of memory devices; selectively encoding each of the groups of N original data bits at the logic device to form groups of N encoded data bits and at least one encoding indicator associated with each of the groups of N encoded data bits; and transmitting the groups of N encoded data bits and their associated at least one encoding indicator for storage in selected ones of the plurality of memory devices, the plurality of memory devices being fabricated on a structure separate from the logic device, the plurality of memory devices not containing the at least one circuit or the encoder that are present on the logic device.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 98.0
- Lexical Diversity: 2.25556
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12136868', '14833876', '12366379', '15954149', '14804027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3029823908398158
- 35 USC 102 Novelty (BERT): 0.5671734949545555
- Combined Prediction Score: 0.3294015012512898
- Mean Citation Score: 361.067166
- Max Citation Score: 447.6729
- Similarity Product: 413.3745315924704

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test