PATENT CLAIM ANALYSIS

Application Number: 15887190
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "154000"]

Abstract:
When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Claim (Index 3):
A semiconductor device according to  claim 2 , further comprising:\n a write amplifier coupled to the bit lines for writing data to the static memory cells, and wherein the first MOS transistor is arranged between the random access memory cell array and the write amplifier.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 88.0
- Lexical Diversity: 1.66667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13443511', '10733270', '12222753', '12891208', '11717629']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.835713916365374
- 35 USC 102 Novelty (BERT): 0.5449493311586503
- Combined Prediction Score: 0.8066374578447016
- Mean Citation Score: 395.351422
- Max Citation Score: 419.2212
- Similarity Product: 324.73724943437577

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test