PATENT CLAIM ANALYSIS

Application Number: 15909589
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["714", "755000"]

Abstract:
A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.

Claim (Index 8):
The memory system according to  claim 6 , further comprising:\n a data input unit that inputs the bit sequence of the estimated in-error bits that are retained in the in-error-bit estimation unit and the sequence of the error levels which are recorded in the first error level calculation unit; a test pattern generation unit that causes one or more bits in the bit sequence to be inverted with the reception word being set to be a reference, based on the bit sequence of the estimated in-error bits and the sequence of the error levels, which are input, to generate one or more test patterns; a bounded distance decoding unit that performs bounded distance decoding on the one or more test patterns, using a rule for the external code, to generate one or more decoded word candidates; a second error level calculation unit that compares the reception word and each of the one or more decoded word candidates with each other, specifies a position at which bit inversion occurs between the reception word and each of the one or more decoded word candidates, and calculates a sum of error levels at the specified position; and a maximum likelihood decoded word selection unit that selects a decoded word candidate, a sum of whose error levels is the largest among sums of the error levels of the one or more decoded word candidates, as a maximum likelihood decoded word.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 2.78571
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13679970', '12153121', '13547288', '13529390', '12379746']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.292735565510674
- 35 USC 102 Novelty (BERT): 0.4728710541640943
- Combined Prediction Score: 0.310749114376016
- Mean Citation Score: 179.27520399999997
- Max Citation Score: 181.89594
- Similarity Product: 132.66521307131762

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test