PATENT CLAIM ANALYSIS

Application Number: 15768948
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["377", "064000"]

Abstract:
A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Claim (Index 6):
The shift-buffer circuit according to  claim 3 , wherein:\n the buffer input circuit includes a first buffer transistor, a first electrode of the first buffer transistor being connected with the buffer input terminal, a gate electrode of the first buffer transistor being connected with an enabled signal terminal, and a second electrode of the first buffer transistor being connected with the buffer pull-up node; the first buffer reset circuit includes a second buffer transistor, a first electrode of the second buffer transistor being connected with the buffer pull-up node, a gate electrode of the second buffer transistor being connected with the first buffer pull-down node, and a second electrode of the second buffer transistor being connected with the second power supply terminal; the buffer output circuit includes a third buffer transistor, a first electrode of the third buffer transistor being connected with the buffer clock signal terminal, a gate electrode of the third buffer transistor being connected with the buffer pull-up node, and a second electrode of the third buffer transistor being connected with the buffer output terminal; the first buffer output pull-down circuit includes a fourth buffer transistor, a first electrode of the fourth buffer transistor being connected with the buffer output terminal, a gate electrode of the fourth buffer transistor being connected with the first buffer pull-down node, and a second electrode of the fourth buffer transistor being connected with the second power supply terminal; and a first terminal of the buffer storage capacitor is connected with the buffer pull-up node, and a second terminal of the buffer storage capacitor is connected with the buffer output terminal.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 3.28205
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15539887', '15327852', '15540150', '15759722', '10460856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7616635968793797
- 35 USC 102 Novelty (BERT): 0.4869873596511136
- Combined Prediction Score: 0.734195973156553
- Mean Citation Score: 291.98258
- Max Citation Score: 306.48282
- Similarity Product: 240.9136588048053

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test