PATENT CLAIM ANALYSIS

Application Number: 16121570
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2018-12
Patent Classification: ["327", "210000"]

Abstract:
Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Claim (Index 11):
The circuit of  claim 10 , wherein the inverter storage loop is a first inverter storage loop, the circuit comprising:\n a second inverter storage loop for storing state information; sixth and seventh PFETs connected to a first node of the second inverter storage loop, a gate terminal of the sixth PFET being connected to the first control input and a gate terminal of the seventh PFET being connected to the second control input; eighth and ninth PFETs connected to a second node of the second inverter storage loop, a gate terminal of the eighth PFET being connected to the second control input and a gate terminal of the ninth PFET being connected to the first control input; a third FET connected between the first node of the second inverter storage loop and the sixth and seventh PFETs, a gate terminal of the third FET being connected to the Enable multiplexing control input; and a fourth FET connected between the second node of the second inverter storage loop and the eighth and ninth PFETs, a gate terminal of the fourth FET being connected to the Enable B multiplexing control input; wherein the first node of the first inverter storage loop is connected to the first node of the second inverter storage loop and the second node of the first inverter storage loop is connected to the second node of the second inverter storage loop.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.25926
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15227326', '10977146', '10825481', '13746528', '15419587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7641506389516471
- 35 USC 102 Novelty (BERT): 0.540168070535321
- Combined Prediction Score: 0.7417523821100145
- Mean Citation Score: 246.726452
- Max Citation Score: 395.34314
- Similarity Product: 373.18483934935807

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test