PATENT CLAIM ANALYSIS

Application Number: 15940812
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["330", "253000"]

Abstract:
A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-based differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-based differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Claim (Index 1):
A circuit, comprising:\n a first transistor including a first control input and first and second current terminals; a second transistor including a second control input and third and fourth current terminals, wherein the fourth current terminal is connected to the second current terminal; a third transistor including a third control input and fifth and sixth current terminals, wherein the sixth current terminal is connected to the first current terminal and the third control input is connected to the first control input at a first input node of the circuit; a fourth transistor including a fourth control input and seventh and eighth current terminals, wherein the eighth current terminal is connected to the third current terminal at an output node of the circuit and the fourth control input is connected to the second control input at a second input node of the circuit; a first current source transistor connected to the second and fourth current terminals; a second current source transistor connected to the fifth and seventh current terminals; a fifth transistor including a fifth control input and ninth and tenth current terminals, wherein the fifth control input is connected to the first input node of the circuit; a first resistor connected to the tenth current terminal; and a second resistor connected to the eighth current terminal at the output node and to the first resistor.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 90.0
- Lexical Diversity: 3.84211
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15862510', '12805265', '12636100', '15261500', '11712938']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7621914940843981
- 35 USC 102 Novelty (BERT): 0.509065894241266
- Combined Prediction Score: 0.736878934100085
- Mean Citation Score: 258.235696
- Max Citation Score: 266.01843
- Similarity Product: 202.3549204702628

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test