PATENT CLAIM ANALYSIS

Application Number: 15977543
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185170"]

Abstract:
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Claim (Index 9):
A semiconductor memory device, comprising:\n a memory cell array including:\n a first memory string including a first selection transistor, a second selection transistor, and a first memory cell connected between the first selection transistor and the second selection transistor, the first memory cell being capable of storing data; and \n a second memory string including a third selection transistor, a fourth selection transistor, and a second memory cell connected between the third selection transistor and the fourth selection transistor, the second memory cell being capable of storing data; \n a word line connected to gates of the first memory cell and the second memory cell; a bit line connected to the first selection transistor and the third selection transistor; a first selection gate line connected to a gate of the first selection transistor; a second selection gate line connected to a gate of the third selection transistor; and a controller configured to read the data stored in the first memory cell by performing a read operation, the read operation including:\n in a first period, applying a first voltage to the first selection gate line and the second selection gate line, \n in a second period after the first period, applying a second voltage to the first selection gate line and the second selection gate line to turn on the first selection transistor and the third selection transistor, the second voltage being higher than the first voltage, and \n in a third period after the second period, applying a third voltage (to the second selection gate line to turn off the third selection transistor, while maintaining the second voltage applied to the first selection gate line, the third voltage being higher than the first voltage and lower than the second voltage.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 2.56
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15231715', '15498029', '15174114', '14634702', '15051546']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7743520052603641
- 35 USC 102 Novelty (BERT): 0.5008074588079885
- Combined Prediction Score: 0.7469975506151265
- Mean Citation Score: 250.302798
- Max Citation Score: 285.19125
- Similarity Product: 235.6594185590744

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test