PATENT CLAIM ANALYSIS

Application Number: 15918536
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "154000"]

Abstract:
A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Claim (Index 5):
The semiconductor memory apparatus according to  claim 1 ,\n wherein the semiconductor memory apparatus further comprises: a memory bank region configured to store the data; and a data transmission line configured to transmit the data, wherein the input/output circuit block couples the data transmission line and a data bus which is coupled with an external apparatus, and wherein the data line repeater block couples the data transmission line and the memory bank region.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.83871
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15706218', '15017994', '12232719', '15597795', '12459106']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5376620895542713
- 35 USC 102 Novelty (BERT): 0.4724867909186613
- Combined Prediction Score: 0.5311445596907103
- Mean Citation Score: 177.27008800000004
- Max Citation Score: 182.9408
- Similarity Product: 141.33627746009827

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test