PATENT CLAIM ANALYSIS

Application Number: 15950610
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "185110"]

Abstract:
A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.

Claim (Index 3):
The memory device according to  claim 1 , wherein:\n the first and second cell strings are included in a first memory block, and the third and fourth cell strings are included in a second memory block.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.875
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15060726', '15873069', '15648681', '15148123', '14691263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7841103020519152
- 35 USC 102 Novelty (BERT): 0.5048941818263484
- Combined Prediction Score: 0.7561886900293586
- Mean Citation Score: 225.527866
- Max Citation Score: 272.6365
- Similarity Product: 204.26659103909137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test