PATENT CLAIM ANALYSIS

Application Number: 15863983
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["375", "371000"]

Abstract:
A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Claim (Index 5):
The CDR circuit according to  claim 4 , wherein the loop gain controller decreases the proportional path gain factor and decrease the integral path gain factor to keep a predetermined ratio of the proportional path gain factor to the integral path gain factor.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 1.84906
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13833321', '13235628', '15602239', '14145493', '13081941']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5257835160473538
- 35 USC 102 Novelty (BERT): 0.5037166232154671
- Combined Prediction Score: 0.5235768267641652
- Mean Citation Score: 242.94647
- Max Citation Score: 264.6696
- Similarity Product: 193.0992677158356

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test