PATENT CLAIM ANALYSIS

Application Number: 15952845
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "499000"]

Abstract:
A power semiconductor device includes a substrate including a first epitaxial layer, a second epitaxial layer, and a base substrate where the first epitaxial layer is disposed between the second epitaxial layer and the base substrate. The power semiconductor device includes an anode electrode and a cathode electrode disposed on the substrate, a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity. The power semiconductor device includes an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration. The power semiconductor device includes an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.

Claim (Index 5):
The power semiconductor device of  claim 1 , further comprising an n-type barrier layer disposed on a side of the NISO region, inside the substrate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 3.25
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15337748', '14845939', '13180822', '13683505', '15010052']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9237026080670458
- 35 USC 102 Novelty (BERT): 0.5443747440215903
- Combined Prediction Score: 0.8857698216625004
- Mean Citation Score: 268.749168
- Max Citation Score: 394.71887
- Similarity Product: 328.2300534908813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test