PATENT CLAIM ANALYSIS

Application Number: 16035388
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["348", "308000"]

Abstract:
A comparator includes a first stage coupled to compare a reference voltage to an image charge voltage signal. The first stage includes first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices to receive the reference voltage and the image charge voltage signal. A first auto-zero switch is between a gate of the first NMOS input transistor and a first node. The first node is between the first NMOS input transistor and the first cascode device. A second auto-zero switch is between a gate of the second NMOS input transistor and a second node. The second node is between the second cascode device and a second PMOS transistor. A voltage difference between the first and second nodes during an auto-zero period reduces an amount of kickback that occurs during an ADC period.

Claim (Index 8):
An imaging system, comprising:\n an array of pixels to receive image light and generate an image charge voltage signal in response; readout circuitry coupled to receive the image charge voltage signal from the array of pixels and provide a digital representation of the image charge voltage signal in response, the readout circuitry including a comparator to receive the image charge, compare the image charge voltage signal to a reference voltage, and provide the digital representation of the image charge voltage signal in response, wherein the comparator comprises:\n a first stage coupled to receive the image charge and the reference voltage and provide a first output in response; and \n a second stage coupled to receive the first output and provide the digital representation of the image charge voltage signal in response, the second stage comprising:\n an input coupled to receive the first output; \n a first capacitor coupled to store a second stage reference voltage; \n a reference voltage input coupled to the input, and further coupled to the first capacitor at a gate; and \n a first control switch coupled between the input and a third node of the first stage, and \n wherein the first capacitor is charged to a voltage based on a voltage on the third node of the first stage in response to the first control switch being enabled.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 3.0625
- Patent Class: 348.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15277648', '16035363', '15486815', '15486896', '15277642']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6077732474101953
- 35 USC 102 Novelty (BERT): 0.5391167514949413
- Combined Prediction Score: 0.60090759781867
- Mean Citation Score: 295.17652400000014
- Max Citation Score: 373.1176
- Similarity Product: 300.0868582069397

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test