PATENT CLAIM ANALYSIS

Application Number: 15768305
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["327", "157000"]

Abstract:
Disclosed is a phase-locked loop having a high bandwidth using the rising edge and falling edge of a signal. The disclosed phase-locked loop controls the frequency of a voltage control oscillator by comparing both a phase difference between rising edge of a reference signal and rising edge of a feedback signal and a phase difference between falling edge of the reference signal and falling edge of the feedback signal.

Claim (Index 5):
The phase-locked loop of  claim 4 , wherein the rising edge up signal is a signal having a high value between the rising edge of the reference signal and the rising edge of the feedback signal when the rising edge of the reference signal is earlier than the rising edge of the feedback signal, and\n the rising edge down signal is a signal having a high signal in an interval between the rising edge of the reference signal and the rising edge of the feedback signal when the rising edge of the reference signal is later than the rising edge of the feedback signal.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.21875
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15779119', '15151198', '14718677', '13870742', '10717778']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8024706077643552
- 35 USC 102 Novelty (BERT): 0.5022832861492232
- Combined Prediction Score: 0.772451875602842
- Mean Citation Score: 259.790224
- Max Citation Score: 271.93344
- Similarity Product: 195.9511061352539

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test