PATENT CLAIM ANALYSIS

Application Number: 15873357
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["714", "764000"]

Abstract:
A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.

Claim (Index 16):
The system of  claim 11 , wherein in response to detection by the ECC circuitry of single bit errors in adjacent quadrants, the ECC circuitry will not alias a data bit.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 2.05797
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14998142', '10418549', '10418546', '14981649', '15605310']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3327992999853651
- 35 USC 102 Novelty (BERT): 0.5304949979899811
- Combined Prediction Score: 0.3525688697858268
- Mean Citation Score: 258.73493
- Max Citation Score: 371.23788
- Similarity Product: 259.9773039768362

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test