PATENT CLAIM ANALYSIS

Application Number: 15748651
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "433000"]

Abstract:
A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.

Claim (Index 10):
The packaging method according to  claim 9 , wherein the cutting the wafer to be packaged and the cover substrate along the sawing lane regions comprises:\n performing a first cutting process, which comprises cutting the wafer to be packaged along the sawing lane regions from a second surface of the wafer to be packaged opposite to the first surface of the wafer to be packaged until the first surface of the wafer to be packaged is reached, to form a first cutting groove; performing a second cutting process, which comprises cutting the cover substrate along the sawing lane regions from a second surface of the cover substrate opposite to the first surface of the cover substrate until a predetermined depth is reached, to form a second cutting groove, wherein a width of the second cutting groove gradually decreases in a direction from the second surface of the cover substrate to the first surface of the cover substrate; and performing a third cutting process, which comprises continuing cutting the cover substrate until a third cutting groove connecting the first cutting groove and the second cutting groove is formed, to simultaneously form a plurality of the chip package structures, wherein the upper cover plate structure further comprises a side wall comprising a vertical wall and an inclined wall, a first end of the inclined wall is connected to an edge of the second surface of the cover substrate, and a second end opposite to the first end of the inclined wall is connected to the top of the vertical wall, such that an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 3.32558
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15507901', '14450143', '15549987', '15765802', '15765968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9126429642984016
- 35 USC 102 Novelty (BERT): 0.4854082021683556
- Combined Prediction Score: 0.8699194880853972
- Mean Citation Score: 194.468208
- Max Citation Score: 203.85362
- Similarity Product: 147.65798679702044

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test