PATENT CLAIM ANALYSIS

Application Number: 15874005
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "288000"]

Abstract:
Semiconductor devices employing reduced area conformal contacts for reducing parasitic capacitance and improving performance, and related methods are disclosed. The area of the source/drain contacts for providing an electrical contract to a source/drain is reduced in size to reduce parasitic capacitance between a gate and the source/drain contacts for improved performance. To mitigate or avoid increase in contact resistance between the source/drain contacts and source/drain, a conformal contact layer of a desired thickness is disposed adjacent to the source/drain to reduce the source/drain contact resistance. Thus, the source/drain contacts may only have to extend down adjacent to an upper region of the source/drain to still achieve a desired, lower contact resistance with the source/drain contacts, which results in a reduced area source/drain contact for reducing parasitic capacitance.

Claim (Index 18):
The semiconductor device of  claim 1 , wherein the one or more channel structures comprise one or more fins.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.15873
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15602326', '15598393', '15585865', '14951660', '15728615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9278645383904668
- 35 USC 102 Novelty (BERT): 0.5051113570075697
- Combined Prediction Score: 0.885589220252177
- Mean Citation Score: 246.22445
- Max Citation Score: 268.69943
- Similarity Product: 197.0429216648412

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test