PATENT CLAIM ANALYSIS

Application Number: 15980813
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["365", "203000"]

Abstract:
In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

Claim (Index 9):
The apparatus of  claim 1 , further comprising a memory controller coupled to the memory array, wherein the memory controller, in response to a read request, is to:\n issue a combined activate and precharge command to the memory array; and thereafter issue a plurality of read requests to the memory array.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.71698
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10967899', '11257816', '15013897', '13540227', '10925495']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7898673772000104
- 35 USC 102 Novelty (BERT): 0.4820148405139519
- Combined Prediction Score: 0.7590821235314047
- Mean Citation Score: 197.163996
- Max Citation Score: 216.51216
- Similarity Product: 155.75822600060462

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test