PATENT CLAIM ANALYSIS

Application Number: 16116463
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["327", "109000"]

Abstract:
A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

Claim (Index 1):
A power semiconductor device, comprising:\n a semiconductor body coupled to a first load terminal structure and to a second load terminal structure and configured to conduct a load current during a conducting state of the power semiconductor device and to block a load current during a blocking state of the power semiconductor device; a first cell and a second cell, each cell being configured for controlling the load current and each cell being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type; a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; and a second mesa included in the second cell, the second mesa including: a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region, wherein each of the first mesa and the second mesa has a total extension of less than 100 nm in a direction perpendicular of the load current within the respective mesa, wherein the first and second cells are configured to fully deplete the first and second channel regions of mobile charge carriers of the second conductivity type in the conducting state, wherein the first cell is configured to induce a current path for mobile charge carriers of the first conductivity type in the first channel region in the conducting state and no current path for mobile charge carriers of the first conductivity type in the blocking state, wherein the power semiconductor device is configured to concurrently induce an accumulation channel for charge carriers of the second conductivity type in the second channel region and a current path for charge carriers of the first conductivity type in the first channel region in a switching state of the power semiconductor device.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 96.0
- Lexical Diversity: 2.85714
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15637170', '15637459', '15634720', '15635300', '15635987']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8098375190809481
- 35 USC 102 Novelty (BERT): 0.5387559447415461
- Combined Prediction Score: 0.7827293616470079
- Mean Citation Score: 387.73899
- Max Citation Score: 397.92432
- Similarity Product: 338.4534139917183

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test