PATENT CLAIM ANALYSIS

Application Number: 15873395
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["711", "150000"]

Abstract:
A system includes a host interface, a storage interface, and one or more control circuits coupled to the host interface and coupled to the storage interface. The one or more control circuits include a common set of registers configured to maintain first entries according to a first storage protocol for first storage devices connected to the storage interface and to maintain second entries according to a second storage protocol for second storage devices connected to the storage interface.

Claim (Index 14):
The method of  claim 13  further comprising:\n populating the common registers with a Command Descriptor Block (CDB) entry, a data buffer entry, and a completion status entry for the SAS storage device; \n populating the common registers with a submission queue entry and a completion queue entry for the NVMe storage device; and \n copying contents of the common registers including the CDB entry, the data buffer entry, the completion status entry, the submission queue entry, and the completion queue entry between the common registers and the common address space in the host volatile memory.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 86.0
- Lexical Diversity: 2.41176
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14597094', '15385158', '14272214', '14712372', '13355823']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5147082385137383
- 35 USC 102 Novelty (BERT): 0.491198838305056
- Combined Prediction Score: 0.51235729849287
- Mean Citation Score: 191.86987800000003
- Max Citation Score: 210.86406
- Similarity Product: 142.2204912030101

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test