PATENT CLAIM ANALYSIS

Application Number: 15910384
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-01
Patent Classification: ["257", "139000"]

Abstract:
A semiconductor device includes a semiconductor layer between a collector electrode and an emitter electrode. The semiconductor layer includes a base region of a first conductivity type, a first collector layer of a second conductivity type between the collector electrode in a cell region in which an emitter layer is arranged and the base layer, and a second collector layer of the second conductivity type between the collector electrode in a boundary region in which a gate wiring is arranged and the base layer. A peak value of an impurity concentration of the second conductivity type in the second collector layer is higher than a peak value of an impurity concentration of the second conductivity type in the first collector layer.

Claim (Index 6):
A semiconductor device comprising:\n a first semiconductor layer having a first main surface and a second main surface; a collector electrode provided on the first main surface; an emitter electrode provided on the second main surface; a gate electrode provided in the second main surface side of the first semiconductor layer and extending in a first direction; a gate wiring provided on the second main surface and extending in a second direction intersecting with the first direction and connected to the gate electrode; and a gate insulating film provided between the gate electrode and the first semiconductor layer, wherein the first semiconductor layer comprises: a base layer of a first conductivity type; a base layer of a second conductivity type between the base layer of the first conductivity type and the emitter electrode; an emitter layer of the first conductivity type between the base layer of the second conductivity type and the emitter electrode and connected to the emitter electrode; a first collector layer of the second conductivity type between the collector electrode in a cell region in which the emitter layer is arranged and the base layer of the first conductivity type; and a second collector layer of the second conductivity type between the collector electrode in a boundary region in which the gate wiring is arranged and the base layer of the first conductivity type, the number of the second conductivity type impurities per unit area in the second collector layer being higher than the number of the second conductivity type impurities per unit are in the first collector layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 3.40541
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11626141', '11221702', '10843571', '12103911', '13205845']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9238832814034474
- 35 USC 102 Novelty (BERT): 0.4918282733259508
- Combined Prediction Score: 0.8806777805956978
- Mean Citation Score: 263.21170199999995
- Max Citation Score: 271.78302
- Similarity Product: 239.3372398282672

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test