PATENT CLAIM ANALYSIS

Application Number: 16082212
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-06
Patent Classification: ["257", "334000"]

Abstract:
A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.

Claim (Index 12):
The semiconductor device according to  claim 1 , wherein a punch through current flows between the second well region and the third well region through the dividing region.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 97.0
- Lexical Diversity: 2.62069
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14779255', '15567670', '15502409', '13643468', '14426062']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.933454042743728
- 35 USC 102 Novelty (BERT): 0.5136572073914599
- Combined Prediction Score: 0.8914743592085012
- Mean Citation Score: 289.476332
- Max Citation Score: 305.3279
- Similarity Product: 233.55219868188505

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test