PATENT CLAIM ANALYSIS

Application Number: 16040837
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "314000"]

Abstract:
Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

Claim (Index 11):
The 3D semiconductor memory device of  claim 10 , wherein each of the plurality of intermediate stack structures comprises a plurality of intermediate electrodes vertically stacked,\n wherein the plurality of intermediate electrodes of each of the plurality of intermediate stack structures comprise an uppermost one of the plurality of intermediate electrodes and remaining ones of the plurality of intermediate electrodes that are between the substrate and the uppermost one of the plurality of intermediate electrodes, wherein the plurality of lower electrodes comprises an uppermost one of the plurality of lower electrodes and remaining ones of the plurality of lower electrodes that are between the substrate and the uppermost one of the plurality of lower electrodes, wherein each of the remaining ones of the plurality of lower electrodes comprises a lower pad region exposed by one of the plurality of lower electrodes disposed immediately thereon on the connection region, wherein each of the remaining ones of the plurality of intermediate electrodes comprises an intermediate pad region exposed by one of the plurality of intermediate electrodes disposed immediately thereon on the connection region, wherein respective lengths of the intermediate pad regions in the first direction are substantially equal to each other, wherein respective widths of the intermediate pad regions in a second direction that is substantially perpendicular to the first direction are substantially equal to each other, wherein the lower pad regions have respective lengths in the first direction and respective widths in the second direction, wherein the lengths and the widths of the lower pad regions decrease as a vertical distance from the substrate increases, and wherein the intermediate pad regions of the plurality of intermediate electrodes of each of the plurality of intermediate stack structures are arranged in the second direction in a plan view.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 95.0
- Lexical Diversity: 2.96296
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15383213', '15964190', '15373922', '15381823', '15350305']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9369421525359308
- 35 USC 102 Novelty (BERT): 0.5676104389535338
- Combined Prediction Score: 0.9000089811776911
- Mean Citation Score: 351.804364
- Max Citation Score: 463.75253
- Similarity Product: 380.7747896204704

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test