PATENT CLAIM ANALYSIS

Application Number: 15927373
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "686000"]

Abstract:
A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.

Claim (Index 11):
The semiconductor package of  claim 1 , wherein a molding layer is formed along the side surfaces of the first semiconductor chip, the second semiconductor chip, and the insulating bonding layer.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 90.0
- Lexical Diversity: 2.70588
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15475650', '13678205', '15832266', '15222114', '14064110']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9344112667730664
- 35 USC 102 Novelty (BERT): 0.5141320721147371
- Combined Prediction Score: 0.8923833473072333
- Mean Citation Score: 245.925508
- Max Citation Score: 316.8989
- Similarity Product: 281.71144846321937

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test