PATENT CLAIM ANALYSIS

Application Number: 15743745
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["712", "222000"]

Abstract:
A data processing system ( 2 ) supports vector processing operations performed upon vector operands comprising a plurality of vector operand elements. The data processing system includes a processor ( 4 ) having an instruction decoder ( 14 ) which decodes mixed-element-sized vector arithmetic instructions to generate control signals ( 16 ) which control processing circuitry ( 18 ) to perform arithmetic operations upon a first vector of first source operand elements a i  of a first bit size A, and a second vector of second source operand elements b j  of a second bit size B. The second bit size B is greater than the first bit size A.

Claim (Index 9):
Apparatus as claimed in  claim 1 , wherein said at least one mixed-element-sized vector arithmetic instruction includes a mixed-element-sized vector shift instruction and said arithmetic processing operation is a shift operation that shifts said first source operand elements by a shift amount specified by a corresponding second source operand element.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16081147', '15833372', '13353805', '14582968', '13439161']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6164429105504885
- 35 USC 102 Novelty (BERT): 0.496883162839315
- Combined Prediction Score: 0.6044869357793712
- Mean Citation Score: 240.07712
- Max Citation Score: 258.1912
- Similarity Product: 192.7617415741921

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test