PATENT CLAIM ANALYSIS

Application Number: 15890204
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["714", "764000"]

Abstract:
Examples include techniques for implementing read and write operations between a memory controller and a memory device. In an embodiment, the memory controller is configured to receive data bits to write to the memory device, to determine, using a memory controller ECC component and the data bits, a plurality of memory controller ECC check bits and one or more parity bits, to append the memory controller ECC check bits and the one or more parity bits to the data bits, and to send the data bits, the memory controller ECC check bits, and the one or more parity bits to the memory device during a write operation. In an embodiment, the memory controller is configured to receive the data bits and the memory controller ECC check bits from the memory device, to check the data bits against the memory controller ECC check bits and correct errors detected, and to return the data bits during a read operation.

Claim (Index 28):
The method of  claim 22 , further comprising abandoning correction of data bits by the on-die ECC component when a multi-bit error is detected.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 3.6383
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15873357', '10710066', '15870220', '13565430', '12098427']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3286669089354949
- 35 USC 102 Novelty (BERT): 0.5084041864534354
- Combined Prediction Score: 0.3466406366872889
- Mean Citation Score: 249.42912400000003
- Max Citation Score: 261.5779
- Similarity Product: 148.95925131258966

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test