PATENT CLAIM ANALYSIS

Application Number: 16372667
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-07
Patent Classification: ["327", "203000"]

Abstract:
In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

Claim (Index 10):
An integrated circuit layout on a semiconductor substrate, comprising:\n a first clock inverter circuit residing within the integrated circuit layout and configured to provide a first clock signal; a second clock inverter circuit residing within the integrated circuit layout and configured to provide a second clock signal, the second clock signal being inverted with regards to the first clock signal, and the first clock inverter circuit and the second clock inverter circuit being traversed by a first line in the integrated circuit layout; a first flip-flop residing within the integrated circuit layout and disposed to a first side of the first line, the first flip-flop receiving the first clock signal from the first clock inverter circuit, and the first clock signal extending through the first flip-flop along a second line perpendicular to the first line; and a second flip-flop residing within the integrated circuit layout and disposed to a second side of the first line, the second flip-flop receiving the first clock signal from the first clock inverter circuit, and the first clock signal extending through the second flip-flop along the second line.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 100.0
- Lexical Diversity: 3.16949
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15143676', '15496575', '12723796', '14873634', '15663852']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7961925233812834
- 35 USC 102 Novelty (BERT): 0.5673491790420396
- Combined Prediction Score: 0.7733081889473591
- Mean Citation Score: 351.39420600000005
- Max Citation Score: 474.24704
- Similarity Product: 378.2063677188874

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test