PATENT CLAIM ANALYSIS

Application Number: 15872097
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["714", "764000"]

Abstract:
Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Claim (Index 13):
The apparatus of  claim 8 , wherein selecting the order of the ECC decoder is further based on at least one selected from a group consisting of: memory maintenance results, memory controller self-test results, a mode of the ECC, and an application error tolerance.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.76087
- Patent Class: 714.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15143865', '13015850', '11907876', '15640182', '13523091']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3471038246981186
- 35 USC 102 Novelty (BERT): 0.4771115221676665
- Combined Prediction Score: 0.3601045944450734
- Mean Citation Score: 180.850824
- Max Citation Score: 194.23546
- Similarity Product: 140.47448133259772

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test