PATENT CLAIM ANALYSIS

Application Number: 15877273
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "347000"]

Abstract:
Etching trench isolation structures into a semiconductor structure that includes an upper thin semiconductor layer disposed over a buried insulator layer and a buried compressively strained stressor layer under the buried insulator layer, the compressively strained stressor layer being disposed on an underlying semiconductor substrate, causes edge relaxation of the compressively strained stressor layer. The edge relaxation results in the buried insulation layer being deformed, thus inducing tensile strain in an upper surface of the thin semiconductor layer across at least a first portion of a lateral extent of the thin semiconductor layer between walls of one or more trenches formed by the etching.

Claim (Index 20):
The method of  claim 12 , wherein the tensile strain within the top surface of thin semiconductor layer is non-uniform over the lateral extent of the thin semiconductor layer.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 86.0
- Lexical Diversity: 1.81667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12869978', '15594436', '13762677', '15191369', '12110030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.94418469684741
- 35 USC 102 Novelty (BERT): 0.5521929397751504
- Combined Prediction Score: 0.904985521140184
- Mean Citation Score: 397.336746
- Max Citation Score: 427.53683
- Similarity Product: 338.0674970324141

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test