PATENT CLAIM ANALYSIS

Application Number: 16249642
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["398", "136000"]

Abstract:
The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Claim (Index 19):
A transceiver system comprising:\n an input terminal for receiving an input data stream, the input data stream being characterized by a first frequency; a first voltage gain amplifier being configured to generate a first driving signal, the first voltage gain amplifier being characterized by a bandwidth of at least 13 GHz; a second voltage gain amplifier being configured to generate a second driving signal, the second voltage gain amplifier being characterized by a gain range of least 12 dB; a track and hold (T/H) module comprising a first plurality of T/H circuits and a second plurality of T/H circuits, the first plurality of T/H circuits being controlled by the first driving signal for holding the input data stream at a second frequency, the second T/H circuit being controlled by the second driving signal for holding the input data stream at the second frequency; a shift and hold (SH) buffer comprising a plurality of buffer units corresponding to the first plurality of T/H circuits and to store a first plurality of samples based on the input data stream; and an analog-to-digital converter (ADC) module comprising a first plurality of ADC circuits being configured to convert the first plurality of samples.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 1.8
- Patent Class: 398.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15809902', '15061923', '15426506', '14990309', '14984849']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6386506066350749
- 35 USC 102 Novelty (BERT): 0.5619320789383753
- Combined Prediction Score: 0.6309787538654049
- Mean Citation Score: 267.972484
- Max Citation Score: 382.79895
- Similarity Product: 363.6565565609693

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test