PATENT CLAIM ANALYSIS

Application Number: 16263964
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["341", "141000"]

Abstract:
A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

Claim (Index 9):
The converter of  claim 8  further comprising a second capacitor, second capacitor shuffled between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC, wherein the second capacitor includes one or more capacitors that together have a capacitance equal to approximately one-half of a total capacitance of the binary weighted capacitor array of the NDAC.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 99.0
- Lexical Diversity: 1.22727
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15271697', '12113307', '12773768', '14919830', '13673103']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5869300976907738
- 35 USC 102 Novelty (BERT): 0.5516459291385278
- Combined Prediction Score: 0.5834016808355492
- Mean Citation Score: 261.224594
- Max Citation Score: 396.1421
- Similarity Product: 327.545041265291

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test