PATENT CLAIM ANALYSIS

Application Number: 16022357
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["327", "291000"]

Abstract:
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.

Claim (Index 7):
The IC chip of  claim 6 , wherein the third circuitry is to detect one of a temperature change or a voltage change at the IC chip, and wherein the third circuitry is to intermittently update the control signal responsive to the one of the temperature change or the voltage change.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.57627
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16019924', '14626441', '14106269', '12757597', '13945607']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.763499504370478
- 35 USC 102 Novelty (BERT): 0.4930414837282896
- Combined Prediction Score: 0.7364537023062592
- Mean Citation Score: 144.85056400000005
- Max Citation Score: 155.35028
- Similarity Product: 91.11084484702828

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test