PATENT CLAIM ANALYSIS

Application Number: 15948958
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["257", "666000"]

Abstract:
Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Claim (Index 39):
The semiconductor package of  claim 35 , wherein the first solder bump is electrically coupled to the first conductive trace by a third conductive trace, and wherein the second solder bump is electrically coupled to the second conductive trace by a fourth conductive trace.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.13208
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14491892', '15899222', '14930514', '14586580', '12591812']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9261061101241556
- 35 USC 102 Novelty (BERT): 0.5120923141749569
- Combined Prediction Score: 0.8847047305292357
- Mean Citation Score: 212.89848
- Max Citation Score: 287.4933
- Similarity Product: 205.48158413237925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test