PATENT CLAIM ANALYSIS

Application Number: 16049624
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["719", "312000"]

Abstract:
Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

Claim (Index 8):
A user device comprising:\n a first processor apparatus and a second processor apparatus; a shared memory structure comprising a first data array structure and a second data array structure; and a non-transitory computer-readable apparatus comprising a storage medium having a computer program stored thereon, the computer program comprising instructions configured to, when executed, cause the second processor apparatus to:\n read a plurality of first data structures from the first data array structure of the shared memory structure, wherein the plurality of first data structures is written by the first processor apparatus; \n transmit one or more payloads corresponding to the plurality of first data structures to another device in wireless data communication with the user device in an order based on a sequence of the plurality of first data structures; \n subsequent to the transmission of the one or more payloads to the another device, write to the second data array structure of the shared memory structure a plurality of second data structures corresponding to the plurality of first data structures in the order based on the sequence, the plurality of second data structures indicative of a completion status corresponding to transfer of the one or more payloads between the first and second processor apparatus, the writing of the plurality of second data structures enabling signaling of completion of the transfer between the first and second processor apparatus; \n wherein the signaling of completion comprising detection of presence of at least one of the written plurality of second data structures by the first processor apparatus at a dynamically determined time interval, the time interval being contracted or expanded based at least on evaluation of a number of transfers relative to a threshold number of transfers.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 1.93902
- Patent Class: 719.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15984153', '15865638', '14879030', '15011291', '15721200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5397764130682893
- 35 USC 102 Novelty (BERT): 0.5112269537568129
- Combined Prediction Score: 0.5369214671371416
- Mean Citation Score: 260.273578
- Max Citation Score: 303.18237
- Similarity Product: 239.8919631064796

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test