PATENT CLAIM ANALYSIS

Application Number: 16297596
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.

Claim (Index 1):
An integrated circuit comprising:\n a plurality of logic tiles, wherein each logic tile includes:\n a configurable switch interconnect network, wherein the configurable switch interconnect network includes a plurality of switch matrices, wherein the plurality of switch matrices are configured into a plurality of stages including:\n first and second stages of switch matrices connected in a hierarchical network, and \n a third stage of switch matrices (i) connected in a mesh network and (ii) directly connected to at least one of the first and second stages of the hierarchical network of the configurable switch interconnect network of the same logic tile, wherein each switch matrix of the third stage of switch matrices includes:\n a first output which is directly connected to an input of a switch matrix of the third stage of switch matrices of the configurable switch interconnect network of the same logic tile, and \n a second output which is directly connected to an input of a switch matrix of the third stage of switch matrices of the configurable switch interconnect network of a first different logic tile.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 99.0
- Lexical Diversity: 2.74576
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15898796', '15041085', '15375309', '15347071', '16186882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.772646820624761
- 35 USC 102 Novelty (BERT): 0.6444333379131257
- Combined Prediction Score: 0.7598254723535975
- Mean Citation Score: 569.8603059999998
- Max Citation Score: 659.7848
- Similarity Product: 591.2164354981422

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test