PATENT CLAIM ANALYSIS

Application Number: 16055128
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.

Claim (Index 6):
The vertical transistor of  claim 5 , wherein the gate dielectric further comprises a third portion on top of the third portion of the channel.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 96.0
- Lexical Diversity: 2.92308
- Patent Class: nan
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16055129', '12984653', '11860459', '14588318', '11315031']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5506624257142801
- 35 USC 102 Novelty (BERT): 0.5101367505746665
- Combined Prediction Score: 0.5466098582003188
- Mean Citation Score: 217.76421
- Max Citation Score: 299.30948
- Similarity Product: 233.71268339018343

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test