PATENT CLAIM ANALYSIS

Application Number: 15987075
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "774000"]

Abstract:
Provided are a semiconductor device and a method of manufacturing the same. The method may, for example, comprise forming an interposer on a dummy substrate; forming a conductive pillar on the interposer; contacting the top of the interposer with at least one semiconductor die; encapsulating the conductive pillar and the at least one semiconductor die with an encapsulant; forming a redistribution layer that is electrically connected to the conductive pillar, on the semiconductor die; removing the dummy substrate from the interposer; attaching the interposer, which has the at least one semiconductor die in contact, to a substrate and testing the at least one semiconductor die; and contacting a stacked semiconductor device with the redistribution layer.

Claim (Index 30):
A method of manufacturing a semiconductor device, the method comprising:\n providing a dummy substrate comprising a first surface and a second surface opposite the first surface; building on the first surface of the dummy substrate, a first multilayer structure comprising:\n a first circuit pattern, \n a second circuit pattern electrically connected to the first circuit pattern, and \n a dielectric structure\n exposing a portion of the first circuit pattern at a first surface of the first multilayer structure and \n exposing a portion of the second circuit pattern at a second surface of the first multilayer structure opposite the first surface of the first multilayer structure; \n \n providing a conductive pillar in contact with a first portion of the second circuit pattern exposed by the dielectric material; attaching a conductive terminal on a first surface of a semiconductor die to a second portion of the second circuit pattern of the first multilayer structure exposed by the dielectric material; encapsulating the conductive pillar, the semiconductor die, and the second surface of the first multilayer structure, with an encapsulant; building a second multilayer structure over an exposed second end of the conductive pillar opposite the first end of the conductive pillar, an exposed second surface of the semiconductor die opposite the first surface of the semiconductor die, and a top surface of the encapsulant, to electrically interconnect the second multilayer structure to the second circuit pattern of the first multilayer structure; removing at least a portion of the dummy substrate to expose the first circuit pattern of the first multilayer structure; and attaching a conductive element of a stacked semiconductor device to an exposed circuit pattern of the second multilayer structure.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 2.48077
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14719539', '13863457', '15429591', '15207287', '14313724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9250584922216272
- 35 USC 102 Novelty (BERT): 0.4848326116956861
- Combined Prediction Score: 0.8810359041690331
- Mean Citation Score: 234.527334
- Max Citation Score: 253.8373
- Similarity Product: 221.350084303391

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test