PATENT CLAIM ANALYSIS

Application Number: 15988218
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "737000"]

Abstract:
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.

Claim (Index 13):
A method for manufacturing a chip-size double side connection package according to  claim 10 , wherein, on the second main face side, a back face insulation layer is applied to the ground semiconductor substrate such that the tip ends of the through electrodes are exposed, and back face wiring traces to be connected to the tip ends of the through electrodes are formed.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 93.0
- Lexical Diversity: 1.95455
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12991143', '14053481', '12864125', '12991149', '12935341']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9409541364742382
- 35 USC 102 Novelty (BERT): 0.5656924902694593
- Combined Prediction Score: 0.9034279718537604
- Mean Citation Score: 380.432996
- Max Citation Score: 451.8139
- Similarity Product: 392.7156414982141

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test