PATENT CLAIM ANALYSIS

Application Number: 16052570
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["377", "075000"]

Abstract:
A shift register unit, a driving method, a gate driving circuit and a display device are described. The shift register unit comprises a control circuit, a first output circuit and a second output circuit, wherein the first output circuit is connected with a first signal terminal, a first node and an output terminal, respectively; the second output circuit is connected with the output terminal, a second node, a first clock signal terminal and a second signal terminal, respectively; the control circuit is connected with the first node, the second node, the first signal terminal, the second signal terminal, the first clock signal terminal, a second clock signal terminal and an input terminal, respectively, and used for controlling the potentials of the first node and the second node. The shift register unit provided by the disclosure solves the problems that the circuit structure of a shift register unit is complex and its control process is cumbersome, and achieves the goal of simplifying the circuit structure and control process of the shift register unit.

Claim (Index 2):
The shift register unit as claimed in  claim 1 , wherein the control circuit comprises a pull-down sub-circuit, a first pull-up sub-circuit, a control sub-circuit and a second pull-up sub-circuit; and\n the pull-down sub-circuit is connected with the second signal terminal, the first clock signal terminal, a third node and a fourth node, respectively, and configured to output the second control signal of the second signal terminal to the fourth node under the control of the third node and the first clock signal from the first clock signal terminal; the first pull-up sub-circuit is connected with the input terminal, the first clock signal terminal, the third node and the fourth node, respectively, and configured to output the first clock signal to the third node and the fourth node, respectively, under the control of the input signal from the input terminal and the first clock signal from the first clock signal terminal; the control sub-circuit is connected with the second clock signal terminal, the input terminal, the fourth node, the first node and the second node, respectively, and configured to output the input signal from the input terminal to the first node and outputting the potential of the fourth node to the second node under the control of the second clock signal from the second clock signal terminal; and the second pull-up sub-circuit is connected with the first signal terminal, the first node and the second node, respectively, and configured to output the first control signal from the first signal terminal to the second node under the control of the first node.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 96.0
- Lexical Diversity: 3.59259
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15539124', '15827553', '15300930', '16091128', '15752518']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7808797054163302
- 35 USC 102 Novelty (BERT): 0.5167541040113656
- Combined Prediction Score: 0.7544671452758338
- Mean Citation Score: 344.749524
- Max Citation Score: 385.89087
- Similarity Product: 357.5082799456752

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test