PATENT CLAIM ANALYSIS

Application Number: 16049855
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "190000"]

Abstract:
A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.

Claim (Index 27):
An apparatus including a plurality of specialized processing blocks, comprising:\n a first specialized processing block including\n first, second, and third inputs that respectively receive first, second, and third signals, \n configurable interconnect circuitry that routes the first and second signals from the first and second inputs, \n an adder stage that receives the first and second signals from the configurable interconnect circuitry and computes a sum of the first and second signals, and \n a first multiplier stage that computes a product of the third signal and the sum of the first and second signals, wherein the configurable interconnect circuitry routes the sum of the first and second signals from the adder stage to the multiplier stage and routes the third signal from the third input to the multiplier stage, and \n a second specialized processing block including\n a second multiplier stage that receives the product of the third signal and the sum of the first and second signals.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 1.94444
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14919429', '13752661', '15478056', '14880633', '15988458']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4941012197656899
- 35 USC 102 Novelty (BERT): 0.5623589515208041
- Combined Prediction Score: 0.5009269929412014
- Mean Citation Score: 357.683708
- Max Citation Score: 437.87836
- Similarity Product: 375.3923539156961

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test