PATENT CLAIM ANALYSIS

Application Number: 16144286
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Claim (Index 18):
An integrated chip, comprising:\n a select gate electrode extending over an upper surface of a substrate in a first direction, the select gate electrode separated from the upper surface of the substrate by way of one or more select gate dielectric layers; a control gate electrode extending over the upper surface of the substrate, the control gate electrode spaced apart from the select gate electrode in a second direction that is perpendicular to the first direction, and the control gate electrode separated from the upper surface of the substrate by way of a charge trapping dielectric structure, the charge trapping dielectric structure comprising a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer; a logic gate electrode separated from the substrate by way of a thermal gate dielectric layer, wherein the substrate has a first upper surface below the thermal gate dielectric layer, which is recessed with respect to a substantially planar upper surface of the substrate below the control gate electrode and the select gate electrode; and wherein the control gate electrode extends in the first direction between first and second portions of an isolation structure arranged within the substrate, and wherein the tunnel dielectric layer has a first thickness proximate to the first portion of the isolation structure and has a second thickness in a central region of the control gate electrode approximately midway between the first and second portions of the isolation structure, the second thickness being less than the first thickness.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 97.0
- Lexical Diversity: 2.39683
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15365156', '14865179', '14645993', '14779938', '14983682']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9207767895618856
- 35 USC 102 Novelty (BERT): 0.5036022753502385
- Combined Prediction Score: 0.8790593381407209
- Mean Citation Score: 234.062562
- Max Citation Score: 295.94983
- Similarity Product: 254.1272260562146

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test