PATENT CLAIM ANALYSIS

Application Number: 16102534
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "226000"]

Abstract:
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Claim (Index 18):
The method of  claim 17 , wherein:\n the first mode of operation uses a first bias level of a word line of the memory device; the second mode of operation uses a second bias level greater than the first bias level; and the overlay window sets a bias level of the word line from the first bias level to the second bias level based at least in part on the determining.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 96.0
- Lexical Diversity: 1.83582
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15633316', '14703668', '13605538', '14457039', '15948928']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7631147846960377
- 35 USC 102 Novelty (BERT): 0.4803358695881414
- Combined Prediction Score: 0.734836893185248
- Mean Citation Score: 159.59877
- Max Citation Score: 215.28851
- Similarity Product: 175.12511218540251

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test