PATENT CLAIM ANALYSIS

Application Number: 15895321
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["326", "038000"]

Abstract:
A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.

Claim (Index 3):
The PLU of  claim 2 , wherein the first RHL includes:\n a first reconfigurable inverter of the plurality of reconfigurable inverters, the first reconfigurable inverter associated with the first configuration cell, the first reconfigurable inverter arranged to receive the first input; a second reconfigurable inverter of the plurality of reconfigurable inverters, the second reconfigurable inverter associated with the second configuration cell, the second reconfigurable inverter arranged to receive the fourth input; a first two-input NAND gate arranged to receive the second input and coupled with the first reconfigurable inverter to receive the output of the first reconfigurable inverter; a first two-input NOR gate arranged to receive the third input and coupled with the second reconfigurable inverter to receive the output of the second reconfigurable inverter; a third reconfigurable inverter of the plurality of reconfigurable inverters, the third reconfigurable inverter associated with the third configuration cell, the third reconfigurable inverter coupled with the first two-input NAND gate to receive the output of the first two-input NAND gate; a fourth reconfigurable inverter of the plurality of reconfigurable inverters, the fourth reconfigurable inverter associated with the fourth configuration cell, the fourth reconfigurable inverter coupled with the first two-input NOR gate to receive the output of the first two-input NOR gate; a second two-input NAND gate coupled with the third reconfigurable inverter and the fourth reconfigurable inverter to receive the outputs of the third reconfigurable inverter and the fourth reconfigurable inverter; and a fifth reconfigurable inverter of the plurality of reconfigurable inverters, the fifth reconfigurable inverter associated with the fifth configuration cell, the fifth reconfigurable inverter coupled with the second two-input NAND gate to receive the output of the second two-input NAND gate, the output of the fifth reconfigurable inverter connected to the first output.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 88.0
- Lexical Diversity: 2.0303
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['09754632', '14458456', '14089238', '14890911', '15224224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6738923620998086
- 35 USC 102 Novelty (BERT): 0.484449109943518
- Combined Prediction Score: 0.6549480368841796
- Mean Citation Score: 170.86310399999996
- Max Citation Score: 185.4701
- Similarity Product: 124.24530346486569

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test