PATENT CLAIM ANALYSIS

Application Number: 16020739
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-09
Patent Classification: ["257", "314000"]

Abstract:
A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

Claim (Index 18):
A three-dimensional memory device, comprising:\n a stack of a conductive plate layer and source-level material layers overlying a substrate; a first-tier structure overlying the source-level material layers, the first-tier structure including a first alternating stack of first insulating layers and first electrically conductive layers, a first retro-stepped dielectric material portion overlying first stepped surfaces of the first alternating stack, and a first dielectric pillar structure overlying a portion of the source-level material layers; a second-tier structure overlying the first-tier structure, the second-tier structure including a second alternating stack of second insulating layers and second electrically conductive layers, a second retro-stepped dielectric material portion overlying second stepped surfaces of the second alternating stack, and a second dielectric pillar structure overlying the first dielectric pillar structure; memory stack structures extending through each electrically conductive layer in the first and second alternating stacks and comprising a respective memory film and a vertical semiconductor channel; a plate contact via structure extending through the first and second dielectric pillar structures, contacting a top surface of the conductive plate layer, and having a horizontal step between the first and second pillar structures; lower-level metal interconnect structures embedded in lower-level dielectric material layers overlying the substrate and underlying the conductive plate layer; a peripheral-region contact via structure vertically extending through the second retro-stepped dielectric material portion and the first retro-stepped dielectric material portion and contacting one of the lower-level metal interconnect structures; and an array-region contact via structure vertically extending through the second dielectric pillar structure and the first dielectric pillar structure and contacting another one of the lower-level metal interconnect structures.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.46667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16020817', '16020637', '15632983', '15489050', '15269041']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9379682089796132
- 35 USC 102 Novelty (BERT): 0.6231025562130277
- Combined Prediction Score: 0.9064816437029548
- Mean Citation Score: 534.9928540000002
- Max Citation Score: 623.14215
- Similarity Product: 503.2716760986507

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test