PATENT CLAIM ANALYSIS

Application Number: 15973061
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "189050"]

Abstract:
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes a identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.

Claim (Index 8):
An apparatus comprising:\n a plurality of semiconductor chips, each of the plurality of semiconductor chips comprising:\n first and second input terminals configured to receive first and second input signals, respectively; and \n first and second output terminals configured to output first and second output signals, respectively, the first output signal being produced responsive to the first input signal and having a different logic level from the first input signal, the second output signal being produced responsive to the second input signal and having a same logic level as the second input signal, \n wherein the plurality of semiconductor chips are stacked with each other such that the first and second output terminals of a lower one of the plurality of semiconductor chips are coupled to the second and first input terminals of an upper one of the plurality of semiconductor chips, respectively, and wherein each semiconductor chip of the plurality of semiconductor chips is configured to execute a command in a received command signal based on a chip enable signal having a first value, the chip enable signal output from a gate responsive to a comparison between unique identification information with externally supplied access layer identification information.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 2.55357
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14746435', '14330223', '14447531', '14657345', '13747318']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7690810814886643
- 35 USC 102 Novelty (BERT): 0.5135718866958618
- Combined Prediction Score: 0.743530162009384
- Mean Citation Score: 171.32105800000005
- Max Citation Score: 328.5619
- Similarity Product: 264.1070790347636

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test