PATENT CLAIM ANALYSIS

Application Number: 16180033
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "368000"]

Abstract:
The present invention provides a method for fabricating a semiconductor structure, the method at least comprises: firstly, a substrate is provided, a dielectric layer is formed on the substrate, a gate conductive layer and two spacers are formed and disposed in the dielectric layer, wherein the two spacers are respectively disposed on both sides of the gate conductive layer, next, parts of the gate conductive layer are removed, and parts of the two spacers are removed, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and afterwards, a stress cap layer is then formed, overlying the gate conductive layer and the two spacers, wherein parts of the stress cap layer is located right above the two spacers.

Claim (Index 3):
The method of  claim 2 , wherein a top surface of each contact etch stop layer is higher than the top surfaces of the two spacers.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 2.67925
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15627427', '14161724', '14161721', '14822340', '14267555']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.924758977146443
- 35 USC 102 Novelty (BERT): 0.4990452704484953
- Combined Prediction Score: 0.8821876064766482
- Mean Citation Score: 211.178226
- Max Citation Score: 263.4376
- Similarity Product: 207.4875155552864

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test