PATENT CLAIM ANALYSIS

Application Number: 16258405
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "185020"]

Abstract:
A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Claim (Index 4):
The method of  claim 1 , wherein the reprogramming narrows a distribution of an erase state for each of the identified deeply erased cells.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 99.0
- Lexical Diversity: 1.53125
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15471781', '14546133', '14858480', '13453898', '15055186']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8108978736062576
- 35 USC 102 Novelty (BERT): 0.5083919137849374
- Combined Prediction Score: 0.7806472776241256
- Mean Citation Score: 224.43396
- Max Citation Score: 299.719
- Similarity Product: 213.6096983718872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test