PATENT CLAIM ANALYSIS

Application Number: 16270886
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-12
Patent Classification: ["385", "014000"]

Abstract:
Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Claim (Index 13):
A package structure comprising:\n a first chip comprising a first critical edge, a first integrated waveguide, and a second integrated waveguide, wherein the first and second integrated waveguides of the first chip each comprise an end portion that terminates on the first critical edge of the first chip; a second chip comprising a second critical edge, a first integrated waveguide, a second integrated waveguide, and a signal reflection structure, wherein the first and second integrated waveguides of the second chip each comprise an end portion that terminates on the second critical edge of the second chip, and an end portion that is coupled to the signal reflection structure, wherein the signal reflection structure is configured to reflect an optical signal propagating in at least one of the first and second integrated waveguides of the second chip; wherein the first and second chips are edge-coupled at the first and second critical edges such that the end portions of the first integrated waveguides of the first and second chips are aligned to each other, and the end portions of the second integrated waveguides of the first and second chips are aligned to each other; wherein the signal reflection structure of the second chip comprises a Bragg reflector structure connected to end portions of the first and second integrated waveguides of the second chip; wherein the first integrated waveguide and the second integrated waveguide of the second chip have converging end portions which interface with a non-curved Bragg grating of the Bragg reflector structure, wherein the non-curved Bragg grating comprises a plurality of straight partial reflectors arranged in parallel and adjacent to each other.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 99.0
- Lexical Diversity: 2.42373
- Patent Class: 385.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16015884', '16239864', '14662610', '15222169', '15480277']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8332289145145206
- 35 USC 102 Novelty (BERT): 0.5623305279528417
- Combined Prediction Score: 0.8061390758583528
- Mean Citation Score: 308.358284
- Max Citation Score: 435.08148
- Similarity Product: 432.78896180181033

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test