PATENT CLAIM ANALYSIS

Application Number: 16220423
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["438", "586000"]

Abstract:
A method for fabricating an electronic device is provided to include: forming a hard mask pattern over a substrate to expose a gate formation region; forming a gate trench by etching the substrate using the hard mask pattern; forming a gate insulating layer over an inner wall of the gate trench; forming a gate electrode filling a lower portion of the gate trench in which the gate insulating layer is formed; forming an insulating material covering a resultant structure in which the gate electrode is formed; forming a gate protective layer having a top surface lower than a bottom surface of the hard mask pattern; removing the hard mask pattern; recessing the substrate so that a top surface of the substrate is lower than the top surface of the gate protective layer; and forming a conductive pattern filling a space formed by the recessing of the substrate.

Claim (Index 19):
The electronic device of  claim 18 , wherein the variable resistance element includes a pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed therebetween.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 98.0
- Lexical Diversity: 2.66102
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15299323', '15143540', '14322814', '15075016', '14188576']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.882204108726095
- 35 USC 102 Novelty (BERT): 0.5124574087329061
- Combined Prediction Score: 0.8452294387267761
- Mean Citation Score: 266.740526
- Max Citation Score: 272.53503
- Similarity Product: 178.0257378284419

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test