PATENT CLAIM ANALYSIS

Application Number: 16112996
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["712", "225000"]

Abstract:
This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

Claim (Index 17):
The electronic system of  claim 16 , wherein the second memory is a level 2 (L2) cache of the processing core.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 96.0
- Lexical Diversity: 2.27941
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15384355', '15384378', '15384342', '15384416', '15384514']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7017073948140051
- 35 USC 102 Novelty (BERT): 0.5536712065171653
- Combined Prediction Score: 0.6869037759843212
- Mean Citation Score: 436.6317
- Max Citation Score: 463.8435
- Similarity Product: 324.7131151967347

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test