PATENT CLAIM ANALYSIS

Application Number: 16122801
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["717", "140000"]

Abstract:
A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

Claim (Index 9):
A system comprising one or more computers and one or more storage devices storing instructions that operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:\n receiving a first sequence of instructions of a first instruction set architecture, wherein the first sequence of instructions (i) defines an image processing algorithm and (ii) includes one or more load instructions and one or more arithmetic instructions, wherein each load instruction specifies, using a two-dimensional address, a position of data within a region of image data; receiving a request to translate the first sequence of instructions into instructions of a second instruction set architecture, wherein instructions in the second instruction set architecture are executable by an image processer comprising a two-dimensional array of processing elements and a two-dimensional shift-register array, wherein each shift-register in the two-dimensional shift-register array is dedicated to a respective processing element in the two-dimensional array of processing elements; and in response, translating the one or more load instructions in the first instruction set architecture into one or more shift instructions of the second instruction set architecture, wherein each shift instruction is operable to cause the image processor to shift data at the position within the region of image data specified by the two-dimensional address of a corresponding load instruction from a source register in the two-dimensional shift-register array to a destination register.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 97.0
- Lexical Diversity: 1.73214
- Patent Class: 717.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15591960', '14694856', '15598082', '15598933', '15625972']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3426675254179347
- 35 USC 102 Novelty (BERT): 0.5230322060051149
- Combined Prediction Score: 0.3607039934766528
- Mean Citation Score: 252.51270800000003
- Max Citation Score: 292.3338
- Similarity Product: 239.43084535034896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test