PATENT CLAIM ANALYSIS

Application Number: 15871484
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "230050"]

Abstract:
A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

Claim (Index 19):
The semiconductor memory device according to  claim 18 , wherein the CBLs of the second pair are stepped between the first and second subarrays.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15388991', '14974913', '10299696', '14137859', '14671587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7743805295610112
- 35 USC 102 Novelty (BERT): 0.5514213670718441
- Combined Prediction Score: 0.7520846133120945
- Mean Citation Score: 215.45555600000003
- Max Citation Score: 419.6561
- Similarity Product: 372.5638227690339

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test