PATENT CLAIM ANALYSIS

Application Number: 16023584
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["365", "200000"]

Abstract:
A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Claim (Index 16):
The semiconductor memory device of  claim 1 , wherein the fuse information has a first logic level with respect to each of word-lines included in the second cell region,\n wherein the fuse information has a second logic level with respect to each of word-lines included in the first cell region, wherein the memory cell array includes a plurality of bank arrays, and wherein each of the plurality of bank arrays includes the second cell region which is different in each of the plurality of bank arrays.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12320892', '14030066', '13008431', '10657790', '12320891']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8313454290996634
- 35 USC 102 Novelty (BERT): 0.4970797667298984
- Combined Prediction Score: 0.7979188628626869
- Mean Citation Score: 271.242584
- Max Citation Score: 280.63547
- Similarity Product: 219.3353993402713

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test