PATENT CLAIM ANALYSIS

Application Number: 15868506
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["257", "004000"]

Abstract:
A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.

Claim (Index 13):
The resistive switching memory stack of  claim 6 , wherein the bottom layer is formed from TiN, the intermediate layer is formed from (M)AlC, the top layer is formed from TiN, the particular one of the plurality of metals is Al in the intermediate layer, and M is a transition metal selected from the group consisting of Ti, Ta, and Nb.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.56364
- Patent Class: 257.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15421659', '13872932', '15800521', '14989300', '13224021']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9319026104680712
- 35 USC 102 Novelty (BERT): 0.5284085262296533
- Combined Prediction Score: 0.8915532020442295
- Mean Citation Score: 235.41689
- Max Citation Score: 354.17114
- Similarity Product: 254.9076226333606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test