PATENT CLAIM ANALYSIS

Application Number: 15969855
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "288000"]

Abstract:
Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets.

Claim (Index 20):
A semiconductor structure comprising:\n a first nanosheet field effect transistor (FET) device and a second nanosheet FET formed on a substrate; wherein the first nanosheet FET includes:\n a first gate spacer having a first thickness dimension and formed along a first gate region of the first nanosheet FET device; \n first channel nanosheets each having a desired first final channel nanosheet width dimension (F-Wf); and \n a first inner spacer having a second thickness dimension and formed between the first channel nanosheets, the first thickness dimension less than the second thickness dimension; \n wherein the second nanosheet FET includes:\n a second gate spacer having a third thickness dimension and formed along a second gate region of the second nanosheet FET device; \n second channel nanosheets each having a desired second final channel nanosheet width dimension (S-Wf); and \n a second inner spacer having the second thickness dimension and formed between the second channel nanosheets, the third thickness dimension less than the second thickness dimension; \n wherein the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer comprise the same type of spacer material; \n wherein a gate pitch from the first gate region to the second gate region is equal to or less than about 44 nanometers (nm); wherein a space between the first gate region and the second gate region is between about 7 nm and about 18 nm.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 2.74138
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15944322', '15926664', '15924799', '15468755', '15629306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.928649302877844
- 35 USC 102 Novelty (BERT): 0.5452378758241995
- Combined Prediction Score: 0.8903081601724794
- Mean Citation Score: 350.451002
- Max Citation Score: 408.97647
- Similarity Product: 321.63594867361667

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test