PATENT CLAIM ANALYSIS

Application Number: 15901994
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["257", "341000"]

Abstract:
A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.

Claim (Index 1):
A semiconductor device comprising:\n a semiconductor layer having a first plane and a second plane; a first semiconductor region of a first conductivity type provided in the semiconductor layer and extending in a first direction; a second semiconductor region of a second conductivity type provided in the semiconductor layer and extending in the first direction; a third semiconductor region of the second conductivity type provided in the semiconductor layer, extending in the first direction, and the first semiconductor region interposed between the third semiconductor region and the second semiconductor region; a first well region of the first conductivity type provided between the first semiconductor region and the first plane, and having higher first conductivity-type impurity concentration than the first semiconductor region; a second well region of the first conductivity type provided between the first semiconductor region and the first plane, having higher first conductivity-type impurity concentration than the first semiconductor region, and separated from the first well region in the first direction; a first source region of the second conductivity type provided between the first well region and the first plane; a second source region of the second conductivity type provided between the first well region and the first plane; a first contact region of the first conductivity type provided between the first well region and the first plane and provided between the first source region and the second source region, and having higher first conductivity-type impurity concentration than the first well region; a third source region of the second conductivity type provided between the second weld region and the first plane; a fourth source region of the second conductivity type provided between the second well region and the first plane; a second contact region of the first conductivity type provided between the second well region and the first plane and provided between the third source region and the fourth source region, and having higher first conductivity-type impurity concentration than the second well region; a gate electrode having a first to region, a second gate region, a third gate region, a fourth gate region, and a fifth gate region, and extending in the first direction, the first gate region being provided on the first well region between the second semiconductor region and the first source region, the second gate region being provided on the first well region between the third semiconductor region and the second source region, the third gate region being provided on the second well region between the second semiconductor region and the third source region, the fourth gate region being provided on the second well region between the third semiconductor region and the fourth source region, and the fifth gate region being provided on the first semiconductor region between the first well region and the second well region; a first insulating film provided between the first gate region and the first well region; a second insulating film provided between the second gate region and the first well region; a third insulating film provided between the third gate region and the second well region; a fourth insulating film provided between the fourth gate region and the second well region; a fifth insulating film provided between the fifth gate region and the first semiconductor region; a source electrode having a first region and a second region, the first region being in contact with the first source region, the second source region, and the first contact region, and the second region being in contact with the third source region, the fourth source region, and the second contact region; and a drain electrode in contact with the second plane.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 88.0
- Lexical Diversity: 4.48571
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13234802', '13639738', '15070854', '14618068', '12019228']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9178934473586924
- 35 USC 102 Novelty (BERT): 0.4841051237804384
- Combined Prediction Score: 0.8745146150008671
- Mean Citation Score: 233.30881600000004
- Max Citation Score: 237.50664
- Similarity Product: 199.7579109641933

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test