PATENT CLAIM ANALYSIS

Application Number: 15958332
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["361", "783000"]

Abstract:
A printed wiring board includes a core laminate including insulating layers and conductor layers, a first build-up layer formed on first surface of the laminate and including first interlayer resin and conductor layers, and a second build-up layer formed on second surface of the core laminate on the opposite side and including second interlayer resin and conductor layers. The conductor layers in the laminate include first and second conductor layers such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the laminate, and the first interlayer resin layer has thickness greater than thickness of the second interlayer resin layer.

Claim (Index 13):
A semiconductor package, comprising:\n a printed wiring board; a semiconductor component mounted on a surface of the printed wiring board; and a substrate mounted on the surface of the printed wiring board, wherein the printed wiring board comprises a core laminate comprising a plurality of insulating layers and a plurality of conductor layers, a first build-up layer formed on a first surface of the core laminate and comprising a first interlayer resin insulating layer and a conductor layer laminated on the first interlayer resin insulating layer, a second build-up layer formed on a second surface of the core laminate on an opposite side with respect to the first surface of the core laminate and comprising a second interlayer resin insulating layer and a conductor layer laminated on the second interlayer resin insulating layer, and a solder resist layer formed on the conductor layer of the first build-up layer such that the solder resist layer has a plurality of opening portion exposing plural portions of the conductor layer, respectively, the plurality of conductor layers in the core laminate includes a first conductor layer and a second conductor layer such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the core laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the core laminate, the first interlayer resin insulating layer has a thickness which is greater than a thickness of the second interlayer resin insulating layer, and the substrate has a plurality of bumps such that the plurality of bumps is connected to the plural portions of conductor layer exposed from the solder resist layer, respectively.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 91.0
- Lexical Diversity: 3.27273
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14700313', '14857074', '15793084', '14886544', '15581253']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8656381860293052
- 35 USC 102 Novelty (BERT): 0.5571960356167431
- Combined Prediction Score: 0.834793970988049
- Mean Citation Score: 364.05341800000014
- Max Citation Score: 435.12634
- Similarity Product: 419.8805154201712

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test