PATENT CLAIM ANALYSIS

Application Number: 15993206
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["716", "115000"]

Abstract:
A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.

Claim (Index 7):
The method of  claim 6  and wherein, if the first voltage fluctuation in not within the predetermined limit, as part of the first iteration, calculating a delta capacitance value and incrementing the extra capacitor value by the delta capacitor value.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.18182
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15869484', '12979137', '14608410', '11023829', '10749501']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3453439845334127
- 35 USC 102 Novelty (BERT): 0.4670199535869026
- Combined Prediction Score: 0.3575115814387617
- Mean Citation Score: 154.035466
- Max Citation Score: 177.5951
- Similarity Product: 123.3336625298679

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test