PATENT CLAIM ANALYSIS

Application Number: 15875052
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "063000"]

Abstract:
Embodiments include a method, memory system and a device for the operating a bit-line sensing circuit for bias-controlled bit-line sensing, the embodiments include an input for receiving a single-ended local bit-line signal, a pass device having a first terminal coupled to the input and a second terminal connected to a global bit-line node, The embodiments also include a first inverter having an input connected to the global bit-line node, a header circuit coupled to the first inverter and a first direct current (DC) bias circuit, and a footer circuit coupled to the first inverter and a second DC bias circuit. The embodiments include a second gated inverter having an input coupled to an output of the first inverter.

Claim (Index 12):
The memory of  claim 10 , wherein the p-bias signal and the n-bias signal are configured to be weighted to at least one of a high state or low state.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 2.66667
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14068653', '12202843', '12417594', '12205867', '12426271']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8136338407928045
- 35 USC 102 Novelty (BERT): 0.5142936561461633
- Combined Prediction Score: 0.7836998223281404
- Mean Citation Score: 230.46331
- Max Citation Score: 285.31073
- Similarity Product: 160.2819570559442

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test