PATENT CLAIM ANALYSIS

Application Number: 16269687
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-09
Patent Classification: ["257", "296000"]

Abstract:
An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.

Claim (Index 35):
The array of  claim 30  wherein one of the fifth-level conductive shield lines is laterally between every immediately-adjacent of the fifth-level digitlines.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 99.0
- Lexical Diversity: 2.5122
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15928956', '15965632', '15402463', '15401372', '15818934']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9096362301322678
- 35 USC 102 Novelty (BERT): 0.5294457797694433
- Combined Prediction Score: 0.8716171850959853
- Mean Citation Score: 232.658384
- Max Citation Score: 330.99
- Similarity Product: 258.8157750070095

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test