PATENT CLAIM ANALYSIS

Application Number: 15861924
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["713", "189000"]

Abstract:
Memory security technologies are described. An example processing system includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can receive a content read instruction from an application. The processor core can identify a cache line (CL) from a plurality of CLs of a cryptographic cache block (CCB) requested in the content read instruction. The processor core can load, from a cryptographic tree, tree nodes with security metadata. The processor core can retrieve, from the memory, the CCB. The processor core can generate a second MAC from the CCB. The processor core can compare the first MAC with the second MAC. The processor core can decrypt the CCB using security metadata when the first MAC matches the second MAC. The processor core can send at least the identified CL from the decrypted CCB to the application.

Claim (Index 20):
The non-transitory computer readable storage medium of  claim 17 , the processing device further to send a security exception to the application when the first MAC does not match the second MAC.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 2.54688
- Patent Class: 713.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14863353', '14865304', '14803956', '14661044', '14753987']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4053025428370118
- 35 USC 102 Novelty (BERT): 0.5876089650322287
- Combined Prediction Score: 0.4235331850565335
- Mean Citation Score: 263.342028
- Max Citation Score: 518.5871599999998
- Similarity Product: 416.02432301176526

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test