PATENT CLAIM ANALYSIS

Application Number: 16137562
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["710", "009000"]

Abstract:
A bus node is capable of performing a method for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes of the data bus system in an assignment time period. After the assigning of bus node addresses to the bus nodes in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.

Claim (Index 10):
An addressable bus node for a serial data bus system, the data bus system comprising:\n a bus line; a bus master connected to a downstream end of the bus line; and a plurality of bus nodes serially connected to the bus line, the plurality of bus nodes including two or more addressable bus nodes adapted to their respective addresses assigned by the bus master and zero or more standard bus nodes with already fixed addresses, the addressable bus node comprising:\n a current measurement circuit; \n a first addressing current source for feeding an address current into the bus line and via the bus line to the bus master while the address current is detected by the current measurement circuit; \n a quiescent current source for feeding a quiescent current into the bus line and via the bus line to the bus master, wherein the quiescent current source can be identical with the first addressing current source; and \n a control unit for controlling at least the first addressing current source for feeding the address current via selectively one of two electrical nodes into the bus line, the two electrical nodes including a first electrical node and a second electrical node; wherein:\n the current measurement circuit is arranged between the two first electrical node and the second electrical node; \n the control unit comprises an evaluating unit for detecting one of the first electrical node or the second electrical node at which, upon feeding the address current or a test current, the current measurement circuit detects the address current or the test current, and \n the control unit is configured to configure the addressable bus node such that the address current or the test current is fed into the bus line via the one of the first electrical node or second electrical node at which the current measurement circuit detects the address current or the test current.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 2.86792
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16137563', '16137561', '14043186', '16470585', '15048354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6594614459582347
- 35 USC 102 Novelty (BERT): 0.5862823811994535
- Combined Prediction Score: 0.6521435394823566
- Mean Citation Score: 325.28069
- Max Citation Score: 507.13895
- Similarity Product: 428.6809063945413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test