PATENT CLAIM ANALYSIS

Application Number: 16018892
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "194000"]

Abstract:
A circuit includes a plurality of memory cells, a first tracking word line driver, and a second tracking word line driver. The first tracking word line driver outputs a first signal in response to a first region of the plurality of memory cells being accessed, the first signal having a first pulse width. The second tracking word line driver outputs a second signal in response to a second region of the plurality of memory cells being accessed, the second signal having a second pulse width, the second pulse width being different from the first pulse width.

Claim (Index 10):
The circuit of  claim 9 , further comprising a plurality of word line drivers corresponding to the plurality of memory cells, wherein each word line driver of the plurality of word line drivers is configured to\n couple an associated memory cell of the plurality of memory cells with a bit line in response to the address signal indicating the associated memory cell of the plurality of memory cells being accessed, and decouple the associated memory cell of the plurality of memory cells from the bit line in response to the reset signal.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 94.0
- Lexical Diversity: 3.25
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14300750', '15589313', '14924069', '14030497', '14598272']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7770603969080412
- 35 USC 102 Novelty (BERT): 0.4744944333793103
- Combined Prediction Score: 0.746803800555168
- Mean Citation Score: 162.55373400000005
- Max Citation Score: 174.98654
- Similarity Product: 121.56619536834717

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test