PATENT CLAIM ANALYSIS

Application Number: 16005615
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["438", "152000"]

Abstract:
A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.

Claim (Index 19):
A manufacturing method of a semiconductor device, comprising the steps of:\n (a) preparing a substrate that includes a semiconductor substrate, an insulating layer on the semiconductor substrate, a semiconductor layer on the insulating layer, a first insulating film on the semiconductor layer, a trench penetrating the first insulating film, the semiconductor layer and the insulating layer so as to reach the semiconductor substrate, and a second insulating film embedded in the trench, the insulating layer, the first insulating film and the second insulating film being made of the same material as one another; (b) after the step (a), forming a first mask layer that covers the first insulating film in a first region of the substrate and exposes the first insulating film in a second region different from the first region of the substrate; (c) after the step (b), removing the first insulating film in the second region by etching using the first mask layer as an etching mask, thereby exposing the semiconductor layer in the second region; (d) after the step (c), removing the semiconductor layer in the second region by isotropic dry etching using the first mask layer as an etching mask, thereby exposing the insulating layer in the second region; (e) after the step (d), performing etching for the insulating layer in the second region using the first mask layer as an etching mask, thereby reducing a thickness of the insulating layer in the second region; (f) after the step (e), removing the first mask layer; (g) after the step (f), forming a first semiconductor region by ion-implanting an impurity to the semiconductor substrate in the first region, and forming a second semiconductor region by ion-implanting an impurity to the semiconductor substrate in the second region; (h) after the step (g), removing the first insulating film in the first region and the insulating layer in the second region by wet etching, thereby exposing the semiconductor layer in the first region and the semiconductor substrate in the second region; and (i) after the step (h), forming a first transistor on the semiconductor layer in the first region, and forming a second transistor on the semiconductor substrate in the second region.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 94.0
- Lexical Diversity: 4.0
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15679047', '15603564', '15942754', '14803040', '14469371']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8581727796111143
- 35 USC 102 Novelty (BERT): 0.5592266228044307
- Combined Prediction Score: 0.828278163930446
- Mean Citation Score: 339.610742
- Max Citation Score: 422.22296
- Similarity Product: 361.99821174685

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test