PATENT CLAIM ANALYSIS

Application Number: 15963049
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "300000"]

Abstract:
A method of manufacturing a varactor transistor includes providing a semiconductor structure including a semiconductor fin and an initial insulator layer on the semiconductor fin, and forming a plurality of gate structures spaced apart from each other and surrounding a portion of the semiconductor fin. The gate structures include a first dummy gate structure on a first edge of the semiconductor fin, a second dummy gate structure on a second edge of the semiconductor fin, and a first gate structure between the first and second dummy gate structures and spaced apart from the first and second dummy gate structures. The first and second dummy gate structures and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate.

Claim (Index 15):
The method of  claim 14 , wherein the gate comprising a work function adjusting layer on the high-k dielectric layer on the interface layer and a conductive material layer on the work function adjusting layer.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 91.0
- Lexical Diversity: 3.45238
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15400201', '15473183', '15918719', '15603754', '15925390']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922540179119078
- 35 USC 102 Novelty (BERT): 0.531963180478107
- Combined Prediction Score: 0.8834824792549809
- Mean Citation Score: 285.237878
- Max Citation Score: 367.97083
- Similarity Product: 262.773410223254

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test