PATENT CLAIM ANALYSIS

Application Number: 15955122
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "336000"]

Abstract:
An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Claim (Index 2):
The integrated circuit of  claim 1 , wherein the EDMOS transistor includes:\n a buried drain layer extending under the drain layer and overlapping the source region, the buried drain layer having the second conductivity type.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 3.02041
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15182658', '14559239', '13922381', '13284054', '14073472']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927824304848941
- 35 USC 102 Novelty (BERT): 0.6129327011142803
- Combined Prediction Score: 0.8963351444754749
- Mean Citation Score: 400.144908
- Max Citation Score: 522.22766
- Similarity Product: 514.1283640779592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test