PATENT CLAIM ANALYSIS

Application Number: 15939307
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["438", "107000"]

Abstract:
A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.

Claim (Index 17):
A method of manufacturing a semiconductor package structure, comprising:\n bonding a die and a dummy die to a wafer; forming a dielectric material layer on the wafer to cover top surfaces and sidewalls of the die and the dummy die; and removing a portion of the dielectric material layer and a portion of the die by performing at least one planarization process, wherein the sidewalls of the die are laterally protected by the dielectric material layer and the dummy die during the at least one planarization process.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.39535
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15874893', '15662279', '15706783', '15717974', '15905756']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.848948003357017
- 35 USC 102 Novelty (BERT): 0.4882320454071738
- Combined Prediction Score: 0.8128764075620327
- Mean Citation Score: 180.161332
- Max Citation Score: 215.95485
- Similarity Product: 158.86856333554385

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test