PATENT CLAIM ANALYSIS

Application Number: 15985957
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "782000"]

Abstract:
A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.

Claim (Index 14):
The manufacturing method for semiconductor device according to  claim 9 ,\n wherein in the step (c) or the step (d), the sintered-silver-use paste is applied to the second front surface of the chip mounting part at multiple points.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 93.0
- Lexical Diversity: 2.46429
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13639509', '12147676', '13196171', '14252740', '13490459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9125821020345036
- 35 USC 102 Novelty (BERT): 0.5006718068847272
- Combined Prediction Score: 0.871391072519526
- Mean Citation Score: 228.164784
- Max Citation Score: 243.84782
- Similarity Product: 189.37342416307808

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test