PATENT CLAIM ANALYSIS

Application Number: 15987238
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["716", "052000"]

Abstract:
A method for determining whether to order a mask structure using a processor may include acquiring a simulation result of an EUV pattern layout, determining a correlation parameter (CP), generating a predicted wafer process window, and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window. The processor may determine the CP based on a weighting value and a simulated depth of focus (DOF), a simulated energy latitude (EL), and simulated line-LER area and LER-width parameters in the simulation result. The CP may indicate a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout. The predicted wafer process window may be generated using the processor based on the CP. The predicted wafer process window may indicate whether the actual wafer result of the EUV pattern layout will include a patterning defect.

Claim (Index 18):
An apparatus for determining whether to order a mask structure, the apparatus comprising:\n a memory; and a processor coupled to the memory,\n the processor, in response to executing instructions received from the memory, being configured to determine a correlation parameter (CP), based on a simulated depth of focus (DOF), a simulated energy latitude (EL), a simulated line-edge roughness (LER) area parameter, a simulated LER width parameter, and a weighting value, \n the simulated DOF, the simulated EL, the simulated LER area parameter, the simulated LER width parameter being based on a simulation result of an EUV patterning layout, the CP indicating a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout,\n the processor being configured to generate a predicted wafer process window based on the CP, the predicted wafer process window indicating whether the actual wafer result of the EUV pattern layout will include a patterning defect, and \n the processor being configured to determine the mask structure is suitable for ordering based on the CP and the predicted wafer process window.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.55385
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13802257', '09906920', '14013593', '15116486', '14051640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2925806995996554
- 35 USC 102 Novelty (BERT): 0.4726542179249597
- Combined Prediction Score: 0.3105880514321858
- Mean Citation Score: 186.873686
- Max Citation Score: 194.49612
- Similarity Product: 139.08034789078474

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test