PATENT CLAIM ANALYSIS

Application Number: 16177244
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-06
Patent Classification: ["326", "041000"]

Abstract:
An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.

Claim (Index 4):
An architecture in a user-programmable integrated circuit comprising:\n a hard logic block having inputs and outputs; a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block; a shadow soft logic block having inputs and outputs, first selected ones of the inputs of the shadow soft logic coupled to the first group of user-configurable general-purpose routing resources and to the first selected ones of the inputs of the hard logic block, first selected ones of the outputs of the shadow soft logic block coupled to second selected ones of the inputs to the hard logic block; a second group of user-configurable general-purpose routing resources directly coupled to first selected ones of the outputs of the hard logic block; and a shadow multiplexer having first data inputs, second data inputs, a select input, and data outputs, the first data inputs of the shadow multiplexer coupled to second selected ones of the outputs of the shadow soft logic block, the second data inputs of the shadow multiplexer coupled to second selected ones of the outputs of the hard logic block, the data outputs of the shadow multiplexer connected to the second group user-configurable general-purpose routing resources, and the select input of the shadow multiplexer driven by a programmable memory cell.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 4.0303
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13152131', '12819900', '11543417', '11036109', '11351882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6378915354015932
- 35 USC 102 Novelty (BERT): 0.4874132514812255
- Combined Prediction Score: 0.6228437070095564
- Mean Citation Score: 233.653326
- Max Citation Score: 236.99185
- Similarity Product: 189.4024594284594

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test