PATENT CLAIM ANALYSIS

Application Number: 15983069
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-09
Patent Classification: ["327", "143000"]

Abstract:
A power on reset circuit includes a first inverting circuit, a second inverting circuit, a charging apparatus, an output buffer, a current drainer, and a first capacitor. The first inverting circuit and the second inverting circuit are coupled between a voltage detection end and a signal control end in opposite directions. The current drainer drains a current from the voltage detection end according to a power voltage and a voltage on the signal control end. The charging apparatus charges the voltage detection end according to the voltage on the signal control end. The output buffer generates a reset signal according to the voltage on the signal control end.

Claim (Index 12):
The power on reset circuit as claimed in  claim 1 , wherein the output buffer comprises at least one inverter, the input end of the at least one inverter is coupled to the signal control end, the output end of the at least one inverter generates the reset signal.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 2.95
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14876848', '14689041', '14478780', '10569043', '13569829']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.779977923421453
- 35 USC 102 Novelty (BERT): 0.4756194399554808
- Combined Prediction Score: 0.7495420750748558
- Mean Citation Score: 189.03351000000004
- Max Citation Score: 198.82077
- Similarity Product: 155.83498596181872

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test