PATENT CLAIM ANALYSIS

Application Number: 16047883
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-08
Patent Classification: ["326", "003000"]

Abstract:
A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

Claim (Index 7):
The circuit of  claim 4 , wherein a first of the at least two bias inputs is closer to the input than to the output of the gate circuit and a second of the at least two bias inputs is closer to the output than to the input of the gate circuit, and wherein a DC offset of the bias signal of the second bias input is +\u03a6 0 /2, such that the gate circuit is a logical inverter.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 95.0
- Lexical Diversity: 1.48529
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15887524', '15810954', '15886626', '15937418', '15810907']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7582657973318654
- 35 USC 102 Novelty (BERT): 0.5994479989799946
- Combined Prediction Score: 0.7423840174966784
- Mean Citation Score: 446.457114
- Max Citation Score: 667.6732
- Similarity Product: 447.04210440657135

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test