PATENT CLAIM ANALYSIS

Application Number: 16127068
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["716", "104000"]

Abstract:
Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Claim (Index 9):
An application specific integrated circuit (ASIC) chip comprising:\n a first intellectual property (IP) block and a second IP block; a first interface and a second interface configured to utilize a communication protocol between the first and second IP blocks; a communications link connecting the first and second interfaces based on the communication protocol; and at least one gasket inserted between the first and second interfaces and configured to provide control of timing requirements of the communications, the at least one gasket is inserted based on identifying the communication protocol and determining timing estimates between the first and second IP blocks, wherein the communications link utilizes a communication protocol method comprising:\n using delay insensitive (DI) codes to encode information to be communicated between the first and second IP block, \n using quasi-delay-insensitive-logic to communicate the encoded information between the first and second IP block, \n using temporal compression between the first and second IP block, and \n using signals to indicate availability and readiness of information to be communicated between the first and second IP block.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 1.45455
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15344441', '15344416', '15876047', '15876059', '15344420']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3171159855175851
- 35 USC 102 Novelty (BERT): 0.4819442265520583
- Combined Prediction Score: 0.3335988096210325
- Mean Citation Score: 212.818108
- Max Citation Score: 255.43489
- Similarity Product: 191.6243092847979

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test