PATENT CLAIM ANALYSIS

Application Number: 16019677
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["257", "324000"]

Abstract:
A first memory film and a sacrificial fill structure are formed within each first-tier memory opening through a first alternating stack of first insulating layers and first spacer material layers. A second alternating stack of second insulating layers and second spacer material layers is formed over the first alternating stack, and a second-tier memory opening is formed over each sacrificial fill structure. A second memory film is formed in each upper opening, and the sacrificial fill structures are removed from underneath the second-tier memory openings to form memory openings. A semiconductor channel is formed on each vertically neighboring pair of a first memory film and a second memory film as a continuous layer. The first memory film is protected by the sacrificial fill structure during formation of the second-tier memory openings.

Claim (Index 22):
The monolithic three-dimensional memory device of  claim 10 , wherein:\n the monolithic three-dimensional memory structure comprises a monolithic three-dimensional NAND memory device; the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; the substrate comprises a silicon substrate; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and the array of monolithic three-dimensional NAND strings comprises:\n a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; \n a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and \n a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 2.60377
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15914560', '15071575', '15347101', '15434544', '15335850']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9364961391052684
- 35 USC 102 Novelty (BERT): 0.5452805157988257
- Combined Prediction Score: 0.8973745767746243
- Mean Citation Score: 389.59602800000016
- Max Citation Score: 401.63498
- Similarity Product: 389.2656341188908

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test