PATENT CLAIM ANALYSIS

Application Number: 15954874
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "306000"]

Abstract:
An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Claim (Index 4):
A method, comprising the steps of:\n depositing a first polysilicon layer; etching the first polysilicon layer to form a first capacitor electrode and a transistor gate; depositing, in order, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on both the first capacitor electrode and transistor gate; depositing a second polysilicon layer; etching the second polysilicon layer to form a second capacitor electrode separated from the first capacitor electrode by the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer; etching the second silicon oxide layer where not covered by the second capacitor electrode to leave first portions of the first silicon oxide layer and the silicon nitride layer extending beyond side edges of the second capacitor electrode; forming first sidewall spacers on the side edges of the second capacitor electrode, adjacent a side edge of the first capacitor electrode and adjacent side edges of the transistor gate, wherein said first sidewall spacers rest on the first portions of the silicon nitride layer; etching the silicon nitride layer where not covered by the first sidewall spacers to leave second portions of the first silicon oxide layer; and forming second sidewall spacers adjacent side edges of the second capacitor electrode, the first capacitor electrode and the transistor gate, wherein said second sidewall spacers rest on the second portions of the first silicon oxide layer.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 2.86538
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15133394', '11738003', '15296205', '14305137', '15370149']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9067001041285806
- 35 USC 102 Novelty (BERT): 0.5797855797722639
- Combined Prediction Score: 0.874008651692949
- Mean Citation Score: 310.011526
- Max Citation Score: 476.95374
- Similarity Product: 403.3511477961016

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test