PATENT CLAIM ANALYSIS

Application Number: 15884614
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "347000"]

Abstract:
The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

Claim (Index 19):
A method, comprising:\n forming isolation features in a semiconductor substrate, defining first fins in a first region and second fins in a second region; forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins; depositing an inter-layer dielectric (ILD) layer on the semiconductor substrate; removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer; depositing a first tantalum titanium nitride layer in the first and second gate trenches; depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench; forming a patterned mask to cover the second region and uncover the first region; performing an etching process to the titanium aluminum nitride layer in the first gate trench; depositing a second tantalum titanium nitride layer in the first gate trench; and filling a low resistance metal in the first gate trench.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.92157
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15884711', '15864525', '14969077', '12536878', '15800359']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9170686916600628
- 35 USC 102 Novelty (BERT): 0.4940088414696406
- Combined Prediction Score: 0.8747627066410205
- Mean Citation Score: 226.86826
- Max Citation Score: 263.53586
- Similarity Product: 216.9184635421992

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test