PATENT CLAIM ANALYSIS

Application Number: 15878280
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["327", "109000"]

Abstract:
Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Claim (Index 21):
The circuit of  claim 1 , including:\n a second amplifier configured to apply an average voltage to a back gate of the FET, a first resistor configured to couple the source to a first input of the second amplifier; and a second resistor configured to couple the drain to the first input of the second amplifier, wherein the average voltage is an average of a voltage of the drain of the FET and a voltage of the source of the FET.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 86.0
- Lexical Diversity: 1.76471
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11154135', '12357221', '14794496', '11092070', '11683074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.766920367679537
- 35 USC 102 Novelty (BERT): 0.4473563278123903
- Combined Prediction Score: 0.7349639636928224
- Mean Citation Score: 128.73976199999998
- Max Citation Score: 132.11263
- Similarity Product: 107.1404752164805

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test