PATENT CLAIM ANALYSIS

Application Number: 15927791
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["712", "220000"]

Abstract:
A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each including a plurality of encoding slots that contain a plurality of different operations. The plurality of encoding slots and the operations contained therein for each wide instruction are statically assigned to different phases of execution belonging to an ordered set of phases of execution. The ordered set of phases of execution can have a predefined order that allows data produced by execution of an operation in an earlier phase of execution to be consumed by execution of at least one other operation in a later phase of execution.

Claim (Index 15):
A computer processor according to  claim 1 , wherein:\n the instruction processing pipeline includes a plurality of functional unit slots that correspond to the plurality of encodings slots and that include functional units that are configurable to execute the phases of operations that are contained in the corresponding encodings slots.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 90.0
- Lexical Diversity: 1.84483
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14515033', '14312159', '14311988', '14312274', '14797432']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6063959721514866
- 35 USC 102 Novelty (BERT): 0.5065015598116296
- Combined Prediction Score: 0.5964065309175008
- Mean Citation Score: 268.646658
- Max Citation Score: 292.77216
- Similarity Product: 227.03629405706403

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test