PATENT CLAIM ANALYSIS

Application Number: 15987207
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "004000"]

Abstract:
A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

Claim (Index 25):
The semiconductor device of  claim 21 , wherein the second memory section includes line patterns, contacts and memory cells disposed above a capacitor of the first memory section.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 93.0
- Lexical Diversity: 2.95918
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15984914', '15986064', '15854551', '15828937', '15273268']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9359713873251212
- 35 USC 102 Novelty (BERT): 0.539759522412352
- Combined Prediction Score: 0.8963502008338444
- Mean Citation Score: 296.64812399999994
- Max Citation Score: 387.1758
- Similarity Product: 296.56522892603874

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test