PATENT CLAIM ANALYSIS

Application Number: 15886045
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "185130"]

Abstract:
A semiconductor memory device may include a data-determining circuit and a memory cell array. The data-determining circuit may receive data to determine a majority level of data among the received data. The data-determining circuit may provide data bus inversion information to invert data of an address including a minority level of data. The memory cell array may store the data bus inversion information through a redundant bit line.

Claim (Index 3):
The semiconductor memory device of  claim 1 , wherein the storing circuit includes a memory cell array,\n wherein the memory cell array comprises: a plurality of memory cells configured to store the majority level of the data and majority level of data which generated by inverting the minority level of the data; and the memory cell array including an redundant memory cell configured to store the data bus inversion information.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 88.0
- Lexical Diversity: 1.89474
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14176218', '14282379', '12327024', '12846053', '15490614']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8146070167508922
- 35 USC 102 Novelty (BERT): 0.4839742844299317
- Combined Prediction Score: 0.7815437435187962
- Mean Citation Score: 218.458644
- Max Citation Score: 258.84576
- Similarity Product: 222.24978848247525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test