PATENT CLAIM ANALYSIS

Application Number: 16036888
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "156000"]

Abstract:
In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

Claim (Index 11):
The semiconductor device of  claim 10 , further comprising a third fin structure embedded in the isolation insulating layer and disposed between the first and second fin structures,\n wherein the dielectric separation wall is disposed on the third fin structure.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 95.0
- Lexical Diversity: 2.37037
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15481672', '15707682', '15653068', '15725655', '14749602']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8744764785965734
- 35 USC 102 Novelty (BERT): 0.498353574418616
- Combined Prediction Score: 0.8368641881787777
- Mean Citation Score: 242.198032
- Max Citation Score: 265.2897
- Similarity Product: 207.46753647784

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test