PATENT CLAIM ANALYSIS

Application Number: 15927442
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["327", "540000"]

Abstract:
An integrated circuit having at least one electrically-controlled control loop that includes one or more loop error amplifiers also includes an analog-to-digital converter having both an input that operably couples to two inputs of each loop error amplifier and an output that couples to an off-chip hardware component comprising a control circuit. This control circuit reads digital versions that correspond to the loop error amplifier inputs. When a particular first input is greater than a second input, the control circuit sources a calibration signal to modify and offset for the loop error amplifier in a first direction. When the first input is less than the second input, the control circuit sources a calibration signal to modify the offset for the loop error amplifier in a second direction that is different from the aforementioned first direction. By one approach the control circuit also controls a sampling rate of the analog-to-digital converter.

Claim (Index 12):
The control loop automatic zeroing apparatus of  claim 11  wherein the first sampling rate is faster than the second sampling rate.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 90.0
- Lexical Diversity: 2.27536
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13310434', '12136226', '10446392', '10362755', '12277465']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.749326208682471
- 35 USC 102 Novelty (BERT): 0.4844540187892968
- Combined Prediction Score: 0.7228389896931536
- Mean Citation Score: 187.19276
- Max Citation Score: 190.98398
- Similarity Product: 141.23387999050738

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test