PATENT CLAIM ANALYSIS

Application Number: 15907444
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["257", "040000"]

Abstract:
Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other. The logic circuit of the invention is configured such that dual-gate thin-film transistors are three-dimensionally stacked, whereby the advantages of the dual-gate structure and of thin-film transistors can be exhibited together and the degree of integration can be drastically increased, and a logic gate is made in the area of a single transistor, thereby remarkably simplifying wire and circuit designs.

Claim (Index 22):
A digital circuit, comprising the logic circuit of  claim 1  in a singular or plural number,\n the digital circuit being any one selected from the group consisting of NOT, AND, OR, NOR, XOR and NXOR.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.48214
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16066862', '15876596', '12686550', '13376834', '12880312']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239922737626052
- 35 USC 102 Novelty (BERT): 0.5203843360828476
- Combined Prediction Score: 0.8836314799946294
- Mean Citation Score: 253.656596
- Max Citation Score: 327.92932
- Similarity Product: 229.2649709605837

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test