PATENT CLAIM ANALYSIS

Application Number: 15911922
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "369000"]

Abstract:
Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

Claim (Index 19):
A semiconductor device, comprising:\n a substrate including a plurality of logic cells arranged in a first direction, each of the plurality of logic cells comprising PMOSFET and NMOSFET regions that are spaced apart from each other in the first direction; and active patterns provided in each of the PMOSFET and NMOSFET regions and arranged in the first direction, the active patterns protruding from the substrate and extending in a second direction crossing the first direction, wherein the plurality of logic cells comprises first, second, and third logic cells arranged in the first direction, the first logic cell interposed between the second and third logic cells, wherein the first logic cell includes first and second cell boundaries, the first cell boundary between the PMOSFET regions of the first and second logic cells and the second cell boundary between the NMOSFET regions of the first and third logic cells, wherein the first logic cell further includes an internal boundary between the PMOSFET and NMOSFET regions of the first logic cell, wherein the internal boundary is equidistant from a first adjacent pair of the active patterns, which include one from the PMOSFET region and other one from the NMOSFET region, that are most adjacent to each other in the first direction, and wherein a first height from the internal boundary to the first cell boundary is greater than a second height from the second cell boundary to the internal boundary.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 2.78
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15496015', '14505788', '15478234', '15821116', '15409202']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9284329440153002
- 35 USC 102 Novelty (BERT): 0.5264065308970651
- Combined Prediction Score: 0.8882303027034767
- Mean Citation Score: 320.386532
- Max Citation Score: 345.9213
- Similarity Product: 309.1732896980166

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test