PATENT CLAIM ANALYSIS

Application Number: 15901437
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["257", "797000"]

Abstract:
According to an embodiment, a first resist pattern that includes a mark including a second pattern provided with first components and a third pattern not provided with the first components is formed. Then, a first recessed area is formed on a processing target layer using the first resist pattern. Thereafter, a second resist pattern that includes a fourth pattern is formed. The fourth pattern is formed such that the third pattern and part of the second pattern, which includes at least one row of the first components arranged along a periphery of the third pattern, are exposed. Then, a second recessed area is formed by using the second resist pattern. Thereafter, a position of the processing target layer is recognized by using a stepped portion formed at the second recessed area, in a light exposure apparatus, and a third resist pattern is formed.

Claim (Index 16):
The semiconductor device manufacturing method according to  claim 1 , wherein\n the mark has an optically observable size, and the first components have an optically unobservable size.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 2.77193
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14965159', '14863938', '14747295', '11491302', '14799787']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9177709308944296
- 35 USC 102 Novelty (BERT): 0.4852891302615433
- Combined Prediction Score: 0.874522750831141
- Mean Citation Score: 170.103488
- Max Citation Score: 187.29083
- Similarity Product: 133.07975792595266

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test