PATENT CLAIM ANALYSIS

Application Number: 16256887
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-09
Patent Classification: ["365", "051000"]

Abstract:
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Claim (Index 19):
The memory according to  claim 17 , wherein:\n a second portion of the conductive path is formed in at least one through-silicon-via (TSV).

Metadata:
- Claim Count in Document: 51.0
- Percentile: 99.0
- Lexical Diversity: 2.57778
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15603333', '14114725', '16175645', '15277949', '15175933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8132562388202095
- 35 USC 102 Novelty (BERT): 0.5258320312737805
- Combined Prediction Score: 0.7845138180655666
- Mean Citation Score: 233.928972
- Max Citation Score: 364.86325
- Similarity Product: 283.2902551953494

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test