PATENT CLAIM ANALYSIS

Application Number: 16042607
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["331", "008000"]

Abstract:
The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage.

Claim (Index 19):
A phase-locked loop (PLL) comprising:\n a frequency detector, which is configured to receive a reference signal and an output signal, and generate a coarse-tuning voltage, wherein the coarse-tuning voltage indicates a frequency difference between the reference signal and the output signal; a sub-sampling phase detector (SSPD), which is configured to sub-sample the output signal using the reference signal, and generate a fine-tuning voltage, wherein:\n the SSPD comprises a first switch, a first capacitor, a unit-gain buffer, a non-overlap generator, a second switch, and a second capacitor; \n the first switch is configured to sub-sample the output signal onto the first capacitor providing a sampled voltage, wherein the first switch is controlled by the reference signal; \n the unit-gain buffer is configured to receive the sampled voltage and generate a buffered sampled voltage; \n the non-overlap generator is configured to generate a non-overlap clock based on the reference signal, wherein the non-overlap clock and the reference signal have a same frequency, and are never overlapped with each other; \n the second switch is configured to sample the buffered sampled voltage onto the second capacitor providing the fine-tuning voltage, wherein the second switch is controlled by the non-overlap clock; and \n the fine-tuning voltage indicates a phase difference between the reference signal and the output signal; and \n a voltage-controlled oscillator (VCO), which is configured to adjust the output signal based on the coarse-tuning voltage and the fine-tuning voltage.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 95.0
- Lexical Diversity: 2.72727
- Patent Class: 331.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12824982', '13406228', '14057276', '15234743', '12219452']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7672473925786337
- 35 USC 102 Novelty (BERT): 0.4879988865046603
- Combined Prediction Score: 0.7393225419712364
- Mean Citation Score: 231.908976
- Max Citation Score: 235.40901
- Similarity Product: 182.3489063941294

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test