PATENT CLAIM ANALYSIS

Application Number: 15867646
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["711", "103000"]

Abstract:
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

Claim (Index 11):
The memory controller circuit of  claim 8  wherein the connectivity read circuit is further configured to transmit a sequence of the bit patterns to the memory device with the connectivity read command.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 86.0
- Lexical Diversity: 2.2381
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14438865', '13514977', '13970606', '15857519', '14861451']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.363533749778453
- 35 USC 102 Novelty (BERT): 0.5465042915788173
- Combined Prediction Score: 0.3818308039584894
- Mean Citation Score: 201.96538000000004
- Max Citation Score: 381.06918
- Similarity Product: 311.16699672125105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test