PATENT CLAIM ANALYSIS

Application Number: 15991020
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["327", "156000"]

Abstract:
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Claim (Index 9):
The time-to-digital converter circuit of  claim 7 , wherein the stop signal generation circuit comprises:\n an AND gate to receive the first and second trigger signals, an output of the AND gate comprising the stop signal; a flip-flop including a clock input to receive the third clock, the flip-flop configured to latch the stop signal from the AND gate to generate a latched stop signal; and a delay element to receive the stop signal from the AND gate and to generate the delayed stop signal.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 93.0
- Lexical Diversity: 2.625
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15183752', '10839201', '15675160', '12018770', '13380392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7719828557343771
- 35 USC 102 Novelty (BERT): 0.4723448173953645
- Combined Prediction Score: 0.7420190519004759
- Mean Citation Score: 171.15700599999997
- Max Citation Score: 173.64496
- Similarity Product: 127.49264482569694

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test