PATENT CLAIM ANALYSIS

Application Number: 16032896
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "296000"]

Abstract:
A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.

Claim (Index 7):
The device according to  claim 6 , wherein the metal gate has a width of 0.03 \u03bcm to 0.06 \u03bcm in parallel with the substrate.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 1.78947
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15231215', '13303096', '14471546', '13245494', '14936848']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9227315629666246
- 35 USC 102 Novelty (BERT): 0.5005838393209366
- Combined Prediction Score: 0.8805167906020559
- Mean Citation Score: 194.151252
- Max Citation Score: 199.7367
- Similarity Product: 123.22399250428676

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test