PATENT CLAIM ANALYSIS

Application Number: 15917168
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "329000"]

Abstract:
An SGT is formed in Si pillars. The SGT includes WSi 2  layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

Claim (Index 14):
A method for producing a semiconductor device including an SGT, the method comprising:\n a step of forming a first semiconductor pillar that stands on a substrate in a vertical direction; a step of forming a first gate insulating layer that surrounds the first semiconductor pillar; a step of forming a first gate conductor layer that surrounds the first gate insulating layer; a step of forming a first impurity region that is positioned below the first gate conductor layer in the vertical direction, is connected to a portion inside the first semiconductor pillar or to a side surface of the first semiconductor pillar, and contains a donor or acceptor impurity; a step of forming a first conductive layer that surrounds a periphery of the first semiconductor pillar in plan view and is in contact with the first gate conductor layer or the first impurity region; a step of forming, on the first conductive layer, a first material layer that surrounds a side surface of a periphery of the first semiconductor pillar with an equal width in plan view; a step of forming, on the first conductive layer, a second material layer that is partly in contact with the first material layer in plan view; and a step of etching the first conductive layer using the first material layer and the second material layer as masks, wherein, as a result of the etching of the first conductive layer, a second conductive layer that is in contact with the first gate conductor layer or the first impurity region and surrounds a side surface of a periphery of the first gate conductor layer or the first impurity region with an equal width in plan view and a third conductive layer that is partly in contact with the second conductive layer are formed.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15655168', '14806053', '15584466', '14689640', '15360488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239082136567884
- 35 USC 102 Novelty (BERT): 0.5456758417507251
- Combined Prediction Score: 0.8860849764661822
- Mean Citation Score: 379.74567
- Max Citation Score: 392.4889
- Similarity Product: 317.39981776309014

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test