PATENT CLAIM ANALYSIS

Application Number: 16162480
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["345", "100000"]

Abstract:
A pulse is inputted to TFTs  101  and  104  so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT  105  then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT  105  further rises due to an operation of capacitance  107  as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT  105.

Claim (Index 2):
A semiconductor device comprising a driver circuit, the driver circuit comprising a pulse output circuit,\n wherein the pulse output circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have a same conductive type, wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to a first line, wherein the other of the source and the drain of the second transistor is electrically connected to a second line, wherein one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor are electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the third transistor is electrically connected to a third line, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second line, wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor, wherein one of a source and a drain of the fifth transistor and one of a source and a drain of the sixth transistor are electrically connected to a gate of the first transistor, wherein one of a source and a drain of the seventh transistor and one of a source and a drain of the eighth transistor are electrically connected to the gate of the fifth transistor, wherein a gate the seventh transistor is electrically connected to a fourth line, and wherein a gate of the eighth transistor is electrically connected to a fifth line.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.13636
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14816124', '15343373', '14332468', '15802524', '13604709']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7486021419782194
- 35 USC 102 Novelty (BERT): 0.6001447075410616
- Combined Prediction Score: 0.7337563985345036
- Mean Citation Score: 488.126016
- Max Citation Score: 489.8225
- Similarity Product: 481.9690329191089

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test