PATENT CLAIM ANALYSIS

Application Number: 15982910
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["702", "119000"]

Abstract:
An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Claim (Index 24):
A tester comprising:\n a system controller for controlling a test program for testing one or two DUTs; a site module board operable to interface with and test said one or two DUTs, said site module board coupled to said system controller, wherein said site module board comprises: a tester processor coupled to communicate with said system controller to receive instructions and data therefrom in accordance with said test program; a programmable instantiated tester block coupled to said tester processor via a bus on said site module board, wherein said programmable instantiated tester block is operable to generate test data for application to said one or two DUTs in a way transparent to said test processor, further operable to receive and compare test data generated by said one or two DUTs in a way transparent to said tester processor, and further yet operable to be programmed to communicate with said one or two DUTs in a communication protocol compatible with said one or two DUTs; and a local memory coupled to said programmable instantiated tester block for storing test data therein; and one or two connectors for coupling said one or two DUTs to said site module board; wherein each programmable instantiated tester block is operable in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said programmable instantiated tester block in a different manner.

Metadata:
- Claim Count in Document: 71.0
- Percentile: 93.0
- Lexical Diversity: 2.35938
- Patent Class: 702.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13773569', '13773555', '13773580', '13781337', '13950164']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2414324138897824
- 35 USC 102 Novelty (BERT): 0.5963756260703144
- Combined Prediction Score: 0.2769267351078356
- Mean Citation Score: 445.41587
- Max Citation Score: 517.82416
- Similarity Product: 469.9290820526314

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test