PATENT CLAIM ANALYSIS

Application Number: 16018571
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "185030"]

Abstract:
A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered. This helps to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. The transition of the memory cell from off to on is also improved.

Claim (Index 6):
The apparatus of  claim 1 , wherein:\n the row decoder circuit is configured to apply a set of increasing read voltages to the selected word line during a sequential read operation; and the current sense circuit is configured to turn off the bit line control transistor in response to a second read voltage applied to the selected word line following a first read voltage in the set of the increasing read voltages.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 2.21918
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11136369', '12385198', '12499237', '16018018', '10867679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8261438032378265
- 35 USC 102 Novelty (BERT): 0.493369793286172
- Combined Prediction Score: 0.7928664022426611
- Mean Citation Score: 256.809304
- Max Citation Score: 272.8812
- Similarity Product: 218.30278374474048

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test