PATENT CLAIM ANALYSIS

Application Number: 16036906
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["714", "820000"]

Abstract:
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects

Claim (Index 1):
A system-on-chip (SoC) comprising:\n memory that includes coherent memory regions; at least one agent that sends read and write transactions; and a coherent interconnect comprising:\n a transport network in communication with the agent; \n a plurality of coherent interconnect elements in communication with the agent, the transport network, and the memory, the plurality of coherent interconnect elements including:\n a selected set of functional coherent interconnect elements; and \n a plurality of checker coherent interconnect elements, \n wherein a driver of an input port of one of the selected set of functional coherent interconnect elements also drives an input port of one of the plurality of checker coherent interconnect elements at least one clock cycle later; and \n \n a controller in communication with the selected set of functional coherent interconnect elements and the plurality of checker coherent interconnect elements such that an output of the one of the selected set of functional coherent interconnect elements is delayed by at least one clock cycle and sent to the controller and the output of the one of the plurality of checker coherent interconnect elements is sent to the controller and the controller analyzes the output of the one of the selected set of functional coherent interconnect elements, relative to the output of the one of the plurality of checker coherent interconnect elements, to detect if a fault has occurred in the output of the one of the selected set of functional coherent interconnect elements when there is a mismatch.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 95.0
- Lexical Diversity: 2.29167
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15391727', '15396416', '13590159', '15494544', '13994282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2357018059301649
- 35 USC 102 Novelty (BERT): 0.5189027665069124
- Combined Prediction Score: 0.2640219019878397
- Mean Citation Score: 180.885234
- Max Citation Score: 332.62067
- Similarity Product: 312.0311664321208

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test