PATENT CLAIM ANALYSIS

Application Number: 16027041
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "692000"]

Abstract:
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

Claim (Index 8):
The method of  claim 1  wherein:\n the conductive interconnects are arranged in an interconnect pattern in the peripheral region of the base substrate; \n the interconnect assembly comprises at least first and second interconnect structures\u2014\n the first interconnect structure being on the first side of the base substrate in the peripheral region, and the first interconnect structure having a first stratum of matrix material and plurality of first interconnect segments arranged in the interconnect pattern; and \n the second interconnect structure being on the first interconnect structure, and the second interconnect structure having a second stratum of matrix material and a plurality of second interconnect segments arranged in the interconnect pattern such that individual second interconnect segments are aligned with corresponding individual first interconnect segments; and \n the method comprises forming the first and second interconnect structures apart from the base substrate, attaching the first and second interconnect structures together apart from the base substrate, and then attaching the first interconnect structure to the first side of the base substrate.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 95.0
- Lexical Diversity: 2.45312
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14714599', '15229668', '14963451', '15393387', '10676883']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.930582342943626
- 35 USC 102 Novelty (BERT): 0.5147174116169928
- Combined Prediction Score: 0.8889958498109628
- Mean Citation Score: 237.45870800000003
- Max Citation Score: 310.4486
- Similarity Product: 263.43025954597

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test