PATENT CLAIM ANALYSIS

Application Number: 16143225
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["375", "230000"]

Abstract:
A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Claim (Index 11):
A method comprising:\n obtaining a plurality of bits associated with a symbol value; providing the input stream of symbol values to a plurality of driver slice circuits, each driver slice circuit having a respective resistive element; generating a signal level according to the plurality of bits associated with the symbol value, the signal level generated using the plurality of driver slice circuits, wherein generating the respective signal level comprises selectively coupling, for each driver slice circuit of the plurality of driver slice circuits, the respective resistive element to a constant-voltage node of a respective group of constant-voltage nodes, the constant-voltage node selected based on the plurality of bits associated with the symbol value; and forming an output symbol value at a common output node connected to (i) the plurality of driver slice circuits and (ii) a wire of a multi-wire bus by forming a summation of signal levels provided by each driver slice circuit of the plurality of driver slice circuits, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.86364
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14315306', '15918851', '15402148', '14829388', '14952491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5244931460119424
- 35 USC 102 Novelty (BERT): 0.5863319704687348
- Combined Prediction Score: 0.5306770284576217
- Mean Citation Score: 403.421006
- Max Citation Score: 496.3756
- Similarity Product: 432.2731719973088

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test