PATENT CLAIM ANALYSIS

Application Number: 15937454
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "156000"]

Abstract:
A SRAM cell, including, in a stack of layers, transistors including at least first and second access transistors connected to a word line, the first access transistor coupling a first bit line and a first storage node and the second access transistor coupling a second bit line and a second storage node, and a flip-flop including a first conduction transistor coupling the first storage node to a source of a first reference potential and having its gate coupled to the second storage node and a second conduction transistor coupling the second storage node to the source of the first reference potential and having its gate coupled to the first storage node.

Claim (Index 13):
The memory of  claim 12 , wherein, for each memory cell, the third and fourth conduction transistors are located in the second level.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 90.0
- Lexical Diversity: 3.16216
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12466733', '12005666', '13097370', '12235870', '12533394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.813184028109384
- 35 USC 102 Novelty (BERT): 0.5034383489919686
- Combined Prediction Score: 0.7822094601976424
- Mean Citation Score: 228.86845
- Max Citation Score: 281.59042
- Similarity Product: 199.22464611979245

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test