PATENT CLAIM ANALYSIS

Application Number: 15761426
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "211000"]

Abstract:
A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

Claim (Index 45):
A multilevel semiconductor device, the device comprising:\n a first level comprising a first array of first memory cells and a first control line; a second level comprising a second array of second memory cells and a second control line; a third level comprising a third array of third memory cells and a third control line,\n wherein said second level overlays said first level, and \n wherein said third level overlays said second level; \n a first access pillar; a second access pillar; a third access pillar; and a memory control level comprising memory control circuits designed to individually control every cell of said first memory cells, second memory cells and third memory cells,\n wherein said memory control level overlays said third level or underlays said first level, \n wherein said device comprises an array of units, \n wherein each of said units comprises a plurality of said first memory cells, said second memory cells, said third memory cells, and a portion of said memory control circuits, \n wherein said array of units comprise at least four rows and four columns of units, and \n wherein said memory control circuits are designed to control independently each of said units. \n The device according to  claim 45 , wherein said first access pillar has a first electrically programmable connection to said first control line.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 3.70968
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15333138', '15911071', '15344562', '15224929', '15452615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9134399809057772
- 35 USC 102 Novelty (BERT): 0.5108843251814025
- Combined Prediction Score: 0.8731844153333397
- Mean Citation Score: 248.33726600000003
- Max Citation Score: 312.55124
- Similarity Product: 258.5360875541568

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test