PATENT CLAIM ANALYSIS

Application Number: 16010664
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["365", "220000"]

Abstract:
A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Claim (Index 18):
The DIMM of  claim 11 , wherein the second interface of the memory controller further to:\n send a second MRS command to the buffer circuit to deactivate the DBI functionality for the memory device.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 94.0
- Lexical Diversity: 2.16
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14787651', '12797557', '14675591', '14951377', '13455691']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8456873510416426
- 35 USC 102 Novelty (BERT): 0.5081233831961066
- Combined Prediction Score: 0.8119309542570889
- Mean Citation Score: 211.78377000000003
- Max Citation Score: 277.6625
- Similarity Product: 167.91597690284254

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test