PATENT CLAIM ANALYSIS

Application Number: 15966775
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["714", "011000"]

Abstract:
A redundant computer system utilizing comparison diagnostics and voting techniques includes a plurality of redundant channels. Each pair of the processors receives/obtains process information from I/O modules via dual redundant sensors (DRS). The processors execute an application program, whereby output module is utilized for comparing output data of the two processors. Output module receives output data from neighboring modules, if there is a deviation or other disparity in the output data. Each pair of processors, a voter and an improper sequence detector component disables the output module, if a majority of signals vote that output module fails. In addition, the system uses 2-of-3 voting, the system remains operational in the presence of up two transient or hard failures.

Claim (Index 2):
The redundant computer system of  claim 1 , wherein:\n said voter component includes a plurality of parallel voting groups that are coupled between a voltage source and a ground node, with each voting group including at least two low power switches, such as a MOSFET or any other suitable transistor or relay for example, connected in series;\n said primary and secondary processor in each channel continually controlling said switches in two groups by the associated lines, while the switches in the third group is controlled by said ISD; \n said voter component produces an output signal as a result of a majority of two-out-of-three voting among signals, which the primary and a secondary processor and the ISD produce on the inputs of said voter component; \n said output signal in each channel is connected to a corresponding input of said logic circuit that disconnects output of the associated channel from output of the system if said majority of two-out-of-three signals vote that said output controller fails; \n a logic circuit in each channel includes an arrangement of plurality of a logic gates, the inputs of said arrangement is in operative communication with said output controller; outputs of said arrangement is in operative communication with inputs of said voting network via an isolation drivers; \n said logic circuit is in operative communication with said output controller and in operative communication with said voting network, said voting network includes three switches in series for each controlled point that is in operative communication with said logic circuit, said three switches in said first, second, and third channels are coupled in parallel for each controlled point for providing an output of the system; \n in normal operation, the system performs 2-of-3 voting among output data produced by said first, second, and third channel; \n a single output controller excludes an own output data from outputs of said logic circuit and uses output data received from the neighboring output controllers, the system then performs the 2-of-2 voting instead of 2-of-3 voting if said disparity signal is activated in said single output controller for some controlled points; \n said output controllers in two channels excludes an own output data from outputs of said associated logic circuits and uses output data received from the neighboring output controllers, the system then performs the 1-of-2 voting instead of 2-of-3 voting if said disparity signal activates in said two channels of the system for some controlled points; \n the system, continues to operate in the presence of said disparity in one or two channels, the system may perform a safe shutdown for the process, if said disparity occurs in all channels concurrently.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.67089
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12316966', '10899667', '11923534', '10758977', '11389349']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2692362331055731
- 35 USC 102 Novelty (BERT): 0.5109744987826097
- Combined Prediction Score: 0.2934100596732768
- Mean Citation Score: 185.776398
- Max Citation Score: 281.1801
- Similarity Product: 208.7628353088141

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test