PATENT CLAIM ANALYSIS

Application Number: 15877219
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "316000"]

Abstract:
A three-dimensional memory device includes semiconductor devices located on a semiconductor substrate, lower interconnect level dielectric layers embedding lower interconnect structures, an alternating stack of insulating layers and electrically conductive layers overlying the lower interconnect level dielectric layers and including stepped surfaces, memory stack structures vertically extending through the alternating stack, and contact via structures extending downward from the stepped surfaces through underlying portions of the alternating stack to the lower interconnect structures. Each of the contact via structures laterally contacts an electrically conductive layer located at the stepped surfaces, and provides electrical interconnection to an underlying semiconductor device. A top portion of each contact via structures contacts an electrically conductive layer, and is electrically isolated from other underlying electrically conductive layers.

Claim (Index 11):
The three-dimensional memory device of  claim 1 , wherein:\n the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; bottom ends of the memory stack structures contact a planar semiconductor material layer; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the planar semiconductor material layer; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the at least one semiconductor device comprises an integrated circuit comprising a driver circuit for monolithic three-dimensional NAND memory device located thereon; the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate; the plurality of control gate electrodes comprises at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and the array of monolithic three-dimensional NAND strings comprises: a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate, and a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.29825
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15489050', '15269294', '15632983', '15269041', '15638672']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9403910620118302
- 35 USC 102 Novelty (BERT): 0.5666401829926871
- Combined Prediction Score: 0.903015974109916
- Mean Citation Score: 437.393132
- Max Citation Score: 450.66562000000016
- Similarity Product: 426.2062108262182

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test