PATENT CLAIM ANALYSIS

Application Number: 16029701
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["326", "041000"]

Abstract:
A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Claim (Index 6):
The field-programmable-gate-array (FPGA) IC chip of  claim 5 , wherein the gate terminal of the floating-gate N-type MOS transistor comprises polysilicon.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 2.22
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15841326', '11171489', '14481943', '10827786', '12283443']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6353692973975664
- 35 USC 102 Novelty (BERT): 0.5547859917115618
- Combined Prediction Score: 0.6273109668289659
- Mean Citation Score: 226.70871
- Max Citation Score: 420.45532
- Similarity Product: 342.34351129026413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test