PATENT CLAIM ANALYSIS

Application Number: 15938101
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-01
Patent Classification: ["257", "326000"]

Abstract:
A vertical-type memory device and a manufacturing method thereof, the device including a substrate having a cell array region and a connection region; gate electrode layers stacked on the cell array region and the connection region of the substrate, the gate electrode layers forming a stepped structure in the connection region; a cell channel layer in the cell array region, the cell channel layer passing through the plurality of gate electrode layers; a dummy channel layer in the connection region, the dummy channel layer passing through at least one gate electrode layer of the plurality of gate electrode layers; a cell epitaxial layer disposed below the cell channel layer; and a dummy epitaxial layer disposed below the dummy channel layer, wherein the dummy epitaxial layer has a shape that is different from a shape of the cell epitaxial layer.

Claim (Index 4):
The vertical-type memory device as claimed in  claim 2 , wherein:\n the cell epitaxial layer is in contact with the cell channel layer, and the lower region of the at least one dummy epitaxial layer is spaced apart from the at least one dummy channel layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.06122
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15252740', '15937932', '15907667', '14987835', '15626395']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9298646061032362
- 35 USC 102 Novelty (BERT): 0.5133480752612685
- Combined Prediction Score: 0.8882129530190395
- Mean Citation Score: 272.487742
- Max Citation Score: 295.43683
- Similarity Product: 221.9954585165501

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test