PATENT CLAIM ANALYSIS

Application Number: 16159287
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["711", "154000"]

Abstract:
There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

Claim (Index 4):
The method of  claim 1 , wherein when the memory cells coupled between the Nth memory cell from the bit line and the Mth memory cell from the source line are erased, the Nth memory cell from the bit line and the Mth memory cell from the source line are not erased.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 2.42593
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16031147', '15264764', '15651477', '13492287', '15867103']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5298625648917358
- 35 USC 102 Novelty (BERT): 0.5323716661136686
- Combined Prediction Score: 0.5301134750139291
- Mean Citation Score: 280.06064000000003
- Max Citation Score: 342.81177
- Similarity Product: 237.01915580867

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test