PATENT CLAIM ANALYSIS

Application Number: 15950302
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["257", "678000"]

Abstract:
A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.

Claim (Index 17):
The packaging method according to  claim 15 , wherein before performing the cutting process, the method further comprises:\n forming a strengthening layer on a side of the wafer facing away from the reinforcing layer, wherein the strengthening layer is located on the outermost side of the package.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.61702
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15765968', '15765802', '15826261', '12905095', '12370537']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9305971111575432
- 35 USC 102 Novelty (BERT): 0.5206979846900505
- Combined Prediction Score: 0.889607198510794
- Mean Citation Score: 262.426234
- Max Citation Score: 283.7158
- Similarity Product: 160.0046207049608

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test