PATENT CLAIM ANALYSIS

Application Number: 15909284
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "226000"]

Abstract:
An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.

Claim (Index 10):
The apparatus of  claim 1 , wherein an individual bit-cell of the bit-cells comprises:\n first and second active regions parallel along a first direction of a substrate; and first, second, third, and fourth gate lines over the first and second active regions, wherein the first, second, third, and fourth gate lines are parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 90.0
- Lexical Diversity: 2.08333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15396341', '14606942', '13976326', '15396339', '14731678']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8002121519678191
- 35 USC 102 Novelty (BERT): 0.4821588584053304
- Combined Prediction Score: 0.7684068226115703
- Mean Citation Score: 181.181528
- Max Citation Score: 195.77084
- Similarity Product: 135.91295806591748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test