PATENT CLAIM ANALYSIS

Application Number: 16107724
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "189150"]

Abstract:
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.

Claim (Index 2):
The system of  claim 1 , wherein the memory device comprises control circuitry configured to cause performance of the in-place inversion by controlling the sensing circuitry to:\n place the inverse of the data value on a complementary pair of data lines to which the sensing circuitry is coupled; disable the compute component latch; while the compute component latch is disabled, enable the sense amplifier latch to store the inverse of the data value therein; and while the sense amplifier is enabled:\n enable a pass transistor; and \n while the pass transistor is enabled, enable the compute component latch such that the inverse of the data value is stored therein.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 96.0
- Lexical Diversity: 1.55556
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14724366', '14715161', '13962399', '15439681', '15651186']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8304860093090964
- 35 USC 102 Novelty (BERT): 0.5401420885637525
- Combined Prediction Score: 0.801451617234562
- Mean Citation Score: 359.610984
- Max Citation Score: 389.48767
- Similarity Product: 347.19944616392195

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test