PATENT CLAIM ANALYSIS

Application Number: 15888050
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["370", "389000"]

Abstract:
A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

Claim (Index 18):
The system of  claim 17 , wherein the information of the packet header comprises identifiers of a L4 connection.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 88.0
- Lexical Diversity: 1.8125
- Patent Class: 370.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14863961', '14864088', '15835233', '15835239', '15835250']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6189352248811302
- 35 USC 102 Novelty (BERT): 0.6617923116519161
- Combined Prediction Score: 0.6232209335582088
- Mean Citation Score: 389.4709019999999
- Max Citation Score: 657.12006
- Similarity Product: 634.0020067512238

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test