PATENT CLAIM ANALYSIS

Application Number: 15911892
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["438", "595000"]

Abstract:
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Claim (Index 9):
The method of  claim 1 , wherein depositing the sacrificial layer comprises depositing a layer of polycrystalline silicon.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.88636
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15258597', '14595756', '14699427', '15267887', '13680257']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9161818817042108
- 35 USC 102 Novelty (BERT): 0.5692995170615538
- Combined Prediction Score: 0.881493645239945
- Mean Citation Score: 446.327568
- Max Citation Score: 451.9066
- Similarity Product: 426.9729198148132

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test