PATENT CLAIM ANALYSIS

Application Number: 15915718
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-06
Patent Classification: ["327", "543000"]

Abstract:
An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.

Claim (Index 1):
An ORing circuit comprising:\n an input port for receiving an input voltage; an output port for outputting an output voltage; an ORing FET (field effect transistor) electrically connected between the input port and the output port and comprising a source, a gate and a drain, wherein the source of the ORing FET is electrically connected with the input port, and the drain of the ORing FET is electrically connected with the output port; a comparing circuit electrically connected with the input port and the gate of the ORing FET; a first transistor comprising a first terminal, a second terminal and a third terminal, wherein the first terminal is electrically connected with the input port and the source of the ORing FET, and the third terminal is electrically connected with the gate of the ORing FET; and a second transistor comprising a fourth terminal, a fifth terminal and a sixth terminal, wherein the fourth terminal is electrically connected with the output port and the drain of the ORing FET, the fifth terminal is connected to the sixth terminal, and the sixth terminal is electrically connected with the second terminal of the first transistor.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 4.82353
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11493992', '13983766', '14371725', '13034518', '15009438']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7722157895353055
- 35 USC 102 Novelty (BERT): 0.4852524541309975
- Combined Prediction Score: 0.7435194559948747
- Mean Citation Score: 220.457076
- Max Citation Score: 244.18417
- Similarity Product: 194.068885244416

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test