PATENT CLAIM ANALYSIS

Application Number: 16154291
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-09
Patent Classification: ["326", "030000"]

Abstract:
Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated with data transmitted using signaling and related techniques. In some cases, the signaling may be multi-level signaling. Such signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data.

Claim (Index 2):
An apparatus, comprising:\n a multi-leg driver that comprises a first partition and a second partition, wherein the first partition is configured to output first data and the second partition is configured to output second data; a controller coupled with the multi-leg driver, the controller configured to determine an output impedance of at least one of the first partition or the second partition, wherein the first data output from the first partition comprises multiple bits including a most-significant bit of data, and the second data output from the second partition comprises multiple bits including a least-significant bit of data; a first transistor coupled with a first leg group of the first partition, the first transistor configured to adjust an impedance level of at least one leg of the first leg group based at least in part on the controller determining the output impedance of the at least one of the first partition or the second partition; a second transistor coupled with at least one leg of a second leg group of the first partition, the second transistor configured to adjust a voltage level of the at least one leg of the second leg group based at least in part on the controller determining the output impedance of the at least one of the first partition or the second partition; and a second resistive component coupled with the leg group, wherein the second resistive component is configured to adjust an impedance level of the first partition based at least in part on the second transistor adjusting a voltage level of the at least one leg of the second leg group.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 97.0
- Lexical Diversity: 1.51064
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15934663', '15893089', '15870502', '15868797', '15854600']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.644490765245913
- 35 USC 102 Novelty (BERT): 0.4822631631810063
- Combined Prediction Score: 0.6282680050394223
- Mean Citation Score: 179.88572399999995
- Max Citation Score: 243.13905
- Similarity Product: 204.4859023363888

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test