PATENT CLAIM ANALYSIS

Application Number: 16114644
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-08
Patent Classification: ["365", "218000"]

Abstract:
Provided herein may be a memory device, a memory system including the memory device, and a method of operating the memory system. The memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a program operation and an erase operation on any of the plurality of memory blocks; and a logic group configured to control the peripheral circuit to perform the program operation and the erase operation. The logic group may control the peripheral circuit to perform, during the program operation on a first memory block, selected as a current open block among the plurality of memory blocks, sub-operations of an erase operation on a second memory block to be selected as a subsequent open block.

Claim (Index 14):
The memory system according to  claim 13 , wherein the memory device alternately performs the first to the N-th program operations and the first to N-th sub-operations of the erase operation.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 96.0
- Lexical Diversity: 2.79592
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15977410', '15095284', '15613649', '15961080', '15936652']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8181715333227589
- 35 USC 102 Novelty (BERT): 0.4933741749681885
- Combined Prediction Score: 0.7856917974873019
- Mean Citation Score: 231.78317400000003
- Max Citation Score: 238.73138
- Similarity Product: 164.39772888895988

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test