PATENT CLAIM ANALYSIS

Application Number: 15762572
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "072000"]

Abstract:
A semiconductor device includes a thin film transistor including an oxide semiconductor layer and a wire connecting portion ( 201 ). The wire connecting portion ( 201 ) includes a lower electrically-conductive portion ( 3 t ) formed out of a same electrically-conductive film as the gate electrode, an insulating layer ( 15 ) having a contact hole (CH 2 ) through which at least a part of the lower electrically-conductive portion ( 3 t ) is exposed, and an upper electrically-conductive portion ( 19 t ), at least a part of which is provided inside the contact hole (CH 2 ). The insulating layer ( 15 ) includes the gate insulating layer ( 4 ), the protection layer ( 9 ) and the interlayer insulating layer ( 13 ). At a lateral wall of the contact hole, the gate insulating layer ( 4 ) includes an upper portion ( 41 ) and a lower portion ( 42 ) which is present on the substrate side of the upper portion ( 41 ), and when viewed in a normal direction of the substrate, a lateral surface of the lower portion ( 42 ) juts out from a lateral surface of the upper portion ( 41 ). The upper electrically-conductive portion ( 19 t ) is in contact with the lower electrically-conductive portion ( 3 t ) and the lateral surface and an upper surface of the lower portion ( 42 ) of the gate insulating layer ( 4 ) inside the contact hole.

Claim (Index 15):
A method for manufacturing a semiconductor device which includes a thin film transistor and a wire connecting portion, the method comprising:\n (A) forming a gate conductive film on a substrate and patterning the gate conductive film such that a gate electrode of the thin film transistor is formed in a TFT formation region in which the thin film transistor is to be formed and that a lower electrically-conductive portion of the wire connecting portion is formed in a wire connecting portion formation region in which the wire connecting portion is to be formed; (B) forming a gate insulating layer so as to cover the gate electrode and the lower electrically-conductive portion; (C) forming an oxide semiconductor film on the gate insulating layer and patterning the oxide semiconductor film, thereby forming an oxide semiconductor layer of the thin film transistor; (D) forming a protection layer on the oxide semiconductor layer and the gate insulating layer so as to cover at least a channel region of the oxide semiconductor layer, the protection layer also being extended over the wire connecting portion formation region, the protection layer having an opening overlapping part of the lower electrically-conductive portion when viewed in a normal direction of the substrate; (E) forming a source conductive film so as to cover the oxide semiconductor layer and patterning the source conductive film such that a source electrode and a drain electrode of the thin film transistor are formed, thereby obtaining the thin film transistor; (F) forming an interlayer insulating layer so as to cover the thin film transistor, the interlayer insulating layer also being extended over the wire connecting portion formation region, (G) etching the interlayer insulating layer, the protection layer and the gate insulating layer such that a contact hole is formed in the wire connecting portion formation region, through which part of the lower electrically-conductive portion is exposed, the etching being carried out under such a condition that an end portion of the protection layer and an upper portion of part of the gate insulating layer underlying the end portion of the protection layer are removed while a lower portion of the part of the gate insulating layer underlying the end portion of the protection layer remains, so that at a lateral wall of the contact hole, the gate insulating layer includes an upper portion and a lower portion which is present on the substrate side of the upper portion and has such a step structure that the lower portion juts out from the upper portion when viewed in the normal direction of the substrate; and (H) inside the contact hole, forming an upper electrically-conductive portion so as to be in contact with the part of the lower electrically-conductive portion and the lateral surface and an upper surface of the lower portion of the gate insulating layer, thereby obtaining the wire connecting portion.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 3.56
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14370996', '14358778', '13823872', '14745677', '15423759']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9244630235981318
- 35 USC 102 Novelty (BERT): 0.5127588833298299
- Combined Prediction Score: 0.8832926095713016
- Mean Citation Score: 283.570946
- Max Citation Score: 315.27234
- Similarity Product: 255.0204880665994

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test