PATENT CLAIM ANALYSIS

Application Number: 16011028
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["365", "158000"]

Abstract:
A memory array that comprises three dimensionally stacked two-dimensional memory arrays. The memory array includes a first layer and a second layer oriented orthogonal to the first layer. The memory array further includes a magnetic tunnel junction adjacent to each of the first layer and the second layer. The magnetic tunnel junction further includes a first magnetic layer adjacent to the second layer. Additionally, the magnetic tunnel junction includes a second magnetic layer adjacent to the first layer. The magnetic tunnel junction also includes a tunnel layer adjacent to the first magnetic layer and the second magnetic layer.

Claim (Index 14):
The method of  claim 11 , further comprising applying the bias voltage to one or more other rows in the second layer to ensure the one or more other memory elements in the memory array are not programmed.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 3.28125
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14811805', '13160306', '13554467', '15030291', '15327017']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7834650415562806
- 35 USC 102 Novelty (BERT): 0.4872436458218031
- Combined Prediction Score: 0.7538429019828329
- Mean Citation Score: 205.985102
- Max Citation Score: 211.82553
- Similarity Product: 141.33143907652436

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test