PATENT CLAIM ANALYSIS

Application Number: 15923174
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["711", "129000"]

Abstract:
In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

Claim (Index 18):
A system comprising:\n a processor comprising:\n a plurality of cores each including a first level cache memory; and \n a cache memory hierarchy coupled to the plurality of cores, the cache memory hierarchy including:\n the first level cache memory included in the plurality of cores; \n a shared cache memory coupled to the first level cache memory, the shared cache memory including:\n a cache controller to control the shared cache memory, the cache controller including a control circuit, in response to a bandwidth on a memory interconnect that couples the processor with a memory that exceeds a first bandwidth threshold, to allocate a virtual write buffer within the shared cache memory and update a replacement policy to preferentially evict clean data from the shared cache memory; and \n \n \n a memory controller to interact with the memory and maintain bandwidth information for the memory interconnect; \n the memory interconnect to couple the processor to the memory; and the memory coupled to the processor via the memory interconnect.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 90.0
- Lexical Diversity: 1.81633
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13942291', '15701795', '14671411', '14137359', '15476816']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.507753023312493
- 35 USC 102 Novelty (BERT): 0.4698946499428288
- Combined Prediction Score: 0.5039671859755266
- Mean Citation Score: 178.78918000000004
- Max Citation Score: 185.46117
- Similarity Product: 144.74184109329343

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test