PATENT CLAIM ANALYSIS

Application Number: 16042070
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "491000"]

Abstract:
A transient voltage suppression device with improved electrostatic discharge (ESD) robustness includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second doped well having the second conductivity type, a second heavily-doped area having the first conductivity type, and a first current blocking structure. The first doped well is arranged in the semiconductor substrate. The first heavily-doped area is arranged in the first doped well. The second doped well is arranged in the semiconductor substrate. The second heavily-doped area is arranged in the second doped well. The first current blocking structure is arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate, and arranged between the first doped well and the second doped well.

Claim (Index 14):
The transient voltage suppression device with improved ESD robustness according to  claim 12 , wherein the first conductivity type is an N type and the second conductivity type is a P type.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 95.0
- Lexical Diversity: 3.57143
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12848531', '13072138', '12888151', '13475599', '15251910']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.93664640335137
- 35 USC 102 Novelty (BERT): 0.5190843206501147
- Combined Prediction Score: 0.8948901950812445
- Mean Citation Score: 310.9118180000001
- Max Citation Score: 320.7966
- Similarity Product: 238.3146359454632

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test