PATENT CLAIM ANALYSIS

Application Number: 15937632
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "225000"]

Abstract:
An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Claim (Index 1):
An image sensor comprising:\n a first semiconductor layer having at least one transistor; a first interlayer insulating layer disposed on the first semiconductor layer; a second interlayer insulating layer disposed on the first interlayer insulating layer; a second semiconductor layer having a photodiode that includes an N-type region and a P-type region, the second semiconductor layer being disposed on the second interlayer insulating layer; a first conductive plug that penetrates the first interlayer insulating layer and is electrically connected to the first semiconductor layer; a second conductive plug that penetrates the second interlayer insulating layer and is electrically connected to the second semiconductor layer; and a conductive pattern between the first and second semiconductor layers, wherein the first semiconductor layer is electrically connected to the second semiconductor layer by the first conductive plug, the second conductive plug, and the conductive pattern, wherein the second semiconductor layer further comprises a transfer transistor, and at least a portion of the transfer transistor overlaps the N-type region in a plan view, wherein the second interlayer insulating layer is disposed between the first interlayer insulating layer and the second semiconductor layer, and is in contact with at least one surface of a gate of the transfer transistor.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 90.0
- Lexical Diversity: 1.68519
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15047444', '13838627', '12684163', '11524695', '11385958']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9148554624157584
- 35 USC 102 Novelty (BERT): 0.5257616731207103
- Combined Prediction Score: 0.8759460834862536
- Mean Citation Score: 314.08184
- Max Citation Score: 343.58737
- Similarity Product: 334.6174323842919

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test