PATENT CLAIM ANALYSIS

Application Number: 16183493
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Claim (Index 33):
The array of  claim 31  wherein, orthogonal the columns, the metal lines are laterally wider than the pillars.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 98.0
- Lexical Diversity: 2.92857
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14461751', '15584413', '14461689', '14461730', '15900537']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9345532586806432
- 35 USC 102 Novelty (BERT): 0.5375701541193463
- Combined Prediction Score: 0.8948549482245137
- Mean Citation Score: 312.93374
- Max Citation Score: 387.34625
- Similarity Product: 224.6458808352053

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test