PATENT CLAIM ANALYSIS

Application Number: 15944175
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["257", "329000"]

Abstract:
A semiconductor device includes a substrate; a vertical channel structure including a pair of active fins extended in a first direction, perpendicular to an upper surface of the substrate, and an insulating portion interposed between the pair of active fins; an upper source/drain disposed on the vertical channel structure; a lower source/drain disposed below the vertical channel structure and on the substrate; a gate electrode disposed between the upper source/drain and the lower source/drain and surrounding the vertical channel structure; and a gate dielectric layer disposed between the gate electrode and the vertical channel structure. An interval between the gate electrode and the upper source/drain may be smaller than an interval between the gate electrode and the lower source/drain in the first direction.

Claim (Index 2):
The semiconductor device as claimed in  claim 1 , wherein the interval between the gate electrode and the upper source/drain in the first direction is equal to a thickness of the gate dielectric layer.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 2.75
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14704485', '11393750', '14824542', '15041612', '15204259']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9271836653275874
- 35 USC 102 Novelty (BERT): 0.4906855752271801
- Combined Prediction Score: 0.8835338563175467
- Mean Citation Score: 233.926732
- Max Citation Score: 245.31737
- Similarity Product: 198.89123506377936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test