PATENT CLAIM ANALYSIS

Application Number: 16204409
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "104000"]

Abstract:
Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

Claim (Index 39):
An apparatus comprising:\n a memory array having rows and columns: the memory array being supported by a silicon-containing base; wordlines along the rows; comparative bitlines along the columns; the comparative bitlines being in pairs along each column; each pair of the comparative bitlines including a first comparative bitline and a second comparative bitline; a plurality of memory cells; each memory cell within the plurality of memory cells being uniquely addressed with one of the wordlines and one pair of the comparative bitlines; each memory cell within the plurality of memory cells comprising two p-channel transistors and two n-channel transistors, with the p-channel and n-channel transistors being arranged within a first inverter and a second inverter; the first and second inverters having first and second inverter outputs, respectively; each memory cell within the plurality of memory cells comprising a first access transistor gatedly coupling the first inverter output with a first comparative bitline of a pair of comparative bitlines uniquely addressing the memory cell, and a second access transistor gatedly coupling the second inverter output with a second comparative bitline of the pair of comparative bitlines uniquely addressing the memory cell; the first and second access transistors having gates coupled with a wordline uniquely addressing the memory cell; one of the memory cells within the plurality of memory cells being a first memory cell and being uniquely addressed by a first wordline and a first pair of the comparative bitlines; the first and second comparative bitlines of said first pair being laterally adjacent to one another and on an opposing side of the first wordline from the p-channel transistors and the n-channel transistors of the first memory cell; one of the memory cells within the plurality of memory cells being a second memory cell vertically stacked relative to the first memory cell and sharing the first pair of the comparative bitlines; and the second memory cell being substantially a mirror image of the first memory cell across a plane extending through the first pair of the comparative bitlines.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.71698
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15796611', '10801334', '15797462', '13746395', '16043653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.775765543824212
- 35 USC 102 Novelty (BERT): 0.5826235563484037
- Combined Prediction Score: 0.7564513450766313
- Mean Citation Score: 313.302702
- Max Citation Score: 485.1104
- Similarity Product: 451.37653410739904

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test