PATENT CLAIM ANALYSIS

Application Number: 16135897
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["438", "007000"]

Abstract:
A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.

Claim (Index 24):
The memory device of  claim 23 , wherein the blocking dielectric layer includes a high K dielectric layer, wherein the high K dielectric layer includes at least one of hafnium based materials, zirconium based material, and yttrium based materials.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 97.0
- Lexical Diversity: 2.77273
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14969468', '15266239', '14562462', '15189668', '15988981']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.862067217694524
- 35 USC 102 Novelty (BERT): 0.5235294052242665
- Combined Prediction Score: 0.8282134364474982
- Mean Citation Score: 267.043512
- Max Citation Score: 304.89883
- Similarity Product: 189.8135704296648

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test