PATENT CLAIM ANALYSIS

Application Number: 15772410
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

Claim (Index 14):
The driving method of a shift register circuitry, according to  claim 13 , wherein the shift register circuitry at least further comprises a pull-down control circuit, a first pull-down circuit, and a second pull-down circuit;\n wherein the plurality of output circuits comprise at least a first output circuit and a second output circuit; wherein the input circuit is coupled to the input signal terminal, a first voltage terminal, a first pull-up point, and a second pull-up point; wherein the first output circuit is coupled to a first clock signal terminal and a first output signal terminal; wherein the second output circuit is coupled to a second clock signal terminal and a second output signal terminal; wherein the pull-down control circuit is coupled to a third voltage terminal, a third clock signal terminal, the first pull-up point, the second pull-up point, and a pull-down point; wherein the first pull-down circuit is coupled to the pull-down point, the third voltage terminal, the first pull-up point, and the first output signal terminal; wherein the second pull-down circuit is coupled to the pull-down point, the third voltage terminal, the second pull-up point, and the second output signal terminal; wherein applying a valid voltage to an input signal terminal such that the plurality of output circuits are in operation comprises:\n applying the valid voltage to the input signal terminal, and applying an invalid voltage to the first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and a reset signal terminal, such that the input circuit couples the first voltage terminal to the first pull-up point and the second pull-up point, voltages at the first pull-up point and the second pull-up point are valid, the first output circuit couples the first clock signal terminal to the first output signal terminal, the first output signal terminal outputs an invalid voltage, the second output circuit couples the second clock signal terminal to the second output signal terminal, and the second output signal terminal outputs an invalid voltage; \n wherein applying a valid voltage to the clock signal terminal such that each of the plurality of output circuits outputs a driving signal comprises:\n applying a valid voltage to the first clock signal terminal, and applying an invalid voltage to the input signal terminal, the second clock signal terminal, the third clock signal terminal, and the reset signal terminal, such that voltages at the first pull-up point and the second pull-up point are valid, the first output circuit couples the first clock signal terminal to the first output signal terminal, the first output signal terminal outputs a valid voltage, the second output circuit couples the second clock signal terminal to the second output signal terminal, and the second output signal terminal outputs an invalid voltage; \n applying a valid voltage to the second clock signal terminal, and applying an invalid voltage to the input signal terminal, the first clock signal terminal, the third clock signal terminal, and the reset signal terminal, such that voltages at the first pull-up point and the second pull-up point are valid, the first output circuit couples the first clock signal terminal to the first output signal terminal, the first output signal terminal outputs an invalid voltage, the second output circuit couples the second clock signal terminal to the second output signal terminal, and the second output signal terminal outputs a valid voltage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.97778
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15680452', '15232095', '15761749', '15780157', '15750679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7243377951899126
- 35 USC 102 Novelty (BERT): 0.5125799692918521
- Combined Prediction Score: 0.7031620126001066
- Mean Citation Score: 288.8553100000001
- Max Citation Score: 305.9340200000001
- Similarity Product: 237.65666956583507

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test