PATENT CLAIM ANALYSIS

Application Number: 16192751
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "059000"]

Abstract:
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Claim (Index 1):
A method of forming an integrated circuit device, comprising:\n forming a sacrificial layer on a handling substrate; forming a semiconductor active layer on the sacrificial layer; selectively etching through the semiconductor active layer and the sacrificial layer to define a patterned substrate comprising a first portion of the semiconductor active layer; forming a multi-layer electrical interconnect network on the patterned substrate; encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer; selectively etching through the inorganic capping layer and the first portion of the semiconductor active layer to expose the sacrificial layer; and selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the inorganic capping layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 98.0
- Lexical Diversity: 2.69492
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12732868', '14334179', '14708893', '15864813', '15243228']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9196475121793916
- 35 USC 102 Novelty (BERT): 0.5138633886816247
- Combined Prediction Score: 0.879069099829615
- Mean Citation Score: 318.784616
- Max Citation Score: 320.9089
- Similarity Product: 315.77136327943805

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test