PATENT CLAIM ANALYSIS

Application Number: 16048364
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["365", "185030"]

Abstract:
Provided is a three dimensional memory including a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layer respectively cover surfaces of the charge storage structures arranged along each of the source lines.

Claim (Index 4):
The three dimensional memory according to  claim 1 , further comprising a metal silicide layer disposed on the source line so as to reduce a resistance between the source line and the bit line.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 95.0
- Lexical Diversity: 3.02083
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13376925', '14757572', '15343332', '15865892', '15971293']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7383264381440002
- 35 USC 102 Novelty (BERT): 0.4913067093136574
- Combined Prediction Score: 0.7136244652609659
- Mean Citation Score: 176.354716
- Max Citation Score: 184.05528
- Similarity Product: 118.00160095813747

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test