PATENT CLAIM ANALYSIS

Application Number: 15864525
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "737000"]

Abstract:
The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Claim (Index 13):
A method for fabricating an integrated circuit, comprising:\n forming a device fin structure on a substrate, wherein the device fin structure includes a plurality of device fins and defines trenches among the device fins; filling the trenches with a first dielectric material layer and a second dielectric material layer, resulting in a fill fin structure having a plurality of fill fins; and forming gate stacks on the device fins and the fill fins.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.24324
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14942740', '15689466', '15686860', '14579728', '14328350']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9194793748793416
- 35 USC 102 Novelty (BERT): 0.4901714752904622
- Combined Prediction Score: 0.8765485849204536
- Mean Citation Score: 218.572096
- Max Citation Score: 221.21724
- Similarity Product: 159.24737130733254

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test