PATENT CLAIM ANALYSIS

Application Number: 16029607
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Claim (Index 2):
The dynamic decode circuit according to  claim 1 , further comprising one or more evaluate transistors, wherein each evaluate transistor is connected to the first power source, wherein the each evaluate transistor is configured to receive an identical evaluation clock signal at a respective base, wherein a third node of the decoder is conductively connected to a first evaluate transistor,\n wherein the each evaluate transistor is configured to conduct based on the evaluation clock signal being active, wherein the each evaluate transistor is configured not to conduct based on the evaluation clock signal being inactive.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 1.43243
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16029577', '15613185', '15796819', '16029604', '15274322']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7759849106199791
- 35 USC 102 Novelty (BERT): 0.5554391677911046
- Combined Prediction Score: 0.7539303363370916
- Mean Citation Score: 483.02547
- Max Citation Score: 489.0524
- Similarity Product: 360.0061428015709

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test