PATENT CLAIM ANALYSIS

Application Number: 16113363
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["257", "347000"]

Abstract:
A semiconductor device includes a substrate including a lower substrate layer, a buried insulation layer on the lower substrate layer, and an upper substrate layer on the buried insulation layer, a first trench passing through the upper substrate layer, the buried insulation layer, and a portion of the lower substrate layer, a second trench passing through the upper substrate layer, the buried insulation layer, and a portion of the lower substrate layer and being spaced apart from the first trench, a field insulation layer in a portion of the first trench and in a portion of the second trench, and a first fin pattern defined by the first trench and the second trench. An upper surface of the field insulation layer is higher than an upper surface of the buried insulation layer.

Claim (Index 4):
The device according to  claim 1 , wherein the first fin pattern includes a first upper substrate pattern that is a portion of the first upper substrate between the first trench and the second trench,\n wherein the first upper substrate pattern has an epi trench, and wherein the device further comprises a first epitaxial pattern filing the epi trench.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 3.6
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14956908', '13243174', '14027372', '15168694', '14751011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9252909340667004
- 35 USC 102 Novelty (BERT): 0.5045016975377047
- Combined Prediction Score: 0.8832120104138008
- Mean Citation Score: 225.300146
- Max Citation Score: 240.32806
- Similarity Product: 158.44262442549348

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test