PATENT CLAIM ANALYSIS

Application Number: 16042949
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["327", "143000"]

Abstract:
Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Claim (Index 1):
A circuit comprising:\n a latch; and a delay circuit coupled to the latch, wherein the delay circuit comprises multiple inverters that are configured to reset the latch to a predetermined state at power-up, and wherein one or more inverters of the multiple inverters are arranged to provide a source supply voltage to at least one other inverter of the multiple inverters.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 2.03571
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15143197', '12134309', '11849296', '15657406', '13491622']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7525923442000286
- 35 USC 102 Novelty (BERT): 0.4955630148312206
- Combined Prediction Score: 0.7268894112631479
- Mean Citation Score: 181.270854
- Max Citation Score: 258.23938
- Similarity Product: 191.6261912550437

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test