PATENT CLAIM ANALYSIS

Application Number: 16013009
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["345", "209000"]

Abstract:
The disclosure discloses an array substrate, a method for driving the same and a display device. The array substrate includes: a plurality of pixel elements, all pixel elements in each column being connected on two data lines and two gate lines, each pixel element in each column is electrically connected with a first data line through a first switch transistor and electrically connected with a second data line through a second switch transistor; all gates of first switch transistors connected with respective pixel elements in each row are connected on a first gate line, all gates of second switch transistors connected with the respective pixel elements in each row are connected on a second gate line; and a first data line and a second data line shared by each column are located respectively on two sides of said column and have drive voltage with opposite polarities and equal amplitudes.

Claim (Index 8):
A display device, comprising an array substrate, wherein the array substrate comprises: a plurality of pixel elements arranged in an array, all pixel elements in each column of pixel elements being connected on two data lines shared by said column of pixel elements, and all pixel elements in each row of pixel elements being connected onto two gate lines shared by said row of pixel elements, wherein:\n each pixel element in each column of pixel elements is electrically connected with a first data line of the two data lines shared by said column of pixel elements respectively through a first switch transistor, and is electrically connected with a second data line of the two data lines shared by said column of pixel elements respectively through a second switch transistor; all gates of first switch transistors connected with respective pixel elements in each row of pixel elements are connected on a first gate line of the two gate lines shared by said row of pixel elements, and all gates of second switch transistors connected with the respective pixel elements in each row of pixel elements are connected on a second gate line of the two gate lines shared by said row of pixel elements; and a first data line and a second data line shared by each column of pixel elements are located respectively on two sides of said column of pixel elements, and drive voltage on the first data line and the second data line shared by said column of pixel elements have opposite polarities and equal amplitudes.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 94.0
- Lexical Diversity: 2.50794
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15552781', '13504435', '14371194', '13392952', '12944477']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6395587962073226
- 35 USC 102 Novelty (BERT): 0.4696653771794162
- Combined Prediction Score: 0.6225694543045319
- Mean Citation Score: 202.004428
- Max Citation Score: 213.8345
- Similarity Product: 186.0743928087056

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test