PATENT CLAIM ANALYSIS

Application Number: 16136046
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["327", "158000"]

Abstract:
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second arid third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

Claim (Index 17):
An apparatus, comprising:\n a clock path including, at least, a delay circuit, the clock path configured to receive a clock signal; and a variable clock divider configured to divide the clock signal based, at least in part, on a delay to the clock signal by the clock path, the delay circuit configured to input the divided clock signal from the variable clock divider, delay the divided clock signal, and the output the delayed divided clock signal.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 97.0
- Lexical Diversity: 1.97674
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15786362', '13415777', '11643916', '11000940', '15059453']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.732574492119199
- 35 USC 102 Novelty (BERT): 0.5344233274157131
- Combined Prediction Score: 0.7127593756488504
- Mean Citation Score: 241.812814
- Max Citation Score: 366.8524
- Similarity Product: 312.1838088842392

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test