PATENT CLAIM ANALYSIS

Application Number: 16242430
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "191000"]

Abstract:
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

Claim (Index 37):
An integrated circuit comprising:\n a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:\n a first silicon controlled rectifier device having a first region, a first floating body region, a first buried layer region, and a first substrate region; \n a second silicon controlled rectifier device having a second region, a second floating body region, a second buried layer region, and a second substrate region; \n a transistor comprising said first region, said first floating body region, said second region, and a gate; and \n a control circuit configured to provide electrical signals to said first and second substrate regions; \n wherein said first floating body region is common to said second floating body region; \n wherein said first buried layer region is common to said second buried layer region; \n wherein said first substrate region is common to said second substrate region; \n wherein a state of said memory cell is maintained through a positive voltage applied to said first and second substrate regions; \n wherein said transistor is usable to access said memory cell; \n wherein said first and second buried layer regions are commonly connected to at least two of said memory cells; and \n wherein said first and second substrate regions are commonly connected to said at least two of said memory cells.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 99.0
- Lexical Diversity: 3.49038
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15933897', '14956103', '14444109', '15290996', '13244916']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8390994329232628
- 35 USC 102 Novelty (BERT): 0.583417680064007
- Combined Prediction Score: 0.8135312576373372
- Mean Citation Score: 388.071104
- Max Citation Score: 400.9049
- Similarity Product: 371.97994921771294

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test