PATENT CLAIM ANALYSIS

Application Number: 15973061
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "189050"]

Abstract:
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes a identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.

Claim (Index 1):
An apparatus comprising:\n a semiconductor chip including first and second surfaces, the semiconductor chip further including: first and second input terminals formed on a side of the first surface and configured to receive first and second input signals, respectively; first and second output terminals formed on a side of the second surface such that the first and second output terminals are horizontally arranged in line with the first and second input terminals, respectively, and configured to output first and second output signals, respectively; a first conductive path coupling the first input terminal to the second output terminal and configured to produce the second output signal that is different in logic level from the first input signal, wherein the first conductive path between the first input terminal and the second output terminal includes an inverter configured to invert the first input signal to provide the second output signal that is different in logic level from the first input signal; a second conductive path coupling the second input terminal to the first output terminal and configured to produce the first output signal that is equal in logic level to the second input signal, wherein the second conductive path between the second input terminal and the first output terminal includes a buffer configured to buffer the second input signal to provide the first output signal that is equal in logic level to the second input signal; a first compare circuit configured to compare a first bit of assigned identification information with a first bit of an externally supplied access layer identification information to determine whether a received command signal is directed to the semiconductor chip.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 2.55357
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14746435', '14330223', '14447531', '14657345', '13747318']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7691133770136147
- 35 USC 102 Novelty (BERT): 0.5121849295751839
- Combined Prediction Score: 0.7434205322697716
- Mean Citation Score: 171.32105800000005
- Max Citation Score: 328.5619
- Similarity Product: 277.6465651894331

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test