PATENT CLAIM ANALYSIS

Application Number: 15950302
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["257", "678000"]

Abstract:
A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.

Claim (Index 19):
The chip packaging method according to  claim 18 , wherein the forming the via holes penetrating the wafer on the second surface of each of the chips to be packaged comprises:\n forming double-stepped holes configured to expose the first contact pads on the second surface of the chip to be packaged, wherein each of the via holes comprises: a groove provided on the second surface of the chip to be packaged, a depth of the groove being less than a thickness of the chip to be packaged, and a through hole located in the groove and penetrating the chip to be packaged, there being a one-to-one correspondence between the through holes and the first contact pads, and the through hole being configured to expose the corresponding first contact pad; forming inverted trapezoid holes configured to expose the first contact pads on the second surface of the chip to be package, wherein an aperture of the via hole gradually increases in a direction from the first surface to the second surface; or forming straight holes configured to expose the first contact pads on the second surface of the chip to be packaged.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.61702
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15765968', '15765802', '15826261', '12905095', '12370537']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9312327546593212
- 35 USC 102 Novelty (BERT): 0.5070674824901664
- Combined Prediction Score: 0.8888162274424056
- Mean Citation Score: 262.426234
- Max Citation Score: 283.7158
- Similarity Product: 216.4908518502236

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test