PATENT CLAIM ANALYSIS

Application Number: 15961010
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["714", "764000"]

Abstract:
In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

Claim (Index 1):
A module comprising:\n a memory array; a primary access port coupled to the memory array; error correction logic coupled to the memory array; a statistics register coupled to the error correction logic; and a secondary access port, coupled to the statistics register, to provide access to the statistics register by an external device.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 91.0
- Lexical Diversity: 2.05882
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15586115', '15354773', '11406669', '14285481', '15846122']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2722897456315458
- 35 USC 102 Novelty (BERT): 0.4531978833871377
- Combined Prediction Score: 0.290380559407105
- Mean Citation Score: 115.334766
- Max Citation Score: 120.45765
- Similarity Product: 89.53684146253468

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test