PATENT CLAIM ANALYSIS

Application Number: 16057648
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["257", "314000"]

Abstract:
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.

Claim (Index 1):
A memory device comprising:\n a first conductive layer extending along a first direction; a second conductive layer being distant from the first conductive layer in a second direction crossing the first direction and extending along the first direction; a first semiconductor member extending in a third direction crossing a plane including the first direction and the second direction, and passing through between the first conductive layer and the second conductive layer; a second semiconductor member extending in the third direction and passing through between the first semiconductor member and the second conductive layer; a first charge storage member provided between the first conductive layer and the first semiconductor member; a first insulating member provided between the first conductive layer and the first charge storage member; a first insulating layer including a first region and a second region, the first region being positioned between the first semiconductor member and the first charge storage member, the second region being positioned between the first semiconductor member and the second semiconductor member; a second charge storage member provided between the second conductive layer and the second semiconductor member; a second insulating member provided between the second conductive layer and the second charge storage member; and a second insulating layer including a third region and a fourth region, the third region being positioned between the second semiconductor member and the second charge storage member, the fourth region being positioned between the second region and the second semiconductor member.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 96.0
- Lexical Diversity: 5.17241
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15917954', '15691931', '15010623', '15696756', '15461590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8958829409900501
- 35 USC 102 Novelty (BERT): 0.5009148125332415
- Combined Prediction Score: 0.8563861281443692
- Mean Citation Score: 206.15958
- Max Citation Score: 289.4813
- Similarity Product: 284.39067373740073

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test