PATENT CLAIM ANALYSIS

Application Number: 15761426
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "211000"]

Abstract:
A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

Claim (Index 34):
The device according to  claim 31 ,\n wherein said second control line comprises a horizontal transistor designed to be used for said electrically programmable connection.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 3.70968
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15333138', '15911071', '15344562', '15224929', '15452615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92213310580904
- 35 USC 102 Novelty (BERT): 0.5211865655188312
- Combined Prediction Score: 0.882038451780019
- Mean Citation Score: 248.33726600000003
- Max Citation Score: 312.55124
- Similarity Product: 204.2135855243588

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test