PATENT CLAIM ANALYSIS

Application Number: 15950912
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["323", "281000"]

Abstract:
The present invention relates to a linear voltage regulator for a low-power digital circuit of a chip, comprising a reference voltage varying with a threshold voltage, a buffer formed by amplifiers, and a compensation capacitor. The reference voltage is used as an input end of the buffer, an output voltage of the buffer, having a current driving capability, is kept consistent with the reference voltage, and the compensation capacitor is configured to decrease the fluctuation range of the output voltage when a current load varies. The reference voltage comprises two gate-source voltages of an MOS operating in a sub-threshold region, and the reference voltage V ref  satisfies the following relation: V ref  ∝ β(|V GS1 |+V GS2 ); the reference voltage V ref  flows through the output buffer formed by the amplifiers to supply a voltage to a digital circuit. By adopting a reference related to the threshold voltage of the MOS, the reference voltage will also vary with the changes in the process conditions and ambient temperature, so that an output of a linear voltage regulator can reflect such changes in the conditions, thereby reducing the operating supply voltage of the digital circuit and greatly reducing the power consumption accordingly.

Claim (Index 1):
A linear voltage regulator for a low-power digital circuit of a chip, comprising:\n a first metal oxide semiconductor (MOS); a second metal oxide semiconductor (MOS); an output buffer formed by at least one amplifier; and a compensation capacitor; wherein the first MOS is a PMOS and the second MOS is an NMOS and an input currency is connected to a source of the first MOS; a reference voltage (V ref ) outputted from the first MOS the second MOS is used as an input positive end of the buffer; an output voltage of the buffer, having a current driving capability, is kept consistent with the reference voltage, and the compensation capacitor is configured to decrease the fluctuation range of the output voltage when a current load varies; a value of the V ref  satisfies the following relation:\n V ref  \u221d \u03b2(| V GS1 |+V GS2 ); \n \n wherein V GS1  is a gate-source voltage of the first MOS operating in the sub-threshold region, and V GS2  is a second gate-source voltage of the MOS operating in the sub-threshold region; the reference voltage (V ref ) flows through the output buffer formed by the at least one amplifier to supply a voltage to a digital circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.22222
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13787181', '12846129', '11348792', '10672540', '13616503']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6974875468723895
- 35 USC 102 Novelty (BERT): 0.4615232698641613
- Combined Prediction Score: 0.6738911191715666
- Mean Citation Score: 129.0029368
- Max Citation Score: 134.6865
- Similarity Product: 97.15791497558357

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test