PATENT CLAIM ANALYSIS

Application Number: 16079355
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "154000"]

Abstract:
A memory device with reduced power consumption is provided. The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.

Claim (Index 3):
The memory device according to  claim 1 ,\n wherein the plurality of memory cells are provided over the precharge circuit.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 96.0
- Lexical Diversity: 2.61905
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15695210', '15447809', '15698138', '15083776', '15272093']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8226044922612664
- 35 USC 102 Novelty (BERT): 0.4986145940406974
- Combined Prediction Score: 0.7902055024392095
- Mean Citation Score: 262.12666
- Max Citation Score: 271.8362
- Similarity Product: 197.29723347392087

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test