PATENT CLAIM ANALYSIS

Application Number: 15894564
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "077000"]

Abstract:
A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.

Claim (Index 1):
A semiconductor device, comprising:\n a first semiconductor chip including a first substrate comprised of a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain; a second semiconductor chip including a second substrate comprised of a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain; and\n a third semiconductor chip including a third substrate comprised of silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain; wherein \n the first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section,\n the third semiconductor chip is mounted over a second chip mounting section which is different from the first chip mounting section, \n \n the first source of the first FET and the third drain of the MOSFET being electrically coupled, \n the second source of the second FET and the third drain of the MOSFET being electrically coupled, \n the first gate electrode of the first FET and the third source of the MOSFET being electrically coupled, and \n the second gate electrode of the second FET and \n the third source of the MOSFET being electrically coupled.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 4.36111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14733776', '14348048', '15017666', '13909293', '15097128']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912792121543426
- 35 USC 102 Novelty (BERT): 0.59950316846107
- Combined Prediction Score: 0.8814632262351904
- Mean Citation Score: 356.74068
- Max Citation Score: 504.80945
- Similarity Product: 477.7655579006404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test