PATENT CLAIM ANALYSIS

Application Number: 16022568
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "185170"]

Abstract:
According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.

Claim (Index 1):
A semiconductor storage device, comprising:\n a plurality of word lines provided above a semiconductor substrate to extend in a first direction and a second direction and separated from each other in a third direction, the first to third directions crossing one another, the word lines including a first array region, a second array region and a third array region arranged in the first direction; a plurality of sense amplifier circuits provided on the semiconductor substrate and under the word lines; a plurality of memory strings intersecting with the word lines and extending in the third direction; a plurality of upper bit lines provided above the word lines to extend in the first direction and separated from each other in the second direction; a plurality of lower bit lines provided below the word lines and above the sense amplifier circuits to extend in the first direction and separated from each other in the second direction, so as to respectively overlap with the upper bit lines when viewed in the third direction; a plurality of first contact plugs provided in a first connection region to extend in the third direction and respectively connect a part of the upper bit lines and a part of the lower bit lines, the first connection region being provided between the first array region and the second array region of the word lines in the first direction; and a plurality of second contact plugs provided in a second connection region to extend in the third direction and respectively connect another part of the upper bit lines and another part of the lower bit lines, the second connection region being provided between the second array region and the third array region of the word lines in the third direction.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.74074
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14788629', '15583609', '13784735', '15905827', '15919480']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8436381511765167
- 35 USC 102 Novelty (BERT): 0.5438040040361543
- Combined Prediction Score: 0.8136547364624805
- Mean Citation Score: 298.93750200000005
- Max Citation Score: 358.5903
- Similarity Product: 320.88376611213687

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test