PATENT CLAIM ANALYSIS

Application Number: 16125117
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["714", "777000"]

Abstract:
In some examples, a memory device may be configured to provide quad bit error correction circuits. For example, the memory device may be equipped with a two layer error correction circuit. In some cases, the first layer may utilized one or more Hamming coders and the second layer may utilize one or Golay coders. In some examples, the Golay coders may be grouped into sets of Golay coders.

Claim (Index 6):
The memory device as recited in  claim 1 , wherein no more than three Golay code bits generated by a Golay coder of the sets of Golay coders are stored in a bit column of the one or more memory arrays.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 97.0
- Lexical Diversity: 1.80952
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14923565', '09821758', '11384965', '10738264', '13281007']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3117958276479942
- 35 USC 102 Novelty (BERT): 0.5428531833850841
- Combined Prediction Score: 0.3349015632217032
- Mean Citation Score: 203.84722
- Max Citation Score: 396.2293
- Similarity Product: 393.2850970133305

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test