PATENT CLAIM ANALYSIS

Application Number: 16247494
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["327", "291000"]

Abstract:
A delay locked-loop includes, in part, a phase/frequency detector responsive to a reference clock signal, a charge pump responsive to the phase/frequency detector, a variable delay line responsive to an output of the charge pump to cause a delay in the reference clock signal thereby to generate an internal clock signal, and a controlled delay line that includes a multitude of fixed delay cells. The controlled delay line causes the internal clock signal to be delayed by a delay across one of the multitude of fixed delay cells in response to the output of the charge pump. The controlled delay line generates the output clock signal of the delay-locked loop. The delay locked-loop may further include an overflow detector configured to cause the selection of one of the multitude of fixed delays in response to the output of the charge pump.

Claim (Index 10):
The retiming circuit of  claim 9  wherein the up/down counter generates a select signal applied to a select input terminal of a multiplexer receiving the plurality of fixed delays of the controlled delay line.

Metadata:
- Claim Count in Document: 60.0
- Percentile: 99.0
- Lexical Diversity: 2.88462
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12392495', '11999162', '09879416', '11187992', '14558072']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7944771032306928
- 35 USC 102 Novelty (BERT): 0.4774332935510008
- Combined Prediction Score: 0.7627727222627235
- Mean Citation Score: 217.535052
- Max Citation Score: 222.72394
- Similarity Product: 182.05494205954312

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test