PATENT CLAIM ANALYSIS

Application Number: 16029604
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Claim (Index 1):
A method for precharging a dynamic decode circuit, the dynamic decode circuit comprising a decoder connected to a first node and an evaluate circuit, the evaluate circuit comprising a first transistor serially connected to a second transistor by way of an interconnecting node, the evaluate circuit connected between a second node and a first power source, the dynamic decode circuit performing a method, the method comprising:\n receiving input signals, by a plurality of inputs of the decoder; based on the plurality of inputs of the decoder being in a predetermined input state and based on being in an evaluation phase, causing, by the decoder, the first node to be low; receiving an evaluation clock signal by a first gate of the first transistor of the evaluate circuit; receiving the first node by a second gate of the second transistor of the evaluate circuit; based on the first node being low and based on being in the evaluation phase, causing, by the evaluate circuit, the second node to be high; precharging the first node to a high state, by a first precharge circuit comprising a first precharge transistor, based on not being in the evaluation phase of the evaluation clock signal; precharging the second node to the high state, by a second precharge circuit comprising a second precharge transistor, based on not being in the evaluation phase of the evaluation clock signal; and precharging the interconnecting node of the evaluate circuit to the high state, by a third precharge circuit comprising a third precharge transistor, based on not being in the evaluation phase of the evaluation clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.10638
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16029603', '16029577', '15796819', '16029607', '15613185']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7651399431779975
- 35 USC 102 Novelty (BERT): 0.5703671295672467
- Combined Prediction Score: 0.7456626618169224
- Mean Citation Score: 469.003724
- Max Citation Score: 498.23557
- Similarity Product: 428.2226581369168

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test