PATENT CLAIM ANALYSIS

Application Number: 16184993
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

Claim (Index 10):
A semiconductor device comprising:\n a first chip having a first via and a second via through the first chip; a second chip provided on the first chip and having a third via and a fourth via through the second chip; and a third chip provided on the second chip, wherein: the first chip includes:\n a first logical operation circuit configured to perform a first logical operation on a first address input signal to output a first address output signal to the second chip; \n a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation on a second address input signal and the first address output signal to output a second address output signal to the second chip; and \n a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal; and \n the second chip includes:\n a third logical operation circuit configured to perform a third logical operation on the first address output signal to output a third address output signal to the third chip; a fourth logical operation circuit connected to the third logical operation circuit, the fourth logical operation circuit being configured to perform a fourth logical operation on the second address output signal and the third address output signal to output a fourth address output signal to the third chip; and \n a second activation circuit connected to the fourth logical operation circuit, the second activation circuit being configured to activate the second chip based on at least the fourth address output signal.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 3.16327
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15819468', '15232391', '13843165', '14552177', '13371931']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9226642740372344
- 35 USC 102 Novelty (BERT): 0.492767902677341
- Combined Prediction Score: 0.8796746369012451
- Mean Citation Score: 263.479202
- Max Citation Score: 287.80817
- Similarity Product: 279.1664022193176

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test