PATENT CLAIM ANALYSIS

Application Number: 15860778
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["365", "189090"]

Abstract:
Provided is an input buffer circuit comprising a high-voltage protection unit coupled to a pad and comprising a low-voltage pass unit and a high-voltage pass unit that are coupled in common to an output signal node. The low-voltage pass unit may transfer the first voltage to the output signal node, when a first voltage falling within a first voltage range is applied through the pad. The high-voltage pass unit may transfer a third voltage lower than the second voltage to the output signal node, when a second voltage falling within a second voltage range higher than the first voltage range is applied through the pad.

Claim (Index 12):
The memory system according to  claim 11 , wherein\n each of the high-voltage protection unit and the well voltage generation unit comprises a plurality of transistors, and a drain-source voltage difference, a gate-drain voltage difference, and a gate-source voltage difference of each of the plurality of transistors do not exceed Li times the input stage supply voltage, when the voltage of the input signal is the first voltage.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.55814
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15858516', '13799866', '14031296', '10825646', '12184271']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8044758876847917
- 35 USC 102 Novelty (BERT): 0.4819347757530774
- Combined Prediction Score: 0.7722217764916204
- Mean Citation Score: 186.244856
- Max Citation Score: 205.264
- Similarity Product: 146.69483662033082

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test