PATENT CLAIM ANALYSIS

Application Number: 15777582
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "091000"]

Abstract:
A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip welding wire region and an external electrode region connected with each other. The chip welding wire region is composed of multiple conductive lines, wherein the central conductive line located in the central position of the chip welding wire region is a straight line section. The conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, so that the entire chip welding wire region forms a circular area. The array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides. The entire chip welding wire region can also form a rectangular area.

Claim (Index 7):
A method for manufacturing a high-density integrated COB white light source, characterized in that, the manufacturing method comprises the steps of: manufacturing a die-bonding substrate, manufacturing height-limiting retainers, electrically connecting welding wires, manufacturing a reflective dam body, pre-curing a filled colloid, and encapsulating a solid-state phosphor;\n manufacturing a die-bonding substrate comprising: 11) designing the configuration of the conductive line layer and the array chips; the conductive line layer including a chip welding wire region and an external electrode region, which are electrically connected with each other; the chip welding wire region being composed of multiple conductive lines; wherein the central conductive line located in the central position of the chip welding wire region is a straight line section, and is the longest line section; the conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, the farther a conductive line lies away from the central conductive line, the shorter its straight line section is, and the longer its arc section is, so that the entire chip welding wire region forms a circular area, which is equally divided into four sector areas, two symmetrically distributed areas of arc sections and two symmetrically distributed areas of straight line sections; or wherein the conductive lines are straight line sections arranged parallel to one another, so that the entire chip welding wire region forms a rectangular area; 12) fabricating the conductive line layer on a heat-sink substrate by a printing process, and at the same time, covering the regions except the conductive line layer with an electrically insulating layer; 13) fixing the array chips in the circular or rectangular area by a die-bonding process, so as to form a die-bonding substrate; manufacturing height-limiting retainers is to manufacture height-limiting retainers at the periphery of the die-bonding region; electrically connecting welding wires is to electrically connect the LED chips in the array chips to the corresponding conductive lines in the conductive line layer by means of a reverse looping and wire bonding process and a gold wire welding process; manufacturing a reflective dam body is to manufacture a reflective dam body at the periphery of the height-limiting retainers; pre-curing a filled colloid is to fill a space enclosed by the reflective dam body with transparent colloid until the height-limiting retainers are submerged, to discharge gases and perform pre-curing after leveling of the colloid; encapsulating a solid-state phosphor is to place the solid-state phosphor on the height-limiting retainers inside the reflective dam body, to maintain a light-pressure state and perform a subsequent deep thermal curing.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.39062
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15782007', '13312237', '15399769', '15927458', '14561946']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912213431903068
- 35 USC 102 Novelty (BERT): 0.4993350153904018
- Combined Prediction Score: 0.8709255902518014
- Mean Citation Score: 201.738766
- Max Citation Score: 237.97736
- Similarity Product: 163.21760082485196

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test