PATENT CLAIM ANALYSIS

Application Number: 16049424
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-09
Patent Classification: ["365", "230030"]

Abstract:
A semiconductor device includes a bank group selection signal generation circuit and a bank group address generation circuit. The bank group selection signal generation circuit stores a bank address based on a command pulse generated to perform a read operation or a write operation. The bank group selection signal generation circuit outputs the stored bank address as a bank group selection signal. The bank group address generation circuit generates a bank group address and an internal bank group address for performing a column operation of a cell array included in a bank group selected based on the bank group selection signal.

Claim (Index 24):
The semiconductor device of  claim 23 ,\n wherein the mode signal is enabled in a bank group mode for a column operation of one bank being performed by one command; and wherein the internal flag is generated if the mode signal is enabled.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 95.0
- Lexical Diversity: 2.44186
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15467360', '15193457', '15687681', '15057843', '14515821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8239949363140648
- 35 USC 102 Novelty (BERT): 0.4968585521004133
- Combined Prediction Score: 0.7912812978926997
- Mean Citation Score: 251.869386
- Max Citation Score: 270.0303
- Similarity Product: 201.1289088895261

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test