PATENT CLAIM ANALYSIS

Application Number: 16125117
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["714", "777000"]

Abstract:
In some examples, a memory device may be configured to provide quad bit error correction circuits. For example, the memory device may be equipped with a two layer error correction circuit. In some cases, the first layer may utilized one or more Hamming coders and the second layer may utilize one or Golay coders. In some examples, the Golay coders may be grouped into sets of Golay coders.

Claim (Index 14):
A error correction circuit comprising:\n a first layer, the first layer including one or more Hamming coders, individual ones of the Hamming coders configured to process data to generate a Hamming code, the Hamming code including the data and Hamming code bits; and a second layer, the second layer including, one or more sets of Golay coders, individual sets of the Golay coders configured to process a portion of the data to generate a corresponding Golay code, the Golay code including the portion of the data and Golay code bits.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 97.0
- Lexical Diversity: 1.80952
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14923565', '09821758', '11384965', '10738264', '13281007']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2889730239550478
- 35 USC 102 Novelty (BERT): 0.5375580745424312
- Combined Prediction Score: 0.3138315290137862
- Mean Citation Score: 203.84722
- Max Citation Score: 396.2293
- Similarity Product: 329.7003356013417

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test