PATENT CLAIM ANALYSIS

Application Number: 15982766
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "503000"]

Abstract:
Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

Claim (Index 9):
The semiconductor integrated circuit device of  claim 6 , wherein the first common power supply interconnect is connected to at least two of the plurality of external connection pads, where the at least two of the plurality of external connection pads include the first pad.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 1.90625
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15493338', '15493321', '12268904', '14243523', '12872678']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9138028694144872
- 35 USC 102 Novelty (BERT): 0.5313641832516544
- Combined Prediction Score: 0.8755590007982039
- Mean Citation Score: 256.64721799999995
- Max Citation Score: 340.84595
- Similarity Product: 280.75158244385125

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test