PATENT CLAIM ANALYSIS

Application Number: 16109645
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["327", "306000"]

Abstract:
A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Claim (Index 2):
The decimated phase detector circuit of  claim 1 , wherein the UP rolling counter is configured to incrementing an UP state each time an UP is provided by the UP output of the BBFD and the DOWN rolling counter is configured to incrementing a DOWN state each time a DOWN is provided by the DOWN output of the BBFD.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.61905
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14362563', '14982910', '12999596', '15256444', '11861505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7457069312128531
- 35 USC 102 Novelty (BERT): 0.5010778873272248
- Combined Prediction Score: 0.7212440268242903
- Mean Citation Score: 192.442444
- Max Citation Score: 199.42598
- Similarity Product: 126.4800766034639

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test