PATENT CLAIM ANALYSIS

Application Number: 16117115
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["711", "141000"]

Abstract:
An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information.

Claim (Index 13):
The method as claimed in  claim 12 , further comprising:\n when the number of the sections of write data collected in the cache area exceeds a predefined amount, notifying the host to issue a programming command; and according to the programming command, programming the sections of write data collected in the cache area to the non-volatile memory.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 96.0
- Lexical Diversity: 1.92453
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15615368', '15652259', '16051950', '15265317', '10247859']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.498261262353735
- 35 USC 102 Novelty (BERT): 0.4936719852551535
- Combined Prediction Score: 0.4978023346438769
- Mean Citation Score: 168.75011
- Max Citation Score: 169.51549
- Similarity Product: 100.94697819722772

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test