PATENT CLAIM ANALYSIS

Application Number: 16075120
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["257", "707000"]

Abstract:
In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

Claim (Index 3):
The apparatus of  claim 2 :\n wherein the apparatus embodies a three-dimensional (3D) semiconductor package having the electrically powered functional silicon die buried internal to the 3D semiconductor package; wherein the electrically powered functional silicon die generates heat which creates a hotspot within an interior core of the 3D semiconductor package; and wherein the 3D semiconductor package dissipates the heat from the hotspot from the interior core of the 3D semiconductor package through the first thermal pad integrated upon the first layer functional silicon die and through the solder bonding the first thermal pad to the second thermal pad integrated upon the second layer functional silicon die and through the second thermal pad into the second layer functional silicon die positioned above the first layer functional silicon die and out a topmost surface of the 3D semiconductor package.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 96.0
- Lexical Diversity: 2.92308
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16075513', '15283055', '15475879', '14588715', '15475902']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9247858967342256
- 35 USC 102 Novelty (BERT): 0.4990471741587549
- Combined Prediction Score: 0.8822120244766786
- Mean Citation Score: 221.117068
- Max Citation Score: 258.28192
- Similarity Product: 199.1220971437836

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test