PATENT CLAIM ANALYSIS

Application Number: 15879576
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "098000"]

Abstract:
A package body for a semiconductor device includes a lead frame, an insulating package, and a reflective coating layer. The lead frame has a first electrode and a second electrode separated from each other. The insulating package provides a housing structure and forming a package cavity therein. The package cavity has a reflective side surface formed by the insulating package. The reflective coating layer partially covers the first electrode and the second electrode and forms a reflective bottom surface of the package cavity. Each of the first electrode and the second electrode may have an angled cut. The insulating package may be made of a binder-filler composite containing white pigments. The package body may be an all diffusive integrated reflecting surfaces (AR-IRS) package body, and may be used in an encapsulant-free semiconductor package.

Claim (Index 1):
A package body for a semiconductor device, comprising:\n a lead frame having a first electrode and a second electrode separated from each other; an insulating package providing a housing structure and forming a package cavity therein, wherein the package cavity has a reflective side surface formed by the insulating package; and a reflective coating layer partially covering the first electrode and the second electrode and forming a reflective bottom surface of the package cavity, wherein at least one semiconductor chip is configured to be attached to the first electrode and electrically connected to the first electrode and the second electrode respectively; and wherein the reflective coating layer has a first recess, a second recess and at least one chip recess formed thereon, wherein: a portion of the lead frame is exposed through each of the at least one chip recess to provide a chip-attaching area, such that the at least one semiconductor chip is attached to the lead frame via the at least one chip recess; a portion of the first electrode is exposed through the first recess to provide a wire-bonding area, such that each of the at least one semiconductor chip is electrically connected to the first electrode through a first wire via the first recess; and a portion of the second electrode is exposed through the second recess to provide a wire-bonding area, such that each of the at least one semiconductor chip is electrically connected to the second electrode through a second wire via the second recess.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 86.0
- Lexical Diversity: 2.21212
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15654478', '15179952', '14434551', '13466881', '13524737']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9161278479933432
- 35 USC 102 Novelty (BERT): 0.4773862845018931
- Combined Prediction Score: 0.8722536916441983
- Mean Citation Score: 204.99666399999995
- Max Citation Score: 213.90176
- Similarity Product: 173.5065049510574

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test