PATENT CLAIM ANALYSIS

Application Number: 15899986
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "395000"]

Abstract:
Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

Claim (Index 12):
The structure of  claim 9  wherein the dielectric pillar includes an upper section that is arranged in the cut over the first sidewall spacer and the second sidewall spacer and a lower section that is arranged in the cut horizontally between the first sidewall spacer and the second sidewall spacer.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 2.56604
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15800563', '15612335', '15867036', '15376831', '15658835']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926884933105504
- 35 USC 102 Novelty (BERT): 0.4945719192012126
- Combined Prediction Score: 0.8836536317150747
- Mean Citation Score: 233.36476800000003
- Max Citation Score: 252.09395
- Similarity Product: 200.42435615620013

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test