PATENT CLAIM ANALYSIS

Application Number: 16119676
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "369000"]

Abstract:
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

Claim (Index 24):
The semiconductor chip as recited in  claim 19 , wherein the at least four transistors of the first transistor type include a first transistor of the first transistor type, wherein the at least four transistors of the second transistor type include a first transistor of the second transistor type, wherein a gate electrode feature that forms a gate electrode of the first transistor of the first transistor type and a gate electrode feature that forms a gate electrode of the first transistor of the second transistor type are formed to extend lengthwise along a same gate gridline, wherein no other transistor is positioned on the same gate gridline between the gate electrode features that form the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type,\n wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein a diffusion region of the first transistor of the first transistor type is electrically connected to a diffusion region of the first transistor of the second transistor type, wherein the at least six contact structures include a contact structure substantially centered in the x-direction on the same gate gridline at a location between the diffusion regions of the first transistor of the first transistor type and the first transistor of the second transistor type, wherein an electrical connection between the diffusion region of the first transistor of the first transistor type and the diffusion region of the first transistor of the second transistor type includes at least one first-metal structure and at least one second-metal structure, wherein the at least four transistors of the first transistor type and the at least four transistors of the second transistor type within the region collectively form part of an inverting two-to-one multiplexer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.93478
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16119727', '16119794', '15688187', '15696728', '15696651']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.94244831055597
- 35 USC 102 Novelty (BERT): 0.5830862698391153
- Combined Prediction Score: 0.9065121064842844
- Mean Citation Score: 451.083808
- Max Citation Score: 471.4597
- Similarity Product: 446.46827381708033

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test