PATENT CLAIM ANALYSIS

Application Number: 16226875
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

Claim (Index 18):
The method of  claim 17 , wherein the gate structure comprises a second metal layer, wherein the first metal layer completely separates the second metal layer from the first insulating structure, the second insulating structure, the third insulating structure, and the fourth insulating structure.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 98.0
- Lexical Diversity: 2.85714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15786427', '15715100', '14925680', '15597244', '15089380']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9048371874744964
- 35 USC 102 Novelty (BERT): 0.495093614884974
- Combined Prediction Score: 0.8638628302155441
- Mean Citation Score: 180.8105
- Max Citation Score: 194.82748
- Similarity Product: 137.21512187477109

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test