PATENT CLAIM ANALYSIS

Application Number: 15905020
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "185180"]

Abstract:
According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.

Claim (Index 13):
The semiconductor memory device according to  claim 1 , further comprising:\n a package including a first semiconductor chip and a second semiconductor chip, wherein the nonvolatile memory and the read circuit are disposed in the first semiconductor chip, and wherein the operation circuit and the controller circuit are disposed in the second semiconductor chip.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 88.0
- Lexical Diversity: 3.12821
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14015980', '10409120', '11531082', '13152692', '12040155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7754166779444616
- 35 USC 102 Novelty (BERT): 0.4487462104694519
- Combined Prediction Score: 0.7427496311969606
- Mean Citation Score: 136.933304
- Max Citation Score: 139.8387
- Similarity Product: 110.10766812281013

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test