PATENT CLAIM ANALYSIS

Application Number: 15941381
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["370", "412000"]

Abstract:
Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

Claim (Index 16):
A system comprising:\n a memory; one or more network interface ports coupled with the memory to store incoming packets in the memory; search acceleration logic circuitry coupled with the memory to compare a first incoming packet to a first digest in a first entry of a primary array to determine whether the first incoming packet matches the first digest; when the first incoming packet matches the first digest, the search acceleration logic circuitry to retrieve a first full entry from a secondary array, the first full entry to correspond to the first entry, and to compare the first full entry with the first incoming packet; when the first full entry matches the first incoming packet, the search acceleration logic circuitry to store at least a portion of the first incoming packet at a first memory location, wherein entries in the secondary array comprise at least data and a memory location at which to store at least a portion of one of the incoming packets; and in the absence of a match between the first incoming packet and the first digest or between the first incoming packet and the first full entry, the logic circuitry to compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 90.0
- Lexical Diversity: 3.30435
- Patent Class: 370.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14611105', '09528434', '10965260', '14320448', '15795662']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4945320360152691
- 35 USC 102 Novelty (BERT): 0.476194878183889
- Combined Prediction Score: 0.4926983202321311
- Mean Citation Score: 153.27721599999995
- Max Citation Score: 160.36383
- Similarity Product: 111.09744963294624

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test