PATENT CLAIM ANALYSIS

Application Number: 15981408
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "774000"]

Abstract:
A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

Claim (Index 13):
The integrated circuit of  claim 8 , wherein the first conductive pattern contacts the second conductive pattern.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 93.0
- Lexical Diversity: 2.2549
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15420514', '15865941', '15689008', '15846498', '15343712']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919586415746105
- 35 USC 102 Novelty (BERT): 0.5275800860841704
- Combined Prediction Score: 0.8803857827799115
- Mean Citation Score: 214.781214
- Max Citation Score: 346.34384
- Similarity Product: 278.9076175156307

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test