PATENT CLAIM ANALYSIS

Application Number: 16042910
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["712", "222000"]

Abstract:
The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

Claim (Index 23):
The system of  claim 22 , wherein the first portion of the first mantissa comprises most significant bits of the first mantissa, and the first portion of the second mantissa comprises most significant bits of the second mantissa.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.26923
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15367205', '15367208', '16039029', '15242923', '15270153']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.725849766642159
- 35 USC 102 Novelty (BERT): 0.563140021660276
- Combined Prediction Score: 0.7095787921439707
- Mean Citation Score: 498.582776
- Max Citation Score: 607.45935
- Similarity Product: 329.8291628791898

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test