PATENT CLAIM ANALYSIS

Application Number: 15918077
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "329000"]

Abstract:
Embodiments of the invention are directed to a method and resulting structures for a complementary metal oxide semiconductor (CMOS) having source and drain contacts formed using trench solid and liquid phase epitaxy (SPE/LPE). In a non-limiting embodiment of the invention, an NFET is formed on a substrate. The NFET includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region of the substrate. A PFET is also formed on the substrate. The PFET includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region of the substrate. A first gate is formed over a channel region of the p-type semiconductor fin and a second gate is formed over a channel region of the n-type semiconductor fin. The first gate and the second gate include a common dipole layer. The NFET and PFET each include a linear threshold voltage of about 150 mV to about 250 mV and a difference between the linear threshold voltages of the NFET and PFET is less than about 50 mV.

Claim (Index 1):
A method for forming a semiconductor device, the method comprising:\n forming an n-type field effect transistor (NFET) on a substrate, the NFET comprising a p-type semiconductor fin vertically extending from an n-type bottom source or drain region disposed on the substrate; forming a p-type field effect transistor (PFET) on the substrate, the PFET comprising an n-type semiconductor fin vertically extending from a p-type bottom source or drain region disposed on the substrate; forming the NFET comprises forming a first gate around a channel region of the p-type semiconductor fin; and forming the PFET comprises forming a second gate around a channel region of the n-type semiconductor fin; wherein the first gate and the second gate each comprises a dipole layer; wherein the NFET and PFET each comprise a threshold voltage of about 150 mV to about 250 mV; wherein a difference between the threshold voltages of the NFET and PFET is less than about 50 mV: forming a top spacer on the first gate and adjacent to sidewalls of the p-type semiconductor fin.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.35443
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15804215', '15914096', '15466358', '15455659', '15499084']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281775623793296
- 35 USC 102 Novelty (BERT): 0.5152126642409421
- Combined Prediction Score: 0.886881072565491
- Mean Citation Score: 310.95691
- Max Citation Score: 321.76633
- Similarity Product: 255.5377487414694

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test