PATENT CLAIM ANALYSIS

Application Number: 15913068
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "194000"]

Abstract:
A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. The second type III-V semiconductor layer has a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. The second type III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.

Claim (Index 13):
The method of  claim 12 , wherein the first thickness is between 20 and 50 nanometers, and wherein the second thickness is less than about 20 nanometers.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.66667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15913284', '15361610', '15629783', '15704134', '14478287']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9216566274300156
- 35 USC 102 Novelty (BERT): 0.5439808470329395
- Combined Prediction Score: 0.883889049390308
- Mean Citation Score: 307.4716620000001
- Max Citation Score: 393.22595
- Similarity Product: 184.6540395843596

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test