PATENT CLAIM ANALYSIS

Application Number: 16011490
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["323", "271000"]

Abstract:
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

Claim (Index 1):
A circuital arrangement configured to control a high side (HS) device and a low side (LS) device arranged in a stacked configuration, the HS device and the LS device capable of withstanding a voltage higher than or equal to a first voltage, the circuital arrangement comprising:\n a HS control circuit operating between a first selected switching voltage and a second selected switching voltage based on the first selected switching voltage, the first selected switching voltage being an output voltage at a common output node of the stacked HS device and LS device, the HS control circuit configured to provide a HS output control signal at a voltage higher than the first voltage to the HS device; a LS control circuit configured to provide a LS output control signal to the LS device; and a dead time control circuit configured, to generate timing information for the HS output control signal and the LS output control signal, wherein all transistor devices of the HS control circuit, the LS control circuit and the dead time controller circuit, are each configured to withstand a second voltage substantially smaller than the first voltage.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 94.0
- Lexical Diversity: 1.91358
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14992989', '15842753', '15286097', '14661848', '16011362']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7873052237756716
- 35 USC 102 Novelty (BERT): 0.612924462834745
- Combined Prediction Score: 0.7698671476815789
- Mean Citation Score: 465.152544
- Max Citation Score: 542.8671
- Similarity Product: 539.0844227911413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test