PATENT CLAIM ANALYSIS

Application Number: 16000563
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "330000"]

Abstract:
A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.

Claim (Index 11):
A method for manufacturing a semiconductor device, comprising:\n forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer comprising a first concentration of germanium on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer, wherein the first and third semiconductor layers each comprise a concentration of germanium which is greater than the first concentration of germanium; patterning the first, second and third semiconductor layers into at least one fin; covering the second semiconductor layer with a mask layer; simultaneously growing a bottom source/drain region from the first semiconductor layer and a top source/drain region from the third semiconductor layer; removing the mask layer from the second semiconductor layer; forming a gate structure on and around the second semiconductor layer; forming a germanium oxide layer on the top and bottom source/drain regions and on the second semiconductor layer; and performing an annealing process to convert the germanium oxide layer formed on the top and bottom source/drain regions into top and bottom oxide spacer layers.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 2.75
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15954843', '15935468', '15916525', '15156923', '15854229']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927983292815192
- 35 USC 102 Novelty (BERT): 0.5477208565487212
- Combined Prediction Score: 0.8899570491885448
- Mean Citation Score: 333.56069
- Max Citation Score: 409.8191
- Similarity Product: 359.1777191538453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test