PATENT CLAIM ANALYSIS

Application Number: 15899556
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["327", "156000"]

Abstract:
A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.

Claim (Index 15):
The integrated circuit according to  claim 10 , wherein\n the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the detected edge number becomes equal to or less than a threshold value.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 88.0
- Lexical Diversity: 3.14286
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11218528', '10278800', '14854961', '12071371', '14032738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7854092292002721
- 35 USC 102 Novelty (BERT): 0.4754046871118532
- Combined Prediction Score: 0.7544087749914302
- Mean Citation Score: 181.420948
- Max Citation Score: 187.92738
- Similarity Product: 140.1410096162224

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test