PATENT CLAIM ANALYSIS

Application Number: 16038052
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-04
Patent Classification: ["257", "296000"]

Abstract:
Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Claim (Index 18):
The semiconductor memory device of  claim 17 ,\n wherein the semiconductor pattern comprises a first impurity region, a second impurity region, and a channel region that is between the first impurity region and the second impurity region, wherein the second conductive line is connected to the first impurity region, and wherein the electrode is connected to the second impurity region.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.75
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15708266', '15259941', '14735811', '15245218', '13366818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9147162043282472
- 35 USC 102 Novelty (BERT): 0.5022022793262115
- Combined Prediction Score: 0.8734648118280437
- Mean Citation Score: 236.367428
- Max Citation Score: 247.97386
- Similarity Product: 191.55161319087148

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test