PATENT CLAIM ANALYSIS

Application Number: 16053356
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "300000"]

Abstract:
An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

Claim (Index 1):
A method of forming an electronic device comprising:\n providing a substrate structure including a strain relaxed buffer region in a relaxed region; forming a tensile strained semiconductor material layer on a first portion of the relaxed region; forming a compressive strained semiconductor material layer on a second portion of the relaxed region; forming a first semiconductor device on the tensile strained semiconductor material layer and a second semiconductor device on the compressive strained semiconductor material layer; and forming a trench capacitor in a third portion of the relaxed region at a depth within the strain relaxed buffer region, wherein a width of the trench capacitor alternates between at least two width dimensions, the trench capacitor including a node dielectric on sidewalls of a trench containing said trench capacitor, wherein the node dielectrically extends vertically along a sidewall of an interlevel dielectric to provide that an upper surface of the node dielectric is coplanar with an upper surface of gate structures for said first semiconductor device and said second semiconductor device.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.51786
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15298733', '15003196', '14323126', '14857182', '15146257']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9358587227781086
- 35 USC 102 Novelty (BERT): 0.557015361297551
- Combined Prediction Score: 0.8979743866300529
- Mean Citation Score: 364.294704
- Max Citation Score: 437.00452
- Similarity Product: 374.90045751047614

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test