PATENT CLAIM ANALYSIS

Application Number: 15868348
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["345", "690000"]

Abstract:
A display device a includes: a display portion including pixels arranged in a matrix form; gate lines extending in a row direction for each pixel row and connected to the pixels; and a gate driver which applies a gate signal of a gate-on voltage to the plurality of gate lines. The gate driver applies the gate signal in the order of a k-th gate line, a (k+3)-th gate line, a (k+1)-th gate line, a (k+4)-th gate line, a (k+2)-th gate line, and a (k+5)-th gate line, where k is an integer greater than 1, and pixels connected to the k-th gate line and the (k+3)-th gate line display a first color, pixels connected to the (k+1)-th gate line and the (k+4)-th gate line display a second color, and pixels connected to the (k+2)-th gate line and the (k+5)-th gate line display a third color.

Claim (Index 9):
A display device comprising:\n a plurality of gate lines connected to a plurality of pixels; and a gate driver which applies a plurality of gate signals to the plurality of gate lines by being synchronized by a plurality of clock signals, wherein the gate driver comprises:\n a first gate driving block which outputs a first gate signal to a first gate line by being synchronized with a first clock signal; \n a second gate driving block which outputs a second gate signal to a second gate line, which is adjacent to the first gate line, by being synchronized with a second clock signal; \n a third gate driving block which outputs a third gate signal to a third gate line, which is adjacent to the second gate line, by being synchronized with a third clock signal; \n a fourth gate driving block which outputs a fourth gate signal to a fourth gate line, which is adjacent to the third gate line, by being synchronized with a fourth clock signal; \n a fifth gate driving block which outputs a fifth gate signal to a fifth gate line, which is adjacent to the fourth gate line, by being synchronized with a fifth clock signal; and \n a sixth gate driving block which outputs a sixth gate signal to a sixth gate line, which is adjacent to the fifth gate line, by being synchronized with a sixth clock signal, and \n wherein the plurality of clock signals having a gate-on voltage is applied to the gate driver in the order of the first clock signal, the fourth clock signal, the second clock signal, the fifth clock signal, the third clock signal and the sixth clock signal.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 86.0
- Lexical Diversity: 3.13333
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15839361', '14587788', '13357780', '15806555', '14822735']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6715371713904998
- 35 USC 102 Novelty (BERT): 0.4973697934876266
- Combined Prediction Score: 0.6541204336002125
- Mean Citation Score: 262.27880600000003
- Max Citation Score: 279.0515
- Similarity Product: 232.99217875218392

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test