PATENT CLAIM ANALYSIS

Application Number: 15936652
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["365", "228000"]

Abstract:
Provided herein may be a memory system and a method of operating the same. The memory system may include a controller configured to generate and output a first command for a program operation in response to a request from a host, and generate and output a second command for a read scan operation when the memory system is powered on after an abnormal power-off is detected; and a semiconductor memory device configured to perform the program operation on a page basis in response to the first command, perform the read scan operation in response to the second command, and perform a single read operation per page using a set read voltage during the read scan operation.

Claim (Index 8):
The memory system according to  claim 7 ,\n wherein the peripheral circuit successively performs a read operation, on the page basis, on the pages included in the selected memory block during the read scan operation, and wherein the read operation on the page basis is performed using a median voltage of program states distributed in a middle of the first to n-th program states as the set read voltage.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 90.0
- Lexical Diversity: 2.17857
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14163762', '15408911', '15378397', '15407027', '15250826']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8120771923649203
- 35 USC 102 Novelty (BERT): 0.4909189936533205
- Combined Prediction Score: 0.7799613724937603
- Mean Citation Score: 214.07735
- Max Citation Score: 245.26814
- Similarity Product: 180.1672965538525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test