PATENT CLAIM ANALYSIS

Application Number: 15905827
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["365", "072000"]

Abstract:
A semiconductor storage device includes a hookup circuit including first and second circuits connected respectively to first and second bit lines, a first circuit group including a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit, a second circuit group including a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit, and a memory cell array that is above the hookup circuit and the first and second circuit groups and includes a first memory cell connected to the first bit line and a second memory cell connected to the second bit line. The first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate.

Claim (Index 13):
A semiconductor storage device comprising:\n a hookup circuit that is above a semiconductor substrate and includes first, second, third, and fourth circuits connected respectively to first, second, third, and fourth bit lines; a first circuit group that includes a first sense amplifier circuit connected to the first circuit, a first data register connected to the first sense amplifier circuit via a first data bus, a second sense amplifier circuit connected to the second circuit, and a second data register connected to the second sense amplifier circuit via a second data bus; a second circuit group that includes a third sense amplifier circuit connected to the third circuit, a third data register connected to the third sense amplifier circuit via a third data bus, a fourth sense amplifier circuit connected to the fourth circuit, and a fourth data register connected to the fourth sense amplifier circuit via a fourth data bus; and a memory cell array that is above the hookup circuit and the first and second circuit groups and includes first, second, third, and fourth memory cells connected respectively to the first, second, third, and fourth bit lines, wherein the first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 3.4
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14013833', '15411225', '14846381', '15405098', '14630505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8116736310793858
- 35 USC 102 Novelty (BERT): 0.4859800440583092
- Combined Prediction Score: 0.7791042723772782
- Mean Citation Score: 264.684034
- Max Citation Score: 271.63287
- Similarity Product: 233.10365932970169

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test