PATENT CLAIM ANALYSIS

Application Number: 16221272
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "077000"]

Abstract:
A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n +  source region and a p-type base region and reaches an n −  drift region. Between adjacent gate trenches, a first p +  region that goes through the p-type base region in the depth direction and reaches the n −  drift region is formed at a position separated from the gate trenches. The first p +  region is formed directly beneath a p ++  contact region. The width of the first p +  region is less than the width w1 of the gate trench. A second p +  region is formed at the bottom of the gate trench. The first and second p +  regions are silicon carbide epitaxial layers.

Claim (Index 1):
A semiconductor device, comprising:\n a semiconductor substrate made of a semiconductor having a wider bandgap than silicon; a first semiconductor layer of a first conductivity type formed on a front surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer on a side opposite to the semiconductor substrate; a first semiconductor region of the first conductivity type selectively formed within the second semiconductor layer; a trench that goes through the first semiconductor region and the second semiconductor layer in a depth direction and reaches the first semiconductor layer; a gate electrode formed within the trench with a gate insulating film interposed between the gate electrode and an inner surface of the trench; a second semiconductor region of the second conductivity type that is formed separated and laterally isolated from the trench, penetrates through and across the second semiconductor layer in the depth direction and reaches the first semiconductor layer so that a bottom of the second semiconductor region is embedded in the first semiconductor layer, the second semiconductor region having a greater impurity concentration than the second semiconductor layer; a third semiconductor region of the second conductivity type that is formed within the first semiconductor layer separated from the second semiconductor layer and the second semiconductor region, covers a bottom of the trench, and has a greater impurity concentration than the second semiconductor layer; a first electrode that is electrically connected to the first semiconductor region and the second semiconductor layer; and a second electrode formed on a rear surface of the semiconductor substrate.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 98.0
- Lexical Diversity: 2.45902
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15665883', '15722934', '15716919', '15800577', '16121096']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9339349083973528
- 35 USC 102 Novelty (BERT): 0.5360176738902017
- Combined Prediction Score: 0.8941431849466379
- Mean Citation Score: 328.31150400000007
- Max Citation Score: 374.74054
- Similarity Product: 358.50640002616643

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test