PATENT CLAIM ANALYSIS

Application Number: 15974862
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["710", "036000"]

Abstract:
A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialisation signal comprising port initialisation data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialisation signal comprising the port initialisation data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialisation signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialisation data and the just obtained original one or more parity bits.

Claim (Index 1):
Method for performing an initialization or a reset of a port of an integrated circuit with a device for supervising ports of said integrated circuit, said device being arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of said integrated circuit and comprising parity controlling means arranged for performing a parity check on one or more parity bits contained in said information exchanged with said central processing unit and generating an error signal in case said parity check yields no match and arranged for, upon a positive response to said request, generating one or more parity bits when performing said write operation to said port, and carrying out a parity check when performing said read operation from said port and generating an error signal in case said parity check yields no match,\n the method comprising receiving in said device for supervising ports, from said central processing unit of said integrated circuit, a port initialisation signal comprising port initialisation data and one or more parity bits, inverting in said device for supervising ports said one or more parity bits in accordance with said port initialization signal, providing said port initialisation signal comprising said port initialisation data and said inverted one or more parity bits to said port of said integrated circuit, on receipt of said port initialisation signal at said port, inverting again in said port said inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing said port initialisation data and the just obtained original one or more parity bits.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.79245
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15974784', '15493424', '14590913', '11779352', '10870959']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6113927003584168
- 35 USC 102 Novelty (BERT): 0.5458714810489562
- Combined Prediction Score: 0.6048405784274707
- Mean Citation Score: 211.65341400000003
- Max Citation Score: 400.6542
- Similarity Product: 301.96302388497594

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test