PATENT CLAIM ANALYSIS

Application Number: 16105790
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "145000"]

Abstract:
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

Claim (Index 12):
The apparatus of  claim 11 , wherein the second set of switching components is configured to connect the second memory cell of the second portion to a virtual ground or a sense component.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 96.0
- Lexical Diversity: 2.28986
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15689940', '15258852', '15969302', '15669785', '15975624']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8210161713730183
- 35 USC 102 Novelty (BERT): 0.5150752901891089
- Combined Prediction Score: 0.7904220832546274
- Mean Citation Score: 276.25597
- Max Citation Score: 333.78085
- Similarity Product: 261.5574491132468

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test