PATENT CLAIM ANALYSIS

Application Number: 16298483
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-10
Patent Classification: ["257", "691000"]

Abstract:
A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device. The trenches are configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs. The staggered devices are also designed for staggered time and staggered heat conductivity delays and current spreading from the package input to an output of a respective pair of devices to improve current and heat conductivity from the package input to an output of a subsequent pair of devices.

Claim (Index 4):
The power semiconductor device and package of  claim 1 , wherein the substrate comprises a metal brazed metal to conductive ceramic to metal brazed metal sandwich including a silicon nitride.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 99.0
- Lexical Diversity: 2.0597
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15947756', '14295309', '15601591', '11676618', '15494399']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9004218294716108
- 35 USC 102 Novelty (BERT): 0.5196325854341884
- Combined Prediction Score: 0.8623429050678686
- Mean Citation Score: 191.459514
- Max Citation Score: 323.2441
- Similarity Product: 321.07347743961213

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test