PATENT CLAIM ANALYSIS

Application Number: 16132208
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185030"]

Abstract:
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

Claim (Index 3):
The semiconductor memory device according to  claim 2 , further comprising:\n a first cell holding information for the writing of the data of the k value, wherein the information is not set to the first cell in the writing of the data of the (k\u22121) value, and the information is set to the first cell in the writing of the data of the k value.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 2.06977
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11469279', '11325917', '15251798', '14861288', '13158508']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8284874708429725
- 35 USC 102 Novelty (BERT): 0.5427511727021237
- Combined Prediction Score: 0.7999138410288876
- Mean Citation Score: 408.626606
- Max Citation Score: 411.96634
- Similarity Product: 314.83429115793706

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test