PATENT CLAIM ANALYSIS

Application Number: 15986549
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "347000"]

Abstract:
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Claim (Index 1):
A method for forming a semiconductor device, the method comprising:\n forming a first fin and a second fin; forming an isolation region between the first fin and the second fin; forming a gate dielectric layer over the first fin, the second fin, and the isolation region; forming a gate electrode layer over the gate dielectric layer; performing a first etching process, wherein the first etching process partially removes an upper portion of the gate electrode layer to form an upper portion of a first gate electrode over the first fin, an upper portion of a second gate electrode over the second fin, and an upper portion of a dummy gate electrode over the isolation region; stopping the first etching process when the gate dielectric layer over an upper surface of the first fin and over an upper surface of the second fin is exposed while the gate dielectric layer over the isolation region is covered by a lower portion of the gate electrode layer; and performing a second etching process after stopping the first etching process, wherein the second etching process partially removes the lower portion of the gate electrode layer to form the first gate electrode, the second gate electrode, and the dummy gate electrode.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 3.46341
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14067424', '14579728', '14942580', '15693202', '14599246']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9038513264919544
- 35 USC 102 Novelty (BERT): 0.4918401168293546
- Combined Prediction Score: 0.8626502055256945
- Mean Citation Score: 227.376134
- Max Citation Score: 247.60686
- Similarity Product: 211.99604442206743

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test