PATENT CLAIM ANALYSIS

Application Number: 15923282
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185290"]

Abstract:
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Claim (Index 3):
The memory system according to  claim 2 , wherein\n the status information includes information as to a progress condition of the first operation.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 90.0
- Lexical Diversity: 2.63265
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15074190', '15361778', '14748351', '14093108', '13425818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8272243988757344
- 35 USC 102 Novelty (BERT): 0.509662021761696
- Combined Prediction Score: 0.7954681611643306
- Mean Citation Score: 230.67682
- Max Citation Score: 258.88852
- Similarity Product: 150.29980191066502

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test