PATENT CLAIM ANALYSIS

Application Number: 16107596
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["375", "376000"]

Abstract:
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Claim (Index 16):
The PLL controller of  claim 15 , wherein the trend comprises:\n means for determining a trend clocking signal based upon the reference input signal and the error signal, wherein the means for sampling is configured to sample the error signal in accordance with the trend clocking signal.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 96.0
- Lexical Diversity: 2.64516
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15135212', '15845193', '15428841', '15965110', '12137332']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5057132227131689
- 35 USC 102 Novelty (BERT): 0.510792188526486
- Combined Prediction Score: 0.5062211192945005
- Mean Citation Score: 238.54122200000003
- Max Citation Score: 297.89014
- Similarity Product: 246.14194263726472

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test