PATENT CLAIM ANALYSIS

Application Number: 15868535
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["710", "308000"]

Abstract:
A memory controller includes a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to an external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via an SRAM bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data in the internal memory device.

Claim (Index 6):
A data storage device, comprising:\n a non-volatile memory device; and a memory controller, coupled to the non-volatile memory device, configured to control operations of the non-volatile memory device, and comprising:\n a central processing unit, comprising an internal memory device; \n an interface logic circuit, coupled to the non-volatile memory device and a standard bus; and \n an arbiter circuit, coupled to the standard bus and the central processing unit, wherein the arbiter circuit is directly coupled to the central processing unit via a static random access memory (SRAM) bus, and \n wherein when the central processing unit has to read predetermined data stored in the non-volatile memory device, the central processing unit issues a first request to the interface logic circuit, and in response to the first request, the interface logic circuit reads the predetermined data from the non-volatile memory device and transmits the predetermined data to the arbiter circuit via the standard bus, and the arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data to the internal memory device.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 3.32609
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12491813', '13419673', '14543549', '09845329', '14979457']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6695007431364556
- 35 USC 102 Novelty (BERT): 0.4728494365245457
- Combined Prediction Score: 0.6498356124752647
- Mean Citation Score: 180.371588
- Max Citation Score: 186.386
- Similarity Product: 138.7408214546442

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test