PATENT CLAIM ANALYSIS

Application Number: 16044260
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["345", "055000"]

Abstract:
Disclosed herein are a gate driver including at least two output buffers to drive at least two gate lines and capable of reducing an output deviation of each output buffer, and a flat panel display device including the same. The gate driver includes a plurality of gate-in-panels (GIPs) for sequentially supplying scan signals to a plurality of gate lines. Each GIP includes one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and the carry signal output unit includes a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.

Claim (Index 9):
A flat panel display device comprising:\n a display panel including a plurality of gate lines and a plurality of data lines and a plurality of subpixels formed in a matrix to supply data voltages to the plurality of data lines in response to scan pulses supplied to the plurality of gate lines to display an image; a gate driver for sequentially supplying the scan pulses to the plurality of gate lines; a data driver for supplying the data voltages to the plurality of data lines; and a timing controller for aligning image data received from outside of the timing controller according to a size and resolution of the display panel to supply the image data to the data driver and respectively supplying a plurality of gate control signals and a plurality of data control signals to the gate driver and the data driver using synchronization signals received from the outside of the timing controller, wherein the gate driver comprises a plurality of gate-in-panels GIP for sequentially supplying scan signals to the plurality of gate lines, wherein each GIP comprises one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and wherein the carry signal output unit comprises a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 2.06154
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12913632', '15967035', '14586432', '13727323', '13725704']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6751103442842803
- 35 USC 102 Novelty (BERT): 0.5007166918138191
- Combined Prediction Score: 0.6576709790372343
- Mean Citation Score: 268.882456
- Max Citation Score: 278.13382
- Similarity Product: 217.5421436019254

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test