PATENT CLAIM ANALYSIS

Application Number: 16015517
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["711", "103000"]

Abstract:
An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory operation if the memory operation is determined to be avoidable. Other embodiments are disclosed and claimed.

Claim (Index 3):
The system of  claim 1 , wherein the logic is further to:\n read an original content of a cacheline from the memory, in response to a request for a cacheline write operation; compare the original content against a current content of the cacheline; and suppress the cacheline write operation if the original content matches the current content.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 94.0
- Lexical Diversity: 1.48276
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16006956', '14320609', '15454389', '13720536', '15394084']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5027807195905187
- 35 USC 102 Novelty (BERT): 0.4544900646588036
- Combined Prediction Score: 0.4979516540973472
- Mean Citation Score: 102.990293
- Max Citation Score: 107.36754
- Similarity Product: 80.02754821587324

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test