PATENT CLAIM ANALYSIS

Application Number: 16109607
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["365", "230060"]

Abstract:
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Claim (Index 6):
The method according to  claim 2 , further comprising:\n setting the delay by selecting one from a plurality of transmit delays, the plurality of transmit delays based on the information, wherein the information is based on multiple combinations of memory system topology and data rate associated with the memory system topology information and data rate information.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.23529
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15626097', '14863366', '13720720', '12477703', '11252957']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7572978618650785
- 35 USC 102 Novelty (BERT): 0.4866500120354466
- Combined Prediction Score: 0.7302330768821154
- Mean Citation Score: 195.723404
- Max Citation Score: 210.8771
- Similarity Product: 152.9540781648517

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test