PATENT CLAIM ANALYSIS

Application Number: 15868058
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["438", "199000"]

Abstract:
One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

Claim (Index 17):
A method of forming a conductive gate-to-source/drain (GSD) contact structure for a first transistor device, the first transistor device comprising a gate electrode, a gate cap covering an upper surface of said gate electrode, and a sidewall spacer covering side surfaces of said gate electrode, the method comprising:\n performing at least one etching process to remove at least a portion of said gate cap so as to expose at least a portion of said upper surface of said gate electrode of said first transistor device, to remove at least a portion of said sidewall spacer so as to expose substantially an entirety of at least an axial portion of one of said side surfaces of said gate electrode, and to expose a portion of a semiconductor substrate located adjacent said gate electrode of said first transistor device; and performing a GSD contact material growth process to form said conductive GSD contact structure that conductively couples said gate electrode of said first transistor device to a source/drain region of said first transistor device, wherein said conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of said gate electrode and a single crystal material portion positioned in said source/drain region on said semiconductor substrate located adjacent said gate electrode of said first transistor device.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15791650', '15791711', '15813471', '15047137', '15214670']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8654134111987632
- 35 USC 102 Novelty (BERT): 0.4990280778941619
- Combined Prediction Score: 0.8287748778683031
- Mean Citation Score: 251.400774
- Max Citation Score: 277.93906
- Similarity Product: 229.99740103852864

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test