PATENT CLAIM ANALYSIS

Application Number: 16150091
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-01
Patent Classification: ["365", "189090"]

Abstract:
The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.

Claim (Index 9):
The semiconductor memory device according to  claim 1 ,\n wherein the plurality of word lines are grouped into a plurality of word line groups, wherein the plurality of word lines are programmed in a sequence from a word line adjacent to a drain select transistor to a word line adjacent to a source select transistor, and wherein the later a word line group among the plurality of the word line groups is programmed, the greater a pre-bias voltage to be applied to word lines included in the word line group is.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 97.0
- Lexical Diversity: 2.77778
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15633417', '13602021', '15948730', '15457119', '14316936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8359250356574922
- 35 USC 102 Novelty (BERT): 0.5621083842595114
- Combined Prediction Score: 0.8085433705176941
- Mean Citation Score: 303.447766
- Max Citation Score: 448.74704
- Similarity Product: 404.0623923816681

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test