PATENT CLAIM ANALYSIS

Application Number: 15997338
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "048000"]

Abstract:
A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.

Claim (Index 11):
The semiconductor device of  claim 1 , wherein the upper dielectric layer comprises:\n a first upper dielectric layer on the chip pad; and second and third upper dielectric layers stacked on the first upper dielectric layer, wherein the second upper dielectric layer comprises an insulating material different from those of the first and third upper dielectric layers.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 94.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15295104', '15222114', '15205414', '15791709', '15201694']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9294654639957062
- 35 USC 102 Novelty (BERT): 0.4969671328371244
- Combined Prediction Score: 0.8862156308798481
- Mean Citation Score: 245.81111
- Max Citation Score: 252.92455
- Similarity Product: 194.42489648346603

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test