PATENT CLAIM ANALYSIS

Application Number: 16235242
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["706", "038000"]

Abstract:
A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. A digital controller interfaces with the crossbar arrays to direct write and read operations to the crossbar arrays.

Claim (Index 3):
The circuit of  claim 2 , wherein the input to the VMM processor includes a VMM signal-processing chain, the chain comprising digital logic blocks that perform a set of sequential functions to prepare floating point data for VMM, the functions including at least one of data formatting, exponent normalization/denormalization, and memristor network mapping/inverse mapping.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 98.0
- Lexical Diversity: 1.41096
- Patent Class: 706.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15427591', '14328043', '15997030', '16235115', '15572852']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3767334430937596
- 35 USC 102 Novelty (BERT): 0.5198450693509141
- Combined Prediction Score: 0.3910446057194751
- Mean Citation Score: 215.79615
- Max Citation Score: 339.46613
- Similarity Product: 264.51804408035576

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test