PATENT CLAIM ANALYSIS

Application Number: 15989460
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["365", "185110"]

Abstract:
A memory device includes: memory cells of first and second planes; and a control circuit suitable for performing multiple read operations on the memory cells in response to a read command. The multiple read operations may include a first read operation which is performed on the memory cells of the first plane in a first read period and a second read operation which is performed on the memory cells of the second plane in a second read period.

Claim (Index 3):
The memory device of  claim 1 , wherein the first and second planes comprise single level cells (SLCs).

Metadata:
- Claim Count in Document: 19.0
- Percentile: 93.0
- Lexical Diversity: 2.21622
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13594624', '14918327', '13614382', '13846854', '14697405']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.801686742227416
- 35 USC 102 Novelty (BERT): 0.4894274581061697
- Combined Prediction Score: 0.7704608138152914
- Mean Citation Score: 179.75546000000003
- Max Citation Score: 188.05144
- Similarity Product: 118.20056074952603

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test