PATENT CLAIM ANALYSIS

Application Number: 16190043
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["714", "764000"]

Abstract:
A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Claim (Index 6):
An apparatus for wear leveling control for storage class memory, the apparatus comprising:\n a cache memory; a nonvolatile memory comprising (D+E) nonvolatile-memory chips, wherein D nonvolatile-memory chips are configured to store input data and E nonvolatile-memory chips are configured to store extended data associated with the input data, wherein D and E are positive integers; a storage class memory (SCM) controller coupled to the cache memory and the nonvolatile memory; and one or more processors; wherein the cache memory, the nonvolatile memory, the SCM controller and said one or more processors are configured to perform at least the following:\n dividing the nonvolatile memory into memory groups; \n mapping N input group addresses corresponding a logic addresses of the memory groups to M output group addresses corresponding to physical group addresses of the memory groups using fixed mapping within a period T, wherein M and N are positive integers and M is greater than N, wherein N memory groups are used as data groups, and one or more memory groups are used as redundant groups, M is equal to a sum of N and number of the redundant groups, and wherein said mapping N input group addresses to M output group addresses causes N data groups among M memory groups to store input data in a rotated fashion; and \n storing Error Correction Code (ECC) check bytes and metadata associated with the data groups and the redundant groups in said E nonvolatile-memory chips, wherein the metadata corresponding to information related to said mapping N input group addresses to M output group addresses to cause N data groups among M memory groups to store the input data in a rotated fashion.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 2.91228
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16190017', '15230414', '12348891', '11767417', '12497368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3547613541107242
- 35 USC 102 Novelty (BERT): 0.5670181768523336
- Combined Prediction Score: 0.3759870363848852
- Mean Citation Score: 308.411966
- Max Citation Score: 488.9064
- Similarity Product: 388.0146347771645

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test