PATENT CLAIM ANALYSIS

Application Number: 15743617
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["345", "212000"]

Abstract:
The present disclosure provides a GOA unit circuit, a method for driving the same, and a GOA circuit. The GOA unit circuit comprises a first input sub-circuit, a pull-up sub-circuit, a first pull-down sub-circuit, a reset sub-circuit, a second input sub-circuit, a noise control sub-circuit, a first de-noising sub-circuit, and a second de-noising sub-circuit. The first pull-down sub-circuit is connected to an output signal terminal, a first clock control signal terminal and a discharge signal terminal, a discharge signal provided by the discharge signal terminal is at a high level higher than that of an input signal provided by the input signal terminal, and the first pull-down sub-circuit is configured to discharge the output signal terminal under the control of the first clock control signal and the discharge signal, to pull down a potential at the output signal terminal to a low level. The GOA unit circuit is configured to drive gate lines of a display apparatus.

Claim (Index 1):
A Gate Driver on Array (GOA) unit circuit, comprising:\n a first input sub-circuit connected to a pull-up node and an input signal terminal, and configured to pull up a potential at the pull-up node for a first time under the control of an input signal provided by the input signal terminal; a pull-up sub-circuit connected to the pull-up node, a first clock control signal terminal and an output signal terminal, and configured to pull up the potential at the pull-up node for a second time and transfer a high level of a first clock control signal provided by the first clock control signal terminal to the output signal terminal for output under the control of the first clock control signal; a first pull-down sub-circuit connected to the output signal terminal, the first clock control signal terminal and a discharge signal terminal, wherein a discharge signal provided by the discharge signal terminal is at a high level higher than that of the input signal provided by the input signal terminal, and the first pull-down module is configured to discharge the output signal terminal under the control of the first clock control signal provided by the first clock control signal terminal and the discharge signal provided by the discharge signal terminal to pull down a potential at the output signal terminal to a low level; a reset sub-circuit connected to the pull-up node, a reset signal terminal and a low level power supply signal terminal, and configured to reset the potential at the pull-up node under the control of a reset signal provided by the reset signal terminal and a low level power supply signal provided by the low level power supply signal terminal; a second input sub-circuit connected to a pull-down node, the pull-up node and the low level power supply signal terminal, and configured to pull down a potential at the pull-down node for a first time under the control of the high potential at the pull-up node and the low level power supply signal provided by the low level power supply signal terminal; a noise control sub-circuit connected to the pull-down node and a second clock control signal terminal, and configured to pull down the potential at the pull-down node for a second time under the control of a second clock control signal provided by the second clock control signal terminal; a first de-noising sub-circuit connected to the pull-up node, the pull-down node and the low level power supply signal terminal, and configured to de-noise the pull-up node under the control of the high potential at the pull-down node and the low level power supply signal provided by the low level power supply signal terminal; and a second de-noising sub-circuit connected to the output signal terminal, the pull-down node and the low level power supply signal terminal, and configured to de-noise the output signal terminal under the control of the high potential at the pull-down node and the low level power supply signal provided by the low level power supply signal terminal.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 3.10714
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15682740', '16066827', '15741742', '14787934', '15529613']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6969404464598344
- 35 USC 102 Novelty (BERT): 0.5387247324349893
- Combined Prediction Score: 0.68111887505735
- Mean Citation Score: 343.007954
- Max Citation Score: 393.1922
- Similarity Product: 318.2415961495638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test