PATENT CLAIM ANALYSIS

Application Number: 15990719
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "288000"]

Abstract:
The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second side wall portion.

Claim (Index 9):
A method of manufacturing a trench power semiconductor component, comprising:\n forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming a trench gate structure in the trench; and forming a base region and a source region in the epitaxial layer, in which the source region is located above the base region; wherein the step of forming the trench gate structure in the trench further includes:\n forming a bottom insulating layer covering a lower inner wall of the trench; \n forming a shielding electrode in the lower half part of the trench; \n forming an upper insulating layer covering two side walls of the trench opposite each other; \n forming a protection structure including a first wall portion and a second side wall portion and covering at least one portion of the upper insulating layer; \n forming an inter-electrode dielectric layer; and \n forming a gate electrode, the inter-electrode dielectric layer being located between the gate electrode and the shielding electrode, wherein the upper insulating layer, the bottom insulating layer, and the inter-electrode dielectric layer jointly define a first slit and a second slit, one located on either side of the inter-electrode dielectric layer.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 93.0
- Lexical Diversity: 2.92727
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15975023', '15988018', '15186685', '15358182', '15005130']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9291128723446144
- 35 USC 102 Novelty (BERT): 0.5358165598240697
- Combined Prediction Score: 0.8897832410925598
- Mean Citation Score: 330.80428599999993
- Max Citation Score: 380.70328
- Similarity Product: 331.5794153090286

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test