PATENT CLAIM ANALYSIS

Application Number: 16411663
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-11
Patent Classification: ["438", "149000"]

Abstract:
A semiconductor device with a novel structure is provided. Input neuron circuits, hidden neuron circuits, and output neuron circuits are hierarchically connected to one another through plural synapse circuits. Each synapse circuit includes an analog memory which stores data corresponding to a connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit which changes the data in the analog memory, and a weighting circuit which outputs an output signal obtained by weighting an input signal in accordance with data in the analog memory. The analog memory is formed using a transistor including an oxide semiconductor having extremely low off-state current. It is not necessary to mount a large-scale capacitor for holding data and to recover analog data by regular refresh operation; thus, reduction in a chip area and reduction in power consumption are possible.

Claim (Index 5):
The semiconductor device according to  claim 2 ,\n wherein the oxide semiconductor comprises indium, gallium, and zinc.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 100.0
- Lexical Diversity: 1.96341
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15210068', '15876724', '15375466', '16293959', '15567091']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8658491493102117
- 35 USC 102 Novelty (BERT): 0.5426710464513811
- Combined Prediction Score: 0.8335313390243286
- Mean Citation Score: 241.599738
- Max Citation Score: 275.0575
- Similarity Product: 196.40519995763896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test