PATENT CLAIM ANALYSIS

Application Number: 16040912
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["710", "110000"]

Abstract:
A data communication system applied in an Inter-Integrated Circuit (I2C) bus to enable functioning without a buffer or hub includes a complex programmable logic device (CPLD), a master device, and a plurality of slave devices. The CPLD detects changes in level of the SDA signal of the I2C bus between the master device and one of the slave devices, and determines a direction of an SDA signal as being from the I2C bus of the master device or from the I2C bus of the slave device.

Claim (Index 1):
A data communication system, comprising:\n a master device and a plurality of slave devices; and a complex programmable logic device (CPLD) coupling between the master device and the plurality of slave devices, and receiving serial data line (SDA) signal and serial clock line (SCL) signal from an Inter-Integrated Circuit (I2C) bus of the master device and an I2C bus of the plurality of slave devices; and wherein the master device selects a communication connection with one of the plurality of slave devices through the CPLD; and wherein the CPLD detects change in level of the SDA signal between the I2C bus of the master device and the I2C bus of the one of the plurality of slave devices, and determines a direction of a current SDA signal between an SDA signal from the I2C bus of the master device and an SDA signal from the I2C bus of the one of the plurality of slave devices; wherein the CPLD comprises a communication unit, the communication unit comprises a clock stretching module, and the clock stretching module supports clock stretching of the I2C bus SCL signal by the one of the plurality of slave devices; wherein the CPLD comprises a selection unit, the master device selects the communication connection with the one of the plurality of slave devices through the selection unit; wherein the communication unit further comprises a direction control module, and the direction control module detects level change state of the SDA signal of the I2C bus between the master device and the one of the plurality of slave devices, and determines a direction of a current SDA signal between an SDA signal from the I2C bus of the master device and an SDA signal from the I2C bus of the one of the plurality of slave devices; and wherein when the direction control module first detects that the SDA signal of the I2C bus of the master device changes from the high level to the low level, the direction control unit pulls a SDA signal line of the slave device low and maintains at a low level, and the direction of the current SDA signal is from the master device to the one of the plurality of slave devices.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 1.93878
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15254962', '13550715', '13541750', '13863565', '14053823']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6573603250280274
- 35 USC 102 Novelty (BERT): 0.4641609349264693
- Combined Prediction Score: 0.6380403860178717
- Mean Citation Score: 160.42706399999997
- Max Citation Score: 171.59418
- Similarity Product: 132.90669035952328

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test