PATENT CLAIM ANALYSIS

Application Number: 15865793
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "359000"]

Abstract:
A method for manufacturing a thin film transistor includes: forming a source electrode and a first insulation pattern, where an orthographic projection of the first insulation pattern at a substrate is within an orthographic projection of the source electrode at the substrate; forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode not covered by the first insulation pattern and the first insulation pattern; exposing a first portion of the action layer on the first insulation pattern by removing parts of the gate electrode and the second insulation pattern; and performing a plasma treatment to the exposed first portion, thereby forming a drain electrode.

Claim (Index 4):
The method of  claim 1 , wherein the forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode which is not covered by the first insulation pattern, and the first insulation pattern, includes:\n forming a first oxide layer, a second oxide layer and a second metal layer on the substrate, the exposed portion of the source electrode which is not covered by the first insulation pattern, and the first insulation pattern; coating second photoresist on the second metal layer in such a manner that a thickness of a first portion of the second photoresist is smaller than a thickness of a second portion of the second photoresist, the first portion of the second photoresist is corresponding to a region where the drain electrode is formed, and the second portion of the second photoresist is corresponding to a region where the gate electrode, the second insulation pattern and the active layer are formed; and exposing and developing the second photoresist with a half-tone mask plate, and then etching the second metal layer, the second oxide layer and the first oxide layer, thereby obtaining the gate electrode, the second insulation pattern and the active layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14764307', '15742153', '13755730', '15505108', '14436995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9330654143597432
- 35 USC 102 Novelty (BERT): 0.5149436002527119
- Combined Prediction Score: 0.8912532329490401
- Mean Citation Score: 288.300038
- Max Citation Score: 311.1226200000001
- Similarity Product: 242.1733794353772

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test