PATENT CLAIM ANALYSIS

Application Number: 15888517
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "051000"]

Abstract:
Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

Claim (Index 8):
A memory device including a memory cell laid out on a semiconductor substrate according to a memory cell layout, the memory cell layout comprising:\n upper and lower cell edges and left and right cell edges corresponding to an outer perimeter of the memory cell on the semiconductor substrate; a first power rail extending in parallel with and lying along the left cell edge or the right cell edge, wherein the first power rail is configured to couple the cell to a first power supply; a second power rail extending in parallel with the first power rail and along a midline of the memory cell, wherein the second power rail is arranged symmetrically between the left and right cell edges and the second power rail is configured to couple the memory cell to a second power supply, the second power supply differing from the first power supply; and two wordlines extending in parallel with the upper and lower cell edges over the memory cell and extending perpendicular to the first and second power rails, wherein only one of the two wordlines is coupled to gates of respective access transistors of the memory cell; and wherein a plurality of metal lines including the first and second power rails extend in parallel with one another and an order of the metal lines moving from the left cell edge to the right cell edge or from the right cell edge to left cell edge is the first power rail, a first of the two wordlines, a bitline, the second power rail, a complementary bitline, and a second of the two wordlines.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 88.0
- Lexical Diversity: 3.26667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15172555', '15249885', '15214790', '15858194', '11171033']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7850517800521001
- 35 USC 102 Novelty (BERT): 0.4714621161012057
- Combined Prediction Score: 0.7536928136570107
- Mean Citation Score: 191.405418
- Max Citation Score: 201.48242
- Similarity Product: 157.41998178303956

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test