PATENT CLAIM ANALYSIS

Application Number: 15761497
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.

Claim (Index 12):
A gate driving circuit, comprising:\n an N-stage shift register circuit including N shift registers coupled in a cascade structure, each of the N shift registers including the shift register according to  claim 1 , and N being an integer larger than 1; and (N\u22121) gating circuits, each of the (N\u22121) gating circuits being coupled to one of a 1st-stage to an (N\u22121)-th-stage shift registers of the N-stage shift register, wherein:\n each of the gating circuits includes an input terminal, a first control terminal, a second control terminal, a first output terminal, and a second output terminal, and is configured to electrically connect the input terminal to the first output terminal when the first control terminal receives an active signal, and to electrically connect the input terminal to the second output terminal when the second control terminal receives an active signal, \n the first input terminal of an n-th-stage shift register is coupled to the first output terminal of an n-th-stage gating circuit, \n the second input terminal of the n-th-stage shift register is coupled to the second output terminal of the n-th-stage gating circuit, \n the signal output terminal of the n-th-stage shift register is coupled to the input terminal of an (n+1)-th-stage gating circuit, \n the reset terminal of the n-th-stage shift register is coupled to the signal output terminal of the (n+1)-th-stage shift register, \n n is a positive integer and 1\u2264n<N, and \n the input terminal of a 1st-stage gating circuit is coupled to a start vertical signal terminal.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 4.09677
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15740121', '15518389', '15541622', '15542365', '15541426']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6918384674854822
- 35 USC 102 Novelty (BERT): 0.5127208340418091
- Combined Prediction Score: 0.6739267041411149
- Mean Citation Score: 313.09041400000007
- Max Citation Score: 322.13254
- Similarity Product: 269.4555907203793

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test