PATENT CLAIM ANALYSIS

Application Number: 16122865
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["710", "005000"]

Abstract:
A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

Claim (Index 10):
The acceleration module according to  claim 9 , wherein:\n the upstream interface includes an FPGA endpoint; the downstream interface includes a FPGA root port, the FPGA root port supporting a configuration space; the FPGA includes a first PF, a second PF, and a downstream filter associated with the FPGA root port, the downstream filter operative to intercept a first acceleration instruction received from the storage device and deliver the first acceleration instruction to the APM-F, the first acceleration instruction being associated with a downstream Filter Address Range (FAR); the FPGA is operative to request a first block of host system addresses from the processor for the first PF and to request a second block of host system addresses from the processor for the second PF; and the FPGA is operative to forward a PCIe transaction received from the processor to the storage device and to forward a second acceleration instruction received from the processor to the APM-F, the PCIe transaction being associated with a first identifier of the first PF the second acceleration instruction being associated with a second identifier of the second PF.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.47297
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14966738', '12468340', '14019777', '15397003', '14019815']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6720292601530854
- 35 USC 102 Novelty (BERT): 0.480257572239595
- Combined Prediction Score: 0.6528520913617364
- Mean Citation Score: 142.17075400000004
- Max Citation Score: 146.5811
- Similarity Product: 95.240160247159

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test