PATENT CLAIM ANALYSIS

Application Number: 16131670
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185180"]

Abstract:
A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

Claim (Index 14):
The semiconductor memory device according to  claim 1 , wherein each of the first and sixth voltages is a ground voltage.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 97.0
- Lexical Diversity: 3.56522
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15693407', '15916551', '14474307', '15688846', '15885076']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8313815285510997
- 35 USC 102 Novelty (BERT): 0.5243258885061045
- Combined Prediction Score: 0.8006759645466002
- Mean Citation Score: 271.261202
- Max Citation Score: 359.03253
- Similarity Product: 332.2505075735807

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test