PATENT CLAIM ANALYSIS

Application Number: 15918800
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "329000"]

Abstract:
Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.

Claim (Index 17):
The method of  claim 12 , further comprising:\n depositing a spacer adjacent the second epitaxial layer, wherein the spacer separates the vertical field effect transistor and the boosted bipolar junction transistor.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.95918
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15840897', '15139937', '15588969', '15254573', '15006284']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9010896965838217
- 35 USC 102 Novelty (BERT): 0.5088327640529138
- Combined Prediction Score: 0.8618640033307308
- Mean Citation Score: 220.82613
- Max Citation Score: 232.31468
- Similarity Product: 149.86689184366227

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test