PATENT CLAIM ANALYSIS

Application Number: 15869917
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "203000"]

Abstract:
A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.

Claim (Index 17):
A method for fabricating a semiconductor device, the method comprising:\n forming a device isolation layer extending in a second direction on a substrate having a placement plane defined by a first direction and the second direction perpendicular to the first direction to define an active region; stacking a first interlayer dielectric, a doped silicon layer, and a second interlayer dielectric on the substrate where the active region is formed and forming a through-hole through the second interlayer dielectric, the doped silicon layer, and the first interlayer dielectric; forming a gate insulating layer on an exposed surface of the doped silicon layer within the through-hole; forming a semiconductor column within the through-hole, the semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region; forming a trench penetrating the second interlayer dielectric and the doped silicon layer with the semiconductor columns, which are arranged in the first direction, interposed therebetween and extending in the first direction; filling the trench with a wordline isolation layer; and forming a bitline being in contact with the second conductive region of the semiconductor column and extending in the second direction.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.80952
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15185388', '15870092', '15394584', '11433753', '11261729']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9202225532563936
- 35 USC 102 Novelty (BERT): 0.5356048263898844
- Combined Prediction Score: 0.8817607805697427
- Mean Citation Score: 271.37967000000003
- Max Citation Score: 377.8438
- Similarity Product: 320.5578141058206

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test