PATENT CLAIM ANALYSIS

Application Number: 15964253
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["257", "401000"]

Abstract:
A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.

Claim (Index 11):
A method, comprising:\n depositing a gate dielectric layer over a first region and a second region; forming a metal oxide layer over in the gate dielectric layer in the first region and the second region; removing the metal oxide layer from the second region; annealing the gate dielectric layer and the remaining metal oxide layer to form a doped gate dielectric layer in the first region; removing the remaining metal oxide layer from the first region; depositing a work function layer on the doped gate dielectric layer; and forming a gate electrode over the work function layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 2.74286
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15664071', '15952534', '15419289', '15455603', '15356439']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9017992653156844
- 35 USC 102 Novelty (BERT): 0.492719677435285
- Combined Prediction Score: 0.8608913065276445
- Mean Citation Score: 219.21479600000004
- Max Citation Score: 230.55353
- Similarity Product: 181.8750264080453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test