PATENT CLAIM ANALYSIS

Application Number: 15963980
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["029", "852000"]

Abstract:
Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

Claim (Index 13):
The method of  claim 11 , wherein the etchant is plasma gas and wherein the plasma gas includes at least one of oxygen, nitrogen, argon and tetrafluoromethane.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.80435
- Patent Class: 29.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14205337', '15723135', '14205331', '15723086', '12483223']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9018083762282232
- 35 USC 102 Novelty (BERT): 0.5208247822612916
- Combined Prediction Score: 0.8637100168315299
- Mean Citation Score: 280.323238
- Max Citation Score: 291.5263700000001
- Similarity Product: 160.7421164423484

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test