PATENT CLAIM ANALYSIS

Application Number: 15778863
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "369000"]

Abstract:
Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

Claim (Index 21):
The integrated circuit of  claim 19 , wherein the tensile-strained semiconductor material included in one or both of the first body or the second body is germanium.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 93.0
- Lexical Diversity: 1.6875
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16474446', '16081215', '15576150', '15753739', '15125437']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920526099517902
- 35 USC 102 Novelty (BERT): 0.474422404409152
- Combined Prediction Score: 0.8759157300070269
- Mean Citation Score: 182.088312
- Max Citation Score: 198.29268
- Similarity Product: 161.1331314633751

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test