PATENT CLAIM ANALYSIS

Application Number: 16151404
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-09
Patent Classification: ["341", "144000"]

Abstract:
A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

Claim (Index 16):
The DSM of  claim 1 , wherein the first loop filter is a first-order integrator.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 2.74419
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15049933', '15389297', '12568811', '13562729', '15603546']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5700173445778947
- 35 USC 102 Novelty (BERT): 0.4949403937973383
- Combined Prediction Score: 0.5625096494998391
- Mean Citation Score: 133.742162
- Max Citation Score: 139.28596000000002
- Similarity Product: 86.02250577605247

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test