PATENT CLAIM ANALYSIS

Application Number: 15918106
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["712", "218000"]

Abstract:
A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to The particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Claim (Index 4):
The hardware processor of  claim 1 , wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 90.0
- Lexical Diversity: 1.98305
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11529728', '15467661', '14749932', '11515720', '10439203']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.635468451310211
- 35 USC 102 Novelty (BERT): 0.545232838547433
- Combined Prediction Score: 0.6264448900339332
- Mean Citation Score: 258.09383800000006
- Max Citation Score: 327.6956
- Similarity Product: 325.4130304004193

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test