PATENT CLAIM ANALYSIS

Application Number: 15917168
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "329000"]

Abstract:
An SGT is formed in Si pillars. The SGT includes WSi 2  layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

Claim (Index 7):
The semiconductor device including an SGT according to  claim 1 , further comprising a fifth conductive layer that is in contact with an inner side surface of the first conductive layer, is positioned between the first conductive layer and the first impurity region, and contains the same metal atom and donor or acceptor impurity atom as the first conductive layer.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15655168', '14806053', '15584466', '14689640', '15360488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.924434095348434
- 35 USC 102 Novelty (BERT): 0.543694361084763
- Combined Prediction Score: 0.8863601219220668
- Mean Citation Score: 379.74567
- Max Citation Score: 392.4889
- Similarity Product: 268.3602746799588

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test