PATENT CLAIM ANALYSIS

Application Number: 15902473
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["710", "313000"]

Abstract:
In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.

Claim (Index 14):
The device of  claim 1 , wherein the data output is coupled to a serial peripheral interface bus.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.81395
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10741761', '11647760', '13921138', '10616473', '12153229']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6974240462457951
- 35 USC 102 Novelty (BERT): 0.4991039021075514
- Combined Prediction Score: 0.6775920318319708
- Mean Citation Score: 203.695898
- Max Citation Score: 219.18843
- Similarity Product: 137.0619199345583

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test