PATENT CLAIM ANALYSIS

Application Number: 15923864
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "003000"]

Abstract:
Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Claim (Index 22):
A method of forming integrated circuitry, comprising:\n forming a structure comprising first conductive lines over a dielectric bonding region; the first conductive lines extending along a first direction; the structure comprising conductive beams over the first conductive lines, and spaced from the first conductive lines by insulative regions; the conductive beams comprising conductive material and being configured as downwardly-opening container shapes; each of the downwardly-opening container shapes including a pair of sidewall regions, and including a top region extending across the sidewall regions; the conductive beams being spaced from one another by semiconductor material walls; gate dielectric material being between the semiconductor material walls and the conductive beams; the conductive beams and the semiconductor material walls extending along a second direction which intersects the first direction; the conductive beams and the semiconductor material walls alternating with one another along the first direction; the semiconductor material walls having bottom surfaces with first and second regions; the first regions being over top surfaces of the first conductive lines, and the second regions being between the first regions; the semiconductor material walls comprising a first semiconductor material; the structure comprising a second semiconductor material under the dielectric bonding region; forming openings extending downwardly through the semiconductor material walls; the openings forming semiconductor material pillars from the semiconductor material walls; the semiconductor material pillars comprising the first regions along the bottom surfaces of the semiconductor walls; filling the openings with insulative material; polishing the first semiconductor material, the conductive material and the insulative material; the polishing removing the top regions of the conductive beams and thereby forming spaced-apart second conductive lines from the sidewall regions of the conductive beams; the polishing forming a planarized surface which extends across the second conductive lines, the semiconductor material pillars and the insulative material; recessing upper surfaces of the second conductive lines relative to the planarized surface; and forming memory structures over the semiconductor material pillars.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 2.86792
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14226643', '15064002', '15650274', '15391604', '13765643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8603146375050894
- 35 USC 102 Novelty (BERT): 0.4849537105916311
- Combined Prediction Score: 0.8227785448137436
- Mean Citation Score: 219.374328
- Max Citation Score: 225.80673
- Similarity Product: 177.105500929057

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test