PATENT CLAIM ANALYSIS

Application Number: 15915147
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Claim (Index 21):
A memory system comprising:\n banks each including plurality of blocks and suitable for storing data; and a controller suitable for controlling the plurality of banks to perform a write operation of data having successive logical addresses on a page-by-page basis, wherein the controller sequentially maps the logical addresses to physical addresses of pages in the respective banks and sets the pages of the respective banks to memory blocks, and wherein the controller performs a wear-leveling operation to the memory blocks upon completion of the write operation.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 90.0
- Lexical Diversity: 1.92105
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15726460', '15618597', '15426298', '13954135', '11771531']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5348712245533838
- 35 USC 102 Novelty (BERT): 0.4987106277861581
- Combined Prediction Score: 0.5312551648766612
- Mean Citation Score: 240.388434
- Max Citation Score: 265.9842
- Similarity Product: 198.12752127610443

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test