PATENT CLAIM ANALYSIS

Application Number: 15898861
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["714", "719000"]

Abstract:
The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Claim (Index 1):
A method comprising:\n receiving digital outputs of a content addressable memory (CAM) (CAM match outputs) on first data inputs of a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits; addressing a random access memory (RAM) via first outputs of the L1 latch circuits and digital inputs of the RAM (RAM inputs); receiving digital outputs (ABIST outputs) of an array built-in self-test (ABIST) controller circuit via a plurality of multiplexer (MUX) circuits, logically coupled to the plurality of L1 latch circuits and via a plurality of exclusive or (XOR) circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, on first scan inputs of the L1 latch circuits; outputting compression data (L2 scan out data) via second outputs of the L2 latch circuits; and providing feedback data via at least two XOR circuits (outer XOR circuits), wherein each of the outer XOR circuits is logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 2.98214
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15298360', '15898893', '10413612', '12268903', '11047419']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2813534266481334
- 35 USC 102 Novelty (BERT): 0.6328847769458482
- Combined Prediction Score: 0.316506561677905
- Mean Citation Score: 362.24091
- Max Citation Score: 619.8430000000002
- Similarity Product: 544.4840368635656

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test