PATENT CLAIM ANALYSIS

Application Number: 15949328
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["438", "586000"]

Abstract:
A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.

Claim (Index 35):
A system-on-chip (SOC) device, comprising:\n a memory array including a plurality of memory cells, wherein each memory cell includes,\n a select gate disposed adjacent to a memory gate and over a substrate, wherein a top surface of the memory gate has a greater elevation than a top surface of the select gate, \n a dielectric structure having a first portion disposed underneath the memory gate and a second portion disposed between and separating the select gate from the memory gate, \n a spacer formed over the select gate, insulating the memory gate and select gate from one another; and \n a peripheral circuitry comprising,\n a plurality of first transistors, each first transistor including a first gate dielectric disposed underneath a first gate, and \n a plurality of second transistors, each second transistor including a second gate dielectric disposed underneath a second gate, \n wherein the first gate dielectric has a greater thickness than the second gate dielectric, and wherein top surfaces of the first and second gates have an approximately same elevation.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 91.0
- Lexical Diversity: 1.93617
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15730979', '13715185', '14580454', '15281010', '15473372']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8564913281995619
- 35 USC 102 Novelty (BERT): 0.4730828860254643
- Combined Prediction Score: 0.8181504839821522
- Mean Citation Score: 165.663752
- Max Citation Score: 173.0237
- Similarity Product: 138.0545413230002

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test