PATENT CLAIM ANALYSIS

Application Number: 16025085
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["438", "172000"]

Abstract:
A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

Claim (Index 20):
The process of  claim 14 , wherein:\n forming the channel layer comprises depositing the channel layer including a first GaN layer, forming the barrier layer comprises depositing the barrier layer including Al b In c Ga (1-b-c) N, wherein 0<b\u22641 and 0\u2264c\u22640.3, forming the sacrificial layer comprises depositing a second GaN layer, forming the etch-stop layer depositing the etch-stop layer including Al d In e Ga (1-d-e) N, wherein 0<d\u22641 and 0\u2264e\u22640.3, and the etch-stop layer has a higher Al content than the barrier layer, forming the access region layer comprises blanket depositing the access region layer including Al f In g Ga (1-f-g) N, wherein 0<f\u22641 and 0\u2264g\u22640.3, wherein the access region layer has an Al content between the Al contents of the barrier and etch-stop layers, the process further comprises:\n removing a portion of the access region layer lying within the gate region, \n forming the p-type semiconductor layer comprises blanket depositing a p-type GaN layer after removing the remaining portions of the etch-stop and sacrificial layers, the process further comprises removing a portion of the p-type semiconductor layer outside the gate region, and the electronic device includes a high electron mobility transistor.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 3.30233
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15581170', '15182405', '15662622', '15270905', '13327422']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8683398997235094
- 35 USC 102 Novelty (BERT): 0.5026389606575786
- Combined Prediction Score: 0.8317698058169164
- Mean Citation Score: 205.654746
- Max Citation Score: 219.76671
- Similarity Product: 140.48786923584225

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test