PATENT CLAIM ANALYSIS

Application Number: 15919036
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "226000"]

Abstract:
Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

Claim (Index 20):
The method of  claim 11 , further comprising receiving the write request from a host application over a bus.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 2.55172
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12807389', '13544893', '11726943', '15855855', '14082624']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7629107426938415
- 35 USC 102 Novelty (BERT): 0.506805239899936
- Combined Prediction Score: 0.737300192414451
- Mean Citation Score: 131.20352799999998
- Max Citation Score: 142.10732
- Similarity Product: 66.16478051175594

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test