PATENT CLAIM ANALYSIS

Application Number: 16448844
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["438", "269000"]

Abstract:
A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

Claim (Index 1):
A semiconductor device, comprising:\n a channel layer; interlayer insulating layers surrounding the channel layer and stacked to be spaced apart from one another along an extension direction of the channel layer; conductive patterns filling interlayer spaces between the insulating layers adjacent to one another, and deviating from the interlayer spaces; and first isolation layers covering a portion of the conductive patterns that deviate from the interlayer spaces, wherein the first isolation layers are formed of an oxide of the conductive patterns.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 100.0
- Lexical Diversity: 1.86
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15487761', '16031588', '15961143', '16410752', '16011975']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8588316409675864
- 35 USC 102 Novelty (BERT): 0.4796203605052097
- Combined Prediction Score: 0.8209105129213486
- Mean Citation Score: 207.786782
- Max Citation Score: 233.1994
- Similarity Product: 200.45752490832805

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test