PATENT CLAIM ANALYSIS

Application Number: 16156613
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-08
Patent Classification: ["327", "299000"]

Abstract:
A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Claim (Index 13):
The semiconductor system of  claim 11 , wherein the frequency detector includes:\n a plurality of first unit delayers that are coupled in series to form a feedback loop for generating the internal clock; a reset signal generator suitable for generating a reset signal that is activated after the activation period of the input clock ends; and a counter suitable for generating the counting signal by counting the toggling number of the internal clock during the activation period of the input clock, and resetting the counting signal based on the reset signal.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 97.0
- Lexical Diversity: 2.36842
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11964824', '12983124', '12428507', '10372265', '13237083']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7863002425631685
- 35 USC 102 Novelty (BERT): 0.4859849973837621
- Combined Prediction Score: 0.756268718045228
- Mean Citation Score: 203.134922
- Max Citation Score: 233.72401
- Similarity Product: 181.92161760683533

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test