PATENT CLAIM ANALYSIS

Application Number: 15947075
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "154000"]

Abstract:
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Claim (Index 7):
The multi-port memory circuit according to  claim 2 ,\n wherein the address control circuit includes first and second address decoders, and first and second assert compulsion circuits configured such that the first assert compulsion circuit performs control as to whether an output from the first address decoder is compulsively asserted and the second assert compulsion circuit performs control as to whether an output from the second address decoder is compulsively asserted, wherein the first address signal is input into the first address decoder, wherein the second address signal is input into the second address decoder, wherein control as to whether the first word line is activated is performed based on an output from the first assert compulsion circuit, wherein control as to whether the second word line is activated is performed based on an output from the second assert compulsion circuit, wherein in the first operation mode, the first assert compulsion circuit outputs the output from the first address decoder as it is without compulsively asserting the output, and the second assert compulsion circuit outputs the output from the second address decoder as it is without compulsively asserting the output, and wherein in the second operation mode, the second assert compulsion circuit compulsively asserts and outputs the output from the second address decoder.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.40426
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15281947', '15606562', '15885449', '14504994', '13750328']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8346086375928486
- 35 USC 102 Novelty (BERT): 0.5909892417728164
- Combined Prediction Score: 0.8102466980108455
- Mean Citation Score: 330.520802
- Max Citation Score: 501.18726
- Similarity Product: 487.392943116517

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test