PATENT CLAIM ANALYSIS

Application Number: 15977712
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "315000"]

Abstract:
In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Claim (Index 8):
An integrated circuit, comprising:\n a floating gate flash bitcell comprising at least a control gate layer, a word line gate layer, and a dielectric layer; and a vertical capacitor disposed on a shallow trench isolation (STI) region, the vertical capacitor comprising the control gate layer, the word line gate layer, and the dielectric layer, the dielectric layer positioned between the control gate layer and the word line gate layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.31034
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15945552', '12109736', '11120118', '11246318', '13534865']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9087813481131314
- 35 USC 102 Novelty (BERT): 0.4735914269791762
- Combined Prediction Score: 0.8652623559997359
- Mean Citation Score: 166.48815
- Max Citation Score: 178.11575
- Similarity Product: 134.64046024015542

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test