PATENT CLAIM ANALYSIS

Application Number: 15870013
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["365", "051000"]

Abstract:
A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.

Claim (Index 19):
The memory of  claim 16 , wherein the global word line segment and the first local word line segment have same polarity signals.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 86.0
- Lexical Diversity: 3.20833
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10386400', '10663860', '10946295', '12687571', '12313487']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7849373333714162
- 35 USC 102 Novelty (BERT): 0.4884538737266557
- Combined Prediction Score: 0.7552889874069402
- Mean Citation Score: 205.722318
- Max Citation Score: 217.67867
- Similarity Product: 161.90880750251767

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test