PATENT CLAIM ANALYSIS

Application Number: 16224159
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "773000"]

Abstract:
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Claim (Index 13):
The inter-tier memory column of  claim 10 , comprising:\n a first bit line bar comprising:\n a first bar segment disposed within said first tier of said 3D IC; and \n a second bar segment horizontally offset from said first bar segment; and \n a second bit line bar comprising:\n a third bar segment disposed within said second tier of said 3D IC; and \n a fourth bar segment perpendicular to said third bar segment. \n wherein said horizontally offset second bar segment and said perpendicular fourth bar segment are connected by a vertical bit line.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 98.0
- Lexical Diversity: 2.58065
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15983786', '15379537', '14077252', '14673108', '14840364']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9210747335040916
- 35 USC 102 Novelty (BERT): 0.5116671516409589
- Combined Prediction Score: 0.8801339753177783
- Mean Citation Score: 262.518248
- Max Citation Score: 319.4898
- Similarity Product: 281.6462757550836

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test