PATENT CLAIM ANALYSIS

Application Number: 16451759
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["708", "190000"]

Abstract:
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.

Claim (Index 14):
The multiplier circuitry of  claim 12 , wherein first exponent has 5 bits.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 100.0
- Lexical Diversity: 1.80247
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15242923', '16039029', '15270495', '15390358', '14218113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5467302403110356
- 35 USC 102 Novelty (BERT): 0.5642596114129428
- Combined Prediction Score: 0.5484831774212263
- Mean Citation Score: 378.63944
- Max Citation Score: 470.81183
- Similarity Product: 280.1145590851635

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test