PATENT CLAIM ANALYSIS

Application Number: 15908175
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "148000"]

Abstract:
In a memory system, variable resistance circuits, such as transistor circuits, in the word line and bit line decoders are set during bias line set times and/or prior to turn-on times of read operations to increased resistance levels. The variable resistance circuits are kept at the increased resistance levels during an initial turn-on time period during which a selected memory cell may conducts a current spike. The increased resistance levels of the variable resistance circuit may operate to reduce or limit the width of the current spike. In response to the initial turn-on time period ending, the variable resistance circuits are set back to low resistance levels to facilitate subsequent sense results detection events and program operations.

Claim (Index 13):
The circuit of  claim 12 , wherein the first voltage level comprises an intermediate voltage level.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 1.95312
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13990187', '15858535', '13636169', '13380624', '13240492']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7762426249964722
- 35 USC 102 Novelty (BERT): 0.4824844076481273
- Combined Prediction Score: 0.7468668032616378
- Mean Citation Score: 182.537612
- Max Citation Score: 188.6388
- Similarity Product: 137.01940201706887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test