PATENT CLAIM ANALYSIS

Application Number: 15902399
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "185020"]

Abstract:
A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

Claim (Index 1):
A memory device comprising:\n a first memory string including a first memory cell, a second memory cell, a first select transistor above the first memory cell, a second select transistor below the second memory cell, and a third select transistor between the first memory cell and the second memory cell; a second memory string including a third memory cell, a fourth memory cell, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third memory cell and the fourth memory cell; a first word line electrically connected to a gate of the first memory cell and a gate of the third memory cell; a second word line electrically connected to a gate of the second memory cell and a gate of the fourth memory cell; and a controller configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase, wherein when a read target is one of the first memory cell and the second memory cell,\n during the first phase, a first voltage is applied to one of the first select transistor and the second select transistor, the third select transistor, and one of the fourth select transistor and the fifth select transistor, and a second voltage lower than the first voltage is applied to the sixth select transistor and the other one of the fourth select transistor and the fifth select transistor, and \n during the second phase, the first voltage is applied to the first select transistor, the second select transistor and the third select transistor, and the second voltage is applied to the fourth select transistor, the fifth select transistor, and the sixth select transistor.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 88.0
- Lexical Diversity: 3.70455
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15693407', '15061967', '13779427', '15457137', '14842637']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8189860518481157
- 35 USC 102 Novelty (BERT): 0.4869058014302431
- Combined Prediction Score: 0.7857780268063285
- Mean Citation Score: 258.225454
- Max Citation Score: 272.36438
- Similarity Product: 239.1724257958365

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test