PATENT CLAIM ANALYSIS

Application Number: 16100455
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["363", "021140"]

Abstract:
An external circuit element R SET  is connected in use to an SET terminal. A synchronous rectification controller generates a pulse signal Si based on a control time determined according to the state of the SET terminal. A driver switches on and off the synchronous rectification transistor according to the pulse signal S 1 . An abnormal state detection circuit is capable of detecting an open-circuit state and/or a short-circuit state that can occur in the SET terminal. When the abnormal state detection circuit detects such an open-circuit state and/or short-circuit state, the abnormal state detection circuit asserts a detection signal S 11 . When the detection signal S 11  is asserted, a primary-side controller arranged on the primary side of the DC/DC converter is instructed to suspend the switching operation of a switching transistor.

Claim (Index 32):
The semiconductor apparatus according to  claim 22 , wherein the semiconductor apparatus is coupled to transmit an assertion of the detection signal with a primary-side controller so as to instruct the primary-side controller to suspend a switching operation of a switching transistor.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 96.0
- Lexical Diversity: 2.13636
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15059445', '15638994', '16100467', '15845424', '14980508']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8607318271451245
- 35 USC 102 Novelty (BERT): 0.5374582441879929
- Combined Prediction Score: 0.8284044688494113
- Mean Citation Score: 350.329114
- Max Citation Score: 402.15256
- Similarity Product: 260.4001260632706

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test