PATENT CLAIM ANALYSIS

Application Number: 15893918
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["711", "122000"]

Abstract:
A processor includes a hierarchical cache memory having a higher-order cache memory and a lower-order cache memory. The hierarchical cache memory is in an inclusive state in which data stored in the higher-order cache memory is included in the lower-order cache memory. The processor also includes a cache hit determination unit configured to determine a cache hit/miss with respect to the higher-order cache memory and the lower-order cache memory at the time of accessing predetermined data, and a control unit configured to perform control to realize the inclusive state, based on the determination results of the cache hit/miss with respect to the higher-order cache memory and the lower-order cache memory.

Claim (Index 10):
the cache memory control device according to  claim 9 , wherein\n when a cache miss occurs in the lower-order cache memory, the cache hit determination unit determines that a cache miss occurs in the higher-order cache memory even though a cache hit occurs in the higher-order cache memory.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 2.55556
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12358873', '12958298', '13723345', '13433022', '13292651']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5177981697178525
- 35 USC 102 Novelty (BERT): 0.5058580497321339
- Combined Prediction Score: 0.5166041577192807
- Mean Citation Score: 239.82142400000004
- Max Citation Score: 250.78171
- Similarity Product: 180.24394297528383

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test