PATENT CLAIM ANALYSIS

Application Number: 16024223
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["257", "532000"]

Abstract:
Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Claim (Index 18):
The capacitor cell of  claim 11 , wherein the capacitor cell is vertically stacked and coupled to a capacitor cell in an adjacent semiconductor package substrate portion.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 1.775
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16017247', '15637969', '16015739', '15853330', '10634163']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917465278631933
- 35 USC 102 Novelty (BERT): 0.4778404910298113
- Combined Prediction Score: 0.8735027998717209
- Mean Citation Score: 142.21192200000004
- Max Citation Score: 166.53413
- Similarity Product: 119.96488007612408

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test