PATENT CLAIM ANALYSIS

Application Number: 15764662
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-07
Patent Classification: ["257", "072000"]

Abstract:
A display panel includes a plurality of scan lines and connection lines. The plurality of scan lines are spaced from each other. The connection lines are connected to end portions of the plurality of scan lines. The connection lines are formed of intrinsic silicon. By having the connection lines that are formed of intrinsic silicon connected with the end portions of all the scan lines, due to intrinsic silicon being almost electrically non-conductive, this does not affect stage by stage activation of the scan lines and provides a way of power consumption by large resistivity of intrinsic silicon for preventing static electricity on end portions of the scan lines thereby overcoming the issue of static electricity being easily caused on the end portions of the scan lines and thus enhancing product quality.

Claim (Index 11):
A manufacturing method of a display panel, comprising:\n Step  1 : providing a base plate, wherein the base plate comprises a display area and a non-display area; Step  2 : forming, in the non-display area, connection lines with intrinsic poly-silicon; Step  3 : forming, in the display area and the non-display area, a first dielectric insulation layer, the first dielectric insulation layer being arranged on the connection lines; Step  4 : forming, in the display area, a plurality of scan lines having end portions extending into the non-display area, the scan lines being arranged on the first dielectric insulation layer; Step  5 : forming, in the display area and the non-display area, a second dielectric insulation layer, the second dielectric insulation layer being arranged on a plurality of the scan lines and the first dielectric insulation layer; Step  6 : simultaneously forming, in the non-display area, a plurality of first vias and a plurality of second vias in the second dielectric insulation layer, such that each of the first vias exposes the end portion of a corresponding one of the scan lines and the plurality of second vias extend through the first dielectric insulation layer to expose the connection lines; and Step  7 : forming, in the non-display area, a plurality of connection conductor layers on the second dielectric insulation layer, each of the connection conductor layers being set in contact and thus connection with the end portion of a corresponding one of the scan lines by way of a corresponding one of the first vias, each of the connection conductor layers being set in contact and connection with the connection lines by way of a corresponding one of the second vias.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 90.0
- Lexical Diversity: 2.17188
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15570366', '15397710', '15836934', '15694861', '12634700']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9084308904626618
- 35 USC 102 Novelty (BERT): 0.4928785566200623
- Combined Prediction Score: 0.8668756570784019
- Mean Citation Score: 183.25487200000003
- Max Citation Score: 192.78569
- Similarity Product: 127.55983516014696

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test