PATENT CLAIM ANALYSIS

Application Number: 15881022
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "774000"]

Abstract:
A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

Claim (Index 14):
The semiconductor package of  claim 12 , further comprising a delamination of the low-k dielectric layers within a first region encompassed by the first seal ring structure, the delamination not extending beyond the first seal ring structure.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 3.51351
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12915170', '12953130', '14730231', '13712665', '15232959']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9098104577759132
- 35 USC 102 Novelty (BERT): 0.4929652289010831
- Combined Prediction Score: 0.8681259348884302
- Mean Citation Score: 169.65573200000003
- Max Citation Score: 172.6217
- Similarity Product: 106.60280101735592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test