PATENT CLAIM ANALYSIS

Application Number: 16265110
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "401000"]

Abstract:
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Claim (Index 12):
A semiconductor structure, comprising:\n a feature defined by a first trench and a second trench in a semiconductor material; a first liner, a first epitaxial growth, and a first insulator material in the first trench; and a second liner, a second epitaxial growth, and a second insulator material in the second trench.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 99.0
- Lexical Diversity: 2.70213
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15182048', '15417597', '15813277', '14750013', '16115967']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9216437658591634
- 35 USC 102 Novelty (BERT): 0.5448054570592837
- Combined Prediction Score: 0.8839599349791755
- Mean Citation Score: 364.81540200000006
- Max Citation Score: 388.9918
- Similarity Product: 318.76049788308137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test