PATENT CLAIM ANALYSIS

Application Number: 15919480
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185170"]

Abstract:
A semiconductor memory device according to an embodiment includes: first to 32nd memory cells; first to 16th bit lines connected to the first to 16th memory cells; 17th to 32nd bit lines connected to the 17th to 32nd memory cells; a first word line connected to gates of the first to 32nd memory cells; first to 16th sense amplifiers configured to determine data read from the first to 16th memory cells at a first timing; and 17th to 32nd sense amplifiers configured to determine data read from the 17th to 32nd memory cells at a second timing. The first timing is different from the second timing.

Claim (Index 16):
The device according to  claim 15 , further comprising a delay circuit configured to generate a second signal by delaying a first signal in the first read mode,\n wherein the first sense amplifier determines the data based on the first signal, and the second sense amplifier determines the data based on the second signal.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 90.0
- Lexical Diversity: 2.85
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15195560', '15911383', '15583609', '11819583', '13784735']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8025945234728437
- 35 USC 102 Novelty (BERT): 0.4886156876862284
- Combined Prediction Score: 0.7711966398941821
- Mean Citation Score: 229.728334
- Max Citation Score: 236.79633
- Similarity Product: 167.04987602634787

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test