PATENT CLAIM ANALYSIS

Application Number: 16281416
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["710", "105000"]

Abstract:
Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.

Claim (Index 3):
The method of  claim 1 , further comprising:\n receiving, by the filtering layer, a second input associated with the core logic layer, the second input not being a part of the one or more predefined inputs; and transmitting, by the filtering layer, the second input to the core logic layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 99.0
- Lexical Diversity: 2.01852
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15182005', '11712380', '11566573', '13304681', '11767385']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6526691654321193
- 35 USC 102 Novelty (BERT): 0.5097342055325911
- Combined Prediction Score: 0.6383756694421665
- Mean Citation Score: 160.80436920000002
- Max Citation Score: 277.17657
- Similarity Product: 173.22402283645752

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test