PATENT CLAIM ANALYSIS

Application Number: 16234970
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-12
Patent Classification: ["327", "306000"]

Abstract:
A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sampling node, respectively, in response to the second clock is at the second logic level; and an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock is at the second logic level.

Claim (Index 8):
A signal receiver circuit, comprising:\n a negative voltage applier suitable for applying a negative voltage or a ground voltage to a common source node in response to a first clock; a first sampling NMOS transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling NMOS transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock; a first precharge PMOS transistor having a gate receiving a second clock, a source coupled to a pull-up voltage terminal, and a drain coupled to a first output node; a second precharge PMOS transistor having a gate receiving the second clock, a source coupled to the pull-up voltage terminal, and a drain coupled to a second output node; a first blocking NMOS transistor having a gate receiving the second clock, a source coupled to the first sampling node, and a drain coupled to the second output node; and a second blocking NMOS transistor having a gate receiving the second clock, a source coupled to the second sampling node, and a drain coupled to the first output node; and an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock, wherein the second clock is an inverted and delayed clock of the first clock, and the first clock and the second clock have the same logic level in a first period and a second period, and the first clock and the second clock have different logic levels in a third period and a fourth period.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 4.43396
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13234811', '12381360', '14175220', '14569178', '11095187']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7797235234678754
- 35 USC 102 Novelty (BERT): 0.4864609837309107
- Combined Prediction Score: 0.750397269494179
- Mean Citation Score: 239.129026
- Max Citation Score: 258.27484
- Similarity Product: 214.9986666981673

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test