PATENT CLAIM ANALYSIS

Application Number: 16077087
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["327", "156000"]

Abstract:
A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.

Claim (Index 9):
The circuit of  claim 8 , wherein the error signal estimator is configured to estimate a jitter gain as estimated error amplitude.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 96.0
- Lexical Diversity: 2.21053
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10776926', '10925870', '11453282', '11284799', '15057858']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7706279974116943
- 35 USC 102 Novelty (BERT): 0.4653621738008179
- Combined Prediction Score: 0.7401014150506068
- Mean Citation Score: 151.90065800000005
- Max Citation Score: 162.73288
- Similarity Product: 124.42310261042591

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test