PATENT CLAIM ANALYSIS

Application Number: 16042949
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["327", "143000"]

Abstract:
Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Claim (Index 13):
The circuit of  claim 12 , wherein the multiple inversion stages include a first inversion stage, a second inversion stage, and a third inversion stage that are arranged in series, wherein an output of the first inversion stage is provided as input to the second inversion stage, and wherein an output of the second inversion stage is provided as input to the third inversion stage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 2.03571
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15143197', '12134309', '11849296', '15657406', '13491622']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7726087584773859
- 35 USC 102 Novelty (BERT): 0.5075518954344638
- Combined Prediction Score: 0.7461030721730937
- Mean Citation Score: 181.270854
- Max Citation Score: 258.23938
- Similarity Product: 163.2860886837005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test