PATENT CLAIM ANALYSIS

Application Number: 15898571
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "390000"]

Abstract:
A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of first memory pillar structures, each containing a memory element, overlying top surfaces of the first conductive rails, second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures, and a one-dimensional array of first cavities free of solid material portions therein, laterally extending along the second horizontal direction and located between neighboring pairs of the second conductive rails.

Claim (Index 24):
A memory device, comprising:\n first conductive rails laterally extending along a first horizontal direction over a substrate; a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, wherein each first memory pillar structure comprises a respective memory element; second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures; a one-dimensional array of first cavities free of solid material portions therein laterally extending along the second horizontal direction and located between neighboring pairs of the second conductive rails; a rectangular array of second memory pillar structures overlying top surfaces of the second conductive rails, wherein each second memory pillar structure comprises a series connection of a respective second selector element and a respective second memory element; and a rectangular array of dielectric isolation pillars located between each neighboring pair of second memory pillar structures spaced along the first horizontal direction, wherein: each first memory pillar structure comprises a series connection of a respective first selector element and a respective first memory element; each of the first cavities has a vertical cross-sectional shape within a vertical plane that is perpendicular to the first horizontal direction; a top portion of the vertical cross-sectional shape includes two vertically protruding regions laterally spaced by a vertically recessed region; the vertical cross-sectional shape is entirely enclosed by an inner surface of at least one dielectric liner located between a respective neighboring pair of second conductive rails and between a respective pair of neighboring rows of the first memory pillar structures that are spaced apart along the first horizontal direction; each first cavity underlies a respective one of the dielectric isolation pillars; each of the dielectric isolation pillars includes a pair of concave bottom surfaces that laterally extend along the second horizontal direction and a downward-protruding portion located between the pair of concave bottom surfaces; and each pair of concave bottom surfaces of the dielectric isolation pillars contacts a respective one of the at least one dielectric liners.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.33333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15888645', '15844005', '15793178', '15715532', '15603989']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9377401560445804
- 35 USC 102 Novelty (BERT): 0.5531903873640472
- Combined Prediction Score: 0.8992851791765272
- Mean Citation Score: 399.677738
- Max Citation Score: 447.13647
- Similarity Product: 326.5403301453494

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test