PATENT CLAIM ANALYSIS

Application Number: 15876530
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "401000"]

Abstract:
Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

Claim (Index 16):
The method of  claim 12  wherein the first airgap is arranged inside a cavity in the first semiconductor layer, and further comprising:\n etching one or more openings extending through the first semiconductor layer and the second semiconductor layer; and \n recessing the first semiconductor layer relative to each of the one or more openings with an isotropic etching process that removes the first semiconductor layer selective to the second semiconductor layer and thereby forms the cavity.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 86.0
- Lexical Diversity: 2.18421
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14083769', '15694109', '15869349', '15479801', '15427403']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9129506762911122
- 35 USC 102 Novelty (BERT): 0.4788101297491011
- Combined Prediction Score: 0.869536621636911
- Mean Citation Score: 192.593014
- Max Citation Score: 198.55922
- Similarity Product: 151.3318482837081

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test