PATENT CLAIM ANALYSIS

Application Number: 16039975
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "324000"]

Abstract:
The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

Claim (Index 1):
A semiconductor memory device, comprising:\n a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction; a logic circuit on the upper surface of the substrate, the logic circuit comprising a first page buffer and a second page buffer; a memory cell array on the logic circuit opposite the substrate, the memory cell array comprising:\n a semiconductor layer; \n a pair of stack structures spaced apart from each other in the second direction, respective ones of the pair of stack structures comprising a plurality of electrodes that are stacked on the semiconductor layer; \n a first bit line and a second bit line on the pair of stack structures, the first and second bit lines extending in the second direction and being adjacent to each other in the first direction; and \n an isolation insulating layer extending in the first direction, the isolation insulating layer between the pair of stack structures; \n an upper insulating layer on the pair of stack structures; a first connection contact penetrating the upper insulating layer and the semiconductor layer to electrically connect the first bit line to the first page buffer; and a second connection contact penetrating the isolation insulating layer and the semiconductor layer to electrically connect the second bit line to the second page buffer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.53191
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14989955', '14523977', '15087127', '16021775', '14735811']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9167056058587612
- 35 USC 102 Novelty (BERT): 0.5196683908958384
- Combined Prediction Score: 0.8770018843624691
- Mean Citation Score: 243.336852
- Max Citation Score: 337.9989
- Similarity Product: 298.6457940199972

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test