PATENT CLAIM ANALYSIS

Application Number: 15914913
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["375", "233000"]

Abstract:
A continuous time linear equalization (CTLE) system is provided. The CTLE system includes a first adjustable circuit comprising a first adjustable resistive-capacitive (RC) source degeneration circuit and a first differential amplifier stage circuit. The CTLE system also includes a second adjustable circuit electrically coupled to the first adjustable circuit and configured to adjust a frequency suppression of a data signal received by the CTLE system. The CTLE system is configured to provide a gain-versus-frequency curve for the data signal based on adjustments to the first adjustable circuit, adjustments to the second adjustable circuit, or a combination thereof.

Claim (Index 4):
The system of  claim 2 , wherein the second adjustable circuit comprises a second differential amplifier stage circuit having the second differential pair of transistors, wherein the data signal is configured to be received by both the first differential amplifier stage circuit and by the second differential amplifier stage circuit.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 90.0
- Lexical Diversity: 2.01887
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14925720', '14633866', '15170751', '14057945', '15597074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4991889019828106
- 35 USC 102 Novelty (BERT): 0.4759789576583163
- Combined Prediction Score: 0.4968679075503611
- Mean Citation Score: 181.296348
- Max Citation Score: 195.79259
- Similarity Product: 154.83056969663318

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test