PATENT CLAIM ANALYSIS

Application Number: 16058550
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "043000"]

Abstract:
A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , group IIIA-nitrides, semiconductor oxides, and any combination thereof.

Claim (Index 44):
The method of  claim 41  wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

Metadata:
- Claim Count in Document: 152.0
- Percentile: 96.0
- Lexical Diversity: 1.89091
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15112083', '15675001', '14524693', '15526640', '15984586']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9380842167329806
- 35 USC 102 Novelty (BERT): 0.5657029091964858
- Combined Prediction Score: 0.9008460859793312
- Mean Citation Score: 361.94157600000005
- Max Citation Score: 447.93643
- Similarity Product: 399.0563201270306

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test