PATENT CLAIM ANALYSIS

Application Number: 16143013
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["711", "154000"]

Abstract:
Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical pre-fetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level pre-fetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.

Claim (Index 17):
The method of  claim 16 , wherein the first processing core is in a first core cluster of the multicore processor, and wherein the second processing core is in a second core cluster of the multicore processor.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 97.0
- Lexical Diversity: 1.67033
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15370440', '14706213', '13269462', '12914135', '15340949']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5144205499072396
- 35 USC 102 Novelty (BERT): 0.6048085481506507
- Combined Prediction Score: 0.5234593497315807
- Mean Citation Score: 243.649198
- Max Citation Score: 566.38257
- Similarity Product: 467.46664853310943

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test