PATENT CLAIM ANALYSIS

Application Number: 16116734
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "776000"]

Abstract:
A semiconductor package may include: a plurality of slave chips stacked over a master chip through a through silicon via (TSV); a first guard unit disposed around each of the slave chips; and a second guard unit formed at a first distance from the first guard unit and disposed at the master chip.

Claim (Index 1):
A semiconductor package comprising:\n a first chip; a plurality of second chips sequentially stacked over the first chip and each of the second chips having a smaller size than the first chip; a first guard unit positioned under the each of the second chips, the first guard unit including an extension pad which expands the size of the each of the second chips to the size of the first chip, and a vertical guard ring for contacting an outer edge of a backside of the each of the second chips with an inner edge of the extension pad; and a second guard unit positioned at an outer edge of the first guard unit, to be parallel with the vertical guard ring, wherein the second guard unit is connected between the extension pad which is formed on a bottom second chip and the extension pad which is formed on an upper second chip.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 1.63889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15462039', '14804880', '14150092', '14064110', '12941640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9217068531367624
- 35 USC 102 Novelty (BERT): 0.4746695599979435
- Combined Prediction Score: 0.8770031238228806
- Mean Citation Score: 174.901976
- Max Citation Score: 242.77931
- Similarity Product: 231.76835295133952

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test