PATENT CLAIM ANALYSIS

Application Number: 15919805
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["710", "316000"]

Abstract:
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Claim (Index 7):
The slave device according to  claim 6 , wherein the selection module comprises an output producer configured to produce the selection module output signal depending on the first low voltage output data signal and the second low voltage output data signal, and wherein the selection module comprises a selection control timing module configured to provide a selection control signal for the output producer, which depends on the low voltage address signal, the medium voltage data signal and the medium voltage clock signal.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14848472', '14028806', '11715478', '10764406', '14217510']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6489207815509995
- 35 USC 102 Novelty (BERT): 0.5668055665208671
- Combined Prediction Score: 0.6407092600479863
- Mean Citation Score: 245.13131600000008
- Max Citation Score: 441.9628
- Similarity Product: 385.1295181511641

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test