PATENT CLAIM ANALYSIS

Application Number: 16026890
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["710", "071000"]

Abstract:
An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.

Claim (Index 14):
The integrated circuit of  claim 13 , wherein:\n the first DDR shift register is driven by a phase locked loop (PLL) clock (pllclk_ 0 ) and a complementary clock (pllclk_ 180 ) of the PLL clock (pllclk_ 0 ); and the second DDR shift register is driven by an offset clock (pllclk_ 90 ) that is a 90 degree offset of the phase locked loop (PLL) clock (pllclk_ 0 ) and a complementary clock (pllclk_ 240 ) of the offset clock (pllclk_ 90 ).

Metadata:
- Claim Count in Document: 25.0
- Percentile: 95.0
- Lexical Diversity: 1.76596
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15606194', '15730552', '10613462', '15410602', '13616173']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6796591472271933
- 35 USC 102 Novelty (BERT): 0.5406535868374828
- Combined Prediction Score: 0.6657585911882223
- Mean Citation Score: 213.085498
- Max Citation Score: 390.28427
- Similarity Product: 368.6542112041873

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test