PATENT CLAIM ANALYSIS

Application Number: 15906098
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["257", "693000"]

Abstract:
A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.

Claim (Index 20):
The semiconductor package structure as claimed in  claim 12 , further comprising:\n a stress buffer layer filled into the holes, wherein the stress buffer layer is made of a polymer material.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 3.1
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15203418', '15700220', '15418896', '15841667', '15335226']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9112356924050384
- 35 USC 102 Novelty (BERT): 0.4970235058427346
- Combined Prediction Score: 0.8698144737488079
- Mean Citation Score: 190.61645600000003
- Max Citation Score: 199.84378
- Similarity Product: 125.7258126189828

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test