PATENT CLAIM ANALYSIS

Application Number: 15777117
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "043000"]

Abstract:
Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Claim (Index 3):
The semiconductor device of  claim 2 , wherein the gate dielectric contacts the sidewall surfaces and the planar surface.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 2.32353
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14757875', '15748842', '14138750', '14133521', '14135534']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9253513546581316
- 35 USC 102 Novelty (BERT): 0.4908076679741529
- Combined Prediction Score: 0.8818969859897337
- Mean Citation Score: 222.437254
- Max Citation Score: 239.56726
- Similarity Product: 189.6130673540724

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test