PATENT CLAIM ANALYSIS

Application Number: 15924584
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["331", "002000"]

Abstract:
Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.

Claim (Index 6):
A circuit, comprising:\n an input receiving a reference signal having an input frequency; an oscillator configured to generate an intermediate signal having a frequency intended to be a geometric mean of the input frequency and a desired output frequency; a controllable oscillator; an oscillator control circuit configured to generate an oscillator control signal for the controllable oscillator; a phase locked loop (PLL) coupled to the input and to the oscillator control circuit, the PLL utilizing the controllable oscillator and controlling the oscillator control circuit to cause multiplication of the input frequency by a PLL loop division number; calibration logic coupled to the input and to the oscillator, the calibration logic configured to count a number of cycles of an actual frequency of the intermediate signal in the input frequency, and to generate a new loop division number by dividing the PLL loop division number by the count; a frequency locked loop (FLL) coupled to the calibration logic, the FLL utilizing the controllable oscillator and controlling the oscillator control circuit to cause multiplication of the frequency of the intermediate signal by a FLL loop division number; a switch coupling the PLL to the oscillator control circuit when the FLL achieves lock.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.75
- Patent Class: 331.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15251570', '15718715', '15471483', '11854917', '12981619']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7489137224829011
- 35 USC 102 Novelty (BERT): 0.5257075241256912
- Combined Prediction Score: 0.7265931026471801
- Mean Citation Score: 296.9770680000001
- Max Citation Score: 336.89383
- Similarity Product: 284.79810794169424

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test