PATENT CLAIM ANALYSIS

Application Number: 16140066
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["365", "233100"]

Abstract:
A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

Claim (Index 4):
The memory controller of  claim 3 , wherein a frequency of the reference clock signal is identical to a frequency of the first data strobe signal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 97.0
- Lexical Diversity: 2.71111
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14573379', '15787101', '12044174', '16103244', '13477642']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8112509283834589
- 35 USC 102 Novelty (BERT): 0.4731374521809098
- Combined Prediction Score: 0.777439580763204
- Mean Citation Score: 199.422098
- Max Citation Score: 204.21288
- Similarity Product: 158.8726782090569

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test