PATENT CLAIM ANALYSIS

Application Number: 15937863
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "103000"]

Abstract:
A data reading method and a storage controller for a rewritable non-volatile memory module are provided. The method includes identifying a plurality of preset bit values corresponding to a plurality of first memory cells of a first physical unit; reading the first memory cells by respectively using a plurality of preset read voltages to obtain a plurality of read bit values corresponding to the first memory cells; adjusting the preset read voltages based on the identified preset bit values and the read bit values corresponding to the first memory cells to obtain a plurality of optimized read voltages; and executing a read command sequence on the first physical unit by using the optimized read voltages.

Claim (Index 6):
A storage controller, configured to control a storage apparatus having a rewritable non-volatile memory module, wherein the storage controller comprises:\n a connection interface circuit, configured to be coupled to a host system; a memory interface control circuit, configured to be coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, and each of the physical units comprises a plurality of memory cells; and a processor, coupled to the connection interface circuit and the memory interface control circuit, wherein the processor is configured to choose a first physical unit of the physical units and identify a plurality of preset bit values of a plurality of first memory cells of the first physical unit, wherein the preset bit values comprise a plurality of different storage statuses that each of all of the memory cells of the rewritable non-volatile memory module is able to exhibit; wherein the processor is further configured to read the first memory cells by respectively using a plurality of preset read voltages of a preset read voltage set, so as to obtain a plurality of read bit values corresponding to the first memory cells, a total number of the preset read voltages is a total number of the storage statuses minus 1, and the preset read voltages are set to respectively distinguish between the storage statuses; wherein the processor is further configured to adjust the preset read voltages of the preset read voltage set based on the read bit values and the identified preset bit values corresponding to the first memory cells, so as to obtain an optimized read voltage set; and wherein the processor is further configured to instruct the memory interface control circuit to execute a read command sequence on the first physical unit by using the optimized read voltage set.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.6087
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15472293', '14018436', '13108004', '15867719', '13901571']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5552151133732792
- 35 USC 102 Novelty (BERT): 0.4815362299872925
- Combined Prediction Score: 0.5478472250346805
- Mean Citation Score: 217.003258
- Max Citation Score: 226.62685
- Similarity Product: 184.51060834009945

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test