PATENT CLAIM ANALYSIS

Application Number: 15977910
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["341", "172000"]

Abstract:
A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

Claim (Index 10):
A device comprising:\n a circuit ground; a plurality of capacitors to sample an analog input signal; a comparator having a first input, a second input and an output wherein the first input is coupled to the plurality of capacitors, wherein the comparator converts the sampled analog input signal into a digital signal; a plurality of switches to connect the plurality of capacitors to the ground to reset the plurality of capacitors; wherein when the plurality of capacitors is reset to ground, the second input of the comparator is directly coupled to the output of the comparator.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 93.0
- Lexical Diversity: 1.91304
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12199803', '14576315', '14490831', '15261643', '15007368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6012354378115708
- 35 USC 102 Novelty (BERT): 0.5034886136682134
- Combined Prediction Score: 0.5914607553972352
- Mean Citation Score: 249.634278
- Max Citation Score: 258.5641
- Similarity Product: 195.1967530333757

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test