PATENT CLAIM ANALYSIS

Application Number: 15937742
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["257", "444000"]

Abstract:
Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder bumps.

Claim (Index 5):
A photosensor integrated circuit comprising:\n a first semiconductor substrate comprising transistors; a plurality of metal layers separated by dielectric layers formed on a first surface of the semiconductor substrate; a plurality of structures formed of at least a shape on a first metal layer of the plurality of metal layers; a plurality of vias formed through the semiconductor substrate a plurality of conductive plugs each formed in a respective one of the plurality of vias, each of the conductive plugs coupled to a shape on the first metal layer; a dielectric formed over a second surface of the semiconductor substrate and sidewalls of the vias, interconnect metal deposited over the dielectric, the interconnect metal forming connection shapes, each connection shape electrically coupled to a conductive plug; and a plurality of solder bumps deposited onto connection shapes of the conductive interconnect layer; wherein each conductive plug is disposed between a connection shape of the connection shapes and a structure of the plurality of structures formed of at least a shape on the first metal layer, the conductive plugs electrically coupling the connection shape to the structure.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.35714
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14528325', '13561868', '13561811', '10360845', '11059825']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.915777402494536
- 35 USC 102 Novelty (BERT): 0.4742462665519482
- Combined Prediction Score: 0.8716242889002773
- Mean Citation Score: 208.14608200000004
- Max Citation Score: 218.75296
- Similarity Product: 186.58444555233

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test