PATENT CLAIM ANALYSIS

Application Number: 16019916
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["438", "212000"]

Abstract:
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material. The first nanosheet FET structure is formed by creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region. The second nanosheet FET structure is formed by creating a second inner spacer formation within a second SiGe channel, wherein the second SiGe channel is comprised in a second channel region of a second FET region.

Claim (Index 13):
The method of  claim 12 , wherein the first and second gates are comprised of polysilicon, and wherein replacing the first and second gates comprises removing the first and second gates via a polysilicon pull process.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 3.09091
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15690601', '15465989', '15260509', '15465962', '15852111']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8947342691793673
- 35 USC 102 Novelty (BERT): 0.5878556223452849
- Combined Prediction Score: 0.864046404495959
- Mean Citation Score: 439.16788
- Max Citation Score: 502.7277
- Similarity Product: 439.0889218783558

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test