PATENT CLAIM ANALYSIS

Application Number: 16014025
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "760000"]

Abstract:
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Claim (Index 8):
The method of  claim 6 , wherein the etch resistant dielectric is a nitride.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 94.0
- Lexical Diversity: 2.40426
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15229470', '16014020', '15992685', '15971783', '14041187']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913878826656848
- 35 USC 102 Novelty (BERT): 0.5442207062133145
- Combined Prediction Score: 0.8769130146124946
- Mean Citation Score: 269.414558
- Max Citation Score: 377.43085
- Similarity Product: 266.5060329731166

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test