PATENT CLAIM ANALYSIS

Application Number: 16038052
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-04
Patent Classification: ["257", "296000"]

Abstract:
Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Claim (Index 8):
The semiconductor memory device of  claim 7 , further comprising a second supporting layer that is between the first end portion and the second end portion of the first electrode and is configured to structurally support the first electrode.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.75
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15708266', '15259941', '14735811', '15245218', '13366818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9042602465550948
- 35 USC 102 Novelty (BERT): 0.509187795427132
- Combined Prediction Score: 0.8647530014422986
- Mean Citation Score: 236.367428
- Max Citation Score: 247.97386
- Similarity Product: 167.6409710070777

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test