PATENT CLAIM ANALYSIS

Application Number: 16038738
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "222000"]

Abstract:
In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.

Claim (Index 10):
The memory controller of  claim 1 , wherein the arbiter comprises a plurality of sub-arbiters for selectively picking accesses based on sub-arbitrations, wherein one sub-arbitration is a page hit and each other sub-arbitration is not a page hit.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 2.58621
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15408126', '15164721', '15211815', '15272626', '15252889']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8015768101441568
- 35 USC 102 Novelty (BERT): 0.5192918137135717
- Combined Prediction Score: 0.7733483105010983
- Mean Citation Score: 279.052524
- Max Citation Score: 310.9701
- Similarity Product: 210.5488845030605

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test