PATENT CLAIM ANALYSIS

Application Number: 16174152
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["257", "365000"]

Abstract:
A 3D semiconductor device, the device including: a first layer including first transistors each including a first silicon channel; a second layer including second transistors each including a second silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer overlying the second transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistors are junction-less transistors.

Claim (Index 9):
The 3D semiconductor device according to  claim 8 ,\n wherein said second layer thickness is less than one micron.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 2.83673
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15862616', '15201430', '14555494', '15351389', '15803732']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9337837433614662
- 35 USC 102 Novelty (BERT): 0.5382359756431385
- Combined Prediction Score: 0.8942289665896335
- Mean Citation Score: 343.951076
- Max Citation Score: 381.8541
- Similarity Product: 360.14714491841187

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test