PATENT CLAIM ANALYSIS

Application Number: 16032675
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Claim (Index 19):
A resistance switching memory-based accelerator configured to be connected to a host including a central processing unit (CPU) and a system memory, the resistance switching memory-based accelerator comprising:\n a resistance switching memory module that stores a kernel offloaded from the host and includes a memory cell array including a plurality of resistance switching memory cells; an accelerator core including a plurality of processing elements, the kernel being executed by a target processing element among the plurality of processing elements; a memory controller unit (MCU) that manages memory requests generated in accordance with execution of the kernel by the target processing element; a memory controller that is connected to the resistance switching memory module, allows data according to the memory request to move between the resistance switching memory module and the target processing element in accordance with the memory request transferred from the MCU, and programs predetermined data for addresses of the memory cell array to be overwritten by the execution of the kernel. a network that integrates the accelerator core, the plurality of processing elements, and the memory controller.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 95.0
- Lexical Diversity: 2.75862
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14191182', '14877807', '15208903', '15605661', '15134068']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4937922898973794
- 35 USC 102 Novelty (BERT): 0.483112869365347
- Combined Prediction Score: 0.4927243478441761
- Mean Citation Score: 170.12736999999996
- Max Citation Score: 177.97249
- Similarity Product: 125.72560788036824

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test