PATENT CLAIM ANALYSIS

Application Number: 15906998
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "201000"]

Abstract:
The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.

Claim (Index 27):
The method of  claim 26 , further comprising:\n setting \u0394T to the rising edge of the clock signal in response to a determination that \u0394T is greater than the rising edge of the clock signal.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 88.0
- Lexical Diversity: 2.32075
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11165853', '15850744', '15787101', '14997268', '15790896']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7747261124508189
- 35 USC 102 Novelty (BERT): 0.4930430412715621
- Combined Prediction Score: 0.7465578053328933
- Mean Citation Score: 163.52646199999995
- Max Citation Score: 168.04543
- Similarity Product: 94.99510794771255

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test