PATENT CLAIM ANALYSIS

Application Number: 15976706
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "180000"]

Abstract:
This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

Claim (Index 11):
The method of  claim 8  wherein the plurality of first lines comprise word lines connected to anodes of the thyristor memory cells, the plurality of second lines comprise bit lines connected to cathodes of the thyristor memory cells, and the plurality of third lines capacitively coupled to P base regions of the thyristor memory cells.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 93.0
- Lexical Diversity: 1.51111
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14590834', '14740186', '14607023', '15216652', '14740209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7966996180410847
- 35 USC 102 Novelty (BERT): 0.5005058213274478
- Combined Prediction Score: 0.7670802383697211
- Mean Citation Score: 255.32215399999995
- Max Citation Score: 272.45346
- Similarity Product: 216.96308437826875

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test