PATENT CLAIM ANALYSIS

Application Number: 15744791
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["345", "055000"]

Abstract:
A scan driving circuit and a display panel are disclosed. A scan driving unit includes a pull-up control circuit configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node. A first reset circuit receives an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage. A pull-down holding circuit receives a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node. A pull-down circuit receives a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node. A pull-up circuit receives the first clock signal to output a stage transmission signal and a scan driving signal of the current stage.

Claim (Index 1):
A scan driving circuit having a plurality of cascaded scan driving units, wherein each scan driving unit comprises:\n a pull-up control circuit comprising a first controllable switch, configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node; a first reset circuit, coupled to the pull-up control circuit, configured for receiving an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage; a pull-down holding circuit, coupled to the pull-up control circuit, configured for receiving a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node; a pull-down circuit, coupled to the pull-up control circuit, configured for receiving a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node; and a pull-up circuit, coupled to the pull-up control circuit, the pull-down holding circuit and the pull-down circuit, configured for receiving the first clock signal to output a stage transmission signal and a scan driving signal of the current stage; wherein if the input signal of the first reset circuit is the first low frequency clock signal, the scan driving circuit further comprises: a second reset circuit, coupled to the pull-up control circuit and the first reset circuit, configure for receiving the second low frequency clock signal, the first clock signal and the second clock signal to reset the pull-up control signal node, wherein the first reset circuit and the second reset circuit are alternately derived according to the first low frequency clock signal or the second low frequency clock signal; wherein the first reset circuit comprises a second controllable switch, a third controllable switch, a fourth controllable switch and a first reset switch; a control end of the second controllable switch coupled to a first end of the second controllable switch receives the input signal; a control end of the first reset switch, a first end of the third controllable switch and a first end of the fourth controllable switch are coupled to a second end of the second controllable switch; a control end of the third controllable switch receives the second clock signal and a control end of the fourth controllable switch receives the first clock signal; the second end of the first controllable switch and the second reset circuit are coupled to a first end of the first reset switch; second ends of the third controllable switch, the fourth controllable switch and the first reset switch are coupled to a first voltage terminal; the second reset circuit comprises a fifth controllable switch, a sixth controllable switch, a seventh controllable switch and a second reset switch; a control end of the fifth controllable switch coupled to a first end of the fifth controllable switch receives the second low frequency clock signal; a control end of the second reset switch, the first end of the sixth controllable switch and a first end of the seventh controllable switch are coupled to a second end of the fifth controllable switch; a control end of the sixth controllable switch receives the second clock signal; a control end of the seventh controllable switch receives the first clock signal; a second end of the second reset switch is coupled to the second end of the first controllable switch; second ends of the sixth controllable switch, the seventh controllable switch and the second reset switch are coupled to the first voltage terminal.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 86.0
- Lexical Diversity: 2.90566
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15326952', '15189468', '15557443', '14398975', '14398744']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6738061890649742
- 35 USC 102 Novelty (BERT): 0.5014365936926157
- Combined Prediction Score: 0.6565692295277384
- Mean Citation Score: 278.24575600000003
- Max Citation Score: 282.22134
- Similarity Product: 230.1751431835592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test