PATENT CLAIM ANALYSIS

Application Number: 15897550
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185220"]

Abstract:
Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Claim (Index 21):
A system, comprising:\n a controller; a substrate; a NAND chain comprising a select gate transistor, a dummy memory cell adjacent to the select gate transistor and a data memory cell, a bottom of the NAND chain is in contact with the substrate; a first voltage driver connected to the substrate; a second voltage driver connected to the dummy memory cell; and a third voltage driver connected to the data memory cell; the controller, in response to an erase command for the data memory cell, is configured to instruct the first voltage driver to apply an erase pulse to the substrate, instruct the second voltage driver to apply a control gate voltage to the dummy memory cell at a level which causes erasing while the erase pulse is applied to the substrate, and instruct the third voltage driver to apply a control gate voltage to the data memory cell at a level which causes erasing while the erase pulse is applied to the substrate, and after the erase pulse is applied to the substrate, the controller is configured to apply a control gate voltage to the dummy memory cell at a level which causes programming.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 2.14493
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14612561', '15816546', '14612601', '15163171', '15693982']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8225240730150981
- 35 USC 102 Novelty (BERT): 0.5060342555662871
- Combined Prediction Score: 0.7908750912702169
- Mean Citation Score: 312.745902
- Max Citation Score: 316.5821
- Similarity Product: 249.2790122061968

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test