PATENT CLAIM ANALYSIS

Application Number: 16018571
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "185030"]

Abstract:
A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered. This helps to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. The transition of the memory cell from off to on is also improved.

Claim (Index 17):
A method comprising:\n applying, by a row decoder circuit, a second read voltage to a selected word line coupled to a set of memory cells after a first read voltage in a sequential read operation, the second read voltage higher than the first read voltage; sinking, by a memory cell associated with the selected word line, a cell current into a source during a transition of the memory cell from a non-conductive state to a conductive state in response to the second read voltage; pulling down a voltage of a selected bit line coupled to the memory cell in response to sinking the cell current; and while pulling down the voltage of the selected bit line,\n lowering, by a current sense circuit, a control gate voltage of a bit line control transistor coupled to the selected bit line, from a first level to a second level, to reduce a bleeding current from the current sense circuit flowing into the selected bit line, the reduced bleeding current shortening a settling time of the voltage of the selected bit line, and \n raising, by the current sense circuit, the control gate voltage of the bit line control transistor, from the second level to the first level, before performing current sensing with respect to a level of the cell current sunk into the source by the memory cell.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 2.21918
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11136369', '12385198', '12499237', '16018018', '10867679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8252270567545451
- 35 USC 102 Novelty (BERT): 0.5014590998240589
- Combined Prediction Score: 0.7928502610614965
- Mean Citation Score: 256.809304
- Max Citation Score: 272.8812
- Similarity Product: 218.3182517473697

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test