PATENT CLAIM ANALYSIS

Application Number: 15871142
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["711", "103000"]

Abstract:
A NAND flash memory including a control unit which includes a signal receiving circuit and a flash array; the signal receiving circuit is used to receive a cache read command from an external NAND controller; the flash array includes at least one chip, each chip includes at least one plane, each plane includes a plurality of blocks, each block includes a plurality of pages; when a cache read command is received, it reads pages in a first block according to an address of the page until reaching the last page in the first block; when the last page in the first block is reached, an address of a next to-be-read page is generated according to an address of the last page in the first block to allow the cache read command to read the next to-be-read page.

Claim (Index 12):
The method according to  claim 8 , wherein after the plurality of blocks in all the planes are read, the next to-be-read page is the first page in the first block of the first plane.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 2.53448
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13530518', '13332469', '15434432', '14822140', '15421113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5505104150181708
- 35 USC 102 Novelty (BERT): 0.5101067098176488
- Combined Prediction Score: 0.5464700444981186
- Mean Citation Score: 215.764356
- Max Citation Score: 221.4733
- Similarity Product: 122.31621333084108

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test