PATENT CLAIM ANALYSIS

Application Number: 15879904
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "680000"]

Abstract:
A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

Claim (Index 40):
The package according to  claim 38  wherein said at least one separator surrounds one or more of said plurality of RDL traces.

Metadata:
- Claim Count in Document: 71.0
- Percentile: 86.0
- Lexical Diversity: 2.375
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15840842', '13085759', '11115579', '14642531', '12107009']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303504364587604
- 35 USC 102 Novelty (BERT): 0.5303897455661072
- Combined Prediction Score: 0.8903543673694949
- Mean Citation Score: 271.575134
- Max Citation Score: 327.32745
- Similarity Product: 161.23335436407032

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test