PATENT CLAIM ANALYSIS

Application Number: 15909547
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "066000"]

Abstract:
Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer includes a first type of semiconductor material. A gate stack is formed over a first exposed surface of the semiconductor layer. A first hydrogenated and doped semiconductor layer is formed over a second exposed surface of the semiconductor layer. A second hydrogenated and doped semiconductor layer is formed over a third exposed surface of the semiconductor layer, wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack, and wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack.

Claim (Index 7):
A method of forming a thin-film transistor (TFT) device, the method comprising:\n forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer comprises a first type of crystalline semiconductor material; forming a gate stack over a first exposed surface of the semiconductor layer, wherein the gate stack comprises a dielectric layer and a gate metal layer; forming a first hydrogenated and doped semiconductor layer over a second exposed surface of the semiconductor layer; and forming a second hydrogenated and doped semiconductor layer over a third exposed surface of the semiconductor layer; wherein a source region of the TFT device comprises:\n the first hydrogenated and doped semiconductor layer; and \n a first portion of the semiconductor layer that is under the first hydrogenated and doped semiconductor layer; \n wherein a drain region of the TFT device comprises:\n the second hydrogenated and doped semiconductor layer; and \n a second portion of the semiconductor layer that is under the second hydrogenated and doped semiconductor layer; \n wherein a channel region of the TFT device comprises a third portion of the semiconductor layer that is under the gate stack; wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack; wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack; wherein the TFT device comprises a plurality of exposed surface regions comprising exposed non-crystalline surface regions of the insulating substrate, exposed non-crystalline surface regions of the gate stack, and exposed crystalline surface regions of the semiconductor layer; and wherein forming the first hydrogenated and doped semiconductor layer or the second hydrogenated and doped semiconductor layer comprises growing a layer of hydrogenated and doped semiconductor material over the plurality of exposed surface regions such that:\n crystalline regions of the layer of hydrogenated and doped semiconductor material are grown over the exposed crystalline surface regions of the semiconductor layer; \n non-crystalline regions of the layer of hydrogenated and doped semiconductor material are grown over the exposed non-crystalline surface regions of the insulating substrate; and \n non-crystalline regions of the layer of hydrogenated and doped semiconductor material are grown over the exposed non-crystalline surface regions of the gate stack.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 3.22222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15833120', '15825656', '15266414', '15606317', '15830639']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.902045863530642
- 35 USC 102 Novelty (BERT): 0.4912652154085749
- Combined Prediction Score: 0.8609677987184352
- Mean Citation Score: 223.620598
- Max Citation Score: 244.84088
- Similarity Product: 208.76720690613743

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test