PATENT CLAIM ANALYSIS

Application Number: 15989925
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "031000"]

Abstract:
Techniques related to a three-dimensional integration for qubits on crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first wafer comprising a first crystalline silicon layer attached to a first patterned superconducting layer, and a second wafer comprising a second crystalline silicon layer attached to a second patterned superconducting layer. The second patterned superconducting layer of the second wafer can be attached to the first patterned superconducting layer of the first wafer. A buried layer can comprise the first patterned superconducting layer and the second patterned superconducting layer. The buried layer can comprise one or more circuits. The superconductor structure can also comprise a transmon qubit that can comprise a Josephson junction and one or more capacitor pads comprising superconducting material. The Josephson junction can comprise a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.

Claim (Index 11):
A method, comprising:\n etching a first superconducting layer of a first wafer into a first patterned superconducting layer, and a second superconducting layer of a second wafer into a second patterned superconducting layer, wherein the first wafer comprises a first crystalline silicon layer attached to the first patterned superconducting layer and the second wafer comprises a second crystalline silicon layer attached to the second patterned superconducting layer; creating a buried layer based on attaching the first patterned superconducting layer and the second patterned superconducting layer, wherein a first pattern of the first patterned superconducting layer mirrors a second pattern of the second patterned superconducting layer, and the first pattern having a matching mirrored alignment with the second pattern; and forming a transmon qubit, above the second wafer, comprising a Josephson junction and one or more capacitor pads that comprise superconducting material, the Josephson junction comprising a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 93.0
- Lexical Diversity: 2.88889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15989873', '15934348', '15934375', '15322705', '15669139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9363139479626074
- 35 USC 102 Novelty (BERT): 0.6125312731660582
- Combined Prediction Score: 0.9039356804829524
- Mean Citation Score: 439.978944
- Max Citation Score: 614.2346
- Similarity Product: 487.3051318803549

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test