PATENT CLAIM ANALYSIS

Application Number: 16059317
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-08
Patent Classification: ["365", "149000"]

Abstract:
A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Claim (Index 6):
The semiconductor device of  claim 3 ,\n wherein the substrate comprises:\n a first well adjacent to an upper surface of the substrate; \n a second well at a lower level than that of the first well; and \n a third well at a lower level than that of the second well, \n wherein the second well is between the first well and the third well, wherein the first well and the third well contain first conductive impurities, and wherein the second well contains second conductive impurities different from the first conductive impurities.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 96.0
- Lexical Diversity: 2.41379
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14702038', '15914168', '12648386', '15589528', '15633941']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8149460452810701
- 35 USC 102 Novelty (BERT): 0.4940123160179978
- Combined Prediction Score: 0.7828526723547629
- Mean Citation Score: 220.408656
- Max Citation Score: 236.20178
- Similarity Product: 160.06690295730948

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test