PATENT CLAIM ANALYSIS

Application Number: 16043789
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["327", "147000"]

Abstract:
An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Claim (Index 3):
An integrated circuit device comprising:\n an analog front-end circuit that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped from a first signal output terminal, and outputs the second signal whose waveform is shaped from a second signal output terminal; a time-to-digital converter that receives the first signal from the analog front-end circuit via a first signal input terminal, receives the second signal from the analog front-end circuit via a second signal input terminal, and converts a time difference between transition timings of the first signal and the second signal into a digital value; a first signal line connecting the first signal output terminal and the first signal input terminal; and a second signal line connecting the second signal output terminal and the second signal input terminal, wherein the first signal line has first redundant wiring, the second signal line has second redundant wiring, and DL 1 <DL 2  and RL 1 >RL 2 , or DL 1 >DL 2  and RL 1 <RL 2  hold, where DL 1  is a distance between the first signal output terminal and the first signal input terminal, DL 2  is a distance between the second signal output terminal and the second signal input terminal, RL 1  is a wiring length of the first redundant wiring, and RL 2  is a wiring length of the second redundant wiring.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 95.0
- Lexical Diversity: 2.6
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16043681', '15715607', '16021458', '15715458', '15712796']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7420752562762071
- 35 USC 102 Novelty (BERT): 0.5227905609143075
- Combined Prediction Score: 0.7201467867400172
- Mean Citation Score: 252.963668
- Max Citation Score: 341.3278200000001
- Similarity Product: 310.44693046044586

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test