PATENT CLAIM ANALYSIS

Application Number: 16039921
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["327", "231000"]

Abstract:
During a period in which a first signal S 1  and second signal S 2  are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal S OUT  our that changes level when the capacitor voltage crosses a predetermined threshold value V TH . Each circuit unit includes a resistor R g  and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S 1  is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S 2  is the second level and the corresponding bit of the input code is a second value.

Claim (Index 1):
A phase interpolator comprising:\n a first input node couled to receive a first signal that transits from a first level to a second level; a second input node coupled to receive a second signal that transits from the first level to the second level with a delay with respect to the first signal; a first line coupled to receive a first voltage; a second line coupled to receive a second voltage; an intermediate line; a capacitor having one end coupled to the intermediate line; an initializing circuit structured to initialize a voltage across the capacitor during a period in which the first signal and the second signal are both set to the first level; a plurality of circuit units that correspond to a plurality of bits of an input code, and coupled in parallel between the intermediate line and the second line; and an output circuit structured to generate an output signal having a level that changes when the voltage across the capacitor crosses a predetermined threshold value, wherein each circuit unit comprises:\n a resistor and a first path arranged in series between the intermediate line and the second line; and \n a second path arranged in parallel with the first path, \n wherein the first path is structured such that, when the first signal is set to the second level and the corresponding bit of the input code is set to a first value, the first path is turned on, and wherein the second path is structured such that, when the second signal is set to the second level and the corresponding bit of the input code is set to a second value, the second path is turned on.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 95.0
- Lexical Diversity: 2.44776
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15258696', '10022551', '13538276', '10371248', '10278800']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7462919353661709
- 35 USC 102 Novelty (BERT): 0.4865312154994724
- Combined Prediction Score: 0.720315863379501
- Mean Citation Score: 224.741762
- Max Citation Score: 235.53111
- Similarity Product: 192.4558365626532

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test