PATENT CLAIM ANALYSIS

Application Number: 15755566
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["365", "072000"]

Abstract:
An embodiment includes a memory array comprising: a memory cell including a switch stack in series with a memory stack; and a bit line above the memory cell and a word line below the memory cell; wherein (a) first switch stack sidewalls of the switch stack are vertically aligned with bit line sidewalls of the bit line and second switch stack sidewalls of the switch stack are vertically aligned with word line sidewalls of the word line; (b) first memory stack sidewalls of the memory stack are vertically aligned with the bit line sidewalls and second memory stack sidewalls of the memory stack are vertically aligned with the word line sidewalls. Other embodiments are described herein.

Claim (Index 23):
The apparatus of  claim 22 , wherein the switch stack includes an insulator below an upper electrode and above a lower electrode.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 3.23077
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15012763', '13997392', '14635419', '15008475', '14698882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7917774373854629
- 35 USC 102 Novelty (BERT): 0.4835545679200118
- Combined Prediction Score: 0.7609551504389178
- Mean Citation Score: 152.46112399999996
- Max Citation Score: 174.00981000000004
- Similarity Product: 113.02878096850458

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test