PATENT CLAIM ANALYSIS

Application Number: 15882722
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["711", "118000"]

Abstract:
A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Claim (Index 14):
The method of  claim 13 , further comprising:\n determining whether a data entry stored in the memory of the cache allocated to the first processor should be replaced with the data requested by the first processor, upon determining that the memory allocated to the first processor should not be expanded; and replacing the data entry with the data requested by the first processor, upon determining that the data entry stored in the memory of the cache allocated to the first processor should be replaced with the data requested by the first processor.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 1.90698
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14933144', '13553884', '14274815', '13326690', '15730893']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4461972855238682
- 35 USC 102 Novelty (BERT): 0.5408276323565138
- Combined Prediction Score: 0.4556603202071327
- Mean Citation Score: 215.40624
- Max Citation Score: 376.49783
- Similarity Product: 300.76244145012856

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test