PATENT CLAIM ANALYSIS

Application Number: 15951557
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "042000"]

Abstract:
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

Claim (Index 3):
The semiconductor device of  claim 1 , wherein the polysilicon layer is substantially free of voids.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.71739
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15281418', '11113509', '14175587', '10641851', '09392034']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8546711958723621
- 35 USC 102 Novelty (BERT): 0.4927317186187674
- Combined Prediction Score: 0.8184772481470026
- Mean Citation Score: 153.89106800000005
- Max Citation Score: 222.26956
- Similarity Product: 163.94885568149567

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test