PATENT CLAIM ANALYSIS

Application Number: 15772682
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "774000"]

Abstract:
Techniques and mechanisms for efficiently providing reliable connection through a substrate such as that of a core of a packaged integrated circuit device. In an embodiment, a substrate has formed therein a through-hole interconnects, wherein an insulator is disposed between the through-hole interconnects in the substrate. A redundant configuration of the through-hole interconnects with respect to each other allows for a higher tolerance of voids being formed in the through-hole interconnects. In another embodiment, the through-hole interconnects are shorted together at one side of the substrate, and are further shorted together at an opposite side of the substrate. A total volume of any voids formed by one of the through-hole interconnects is equal to or more than six thousand cubic micrometers.

Claim (Index 47):
The system of  claim 44 , wherein the total volume of any voids formed by the first through-hole interconnect is in a range between 9\u00b710 3  \u03bcm 3  and 17\u00b710 3  \u03bcm 3 .

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 1.83099
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13183315', '11832742', '13206242', '11218243', '13684165']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9325161968668438
- 35 USC 102 Novelty (BERT): 0.4652247812876021
- Combined Prediction Score: 0.8857870553089197
- Mean Citation Score: 108.925069
- Max Citation Score: 115.055954
- Similarity Product: 79.95030176803684

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test