PATENT CLAIM ANALYSIS

Application Number: 15862064
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "384000"]

Abstract:
Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

Claim (Index 16):
An integrated circuit structure comprising:\n a first transistor comprising:\n a first semiconductor fin comprising a first channel region positioned laterally between first recessed source/drain regions, wherein a width of the first semiconductor fin at the first channel region is less than a width of the first semiconductor fin at the first recessed source/drain regions; \n a first metal gate adjacent to a first top surface and first opposing sides of the first semiconductor fin at the first channel region; \n first epitaxial source/drain regions above and immediately adjacent to the first recessed source/drain regions, wherein a width of the first epitaxial source/drain regions is greater than the width of the first semiconductor fin at the first recessed source/drain regions; and, \n first wrap-around metal plugs adjacent to top and side surfaces of the first epitaxial source/drain regions; \n a second transistor comprising:\n a second semiconductor fin parallel to the first semiconductor fin, the second semiconductor fin comprising a second channel region positioned laterally between second recessed source/drain regions, wherein a width of the second semiconductor fin at the second channel region is less than a width of the second semiconductor fin at the second recessed source/drain regions; \n a second metal gate adjacent to a second top surface and second opposing sides of the second semiconductor fin at the second channel region, wherein the second metal gate is in end to end alignment with the first metal gate and separated from the first metal gate by a dielectric-filled gate cut trench; \n second epitaxial source/drain regions above and immediately adjacent to the second recessed source/drain regions, wherein a width of the second epitaxial source/drain regions is greater than the width of the second semiconductor fin at the second recessed source/drain regions; and, \n second wrap-around metal plugs adjacent to top and side surfaces of the second epitaxial source/drain regions; \n a dielectric sidewall spacer having a first portion adjacent to the first metal gate and a second portion adjacent to the second metal gate, wherein the first portion is physically separated from the second portion by the dielectric-filled gate cut trench; and an interlayer dielectric layer positioned laterally adjacent to the dielectric sidewall spacer, wherein at least two of the dielectric sidewall spacer, the dielectric-filled gate cut trench and the interlayer dielectric layer comprise different dielectric materials.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 1.47561
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15387933', '15658835', '15844840', '15487636', '15632922']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.932323735237276
- 35 USC 102 Novelty (BERT): 0.564613771772889
- Combined Prediction Score: 0.8955527388908372
- Mean Citation Score: 371.574528
- Max Citation Score: 475.87143
- Similarity Product: 361.82855289463873

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test