PATENT CLAIM ANALYSIS

Application Number: 15898816
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-12
Patent Classification: ["375", "376000"]

Abstract:
In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.

Claim (Index 7):
The circuit of  claim 6 , wherein the first duration is equal to the second duration.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.71111
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13803476', '10414876', '15390813', '15727987', '10960367']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5230633820830702
- 35 USC 102 Novelty (BERT): 0.508829518882074
- Combined Prediction Score: 0.5216399957629706
- Mean Citation Score: 238.224544
- Max Citation Score: 253.92339
- Similarity Product: 162.41183162942647

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test