PATENT CLAIM ANALYSIS

Application Number: 16182138
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "145000"]

Abstract:
An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Claim (Index 6):
The integrated circuit of  claim 1 , wherein the sequence of operations further comprises:\n responsive to the verifying operation indicating an error in the second data set, writing the first data set into the second half-cell of each of the selected plurality of memory cells.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 98.0
- Lexical Diversity: 2.10145
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15139865', '12966963', '15019026', '16120107', '15678357']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7821790968932153
- 35 USC 102 Novelty (BERT): 0.5867990281791112
- Combined Prediction Score: 0.7626410900218049
- Mean Citation Score: 289.107706
- Max Citation Score: 487.24094
- Similarity Product: 455.6743369140148

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test