PATENT CLAIM ANALYSIS

Application Number: 15947075
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "154000"]

Abstract:
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Claim (Index 2):
A multi-port memory circuit comprising:\n a plurality of memory cells arranged at matrix; first and second word lines coupled to one of the memory cells; first and second bit lines coupled to one of the memory cells; an address control circuit, wherein the multi-port memory circuit includes first and second operation modes, wherein in the first operation mode, the address control circuit is configurable to control the first word line based on a first address signal and control the second word line based on a second address signal, and wherein in the second operation mode, the address control circuit is configurable to control both the first word line and the second word line based on the first address signal.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.40426
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15281947', '15606562', '15885449', '14504994', '13750328']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8187267490349974
- 35 USC 102 Novelty (BERT): 0.584184089260742
- Combined Prediction Score: 0.7952724830575719
- Mean Citation Score: 330.520802
- Max Citation Score: 501.18726
- Similarity Product: 463.8250478363442

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test