PATENT CLAIM ANALYSIS

Application Number: 16190557
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "156000"]

Abstract:
In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

Claim (Index 8):
The semiconductor device of  claim 7 , further comprising an accelerator which performs data processing according to an instruction from the central processing unit,\n wherein the accelerator is coupled between the CPU and the first control signal line, wherein the CPU outputs a standby signal to the accelerator, and wherein the accelerator outputs the control signal to the first control signal line depending on the standby signal.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 98.0
- Lexical Diversity: 2.03571
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15015643', '13532107', '15386642', '15211364', '15606903']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8195884230902056
- 35 USC 102 Novelty (BERT): 0.5391771344038067
- Combined Prediction Score: 0.7915472942215658
- Mean Citation Score: 324.154534
- Max Citation Score: 419.54395
- Similarity Product: 309.2176400711596

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test