PATENT CLAIM ANALYSIS

Application Number: 15938477
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-01
Patent Classification: ["438", "275000"]

Abstract:
A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

Claim (Index 9):
A method for fabricating a semiconductor device, comprising:\n forming a plurality of fins extending along a first direction on a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, and the plurality of fins are formed on the first and second regions of the semiconductor substrate; forming a plurality of sacrificial gate electrode structures extending along a second direction substantially perpendicular to the first direction over the fins, wherein the sacrificial gate electrode structures each comprise a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer; forming opposing gate sidewall spacers, extending along the second direction, on opposing sides of the sacrificial gate electrode layer; removing the sacrificial gate electrode layers from the plurality of gate electrode structures to form gate spaces; masking the first region; implanting fluorine into the gate sidewall spacers and the fins in the second region after removing the gate electrode layer by performing a first fluorine implantation; removing the sacrificial gate dielectric layers in the second region; forming high-k gate dielectric layers in the gate spaces in the second region; and implanting fluorine into the gate sidewall spacers and the fins in the second region after forming the high-k gate dielectric layers by performing a second fluorine implantation.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.94737
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15651167', '15726113', '15644600', '15804575', '13613868']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8329582010800773
- 35 USC 102 Novelty (BERT): 0.4787122213960308
- Combined Prediction Score: 0.7975336031116727
- Mean Citation Score: 200.732162
- Max Citation Score: 203.40364
- Similarity Product: 168.91557048029424

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test