PATENT CLAIM ANALYSIS

Application Number: 15774064
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "191000"]

Abstract:
Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.

Claim (Index 3):
The integrated circuit of  claim 2 , wherein the second layer is absent between the gate dielectric and the first layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.075
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16080100', '15777744', '15777500', '15774446', '16326846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9157887970979124
- 35 USC 102 Novelty (BERT): 0.4702664618484229
- Combined Prediction Score: 0.8712365635729635
- Mean Citation Score: 150.53991399999995
- Max Citation Score: 161.96625
- Similarity Product: 123.28131632678208

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test