PATENT CLAIM ANALYSIS

Application Number: 16191555
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["710", "300000"]

Abstract:
An embodiment of an extensible memory hub may include one or more upstream interface ports to couple the extensible memory hub to the controller, one or more downstream interface ports to couple the extensible memory hub to one or more of the nonvolatile memory and another extensible memory hub, and a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports and a second clock signal at a second frequency to the one or more downstream interface ports, where the first frequency may be different from the second frequency. Other embodiments are disclosed and claimed.

Claim (Index 2):
The apparatus of  claim 1 , wherein the extensible memory hub further comprises:\n a buffer coupled to the one or more substrates; and logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to actively manage the buffer for data transfer between the one or more upstream interface ports and the one or more downstream interface ports.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 98.0
- Lexical Diversity: 2.55814
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14314181', '15175697', '12166235', '10695383', '12350306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7412742649984032
- 35 USC 102 Novelty (BERT): 0.471656280073009
- Combined Prediction Score: 0.7143124665058639
- Mean Citation Score: 149.359464
- Max Citation Score: 166.502
- Similarity Product: 118.12219519364837

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test