PATENT CLAIM ANALYSIS

Application Number: 15984586
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["438", "479000"]

Abstract:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Claim (Index 26):
A method of preparing a silicon-on-insulator structure, the method comprising:\n bonding a first bonding surface on a front surface layer of a single crystal silicon handle substrate to a second bonding surface on a front surface layer of a single crystal silicon donor substrate; wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, a bulk region between the front and back surfaces, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk region resistivity of 100 Ohm-cm, and further wherein a charge trapping layer is in interfacial contact with the front surface layer of the single crystal silicon handle substrate, the charge trapping layer comprising one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge, and further wherein a semiconductor oxide layer is in interfacial contact with the charge trapping layer, the semiconductor oxide layer comprising the first bonding surface; and wherein the single crystal silicon donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon donor substrate and the other of which is a back surface of the single crystal silicon donor substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon donor substrate, and a central plane of the single crystal silicon donor substrate between the front and back surfaces of the single crystal silicon donor substrate, wherein the single crystal silicon donor substrate comprises a cleave plane and a dielectric layer on the front surface layer of the single crystal silicon donor substrate, the dielectric layer comprising the second bonding surface.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 93.0
- Lexical Diversity: 1.97143
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15526798', '15435428', '16077176', '16077142', '15526640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8959899251672513
- 35 USC 102 Novelty (BERT): 0.5459426755001436
- Combined Prediction Score: 0.8609852002005406
- Mean Citation Score: 403.164596
- Max Citation Score: 413.68033
- Similarity Product: 332.9767922823024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test