PATENT CLAIM ANALYSIS

Application Number: 15976706
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "180000"]

Abstract:
This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

Claim (Index 8):
A method of operating an array of thyristor memory cells, each thyristor memory cell having an anode, a cathode, first and second base regions, the array having a plurality of first lines in a first direction, each first line connected anodes or cathodes of a plurality of thyristor memory cell aligned in the first direction, a plurality of second lines in a second direction perpendicular to the first direction, each second line connected to cathodes or anodes of thyristor memory cells aligned in the second direction, a plurality of third lines in the first direction, each third line capacitively coupled to one of base regions of thyristor memory cells aligned in the first direction, the method comprising:\n turning ON a first set of one or more selected thyristor memory cells and/or turning OFF a second set of one or more selected thyristor memory cells, the selected thyristor memory cells connected to a selected first line and the first and second sets of selected one or more thyristor memory cells connected to one or more selected second lines; then driving all the second lines to a second voltage, driving the selected first line to a first voltage and allowing the second lines to float, and driving a selected third line capacitively coupled to the thyristor memory cells connected to the selected first line to a third voltage, a difference between the third and second voltages sufficient to maintain ON thyristor memory cells connected to the selected first line in ON states but insufficient to turn ON the OFF thyristor memory cells connected to the selected first line and a difference between the first and second voltages sufficient to drive the ON thyristor memory cells into deeper ON states with the third voltage on the selected third line.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 93.0
- Lexical Diversity: 1.51111
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14590834', '14740186', '14607023', '15216652', '14740209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7765948249446081
- 35 USC 102 Novelty (BERT): 0.4994468760928122
- Combined Prediction Score: 0.7488800300594285
- Mean Citation Score: 255.32215399999995
- Max Citation Score: 272.45346
- Similarity Product: 212.594433757782

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test