PATENT CLAIM ANALYSIS

Application Number: 15864832
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "324000"]

Abstract:
Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide, and the first and the second dielectric layers include a nitride. Other embodiments are also disclosed.

Claim (Index 25):
The memory device of  claim 21 , wherein the channel, first and second diffusion regions are formed at least partially within a semiconductor material structure.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.37736
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15335180', '14159315', '13539466', '14811346', '15189547']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9364680204443624
- 35 USC 102 Novelty (BERT): 0.549691225686887
- Combined Prediction Score: 0.897790340968615
- Mean Citation Score: 382.405218
- Max Citation Score: 414.51254
- Similarity Product: 342.201354424243

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test