PATENT CLAIM ANALYSIS

Application Number: 16048186
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["711", "141000"]

Abstract:
Disclosed are embodiments for running an application on a local processor when the application is dependent on pages not locally present but contained in a remote host. The system is informed that the pages on which the application depends are locally present. While running, the application encounters a cache miss and a cache line satisfying the miss from the remote host is obtained and provided to the application. Alternatively, the page containing the cache line satisfying the miss is obtained and the portion of the page not including the cache line is stored locally while the cache line is provided to the application. The cache miss is discovered by monitoring coherence events on a coherence interconnect connected to the local processor. In some embodiments, the cache misses are tracked and provide a way to predict a set of pages to be pre-fetched in anticipation of the next cache misses.

Claim (Index 9):
A device for assisting an application dependent on remote memory of a remote host to run on a local host, the device comprising:\n a first circuit configured to:\n receive a notice of a cache miss caused by the application running on the local host, wherein cache misses occur due to page tables of the running application being programmed to indicate that all pages of the running application are present in a local memory of the local host when at least one page of the running application is not present in the local memory so that memory accesses by the running application cause cache misses instead of page faults; \n obtain a cache line satisfying the cache miss from the remote host responsible for remote memory containing the cache line using a translation table and a network connection to the remote host; \n copy the obtained cache line into the local memory; and \n provide the obtained cache line to the running application; and \n a second circuit configured to:\n monitor cache coherence events caused by the running application; and \n provide the notice of the cache miss to the first circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.25714
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15368947', '14047128', '15650296', '11346399', '13494843']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4811675531159892
- 35 USC 102 Novelty (BERT): 0.4739200895564078
- Combined Prediction Score: 0.480442806760031
- Mean Citation Score: 144.16536000000005
- Max Citation Score: 147.27596
- Similarity Product: 101.27269356854436

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test