PATENT CLAIM ANALYSIS

Application Number: 16138462
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "382000"]

Abstract:
A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Claim (Index 5):
The method of  claim 1 , wherein the silicide layer is formed based on the amorphous layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 2.25
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14311921', '14583444', '14530320', '15893316', '13870854']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92279205707038
- 35 USC 102 Novelty (BERT): 0.5050323624617975
- Combined Prediction Score: 0.8810160876095219
- Mean Citation Score: 211.609398
- Max Citation Score: 239.97937
- Similarity Product: 157.3565393741161

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test