PATENT CLAIM ANALYSIS

Application Number: 15951267
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-01
Patent Classification: ["257", "787000"]

Abstract:
A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method.

Claim (Index 4):
The chip encapsulating method of  claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is away from the second panel level substrate;\n after the chip is encapsulated, the chip encapsulating method further comprises: decapsulating the encapsulating layer, to expose a contact portion of the re-distribution layer contacting the solder ball; and forming the solder ball.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.18605
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13273168', '14058213', '14172832', '13154165', '12370537']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9231516522172486
- 35 USC 102 Novelty (BERT): 0.4750458013730994
- Combined Prediction Score: 0.8783410671328337
- Mean Citation Score: 193.755198
- Max Citation Score: 205.25087
- Similarity Product: 169.29122639891563

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test