PATENT CLAIM ANALYSIS

Application Number: 16004081
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["712", "207000"]

Abstract:
Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.

Claim (Index 24):
The hardware processor of  claim 22 , wherein the prefetch unit further comprises a status register to indicate a status of the prefetch unit.

Metadata:
- Claim Count in Document: 71.0
- Percentile: 94.0
- Lexical Diversity: 2.93617
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14583651', '15445577', '14984233', '15640534', '14628954']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5467494673695495
- 35 USC 102 Novelty (BERT): 0.5432982362184138
- Combined Prediction Score: 0.546404344254436
- Mean Citation Score: 267.512824
- Max Citation Score: 392.03464
- Similarity Product: 246.6817879533673

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test