PATENT CLAIM ANALYSIS

Application Number: 16011884
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-04
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pillar extending in a first direction and a first conductive pattern surrounding the channel pillar. The semiconductor device also has second conductive patterns surrounding the channel pillar above the first conductive pattern, wherein the second conductive patterns are stacked in the first direction and spaced apart from each other. The semiconductor device further has an etch stop pattern disposed above the first conductive pattern and below the second conductive patterns.

Claim (Index 12):
A semiconductor device comprising:\n a first channel pillar and a second channel pillar extending in a first direction from inside a well doped semiconductor layer; a first gate stack structure disposed above the well doped semiconductor layer, wherein the first gate stack structure surrounds the first channel pillar; a second gate stack structure disposed above the well doped semiconductor layer, wherein the second gate stack structure surrounds the second channel pillar; a first channel contact layer disposed between the well doped semiconductor layer and the first gate stack structure, wherein the first channel contact layer surrounds the first channel pillar; a second channel contact layer disposed between the well doped semiconductor layer and the second gate stack structure, wherein the second channel contact layer surrounds the second channel pillar; a slit disposed between the first gate stack structure and the second gate stack structure; and a sidewall insulating layer formed on a sidewall of the slit, wherein each of the first and second gate stack structures includes interlayer insulating layers and gate electrodes, which are alternately stacked along the first direction, and wherein an etch stop pattern is disposed between two gate electrodes of the gate electrodes adjacent to the well doped semiconductor layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.16279
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16011975', '15934477', '15259380', '15280132', '15965139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9310808199343006
- 35 USC 102 Novelty (BERT): 0.5299599735648851
- Combined Prediction Score: 0.8909687352973591
- Mean Citation Score: 312.514078
- Max Citation Score: 365.6654
- Similarity Product: 305.71446096836326

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test