PATENT CLAIM ANALYSIS

Application Number: 16198725
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "189000"]

Abstract:
A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Claim (Index 3):
The integrated circuit structure of  claim 2 , further comprising:\n a first source or drain region at a first side of the gate electrode; and a second source or drain region at a second side of the gate electrode, the second side opposite the first side.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.63158
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15464888', '14778574', '15120803', '15492785', '14908112']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9011368342930456
- 35 USC 102 Novelty (BERT): 0.5253556602553955
- Combined Prediction Score: 0.8635587168892807
- Mean Citation Score: 240.65693
- Max Citation Score: 294.65665
- Similarity Product: 178.75106664999132

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test