PATENT CLAIM ANALYSIS

Application Number: 15910264
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "072000"]

Abstract:
A LTPS TFT comprises a substrate, and a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, a dielectric layer, a source and a drain disposed on the substrate successively. The source contact area and the drain contact area are doped with metal ions individually. The source and the drain are connecting with the source and drain contact areas separately through the dielectric layer. The metal ions include at least one of Cu 2+ , Al 3+ , Mg 2+ , Zn 2+  and Ni 2+ . A method of fabricating the LTPS TFT is also provided. An annealing is performed for driving individually metal ions of the insulation metal oxide layer into the source contact area and the drain contact area. Thus, the step of implanting p-type ions can be omitted, the procedure can be significantly simplified, and the manufacturing cost can be reduced.

Claim (Index 1):
A low temperature polysilicon thin film transistor (LTPS TFT), comprising:\n a substrate; a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, an insulation metal oxide layer, a dielectric layer, a source and a drain disposed on the substrate successively; wherein the source contact area and the drain contact area are disposed in a same layer with the low temperature polysilicon layer and at two opposite sides of the low temperature polysilicon layer separately; wherein the source contact area and the drain contact area are doped with metal ions individually; wherein the insulation metal oxide layer and the dielectric layer are disposed between the gate layer and the source, the source is connecting with the source contact area through the dielectric layer and the insulation metal oxide layer successively to form the ohmic contact, and the insulation metal oxide layer and the dielectric layer are disposed between the gate layer and the drain, the drain is connecting with the drain contact area through the dielectric layer and the insulation metal oxide layer successively to form the ohmic contact; and wherein the metal ions include at least one of Cu2+, Al3+, Mg2+, Zn2+ and Ni2+.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.36486
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15121037', '14779089', '10248770', '14428983', '15393413']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9285111550321468
- 35 USC 102 Novelty (BERT): 0.499275017419829
- Combined Prediction Score: 0.8855875412709149
- Mean Citation Score: 259.438996
- Max Citation Score: 267.19852000000003
- Similarity Product: 205.8459301416016

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test