PATENT CLAIM ANALYSIS

Application Number: 15900030
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["712", "217000"]

Abstract:
A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Claim (Index 29):
The processor of  claim 16  wherein the first and second plurality of control registers include a first and second control register, respectively, to store first and second base addresses of first and second regions in memory, respectively, for storing first and second interrupt data associated with the first and second threads, respectively.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 88.0
- Lexical Diversity: 1.48
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10816103', '13722481', '15088043', '11027445', '14067223']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5805614743835579
- 35 USC 102 Novelty (BERT): 0.5454800774903331
- Combined Prediction Score: 0.5770533346942355
- Mean Citation Score: 300.399834
- Max Citation Score: 397.86548
- Similarity Product: 280.03981213768003

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test