PATENT CLAIM ANALYSIS

Application Number: 16155047
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["710", "105000"]

Abstract:
A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Claim (Index 1):
An apparatus for data transformation of an input data word of 2 N  sections, where N is an integer, comprising:\n a set of N combinatorial circuits, each combinatorial circuit corresponding to a layer of multiplexers, each combinatorial circuit including:\n a first input receiving a bit corresponding to a precalculated shuffle pattern; \n a second input receiving a bit corresponding to a precalculated replicate pattern; \n a third input receiving a bit corresponding to a precalculated rotate pattern; \n a first exclusive OR gate having a first input receiving the bit corresponding to the precalculated shuffle pattern, a second input receiving the bit corresponding the precalculated replicate pattern, and an output; \n a second exclusive OR gate having a first input receiving the bit corresponding to the precalculated replicate pattern, a second input receiving the bit corresponding to the precalculated rotate pattern, and an output; \n a third exclusive OR gate having a first input receiving the bit corresponding to the precalculated rotate pattern, a second input receiving the bit corresponding to the precalculated shuffle pattern, and an output; and \n a control multiplexer having a first input receiving the bit corresponding to the precalculated shuffle pattern, a second input receiving the bit corresponding to the precalculated replicate pattern, a third input receiving the bit corresponding to the precalculated rotate pattern, a fourth input receiving the output of the first exclusive OR gate, a fifth input receiving the output of the second exclusive OR gate, a sixth input receiving the output of the third exclusive OR gate, and a control input, wherein the control multiplexer outputs a selected one of the first, second, third, fourth, fifth or sixth input depending on a signal at the control input.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 1.66667
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15602235', '15651055', '15384514', '15384487', '15971875']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6662209610273679
- 35 USC 102 Novelty (BERT): 0.533386591028924
- Combined Prediction Score: 0.6529375240275236
- Mean Citation Score: 300.081196
- Max Citation Score: 366.82278
- Similarity Product: 292.36724146083

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test