PATENT CLAIM ANALYSIS

Application Number: 15970242
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["326", "030000"]

Abstract:
A memory system includes: a buffer memory device including a reference voltage pad; a memory controller including a controller ZQ pad; and a controller calibration resistor, wherein the reference voltage pad, the controller ZQ pad, and the controller calibration resistor are coupled to each other.

Claim (Index 13):
A memory system comprising:\n a buffer memory device; a memory controller including a first pad; a controller calibration resistor coupled to the memory controller through the first pad; and a memory calibration resistor coupled to the buffer memory device through a second pad, wherein the memory controller performs an impedance calibration operation, based on the resistance of the controller calibration resistor, wherein the buffer memory device determines whether a data signal is logic \u2018high\u2019 or logic \u2018low\u2019 in a data input operation, based on a voltage output from the memory controller through the first pad, and wherein the buffer memory device autonomously performs an impedance calibration operation, based on the resistance of the memory calibration resistor.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 93.0
- Lexical Diversity: 1.92593
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15968026', '15968065', '15922332', '13239478', '14723614']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6910239023163277
- 35 USC 102 Novelty (BERT): 0.5231470678638837
- Combined Prediction Score: 0.6742362188710833
- Mean Citation Score: 289.317988
- Max Citation Score: 361.8324
- Similarity Product: 298.4723229755402

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test