PATENT CLAIM ANALYSIS

Application Number: 16009995
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["365", "185050"]

Abstract:
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

Claim (Index 10):
A memory array, comprising:\n multiple memory cell strings situated in a grid comprising rows and columns of memory cell strings, each memory cell string extending between a connection to a source and a connection to a respective bit line, each memory cell string comprising, multiple charge storage memory cells connected in series, each charge storage memory cell including a control gate transistor and a charge storage structure; a select gate drain transistor electrically between the multiple memory cells and a respective bit line, the select gate transistor having a gate; a first select gate source transistor on the opposite side of the multiple memory cells from the select gate drain transistor, and between the multiple memory cells and a source, the first select gate source transistor having a gate; a second select gate source transistor coupled in series with the first select gate source transistor, and between the multiple memory cells and the source, the second select gate source transistor having a gate; and a first drive transistor coupled to both,\n the gates of select gate drain transistors of a first group of memory cell strings, the first group of memory cell strings extending in a first row or a first column of the grid, and \n the gates of the first select gate source transistors of the first group of memory cell strings; \n a second drive transistor coupled to both,\n the gates of select gate drain transistors of a second group of memory cell strings, the second group of memory cell strings extending in a second row or a second column of the grid, \n the gates of the first select gate source transistors of the second group of memory cell strings; and \n a third drive transistor coupled to gates of the second select gate source transistors in the memory cell strings of the first and second groups of memory cell strings.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 94.0
- Lexical Diversity: 3.58974
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14456222', '15443548', '15131671', '11767234', '13450294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8120480297360845
- 35 USC 102 Novelty (BERT): 0.5147474784526341
- Combined Prediction Score: 0.7823179746077394
- Mean Citation Score: 275.544808
- Max Citation Score: 336.94702
- Similarity Product: 267.5400609809936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test