PATENT CLAIM ANALYSIS

Application Number: 15869803
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["711", "106000"]

Abstract:
A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.

Claim (Index 23):
The method as claimed in  claim 21 , wherein:\n the hth row is a row which is most accessed during the first period, of the first to mth rows. the ith row is a row which is most accessed during the second period, of the first to mth rows, and the jth row is a row which is most accessed during the third period, of the first to mth rows.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 86.0
- Lexical Diversity: 2.88372
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15236895', '15262183', '15134637', '14722634', '14087167']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5373797000888206
- 35 USC 102 Novelty (BERT): 0.5100682492851429
- Combined Prediction Score: 0.5346485550084529
- Mean Citation Score: 192.194376
- Max Citation Score: 198.78749
- Similarity Product: 105.27238543942453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test