PATENT CLAIM ANALYSIS

Application Number: 16167903
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "231000"]

Abstract:
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Claim (Index 13):
An integrated circuit, comprising:\n a first NMOS transistor with a first NMOS gate that crosses opposite NMOS edges of a first NMOS active area and extends past a first of the opposite NMOS edges a first distance; a second NMOS transistor having a second NMOS gate and second NMOS active area, the second NMOS transistor being located adjacent to the first NMOS transistor, wherein the first NMOS active area has a width that is smaller than the second NMOS active area and wherein the first NMOS gate has the same long side dimension as the second NMOS gate; a first PMOS transistor with a first PMOS gate that crosses opposite edges of a first PMOS active area and extends past a first edge of the opposite PMOS edges a second distance, wherein the first distance is greater than the second distance.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 1.66667
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14576659', '15409842', '14584348', '11849798', '13288664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8632574057067381
- 35 USC 102 Novelty (BERT): 0.5141165661508477
- Combined Prediction Score: 0.8283433217511491
- Mean Citation Score: 255.28350200000008
- Max Citation Score: 318.36716
- Similarity Product: 260.82984439522744

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test