PATENT CLAIM ANALYSIS

Application Number: 15990517
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["375", "376000"]

Abstract:
A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.

Claim (Index 12):
A method, comprising:\n generating a quarter-rate clock signal and a quadrature of the quarter-rate clock signal in a clock source within an integrated circuit; transmitting the quarter-rate clock signal and the quadrature of the quarter-rate clock signal to a first frequency doubler within the integrated circuit; generating a first half-rate clock signal in the first frequency doubler responsive to the quarter-rate clock signal and the quadrature of the quarter-rate clock signal; and serializing a parallel input data stream responsive to the first half-rate clock signal in a serializer transmitter within the integrated circuit into a serialized data stream, wherein a data rate for the serialized data stream is twice a frequency for the first half-rate clock signal, and wherein the frequency of the first half-rate clock signal is twice a frequency for the quarter-rate clock signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 1.2
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14320736', '15479423', '15273621', '15667251', '15367071']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4934049360595937
- 35 USC 102 Novelty (BERT): 0.4908516978461105
- Combined Prediction Score: 0.4931496122382454
- Mean Citation Score: 234.69520000000003
- Max Citation Score: 248.81186
- Similarity Product: 197.2162233437312

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test