PATENT CLAIM ANALYSIS

Application Number: 15869718
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["438", "514000"]

Abstract:
Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

Claim (Index 17):
A method of forming an integrated circuit device, the method comprising:\n implanting first dopants into a substrate to form a preliminary impurity region in the substrate, the first dopants having a first conductivity type; heating the substrate to convert the preliminary impurity region into an impurity region; forming an undoped semiconductor layer on the substrate after heating the substrate; forming a first trench and a second trench in the undoped semiconductor layer and the impurity region to define an active fin between the first trench and the second trench; forming a first isolation layer and a second isolation layer in the first trench and the second trench, respectively, wherein the active fin protrudes beyond upper surfaces of the first and second isolation layers such that the first and second isolation layers expose opposing sides of the active fin; forming a pair of source/drain regions in the undoped semiconductor layer thereby defining a channel region in the undoped semiconductor layer between the pair of source/drain regions, the pair of source/drain regions including second dopants that have a second conductivity type that is opposite the first conductivity type; forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin; and forming a gate electrode traversing the active fin, wherein the active fin extends longitudinally in a horizontal direction in a plan view, wherein the channel region comprises a middle portion in the horizontal direction, and the middle portion of the channel region comprises some of the second dopants diffused from the pair of source/drain regions, and wherein a concentration of the some of the second dopants in the middle portion of the channel region is about 5E18-5E20 atoms/cm 3  after forming the gate electrode.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 86.0
- Lexical Diversity: 2.24638
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15385060', '14460404', '13865478', '14978155', '15422907']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8667554192527532
- 35 USC 102 Novelty (BERT): 0.4957994626947159
- Combined Prediction Score: 0.8296598235969496
- Mean Citation Score: 251.58356
- Max Citation Score: 268.44348
- Similarity Product: 220.898442839098

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test