PATENT CLAIM ANALYSIS

Application Number: 15919896
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["326", "095000"]

Abstract:
Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.

Claim (Index 11):
The IC of  claim 1 , wherein the one or more electrically-conductive elements comprise at least one metal segment, at least one polysilicon segment, at least one via, at least one stacked via, or any combination thereof.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 90.0
- Lexical Diversity: 1.77419
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14582971', '10682351', '14583018', '14583007', '14582984']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.662421614919022
- 35 USC 102 Novelty (BERT): 0.4739850075353417
- Combined Prediction Score: 0.6435779541806539
- Mean Citation Score: 140.10854999999998
- Max Citation Score: 141.82858000000004
- Similarity Product: 95.12019526548627

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test