PATENT CLAIM ANALYSIS

Application Number: 16165732
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "191000"]

Abstract:
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Claim (Index 2):
The apparatus of  claim 1 , wherein the microcontroller is coupled to the access line driver, and wherein the microcontroller is configured to calculate the biasing signal based at least in part on an operating condition of the memory array.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.70732
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15474353', '15895290', '13651093', '14989678', '12205867']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8601277980374903
- 35 USC 102 Novelty (BERT): 0.512887599480246
- Combined Prediction Score: 0.8254037781817659
- Mean Citation Score: 275.276722
- Max Citation Score: 324.7241
- Similarity Product: 299.55545138174887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test