PATENT CLAIM ANALYSIS

Application Number: 16257267
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["345", "213000"]

Abstract:
The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.

Claim (Index 1):
A bidirectional scanning circuit comprising:\n a plurality of stages of circuit blocks respectively outputting an active potential to an output electrode; and a clock signal line applying a clock signal to the plurality of stages, wherein the clock signal includes the active potential, at least one stage of circuit block of the plurality of stages of circuit blocks includes a first transistor, a second transistor, a third transistor, a first node, a second node, and a transfer electrode, the active potential can turn on the first transistor, the first transistor connects the clock signal line and the output electrode, and applies the active potential of the clock signal to the output electrode when the first transistor is an ON state, the second transistor connects the clock signal line and the transfer electrode which is electrically connected to the first node of a next stage of the plurality of stages, and applies the active potential of the clock signal to the first node of the next stage when the second transistor is an ON state, the first node is connected to a gate of the first transistor of a present stage and to a gate of the second transistor of the present stage, the third transistor connects the output electrode and a constant voltage line when the third transistor is an ON state, the second node is connected to a gate of the third transistor of the present stage, and the transfer electrode is not directly connected to the output electrode.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 99.0
- Lexical Diversity: 2.47059
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15097414', '15946991', '14094962', '14615410', '16217122']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7036964788609832
- 35 USC 102 Novelty (BERT): 0.5455393521762621
- Combined Prediction Score: 0.687880766192511
- Mean Citation Score: 327.524836
- Max Citation Score: 396.98297
- Similarity Product: 377.7586126409293

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test