PATENT CLAIM ANALYSIS

Application Number: 16025922
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["327", "382000"]

Abstract:
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Claim (Index 2):
An integrated circuit block comprising:\n a first node; a second node; a series arrangement of one or more capacitive elements; and a series arrangement of a plurality of switches, wherein:\n the one or more capacitive elements are in series with the plurality of switches; \n a combination of the one or more capacitive elements and the plurality of switches is coupled between the first node and the second node; \n the plurality of switches are configured to withstand a voltage greater than a voltage withstood by one switch; \n the plurality of switches are configured to receive a control signal to enable or disable the switches and thereby adjusting the capacitance between the two nodes, and \n one or more compensation capacitive elements are coupled across at least one switch of the plurality of switches.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 95.0
- Lexical Diversity: 1.32353
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12803139', '12803064', '14178116', '14165422', '15442491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8662337835290587
- 35 USC 102 Novelty (BERT): 0.5720806757846646
- Combined Prediction Score: 0.8368184727546192
- Mean Citation Score: 484.55348200000014
- Max Citation Score: 493.31763
- Similarity Product: 417.3993265381944

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test