PATENT CLAIM ANALYSIS

Application Number: 16211681
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "415000"]

Abstract:
The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a plurality of interconnect layers disposed within a dielectric structure over a substrate. A passivation layer is over the dielectric structure. A sensing electrode and a bonding electrode have bottom surfaces directly contacting the passivation layer. A microelectromechanical systems (MEMS) substrate is vertically separated from the sensing electrode. The bonding electrode is electrically connected to the MEMs substrate and to one or more of the plurality of interconnect layers. An electrode extension via is configured to electrically connect the sensing electrode to one or more of the plurality of interconnect layers.

Claim (Index 3):
The integrated chip structure of  claim 1 , wherein the bottom surfaces of the sensing electrode and the bonding electrode are separated from the substrate by distances that are approximately equal.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 2.05172
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15193410', '15205619', '15688128', '15716676', '15213519']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9204808485513496
- 35 USC 102 Novelty (BERT): 0.5030677157363181
- Combined Prediction Score: 0.8787395352698466
- Mean Citation Score: 198.800472
- Max Citation Score: 263.80334
- Similarity Product: 197.7605516072369

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test