PATENT CLAIM ANALYSIS

Application Number: 16180604
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["327", "212000"]

Abstract:
A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

Claim (Index 24):
The circuit of  claim 17 , the circuit only toggling when input data changes.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.88095
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15488628', '15488947', '16113174', '15488840', '15483236']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7438227817384307
- 35 USC 102 Novelty (BERT): 0.5176357314440948
- Combined Prediction Score: 0.7212040767089972
- Mean Citation Score: 201.375584
- Max Citation Score: 291.85696
- Similarity Product: 203.7852417527008

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test