PATENT CLAIM ANALYSIS

Application Number: 16166752
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["327", "213000"]

Abstract:
A circuit includes a clock generator configured to generate a first latching clock signal and a second latching clock signal. Responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clock signal or the second latching clock signal has a predetermined logic value. A multiplexing latch circuit is configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal.

Claim (Index 17):
The method of  claim 16 , wherein each of the generating the first latching clock signal and the generating the second latching clock signal comprises outputting a signal from a NAND gate of a clock generator.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 97.0
- Lexical Diversity: 2.88889
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14755999', '10926897', '14304357', '14728741', '12963420']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7483436350775833
- 35 USC 102 Novelty (BERT): 0.5314602524238169
- Combined Prediction Score: 0.7266552968122066
- Mean Citation Score: 224.58515
- Max Citation Score: 353.555
- Similarity Product: 310.71472511291506

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test