PATENT CLAIM ANALYSIS

Application Number: 16101843
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "369000"]

Abstract:
The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first transistor gate stack is disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. A third transistor gate stack is disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises an oxide component and a first interlayer dielectric layer.

Claim (Index 8):
The IC of  claim 7 , further comprising:\n a hard mask disposed on the first gate electrode and contacting top surfaces of the sidewall spacer and the contact etch stop layer.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 96.0
- Lexical Diversity: 2.51064
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15703116', '15688276', '14480017', '13446852', '13785494']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8972017927962622
- 35 USC 102 Novelty (BERT): 0.4855087243703331
- Combined Prediction Score: 0.8560324859536693
- Mean Citation Score: 201.062304
- Max Citation Score: 255.46579
- Similarity Product: 247.2526485144413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test