PATENT CLAIM ANALYSIS

Application Number: 15744615
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["345", "173000"]

Abstract:
The present disclosure provides a display panel including a display area and a non-display area, a base substrate, a plurality of thin film transistors, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area, a ground line area and an insulating layer. The thin film transistor includes a gate, a gate insulating layer, a source and a drain. The non-display area includes a first side and a second side; the array substrate row driving circuit respectively forms a first gap and a second gap with the first test signal line area and the second test signal line area, an orthographic projection of the ground line area on the base substrate is in the projection of the second test signal line area in the base substrate. The present disclosure also provides a display device.

Claim (Index 6):
A display device, comprising a display panel, wherein the display comprises a display area and a non-display area located on two sides of the display area;\n wherein the display panel further comprises a base substrate, a plurality of thin film transistors disposed on the base substrate, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area and a ground line area; wherein an insulating layer is between the thin film transistor and the touch signal line in the display area, the thin film transistor comprises a gate, a gate insulating layer, a source and a drain; the non-display area comprises a first side and a second side spaced apart from the first side; the first test signal line area comprises a first side and a second side opposite to the first side; in the non-display area, the first side is adjacent to the first side of the first test signal line area, a first gap is formed between the second side of the first test signal line area and the array substrate row driving circuit, a second gap is formed between the array substrate row driving circuit and the second test signal line area, and a third gap is formed between the ground line area and the second side; an orthographic projection of the ground line area on the base substrate is partially located within an orthographic projection of the second test signal line area on the base substrate.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15571724', '13918060', '14092102', '15777454', '15325011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6462900210110785
- 35 USC 102 Novelty (BERT): 0.4644067307072929
- Combined Prediction Score: 0.6281016919807
- Mean Citation Score: 194.406074
- Max Citation Score: 198.21724
- Similarity Product: 170.80841492189884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test