PATENT CLAIM ANALYSIS

Application Number: 16448841
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["365", "189050"]

Abstract:
Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.

Claim (Index 6):
The memory device of  claim 5 , wherein the feature detection circuitry comprises an SR latch.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 1.93333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15850744', '15826236', '16200460', '15845874', '16051189']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8223788455565136
- 35 USC 102 Novelty (BERT): 0.5427557988420306
- Combined Prediction Score: 0.7944165408850653
- Mean Citation Score: 274.62590800000004
- Max Citation Score: 402.57297
- Similarity Product: 398.8995659379476

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test