PATENT CLAIM ANALYSIS

Application Number: 16161983
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["327", "538000"]

Abstract:
A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.

Claim (Index 7):
The voltage regulator circuit of  claim 6 , wherein the digital control loop circuit comprises a plurality of individually activatable current sources, and wherein the digital portion is further configured to adjust the number of the plurality of individually activatable current sources which are activated based upon the integration of the analog current to thereby control the digital current applied to the output current summing node.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.38
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15392823', '13197756', '11672309', '13843572', '11864884']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7769089107023115
- 35 USC 102 Novelty (BERT): 0.4969773819989079
- Combined Prediction Score: 0.7489157578319712
- Mean Citation Score: 189.399148
- Max Citation Score: 272.88104
- Similarity Product: 220.9278556372309

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test