PATENT CLAIM ANALYSIS

Application Number: 16440106
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["257", "327000"]

Abstract:
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Claim (Index 6):
The structure of  claim 5 , wherein the gate material is formed on the HfO 2 .

Metadata:
- Claim Count in Document: 3.0
- Percentile: 100.0
- Lexical Diversity: 1.73333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15076036', '15790604', '15406096', '15797315', '15159269']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9166330810746046
- 35 USC 102 Novelty (BERT): 0.511997304640174
- Combined Prediction Score: 0.8761695034311615
- Mean Citation Score: 207.833426
- Max Citation Score: 208.07896
- Similarity Product: 128.8166806610918

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test