PATENT CLAIM ANALYSIS

Application Number: 15887702
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["324", "538000"]

Abstract:
A method of bondwire integrity testing a packaged IC includes forcing a pin current or pin voltage level sufficient to forward bias a parasitic diode at a plurality of pins relative to a selected reference pin. The pins are connected to bond pads (BPs) on the IC by a bondwire. The bond pads coupled to a diffusion of a first type that forms the parasitic diode (D) with a region doped the second type coupled to a bondpad wirebonded to the reference pin. The resulting pin voltages or pin currents at measured, and present pin-pin relationships are determined. The present pin-pin relationships are compared to stored pin-pin relationship data for a device design of the IC. Results from the comparing are used to determine whether any present pin-pin relationships are significantly different as compared to the stored pin-pin relationships to identify a bondwire problem for at least one pin.

Claim (Index 7):
The method of  claim 1 , wherein said reference pin is a common ground for said IC device.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 88.0
- Lexical Diversity: 1.90476
- Patent Class: 324.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15857234', '11034093', '10397402', '11033202', '15337821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5455444573187985
- 35 USC 102 Novelty (BERT): 0.4913018774507066
- Combined Prediction Score: 0.5401201993319893
- Mean Citation Score: 188.010862
- Max Citation Score: 206.57361
- Similarity Product: 145.6499056632024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test