PATENT CLAIM ANALYSIS

Application Number: 16038977
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "369000"]

Abstract:
A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Claim (Index 11):
The device according to  claim 9 , wherein the bump comprises a low-resistive metal and extends to a height of 14 nm to 40 nm above the Si fin.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 95.0
- Lexical Diversity: 2.92453
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15494119', '14017409', '15591814', '13654987', '16026840']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9298244036073272
- 35 USC 102 Novelty (BERT): 0.6029963615355177
- Combined Prediction Score: 0.8971415994001464
- Mean Citation Score: 336.71742400000005
- Max Citation Score: 585.5005
- Similarity Product: 449.3740319783092

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test