PATENT CLAIM ANALYSIS

Application Number: 15920562
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "759000"]

Abstract:
Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

Claim (Index 14):
A method for fabricating a semiconductor chip structure, the method comprising:\n forming at least one back-end-of-line layer (BEOL) dielectric layer on a substrate, the substrate including semiconductor devices; depositing a layer of block copolymers (BCPs) on the BEOL dielectric layer, annealing the BCPs and forming a self-assembled random pattern of BCPs; selectively removing one block from the layer of BCPs leaving voids in the remaining layer of BCPs and forming an etch template; etching, using the etch template, the BEOL dielectric layer, the etching forming trenches of a random fingerprint pattern in the BEOL dielectric layer; and depositing conductive material in the trenches in the BEOL dielectric layer followed by a planarization process to remove overburden of conductive material deposited on top of the BEOL dielectric layer, forming a random pattern of conductive material in the BEOL dielectric layer; and wherein the BEOL dielectric layer including the random pattern of conductive material comprising a chip identification layer, the method further comprising forming a crossbar sensing network comprising at least two layers of electrodes that have a crossbar structure, in which\n a first crossbar, formed on a first side of the chip identification layer, includes a first set of conductors and a first set of electrical contacts in a first grid pattern contacting the first set of electrodes and the first side of the chip identification layer; and \n a second crossbar, formed on a second side of the chip identification layer, includes a second set of electrodes and a second set of electrical contacts in a second grid pattern contacting the second set of electrodes and the second side of the chip identification layer; and \n wherein the depositing a layer of BCPs on the BEOL dielectric layer comprises:\n depositing a layer of surface modification materials, in a surface treatment process, on a surface of the BEOL dielectric layer to control surface affinity for later Directed Self-Assembly (DSA) patterning, followed by depositing the layer of BCPs on the surface of the BEOL dielectric layer treated with the surface treatment process.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 2.90566
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15456758', '15456769', '15793130', '12146546', '15837774']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9117498164195896
- 35 USC 102 Novelty (BERT): 0.4641598559479653
- Combined Prediction Score: 0.8669908203724273
- Mean Citation Score: 176.12813599999996
- Max Citation Score: 180.69688
- Similarity Product: 148.82956397076606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test