PATENT CLAIM ANALYSIS

Application Number: 15947075
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "154000"]

Abstract:
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Claim (Index 10):
The multi-port memory circuit according to  claim 2 , further comprising:\n an operation mode control terminal; and first and second port enable terminals, wherein the multi-port memory is controlled as to whether the multi-port memory operates in the first operation mode or operates in the second operation mode based on an operation mode control signal that is input through the operation mode control terminal, wherein when the multi-port memory operates in the first operation mode,\n the address control circuit performs control of the first word line that is based on the first address signal, on condition that a first enable signal that is input through the first port enable terminal is asserted, and \n the address control circuit performs control of the second word line that is based on the second address signal, on condition that a second port enable signal that is input through the second port enable terminal is asserted, \n wherein when the multi-port memory operates in the second operation mode,\n the address control circuit activates the first word line and the second word line based on the first address signal, on condition that the first port enable signal that is input through the first port enable terminal is asserted and the second port enable signal that is input through the second port enable terminal is negated, and \n the address control circuit activates the first word line and the second word line based on the second address signal, on condition that the second port enable signal is asserted and the first port enable signal is negated.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.40426
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15281947', '15606562', '15885449', '14504994', '13750328']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8184003792577395
- 35 USC 102 Novelty (BERT): 0.5854473330033724
- Combined Prediction Score: 0.7951050746323028
- Mean Citation Score: 330.520802
- Max Citation Score: 501.18726
- Similarity Product: 470.3155140499089

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test