PATENT CLAIM ANALYSIS

Application Number: 15883179
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.

Claim (Index 7):
A method for manufacturing a semiconductor device, the method comprising:\n forming a first isolation structure and a plurality of second isolation structures in a substrate, wherein the plurality of second isolation structures define a crown structure in the substrate, and the first isolation structure defines a plurality of semiconductor fins in the crown structure; forming a gate stack over the plurality of semiconductor fins; forming a dielectric layer over upper surfaces of the plurality of second isolation structures, over an upper surface of the first isolation structure, and over upper surfaces of the plurality of semiconductor fins; performing an etching process, wherein the etching process removes portions of the dielectric layer to expose the upper surfaces of the plurality of second isolation structures and the upper surfaces of the plurality of semiconductor fins, wherein after the etching process, a remaining portion of the dielectric layer covers an entire upper surface of the first isolation structure; and forming an epitaxy structure on the plurality of semiconductor fins, wherein the epitaxy structure leaves at least one void over the first isolation structure.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.82143
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14854915', '14852441', '15635337', '15640645', '13970790']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9199039737340188
- 35 USC 102 Novelty (BERT): 0.4921038845510198
- Combined Prediction Score: 0.8771239648157189
- Mean Citation Score: 214.347494
- Max Citation Score: 267.83072000000004
- Similarity Product: 239.39505300052647

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test