PATENT CLAIM ANALYSIS

Application Number: 15916472
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "189050"]

Abstract:
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

Claim (Index 3):
The system according to  claim 2 , wherein\n the fourth write command designates a word line selected in response to the third write command, and a verify voltage that is used when the data of at least two pages is written in response to the fourth write command is higher than a verify voltage that is used when the data of at least two pages is written in response to the third write command.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 90.0
- Lexical Diversity: 3.18605
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15896365', '15693430', '15459294', '15702476', '15459542']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8206405238315612
- 35 USC 102 Novelty (BERT): 0.4892164431047675
- Combined Prediction Score: 0.7874981157588818
- Mean Citation Score: 235.27253
- Max Citation Score: 249.38452
- Similarity Product: 189.70754444840907

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test