PATENT CLAIM ANALYSIS

Application Number: 16000448
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "298000"]

Abstract:
In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Claim (Index 3):
The unit delay circuit of  claim 2 , wherein the first gate is configured to perform an AND operation on first input signal and the selection signal to output the first output signal, the second gate is configured to perform an AND operation on the first input signal and the selection signal to output the trigger signal, the third gate is configured to perform an OR operation on the second input signal and the trigger signal to output the second output signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13051204', '15234954', '15602239', '15198564', '12491567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7394077939499429
- 35 USC 102 Novelty (BERT): 0.4685808747007941
- Combined Prediction Score: 0.7123251020250281
- Mean Citation Score: 155.301334
- Max Citation Score: 173.3582
- Similarity Product: 140.6677923201561

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test