PATENT CLAIM ANALYSIS

Application Number: 15918536
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "154000"]

Abstract:
A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Claim (Index 10):
The semiconductor memory apparatus according to  claim 9 , wherein the data line repeater block includes at least one repeater which blocks data received through the data transmission line from being outputted to the memory bank region when the data masking signal is an enabled state, and outputs data received through the data transmission line to the memory bank region when the data masking signal is a disabled state.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.83871
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15706218', '15017994', '12232719', '15597795', '12459106']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5329857769823023
- 35 USC 102 Novelty (BERT): 0.4907027435983536
- Combined Prediction Score: 0.5287574736439075
- Mean Citation Score: 177.27008800000004
- Max Citation Score: 182.9408
- Similarity Product: 118.60421568908691

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test