PATENT CLAIM ANALYSIS

Application Number: 16141285
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["712", "215000"]

Abstract:
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Claim (Index 11):
The circuit arrangement of  claim 1 , wherein the second issue logic circuit is further configured to:\n in the first issue cycle, receive the early issue notification signal from the first issue logic circuit; also in the first issue cycle, issue a queued instruction for execution by the second execution slice; and in the second issue cycle, issue the second portion of the multi-width instruction for execution by the second execution slice.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 1.5
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15939367', '15093192', '14595549', '16048946', '15093172']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6583962433186555
- 35 USC 102 Novelty (BERT): 0.5597250991080284
- Combined Prediction Score: 0.6485291288975928
- Mean Citation Score: 354.655344
- Max Citation Score: 439.212
- Similarity Product: 404.9875713558197

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test