PATENT CLAIM ANALYSIS

Application Number: 16277267
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-08
Patent Classification: ["382", "154000"]

Abstract:
In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

Claim (Index 24):
An electronic device, comprising:\n a processor to:\n compute a first three-dimensional convolution across a set of three frames comprising a first frame, a second frame, and a third frame in an image sequence; \n store a convolutional data set for the second frame and the third frame in memory;\n receive a fourth frame in the image sequence; and \n \n use the convolutional data set for the second frame and the third frame to compute a second three-dimensional convolution across a set of three frames comprising the second frame, the third frame, and the fourth frame; and \n a computer readable memory communicatively coupled to the processor.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 99.0
- Lexical Diversity: 1.91667
- Patent Class: 382.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15489149', '15482724', '15581182', '15489015', '15494905']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.33264028985729
- 35 USC 102 Novelty (BERT): 0.5180076187163855
- Combined Prediction Score: 0.3511770227431996
- Mean Citation Score: 230.542614
- Max Citation Score: 299.86023
- Similarity Product: 289.7654170664728

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test