PATENT CLAIM ANALYSIS

Application Number: 15933235
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["331", "008000"]

Abstract:
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Claim (Index 3):
The apparatus of  claim 2 , wherein the first and second counters comprise first and second Gray code counters, respectively.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 1.52273
- Patent Class: 331.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13780173', '14588293', '14244800', '15048040', '13976223']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7575900318199277
- 35 USC 102 Novelty (BERT): 0.5047381984314391
- Combined Prediction Score: 0.7323048484810788
- Mean Citation Score: 164.271462
- Max Citation Score: 180.82045
- Similarity Product: 101.920914587754

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test