PATENT CLAIM ANALYSIS

Application Number: 15951426
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "189020"]

Abstract:
The present disclosure relates to a structure including a column multiplexor circuit with a plurality of bit line groups to perform a read operation of data using half of a plurality of column selection signals in the column multiplexor circuit, and each of the bit line groups comprises a reference bit line column, a plurality of transistors, and a plurality of bit lines.

Claim (Index 16):
A method, comprising:\n inputting data to a first reference bit line column included in a first bit line group in a column multiplexor circuit; selecting a second reference bit line column included in a second bit line group in the column multiplexor circuit as a first reference bit line signal; selecting a third reference bit line column included in a third bit line group in the column multiplexor circuit as an unused multiplexor output; selecting a fourth reference bit line column included in a fourth bit line group in the column multiplexor circuit as a second reference bit line signal; and performing a read operation of the data on the first reference bit line column in the column multiplexor circuit.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 91.0
- Lexical Diversity: 1.91429
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10694761', '11830077', '12398155', '12965504', '13827815']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7401732160757407
- 35 USC 102 Novelty (BERT): 0.4916023925836131
- Combined Prediction Score: 0.715316133726528
- Mean Citation Score: 157.03747600000003
- Max Citation Score: 167.35801999999995
- Similarity Product: 103.49201123918414

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test