PATENT CLAIM ANALYSIS

Application Number: 15746100
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "774000"]

Abstract:
The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.

Claim (Index 6):
A chip stack comprising:\n a substrate having an upper surface on which a substrate pad and a side pad are printed; a plurality of memory semiconductor dies of a multi-chip package type; a connecting member configured to electrically connect the memory semiconductor dies; and a bottom protective member configured to cover the memory semiconductor dies, the entire connecting member, and a part of the substrate.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.07407
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15435719', '14802750', '14028534', '12659391', '13313950']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90987539245709
- 35 USC 102 Novelty (BERT): 0.4535930893123977
- Combined Prediction Score: 0.8642471621426209
- Mean Citation Score: 161.118698
- Max Citation Score: 172.36106999999996
- Similarity Product: 150.73523774764712

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test