PATENT CLAIM ANALYSIS

Application Number: 16055405
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["257", "298000"]

Abstract:
Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

Claim (Index 8):
A method of manufacturing a memory device, the method comprising:\n patterning a substrate to form a first recess and a second recess using a first etching process; patterning the substrate to form a third recess using a second etching process; filling the first recess and the second recess with a dielectric material to form a first isolation region and a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate, wherein the third recess is in the first region; doping the substrate along sidewalls of the third recess; doping the substrate in the third region; forming source/drain regions in the second region; forming a dielectric layer over the first region, the second region, and the third region; and forming a conductive layer over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive layer comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 1.77143
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15242193', '13715641', '14599791', '14017022', '12822992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8893356680274432
- 35 USC 102 Novelty (BERT): 0.4950765289598351
- Combined Prediction Score: 0.8499097541206824
- Mean Citation Score: 166.29520399999996
- Max Citation Score: 210.7589
- Similarity Product: 152.62661035363078

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test