PATENT CLAIM ANALYSIS

Application Number: 15878280
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["327", "109000"]

Abstract:
Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Claim (Index 3):
The circuit of  claim 1 , wherein the FET is configured to receive a control voltage at the gate, and to provide a resistance between the source and the drain based on the control voltage.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 86.0
- Lexical Diversity: 1.76471
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11154135', '12357221', '14794496', '11092070', '11683074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7652748116930849
- 35 USC 102 Novelty (BERT): 0.4557230159313949
- Combined Prediction Score: 0.7343196321169159
- Mean Citation Score: 128.73976199999998
- Max Citation Score: 132.11263
- Similarity Product: 101.15088996397851

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test