PATENT CLAIM ANALYSIS

Application Number: 16181130
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Claim (Index 1):
A semiconductor device, comprising:\n a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein; a passivation layer overlying the semiconductor substrate; an interconnect structure overlying and interfacing a top surface of the passivation layer, the interconnect structure comprising a landing pad conductive element and a plurality of dummy conductive elements, wherein the landing pad conductive element and the dummy conductive elements are electrically separated; a protective layer overlying the interconnect structure and comprising a first opening exposing a portion of the landing pad conductive element and a second opening exposing a portion of each of the plurality of dummy conductive elements; a metal layer comprising a first portion on a topmost surface of the protective layer and on the exposed portion of the landing pad conductive element and a plurality of second portions on the topmost surface of the protective layer and on the exposed portion of the dummy conductive element, the plurality of second portions of the metal layer being electrically separated from the semiconductor substrate and from the first portion of the metal layer; and a single bump on the first portion of the metal layer overlying the landing pad conductive element; wherein each of the plurality of dummy conductive elements adjoins with a respective one of the plurality of second portions of the metal layer to from a plurality of pillars, the plurality of pillars surrounding the single bump in a plan view, and wherein an only bump surrounded by the plurality of pillars is the single bump.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.825
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13313811', '15477717', '13272540', '14058466', '13370895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9012564050056358
- 35 USC 102 Novelty (BERT): 0.4919093073505124
- Combined Prediction Score: 0.8603216952401234
- Mean Citation Score: 220.99029
- Max Citation Score: 258.40744
- Similarity Product: 234.2661470145036

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test