PATENT CLAIM ANALYSIS

Application Number: 15951554
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "189050"]

Abstract:
A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

Claim (Index 19):
The bitline sense amplifier of  claim 16 , further comprising an amplifier connected to the first power supply node and configured to amplify a difference between voltages at first and second output nodes, wherein the sensing circuit provides the sensing result to the amplifier.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 4.86667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15596558', '14264466', '11060308', '11496401', '12904302']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8091963843459816
- 35 USC 102 Novelty (BERT): 0.5419138121952621
- Combined Prediction Score: 0.7824681271309097
- Mean Citation Score: 297.77474999999987
- Max Citation Score: 410.84515
- Similarity Product: 369.6376450664282

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test