PATENT CLAIM ANALYSIS

Application Number: 16046252
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["257", "621000"]

Abstract:
Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a contact hole region at a front side of a first substrate; forming a semiconductor structure at the front side of the first substrate and the semiconductor structure having a first conductive contact, forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; and forming a second conductive layer above the exposed dielectric layer to connect the first conductive contact. The 3D integrated wiring structure can include a first substrate having a contact hole region; a dielectric layer disposed in the contact hole region; a semiconductor structure formed at the front side of the first substrate, having a first conductive contact; a recess formed at the backside of the first substrate to expose at least a portion of the dielectric layer; and a second conductive layer above the exposed dielectric layer.

Claim (Index 1):
A method for forming a 3D integrated wiring structure, comprising:\n forming a dielectric layer in a contact hole region at a front side of a first substrate; forming a semiconductor structure at the front side of the first substrate, comprising forming a semiconductor device layer, a first conductive layer at a front side of the semiconductor device layer, and a first conductive contact, wherein a first end of the first conductive contact connects to the first conductive layer and a second end of the first conductive contact extends vertically through at least a portion of the semiconductor device layer; forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; and forming a second conductive layer above the exposed dielectric layer to connect the first conductive contact.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 95.0
- Lexical Diversity: 3.64583
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16046248', '16046899', '12701672', '15611846', '14989206']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9155768943225888
- 35 USC 102 Novelty (BERT): 0.501702786630489
- Combined Prediction Score: 0.8741894835533788
- Mean Citation Score: 226.92578000000003
- Max Citation Score: 284.83182
- Similarity Product: 235.4068946530581

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test