PATENT CLAIM ANALYSIS

Application Number: 16043674
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["257", "331000"]

Abstract:
Trench gate power MOSFET with an on-region. Cells in the on-region include a first epitaxial layer and a channel region. First trenches corresponding to polysilicon gates penetrate through the channel region, and each polysilicon gate is etched to form a groove in the top, the grooves filled with an interlayer film. A source region formed on side faces of the grooves in a self-aligned mode through angled ion implantation. Through the source region of a side structure, the surface of a portion, between the first trenches, of the channel region is directly exposed and formed with a well contact region. A front metal layer is formed on the surfaces of the cells in the on-region and leads out a source. The front metal layer of the source directly makes contact with well contact region and source region to form a connection structure without contact holes.

Claim (Index 8):
A manufacturing method of a trench gate power MOSFET, comprising the following steps for forming a cell, wherein an on-region pf MOSFET is composed of a plurality of periodically-arrayed cells:\n Step 1, providing a first doped epitaxial layer of a first conduction type, forming a channel region in a surface area of the first epitaxial layer by a well of a second conduction type, and forming a drift region by the first epitaxial layer at a bottom of the channel region; Step 2, forming a hard mask layer on a surface of the first epitaxial layer, defining formation areas of a trench through a photolithograph process, and sequentially etching the hard mask layer and the first epitaxial layer to form the first trench penetrating through the channel region; Step 3, under a condition that the hard mask layer is reversed, forming gate dielectric layers on a bottom surface and side faces of the first trench, and then forming a polysilicon which completely fills the first trench and extends to a surface of the hard mask layer outside the first trench; Step 4, under the condition that the hard mask layer is reversed, etching the polysilicon back until all polysilicon outside the first trench in the on-region is removed, forming a polysilicon gate with a top surface lower than the top surface of the first trench by the polysilicon left in the first trench, and forming a groove in a top of each said polysilicon gate; Step 5, under the condition that the hard mask layer is reserved, conducting heavily-doped angled ion implantation of the first conduction type to form a source region of side structure in the first epitaxial layer of a side face of the groove; Step 6, removing the hard mask layer to directly expose a surface of the channel region located between adjacent first trenches; Step 7, forming an interlayer film, then etching the interlayer film back until the interlayer film in the on-region only fills the groove, and opening a surface of an area between the adjacent first trenches; Step 8, conducting heavily-doped implantation of the second conduction type to directly form a well contact region on the surface of the channel region between the adjacent first trenches, wherein the well contact region has a junction depth smaller than a depth of the source region, and the well contact region makes contact with the channel region and the source region at the same time; and Step 9, forming a front metal layer and patterning the front metal layer to from a source, wherein the front metal layer is formed on the surface of each cell in the on-region at the same time and the source is led out from the front metal layer, the front metal layer of the source directly makes contact with the well contact region and the source region of each cell in the on-region to form a connection structure without contact holes, and thus a pitch of the cells is decreased, and integrity of the device is improved.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.24286
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12137527', '14771089', '12458293', '13377029', '14019159']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9060327095207747
- 35 USC 102 Novelty (BERT): 0.5005962815554046
- Combined Prediction Score: 0.8654890667242379
- Mean Citation Score: 249.28664
- Max Citation Score: 260.66483
- Similarity Product: 211.5942548907244

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test