PATENT CLAIM ANALYSIS

Application Number: 16021352
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["257", "774000"]

Abstract:
An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.

Claim (Index 22):
A method comprising:\n forming a layer of transistors; forming a first interconnect layer on the layer of transistors, the first interconnect layer including a metal; forming an additional layer on the first interconnect layer; forming a first layer that includes a dielectric material, wherein forming the first layer that includes the dielectric material includes forming the first layer that includes the dielectric material on the additional layer; forming a first interconnect line in a second interconnect layer, wherein the first interconnect line includes the metal, the second interconnect layer includes the metal, and the second interconnect layer is formed on the first interconnect layer; forming a second interconnect line in the second interconnect layer, wherein the second interconnect line includes the metal; etching a void in the first layer that includes the dielectric material, the void extending from a top of the first interconnect line to a top of the additional layer; in response to etching the void in the first layer that includes the dielectric material, leaving a portion of the first layer that includes the dielectric material between the first interconnect line and the additional layer; forming a conformal layer on a bottom and opposing sidewalls of the void; forming a second layer that includes the dielectric material, wherein forming the second layer that includes the dielectric material includes forming the second layer that includes the dielectric material on the second interconnect layer; in response to forming the second layer that includes the dielectric material on the second interconnect layer, enclosing air within the void so the void is hollow; forming a third interconnect layer on the second layer that includes the dielectric material, wherein the third interconnect layer includes the metal; wherein (a) a first axis intersects the first and second interconnect lines and the void; (b) a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; and (c) a third axis, orthogonal to the first axis, intersects the second interconnect line and the additional layer.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 94.0
- Lexical Diversity: 4.91176
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16302692', '14137497', '15769432', '16015704', '15992685']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9075144531092296
- 35 USC 102 Novelty (BERT): 0.4686806219053286
- Combined Prediction Score: 0.8636310699888397
- Mean Citation Score: 162.01724
- Max Citation Score: 179.04112
- Similarity Product: 141.80049156986237

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test