PATENT CLAIM ANALYSIS

Application Number: 15918675
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["711", "158000"]

Abstract:
Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Claim (Index 39):
A non-transitory computer-readable medium having stored thereon executable instructions that, in response to execution by a processor, causes a system to perform operations, the operations comprising:\n receiving instructions that require a read request from a memory device, the instructions originating from multiple levels of a computing architecture, the multiple levels comprising at least an application level, a compiler level, an operating system level, and a micro-architectural level, wherein the instructions have associated priority indicators assigned in accordance with prioritization schemes respectively associated with the multiple levels, and the priority indicators comprise first priority indicators assigned to a first subset of the instructions originating at the application level based on relative priorities of applications that generate the first subset of the instructions, second priority indicators assigned to a second subset of the instructions originating at the network level based on a determination of whether the instructions originate from the network level or an internal level, and third priority indicators assigned to a third subset of the instructions originating at the operating system level based on a determination of whether the third subset of the instructions are associated with an interrupt at the operating system level; determining respective priorities of memory access requests associated with the instructions based on the priority indicators; propagating priority information identifying the respective priorities and the memory access requests from higher levels of the computing architecture to lower levels of the computing architecture; and propagating the priority information and the memory access requests to a memory controller.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 90.0
- Lexical Diversity: 1.85366
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14497619', '12886050', '14565255', '12317836', '13586708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4682504444851137
- 35 USC 102 Novelty (BERT): 0.5061467421351221
- Combined Prediction Score: 0.4720400742501146
- Mean Citation Score: 187.144694
- Max Citation Score: 311.73532
- Similarity Product: 298.9193858100748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test