PATENT CLAIM ANALYSIS

Application Number: 16108310
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["327", "065000"]

Abstract:
A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

Claim (Index 16):
The semiconductor circuit of  claim 12 , wherein the clocked comparator is configured to receive the first input signal and the second input signal from the host through a MIPI M-PHY layer of a UFS interface.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 96.0
- Lexical Diversity: 2.36364
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13797645', '15144929', '11848918', '13519316', '11357939']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7738204132543094
- 35 USC 102 Novelty (BERT): 0.4757209973722049
- Combined Prediction Score: 0.744010471666099
- Mean Citation Score: 162.53758799999997
- Max Citation Score: 166.89102
- Similarity Product: 117.97631656637192

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test