PATENT CLAIM ANALYSIS

Application Number: 15984185
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["713", "323000"]

Abstract:
Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S 0 ix) instead of a second low power consumption state (e.g., S 3 ) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Claim (Index 13):
The apparatus of  claim 1 , wherein the processor is to comprise a plurality of processor cores, wherein at least the first wake event or the second wake event is to cause at least one of the plurality of the processor cores to wake from the first or second low power consumption state.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 1.93103
- Patent Class: 713.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14139864', '14125497', '14731311', '14039220', '15153995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3924558292638374
- 35 USC 102 Novelty (BERT): 0.4531055633868957
- Combined Prediction Score: 0.3985208026761432
- Mean Citation Score: 140.43473400000002
- Max Citation Score: 194.64401
- Similarity Product: 188.52144007890527

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test