PATENT CLAIM ANALYSIS

Application Number: 15993963
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-09
Patent Classification: ["257", "040000"]

Abstract:
The present disclosure provides a TFT array substrate and an OLED display panel. The TFT array substrate includes a display area, a non-display area around the display area, a COF bonding area and a test area. The COF bonding area and the test area are arranged in the non-display area. The test area includes several test pads spaced apart. According to the present disclosure, the test pads are arranged on the TFT array substrate. Thus, during testing, it is not necessary to cut off the connection wire between the test pads and the TFT array substrate. Therefore, the problem of uncovered metal residue after the cut-off of the connection wire may be avoided. Moreover, when the test of the TFT array substrate is finished, the test pads will be covered by insulating material such that the problem of uncovered metal residue of the test pads can be avoided.

Claim (Index 4):
The TFT array substrate of  claim 3 , wherein the one portion of the TFT array substrate corresponding to the non-display area further comprises an organic insulating layer disposed on the second insulating layer and surrounding the first metal layer.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 93.0
- Lexical Diversity: 2.44776
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15824084', '15210386', '14435808', '10963925', '11643653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92130102615474
- 35 USC 102 Novelty (BERT): 0.4867766713356432
- Combined Prediction Score: 0.8778485906728303
- Mean Citation Score: 192.623058
- Max Citation Score: 208.81667
- Similarity Product: 155.26892137725412

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test