PATENT CLAIM ANALYSIS

Application Number: 16146446
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-07
Patent Classification: ["326", "038000"]

Abstract:
In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.

Claim (Index 21):
An apparatus comprising:\n a first configurable digital processing block; and a programmable digital interconnect coupled to the first configurable digital processing block, the programmable digital interconnect operable to couple the first configurable digital processing block to:\n a plurality of input/output (I/O) ports, \n at least one peripheral unit, and \n at least one processing element operable to send or receive control signals from the configurable digital processing block.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 97.0
- Lexical Diversity: 2.16279
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13197624', '13914308', '15848944', '11965677', '14968247']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7299205370225693
- 35 USC 102 Novelty (BERT): 0.5283762127295519
- Combined Prediction Score: 0.7097661045932676
- Mean Citation Score: 375.46062
- Max Citation Score: 382.0712
- Similarity Product: 315.4056326895237

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test