PATENT CLAIM ANALYSIS

Application Number: 16008920
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "410000"]

Abstract:
A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having width a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

Claim (Index 10):
The method of  claim 9 , wherein the etching process selectively removes portions of the interfacial layer, the high-k dielectric layer, or both.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 94.0
- Lexical Diversity: 3.04878
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14487252', '15964557', '13440848', '12437696', '13757573']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9292596463821228
- 35 USC 102 Novelty (BERT): 0.5020749579832477
- Combined Prediction Score: 0.8865411775422354
- Mean Citation Score: 248.347608
- Max Citation Score: 258.012
- Similarity Product: 188.24486633205413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test