PATENT CLAIM ANALYSIS

Application Number: 15880493
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["710", "308000"]

Abstract:
In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Claim (Index 22):
The computing node of  claim 21 , wherein the memory mapped interface further transmits a timeout or error notification to an interconnect controller when the outgoing region or the incoming region is determined to be unavailable.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.41935
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14389910', '14601228', '14671566', '12024397', '10439297']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6216208454408657
- 35 USC 102 Novelty (BERT): 0.4952239476628008
- Combined Prediction Score: 0.6089811556630592
- Mean Citation Score: 133.8042168
- Max Citation Score: 257.87292
- Similarity Product: 220.27511117207047

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test