PATENT CLAIM ANALYSIS

Application Number: 16245276
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "043000"]

Abstract:
An array substrate includes a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack. The active layer includes a source transfer portion and a drain transfer portion separated from the source transfer portion and a channel integrally connected to the source transfer portion and the drain transfer portion. Contact resistances between the source transfer portion, the drain transfer portion and the channel are reduced, and interface defects of the channel are reduced, so that through the source transfer portion and the drain transfer portion, an on-state current of a thin film transistor is increased and an off-state current is reduced so that is the on/off ratio is raised to improve the performance of the array substrate.

Claim (Index 7):
A liquid crystal display panel, comprising an array substrate that comprises a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack, wherein the active layer comprises a source transfer portion and a drain transfer portion separated from the source transfer portion, and a channel integrally connected to the source transfer portion and the drain transfer portion; wherein the source transfer portion and the drain transfer portion are formed at a first predetermined temperature and the channel is formed at a second predetermined temperature, the first predetermined temperature being higher than the second predetermined temperature;\n wherein the active layer, source transfer portion, and the drain transfer are simultaneously formed of a layer of a predetermined material, which comprises a first region and a second region respectively at two ends of the layer of the predetermined material and a third region located between and connected to the first and second regions, wherein surface parts of the first region and the second region that are adjacent to a surface of the metal oxide layer distant from the gate insulating layer are formed into the source transfer portion and the drain transfer portion at the first predetermined temperature, respectively, and the third region is formed, at the second predetermined temperature, into the channel that connects between the surface parts of the first and second regions that are formed into the source and drain transfer portions, wherein the surface parts of the first region and the second region that are formed into the source transfer portion and drain transfer portion are integral portions of the metal oxide layer and are integrally connected with the channel.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 99.0
- Lexical Diversity: 2.48148
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15125176', '10875559', '15740606', '15112195', '10608085']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912841095643158
- 35 USC 102 Novelty (BERT): 0.4988728957936653
- Combined Prediction Score: 0.8714442756582088
- Mean Citation Score: 209.49064600000003
- Max Citation Score: 263.85764
- Similarity Product: 203.58488229296685

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test