PATENT CLAIM ANALYSIS

Application Number: 15872845
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Claim (Index 13):
The semiconductor die assembly of  claim 12  wherein an average height of the second dummy pillars is less than an average height of the first dummy pillars.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.32308
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15380877', '15624493', '15345973', '14657900', '12706086']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9216318177373944
- 35 USC 102 Novelty (BERT): 0.5429780293905366
- Combined Prediction Score: 0.8837664389027086
- Mean Citation Score: 232.156538
- Max Citation Score: 397.41824
- Similarity Product: 273.48916089920044

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test