PATENT CLAIM ANALYSIS

Application Number: 15947378
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "315000"]

Abstract:
A method of forming a three-dimensional memory device includes forming memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a substrate, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film. The method also includes forming a stack of a first silicon nitride layer and a second silicon nitride layer over the memory stack structures, such that the first silicon nitride layer has a higher hydrogen-to-nitrogen ratio than the second silicon nitride layer, performing an anneal process at an elevated temperature to diffuse hydrogen from the first silicon nitride layer into the memory stack structures, and removing the first and second silicon nitride layers.

Claim (Index 20):
The method of  claim 1 , wherein:\n the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; the substrate comprises a silicon substrate; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings formed over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the array of monolithic three-dimensional NAND strings; the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and the array of monolithic three-dimensional NAND strings comprises:\n a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and \n a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.18333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15638672', '15863205', '15681886', '15581575', '15605204']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.928499844257374
- 35 USC 102 Novelty (BERT): 0.5726480859916565
- Combined Prediction Score: 0.8929146684308022
- Mean Citation Score: 429.069218
- Max Citation Score: 454.95248
- Similarity Product: 408.9134112007141

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test