PATENT CLAIM ANALYSIS

Application Number: 16173289
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["341", "118000"]

Abstract:
Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced digital-to-analog converter (DAC) topology to enable offset correction without the need for a dedicated compensation DAC. This eliminates addition analog circuitry and die area. To perform the offset correction, the differential SAR ADC couples together inputs thereof to create an offset voltage, converts the offset voltage into a digital representation thereof, stores the digital representation of the offset voltage in an offset register, and corrects for the offset voltage by generating an offset compensation voltage with the capacitor-reduced array DAC controlled by the digital representation stored in the offset register. The digital representation controls scaling of reference voltages to the reduced capacitor array DAC associated with a least-significant-bit (LSB) of the differential SAR ADC.

Claim (Index 3):
The method according to  claim 2 , wherein the plurality of reference voltages are binary weighted from Vrefp to Vrefn voltages.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 97.0
- Lexical Diversity: 2.07042
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16166733', '14255269', '15206433', '14871475', '15017995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6776736795264563
- 35 USC 102 Novelty (BERT): 0.5359216753128531
- Combined Prediction Score: 0.663498479105096
- Mean Citation Score: 333.71620599999994
- Max Citation Score: 357.2428
- Similarity Product: 248.7688480932474

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test