PATENT CLAIM ANALYSIS

Application Number: 16191074
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["375", "260000"]

Abstract:
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Claim (Index 1):
A data processing apparatus operable to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:\n an interleaver operable to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, an address generator operable to generate the set of addresses, the addresses being generated for the input symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the address generator comprising a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of\n R\u2032 i [7]= R\u2032 i-1 [0]\u2295 R\u2032 i-1 [1]\u2295 R\u2032 i-1 [5]\u2295 R\u2032 i-1 [6] \n the permutation order forms, with an additional bit, a nine bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R\u2032 i [n] in accordance with the table: R\u2032 i  bit positions 7 6 5 4 3 2 1 0 R i  bit positions 3 7 4 6 1 2 0 5 and the address generator includes an offset generator operable to add an offset to the formed nine bit address.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 1.85294
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12256746', '15080733', '12249306', '13615732', '13341532']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5723605578752387
- 35 USC 102 Novelty (BERT): 0.5484082722150839
- Combined Prediction Score: 0.5699653293092232
- Mean Citation Score: 406.714032
- Max Citation Score: 409.7795
- Similarity Product: 398.6488430719376

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test