PATENT CLAIM ANALYSIS

Application Number: 15868683
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "369000"]

Abstract:
A complimentary metal-oxide-semiconductor (CMOS) device includes a wafer having a bulk semiconductor layer. A fin-type semiconductor device is formed on a first portion of the wafer. The CMOS devices also includes a nanosheet semiconductor device formed on a second portion of the wafer different from the first portion.

Claim (Index 19):
The CMOS device of  claim 18 , wherein the NFET further comprises a pair of opposing tunnel spacers formed at opposing ends of each void.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 1.76667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15868742', '15342346', '15404469', '15339665', '15866851']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9207471740294644
- 35 USC 102 Novelty (BERT): 0.5249677336402565
- Combined Prediction Score: 0.8811692299905437
- Mean Citation Score: 286.816322
- Max Citation Score: 297.2113
- Similarity Product: 191.9987737474501

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test