PATENT CLAIM ANALYSIS

Application Number: 16105368
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["365", "194000"]

Abstract:
A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

Claim (Index 18):
A memory device comprising:\n a delay-locked loop circuit configured to generate a feedback clock signal and a locked-delayed clock signal by delaying a reference clock signal; a clock divider circuit configured to divide a source clock signal having a first frequency and to generate a divided clock signal having a second frequency being less than the first frequency; a clock selector configured to provide the divided clock signal as the reference clock signal in an initialization mode and provide the source clock signal as the reference clock signal in a normal operation mode; and a delay measurement circuit configured to measure a loop delay of the delay-locked loop circuit after a locking operation of the delay-locked loop circuit is completed in the initialization mode, the loop delay corresponding to a delay of the feedback clock signal with respect to the divided clock signal.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 96.0
- Lexical Diversity: 2.21818
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12697547', '15226310', '15399195', '14219181', '15258672']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7892478152166208
- 35 USC 102 Novelty (BERT): 0.5066820064640434
- Combined Prediction Score: 0.7609912343413631
- Mean Citation Score: 288.38359
- Max Citation Score: 302.08463
- Similarity Product: 247.7122933484996

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test