PATENT CLAIM ANALYSIS

Application Number: 16104921
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-04
Patent Classification: ["257", "339000"]

Abstract:
A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

Claim (Index 1):
A high voltage metal oxide semiconductor (MOS) device, which is formed in a semiconductor substrate, wherein the semiconductor substrate has atop surface and a bottom surface opposite to the top surface in a vertical direction, the high voltage MOS device comprising:\n a well with a first conductivity type, which is formed in the semiconductor substrate, and is located beneath the top surface and contacts the top surface in the vertical direction; a body region with a second conductivity type, which is formed in the well, and is located beneath the top surface and contacts the top surface in the vertical direction; a gate, which is formed on the top surface, wherein part of the gate stacks on and contacts right above part of the body region in the vertical direction; a source with the first conductivity type, which is formed in the body region, and is located beneath the top surface and contacts the top surface in the vertical direction, and the source is in contact with a first side of the gate in a lateral direction; a plurality of body contact regions, which have the second conductivity type, and are formed in the body region, wherein each of the plural body contact regions is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the first side of the gate in the lateral direction, wherein the plural body contact regions are arranged substantially in parallel in a width direction and any two neighboring body connecting regions are at least partially separated from each other in the width direction; and a drain with the first conductivity type, which is formed in the well and is located beneath the top surface and contacts the top surface in the vertical direction, and the drain is located outside a second side of the gate, wherein the source and the drain are separated by the body region and the well; wherein the gate includes a poly-silicon layer serving as an electrical contact of the gate, and all the poly-silicon layer has the first conductivity type.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 96.0
- Lexical Diversity: 2.36667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15662277', '15889051', '16057725', '15937741', '10996849']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9036417954130366
- 35 USC 102 Novelty (BERT): 0.484460024974146
- Combined Prediction Score: 0.8617236183691476
- Mean Citation Score: 229.962944
- Max Citation Score: 258.28168
- Similarity Product: 255.37269629429343

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test