PATENT CLAIM ANALYSIS

Application Number: 15913407
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "158000"]

Abstract:
According to one embodiment, a memory includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.

Claim (Index 5):
The resistance change type memory of  claim 1 , wherein\n the read circuit further includes a third transistor, and one terminal of the third transistor is connected to the other terminal of the first transistor, and the other terminal of the third transistor is connected to a power supply terminal.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 90.0
- Lexical Diversity: 3.22222
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14201664', '14018011', '14018242', '14811237', '15694587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.785456735182101
- 35 USC 102 Novelty (BERT): 0.4936748395023064
- Combined Prediction Score: 0.7562785456141216
- Mean Citation Score: 218.611286
- Max Citation Score: 230.75874
- Similarity Product: 169.0927990071058

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test