PATENT CLAIM ANALYSIS

Application Number: 16048960
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "737000"]

Abstract:
A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Claim (Index 8):
A method comprising:\n bonding a device die to a wafer; encapsulating the device die in an encapsulant; forming an opening in a semiconductor substrate of the wafer to reveal a conductive feature in the wafer; forming a dielectric layer extending into the opening, with the conductive feature being covered by the dielectric layer; removing a portion of the dielectric layer to reveal the conductive feature again; and forming a metal layer extending into the opening, wherein the metal layer has a bottom portion in contact with the conductive feature.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.35135
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15229302', '14724694', '16028763', '14981204', '14599872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916275547230871
- 35 USC 102 Novelty (BERT): 0.4923615721169557
- Combined Prediction Score: 0.8738841497194796
- Mean Citation Score: 175.78573999999998
- Max Citation Score: 203.50955
- Similarity Product: 140.51374149416685

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test