PATENT CLAIM ANALYSIS

Application Number: 16136046
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["327", "158000"]

Abstract:
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second arid third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

Claim (Index 15):
The apparatus of  claim 11 , further comprising:\n a duty cycle adjuster; and a buffer coupled between the clock divider circuit and the duty cycle adjuster, the duty cycle adjuster configured to adjust a duty cycle of the divided clock signal provided, via the buffer, by the clock divider circuit.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 97.0
- Lexical Diversity: 1.97674
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15786362', '13415777', '11643916', '11000940', '15059453']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7333853818838175
- 35 USC 102 Novelty (BERT): 0.5348971761617439
- Combined Prediction Score: 0.7135365613116101
- Mean Citation Score: 241.812814
- Max Citation Score: 366.8524
- Similarity Product: 267.7435266337872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test