PATENT CLAIM ANALYSIS

Application Number: 15959291
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-09
Patent Classification: ["257", "773000"]

Abstract:
A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

Claim (Index 19):
A semiconductor structure comprising conductive lines, comprising:\n a substrate which is divided into a memory region and a peripheral region; a first dielectric layer covering and in direct contact with the substrate; a first conductive line disposed in the peripheral region and in direct contact with the first dielectric layer ; a silicon nitride layer covering and in direct contact with the first conductive line; a silicon carbon nitride layer covering and in direct contact with the silicon nitride layer; and a second dielectric layer covering and in direct contact with the silicon carbon nitride layer.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 2.02222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15915042', '15602114', '15284552', '11241924', '11284237']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8975000389909721
- 35 USC 102 Novelty (BERT): 0.4865184268791118
- Combined Prediction Score: 0.8564018777797862
- Mean Citation Score: 190.87835
- Max Citation Score: 197.10646
- Similarity Product: 148.48102692186475

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test