PATENT CLAIM ANALYSIS

Application Number: 15970884
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["717", "137000"]

Abstract:
Methods and systems for mapping computer code to wires and gates are disclosed. An example method may include acquiring a code written in a programming language and generating, based on the code, a finite state machine (FSM). The method may further include generating, based on the FSM, a wires and gates representation, the wires and gates representation including a plurality of wires and a plurality of combinatorial logics. The method may further include configuring, based on the wires and gates representation, a field-programmable gate array. Input of each of the plurality of wires may represent a symbol selected from a set of symbols of a structured data packet. The size of the symbol can be equal to a number of bits of the structured data packet transferred per a clock cycle according to a data transmission protocol.

Claim (Index 6):
The method of  claim 5 , wherein a number of gates and a number of wires in the wires and gates representation is optimized based on a rate of the transferring protocol or a structure of the structured data packet.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 93.0
- Lexical Diversity: 2.14085
- Patent Class: 717.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15630691', '12609604', '10742284', '12393977', '10402659']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3318612922494752
- 35 USC 102 Novelty (BERT): 0.515299178948014
- Combined Prediction Score: 0.3502050809193291
- Mean Citation Score: 131.32723520000002
- Max Citation Score: 172.94145
- Similarity Product: 105.91687840295435

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test