PATENT CLAIM ANALYSIS

Application Number: 16170479
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["714", "727000"]

Abstract:
A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

Claim (Index 15):
A method of operating a test circuit, comprising:\n generating first and second outputs from an LBIST mode signal and an ATPG mode signal, the first output having a first logic state when the test circuit is operating in either an ATPG mode or a LBIST mode, the second output having a second logic state when the test circuit is operating in either the ATPG mode or the LBIST mode; receiving an ATPG clock and a functional clock; outputting a selected one of the ATPG clock and the functional clock; enabling a first latch as a function of an inverse of the selected one of the ATPG clock and the functional clock, and latching the second output as a first latch output; enabling a second latch as a function of the inverse of the selected one of the ATPG clock and the functional clock, and latching the first output as a second latch output; generating a first AND gate output as a function of a logic AND operation performed on the first latch output and the selected one of the ATPG clock and the functional clock; generating a second AND gate output as a function of a logical AND operation performed on the second latch output and the selected one of the ATPG clock and an LBIST clock; and generating a test clock as a clock gate OR gate output as a function of a logical OR operation performed on the first AND gate output and the second AND gate output.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 3.25
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15268848', '15473100', '15466001', '14152879', '15443990']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3488707613476356
- 35 USC 102 Novelty (BERT): 0.5900527694413833
- Combined Prediction Score: 0.3729889621570104
- Mean Citation Score: 346.330048
- Max Citation Score: 525.98737
- Similarity Product: 463.6342307918037

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test