PATENT CLAIM ANALYSIS

Application Number: 15896091
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["257", "773000"]

Abstract:
A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

Claim (Index 8):
A semiconductor device, comprising:\n a bit line structure on a substrate; a first spacer around the bit line structure; a second spacer on a sidewall of the first spacer, wherein the second spacer comprises a bottom portion and a top portion, the bottom portion and the top portion comprise different dielectric materials, the bottom portion comprises silicon oxide and the top portion comprises silicon nitride, and sidewalls of the bottom portion are vertically aligned with sidewalls of the top portion; and a third spacer on a sidewall of the second spacer.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 88.0
- Lexical Diversity: 2.06977
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15830008', '15172161', '15706655', '15643488', '15092076']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907438761166277
- 35 USC 102 Novelty (BERT): 0.4713174726369759
- Combined Prediction Score: 0.8638266323133469
- Mean Citation Score: 158.15595000000005
- Max Citation Score: 164.39122
- Similarity Product: 122.3564059285212

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test