PATENT CLAIM ANALYSIS

Application Number: 16114491
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "140000"]

Abstract:
A method of manufacturing a semiconductor device includes forming a first trench and a second trench on a surface of a semiconductor substrate, the second trench being narrower than the first trench; forming an emitter connecting part and a trench gate that are separated from each other in the first trench and forming an embedded electrode in the second trench; forming a center insulating film in the first trench between the emitter connecting part and the trench gate; forming an interlayer insulating layer on the semiconductor substrate; forming a contact hole in the interlayer film at a location corresponding to the second trench; and forming an electrode material on the insulating layer so as to connect the electrode material and the embedded electrode in the second trench via the contact hole.

Claim (Index 1):
A method of manufacturing a semiconductor device, comprising:\n forming a first trench and a second trench on a surface of a semiconductor substrate, the second trench being narrower than the first trench; forming an insulating film on the surface of the semiconductor substrate as well as on inner surfaces of the first trench and inner surfaces of the second trench; forming a conductive material layer on the surface of the semiconductor substrate as well as inside the first trench and second trench; selectively removing the conductive material layer formed on the surface of the semiconductor substrate and on a bottom of the first trench via anisotropic etching so as to form an emitter connecting part and a trench gate that are separated from each other in the first trench and forming an embedded electrode in the second trench, the embedded electrode being electrically connected to the emitter connecting part or the trench gate; forming a center insulating film in the first trench between the emitter connecting part and the trench gate; forming an interlayer insulating layer on the semiconductor substrate; forming a contact hole in the interlayer film at a location corresponding to the second trench; and forming an electrode material on the insulating layer so as to connect the electrode material and the embedded electrode in the second trench via the contact hole.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.55556
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14954867', '14470889', '15658049', '15411268', '15005195']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9259471471183814
- 35 USC 102 Novelty (BERT): 0.5322873930598061
- Combined Prediction Score: 0.8865811717125239
- Mean Citation Score: 308.5265960000001
- Max Citation Score: 370.89627
- Similarity Product: 303.4571338218087

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test