PATENT CLAIM ANALYSIS

Application Number: 16007321
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["348", "660000"]

Abstract:
A matrix switcher is provided. A code rate of an ultra-high-definition video signal is reduced on the premise that the quality of the ultra-high-definition video signal is not affected through performing a Color Space Conversion (CSC) process and/or a Digital Stream Compression (DSC) process on the ultra-high-definition video signal at the transmitting side chip, thereby reducing a bandwidth required in conversion, switch and transmission of the ultra-high-definition video signal. A matrix switch chip with a low cost and general performance is used. Then, a corresponding DSC data decompression process and/or CSC process are performed at the receiving side to recover the performance of the ultra-high-definition video signal.

Claim (Index 1):
A matrix switcher, comprising: M transmitting side chips, K matrix switch chips and N receiving side chips, wherein\n the M transmitting side chips are connected to the N receiving side chips via the K matrix switch chips, the K matrix switch chips are configured to forward at least one group of input signals transmitted from the M transmitting side chips to the N receiving side chips, each of M, K and N is an integer greater than or equal to 1, and the value of each of M and N is greater than the value of K; each of the transmitting side chips comprises:\n a signal receiving circuit, configured to receive an ultra-high-definition video signal and unpack the ultra-high-definition video signal; \n a logic processor, configured to perform at least one of a Color Space Conversion (CSC) process and a Digital Stream Compression (DSC) process on the unpacked ultra-high-definition video signal to generate a compressed video signal; and \n a signal transmitting circuit, configured to transmit the compressed video signal to the K matrix switch chips through four universal high-speed differential serial ports SERializer/DESerializer (SERDESs), and \n each of the receiving side chips comprises:\n a signal receiving circuit, configured to receive the compressed video signal outputted from the K matrix switch chips through the four SERDESs; \n a logic processor, configured to perform at least one of a DSC data decompression process and a CSC process on the compressed video signal to generate a decompressed video signal; and \n a signal transmitting circuit, configured to recover the decompressed video signal to generate an ultra-high-definition video signal and transmit the recovered ultra-high-definition video signal to an external device.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 1.81538
- Patent Class: 348.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15534432', '14771702', '14500938', '15259895', '13630798']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6001743270011795
- 35 USC 102 Novelty (BERT): 0.4966430011057234
- Combined Prediction Score: 0.5898211944116338
- Mean Citation Score: 171.3569
- Max Citation Score: 202.0832
- Similarity Product: 127.18276160850525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test