PATENT CLAIM ANALYSIS

Application Number: 15873006
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

Claim (Index 10):
A semiconductor structure comprising:\n a semiconductor fin having a first top surface and first opposing sides; isolation regions in the semiconductor fin and having second top surfaces that are substantially co-planar with the first top surface of the semiconductor fin and further having second opposing sides; isolation bumps on the isolation regions, respectively, and having third top surfaces; bump sidewall spacers positioned laterally adjacent to the isolation bumps and having at least outer portions above and immediately adjacent to the first top surface of the semiconductor fin; non-functional gate structures being above and immediately adjacent to the third top surfaces of the isolation bumps; a transistor between the isolation regions and comprising:\n source/drain regions in the semiconductor fin; \n a channel region within the semiconductor fin and positioned laterally between the source/drain regions such that each source/drain region has a first side adjacent to the channel region and a second side opposite the first side so as to be adjacent to but physically separated from one of the isolation regions; and \n a functional gate structure adjacent to the first top surface and the first opposing sides of the semiconductor fin at the channel region; \n gate sidewall spacers positioned laterally adjacent to the non-functional gate structures and the functional gate structure, wherein any of the gate sidewall spacers that are positioned laterally adjacent to the non-functional gate structures are above and immediately adjacent to the third top surfaces of the isolation bumps and further extend laterally onto the bump sidewall spacers; and a dielectric layer adjacent to the first opposing sides of the semiconductor fin at the source/drain regions and the second opposing sides of the isolation regions, wherein the isolation bumps extends laterally beyond the second opposing sides of the isolation regions onto the dielectric layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.07895
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15589292', '15487636', '15387933', '15862064', '15658835']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92990026536351
- 35 USC 102 Novelty (BERT): 0.5690356142534879
- Combined Prediction Score: 0.8938138002525079
- Mean Citation Score: 360.567114
- Max Citation Score: 473.23163
- Similarity Product: 390.5389015297836

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test