PATENT CLAIM ANALYSIS

Application Number: 15895321
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["326", "038000"]

Abstract:
A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.

Claim (Index 17):
The method of  claim 15 , wherein mapping the Boolean function to the second PLU includes:\n mapping the second sub-function to the first RHL in response to the third NPN being included in the first list; mapping the second sub-function to the second RHL in response to the third NPN not being included in the first list and being included in the second list; and mapping the second sub-function to the third RHL in response to the third NPN not being included in any of the first list and the second list, and being included in the third list.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 88.0
- Lexical Diversity: 2.0303
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['09754632', '14458456', '14089238', '14890911', '15224224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6713079173826746
- 35 USC 102 Novelty (BERT): 0.4958733776329591
- Combined Prediction Score: 0.6537644634077031
- Mean Citation Score: 170.86310399999996
- Max Citation Score: 185.4701
- Similarity Product: 109.61066614651084

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test