PATENT CLAIM ANALYSIS

Application Number: 15965076
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-01
Patent Classification: ["438", "126000"]

Abstract:
A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.

Claim (Index 8):
The method of  claim 1 , wherein the thermal annealing process is performed at a temperature from 600\u00b0 C. to 800\u00b0 C.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 91.0
- Lexical Diversity: 2.92727
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15454118', '15725174', '15785071', '14787773', '14601745']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.862967188772002
- 35 USC 102 Novelty (BERT): 0.4942813437895217
- Combined Prediction Score: 0.826098604273754
- Mean Citation Score: 174.26786399999995
- Max Citation Score: 192.77573
- Similarity Product: 126.91730121794224

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test