PATENT CLAIM ANALYSIS

Application Number: 16055405
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["257", "298000"]

Abstract:
Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

Claim (Index 6):
The method of  claim 1 , wherein the dielectric layer and the conductive electrode extend continuously from the first isolation region to the second isolation region.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 1.77143
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15242193', '13715641', '14599791', '14017022', '12822992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9003991209255505
- 35 USC 102 Novelty (BERT): 0.4985823194413937
- Combined Prediction Score: 0.8602174407771349
- Mean Citation Score: 166.29520399999996
- Max Citation Score: 210.7589
- Similarity Product: 150.59297709013225

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test