PATENT CLAIM ANALYSIS

Application Number: 16169480
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["710", "022000"]

Abstract:
A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

Claim (Index 9):
The memory management circuit of  claim 1 , further comprising a second DMA channel, the second DMA channel including:\n logic configured to receive a second buffer of data to be written using DMA; and a second circuit including logic configured to perform bit manipulation in real-time during a DMA write cycle of the second buffer of data; wherein:\n the first buffer of data includes mask information for the second circuit; \n the first circuit is configured to issue a trigger to the second DMA channel upon loading data into the first buffer; and \n upon reception of the trigger, the second circuit is configured to apply bit manipulation using the mask information from the first buffer of data to the second buffer during a DMA write of the second buffer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 1.6
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11080376', '11132070', '11626414', '12205386', '13791345']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6684619555259066
- 35 USC 102 Novelty (BERT): 0.475115376265897
- Combined Prediction Score: 0.6491272975999056
- Mean Citation Score: 165.02706
- Max Citation Score: 171.05841
- Similarity Product: 119.71241807569209

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test