PATENT CLAIM ANALYSIS

Application Number: 16039921
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["327", "231000"]

Abstract:
During a period in which a first signal S 1  and second signal S 2  are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal S OUT  our that changes level when the capacitor voltage crosses a predetermined threshold value V TH . Each circuit unit includes a resistor R g  and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S 1  is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S 2  is the second level and the corresponding bit of the input code is a second value.

Claim (Index 6):
The phase interpolator according to  claim 1 , wherein one end of the resistor is coupled to the intermediate line,\n and wherein the first path is arranged between the other end of the resistor and the second line.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 95.0
- Lexical Diversity: 2.44776
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15258696', '10022551', '13538276', '10371248', '10278800']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.767808288657644
- 35 USC 102 Novelty (BERT): 0.4908104178970267
- Combined Prediction Score: 0.7401085015815821
- Mean Citation Score: 224.741762
- Max Citation Score: 235.53111
- Similarity Product: 188.046630777728

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test