PATENT CLAIM ANALYSIS

Application Number: 16278339
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["365", "193000"]

Abstract:
A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

Claim (Index 3):
The semiconductor memory device of  claim 2 , wherein an EDC hold pattern is generated for each rank when the semiconductor memory device has a multi-rank structure.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 1.7619
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15081071', '15938092', '15624491', '13828869', '16249594']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8122652015001666
- 35 USC 102 Novelty (BERT): 0.5441195088078248
- Combined Prediction Score: 0.7854506322309324
- Mean Citation Score: 272.540272
- Max Citation Score: 429.03146
- Similarity Product: 304.3738659970212

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test