PATENT CLAIM ANALYSIS

Application Number: 15910360
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "738000"]

Abstract:
A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

Claim (Index 13):
The semiconductor device package of  claim 12 , wherein:\n the first interconnect structures extend through openings in the block material and are in direct physical contact with the metal segments of the redistribution layer nearest the substrate; and the second interconnect structures are in direct physical contact with the metal segments of the redistribution layer nearest the at least one chip.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 3.375
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14731380', '14814524', '14731382', '15396817', '14745473']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919905488429198
- 35 USC 102 Novelty (BERT): 0.5244898009642502
- Combined Prediction Score: 0.8803639196827033
- Mean Citation Score: 228.011048
- Max Citation Score: 326.79114
- Similarity Product: 243.05505145516275

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test