PATENT CLAIM ANALYSIS

Application Number: 16037111
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
According to one embodiment, a storage system receives, from a host, a data copy command including an address of a copy source block, an address of a copy start page in the copy source block, an address of a copy destination block, an address of a transfer start page in the copy destination block, management data indicating validity/invalidity of data in each page, and a termination condition. The storage system starts, beginning with the copy start page, a data copy operation of copying valid data in the copy source block to a copy destination region of the copy destination block beginning with the transfer start page of the copy destination block, and skipping copying of invalid data in the copy source block.

Claim (Index 6):
An information processing system comprising:\n a memory system; and a host device including a processor, the processor programmed to control the memory system, the memory system including: a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for erasing of data and including a plurality of pages, each of the pages being a unit for reading and writing of data and configured to store a plurality of data units; and a controller electrically connected to the nonvolatile memory and configured to receive, from the host device, a data copy command that includes management data and designates a copy source and a copy destination, the management data being indicative of validity or invalidity of each of data units stored in a first page in a first block of the copy source, wherein in a case where the first page in the first block stores a valid data unit and an invalid data unit, the controller copies the valid data unit to a second page in a second block of the copy destination and does not copy the invalid data unit to the second page in the second block, and the controller notifies the host device of an identifier of the copied valid data unit, and information indicating a location in the second block where the valid data unit is stored, and wherein the processor is configured to manage an address translation table which manages mapping between a logical block address of a data unit and a physical address in the nonvolatile memory where the data unit is stored, and update the address translation table based on the notified identifier and the notified information.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 3.06818
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15250011', '15249968', '15249924', '15250215', '15700376']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5283052937299701
- 35 USC 102 Novelty (BERT): 0.5715744664986917
- Combined Prediction Score: 0.5326322110068423
- Mean Citation Score: 360.480316
- Max Citation Score: 462.83438
- Similarity Product: 393.65944883963584

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test