PATENT CLAIM ANALYSIS

Application Number: 16279721
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["711", "120000"]

Abstract:
Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

Claim (Index 11):
The data processing apparatus of  claim 10 , comprising:\n a second level cache; and a second memory controller to control access to the second level cache; wherein the first memory controller is configured to provide the pending service request corresponding to the first entry to the second memory controller for servicing using the second level cache.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 99.0
- Lexical Diversity: 2.17391
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15730893', '14579654', '14581487', '15270018', '14335351']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.517216417266943
- 35 USC 102 Novelty (BERT): 0.5700609030655713
- Combined Prediction Score: 0.5225008658468059
- Mean Citation Score: 341.22142
- Max Citation Score: 495.50256
- Similarity Product: 345.50918843719484

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test