PATENT CLAIM ANALYSIS

Application Number: 16128414
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["257", "777000"]

Abstract:
Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.

Claim (Index 17):
The device of  claim 13  wherein the substrate is a first substrate, and wherein the first substrate, the first die, the second die, the first plurality of interconnects, and the second plurality of interconnects together comprise a first stacked package, the device further comprising a second stacked package spaced apart from the first stacked package and including:\n a second substrate having an upper surface and a lower surface; \n a third die mounted to the upper surface of the second substrate and including an active side and a plurality of third inductors at the active side of the third die; \n a fourth die mounted to the third die in an offset position such that an edge of the fourth die extends beyond a corresponding edge of the third die, wherein the fourth die includes an active side and a plurality of fourth inductors at the active side of the fourth die, and wherein one or more of the third inductors are inductively coupled to one or more corresponding fourth inductors; and \n a third plurality of interconnects electrically coupling the second substrate to the third die; and \n a fourth plurality of interconnects electrically coupling and extending from the active side of the fourth die to the lower surface of second substrate.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 97.0
- Lexical Diversity: 3.06122
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15693039', '15481331', '14264584', '15144699', '15007615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9149852862382852
- 35 USC 102 Novelty (BERT): 0.5098170654155941
- Combined Prediction Score: 0.8744684641560161
- Mean Citation Score: 204.640584
- Max Citation Score: 280.2919
- Similarity Product: 198.1069356760144

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test