PATENT CLAIM ANALYSIS

Application Number: 16113470
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-11
Patent Classification: ["365", "189011"]

Abstract:
According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.

Claim (Index 6):
The semiconductor memory device according to  claim 1 , further comprising:\n a discharge circuit connected to the first bit line, wherein the discharge circuit adjusts a current amount discharged from the first bit line when the first bit line transitions from the first voltage to the second voltage.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 96.0
- Lexical Diversity: 2.52381
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15174114', '15909404', '16112378', '15410470', '15051546']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7670670029876963
- 35 USC 102 Novelty (BERT): 0.4858106475476594
- Combined Prediction Score: 0.7389413674436927
- Mean Citation Score: 222.07650400000003
- Max Citation Score: 228.69054
- Similarity Product: 177.62874507287978

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test