PATENT CLAIM ANALYSIS

Application Number: 15941405
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-06
Patent Classification: ["257", "774000"]

Abstract:
A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.

Claim (Index 14):
The fan-out semiconductor package of  claim 10 , wherein the core member includes a first insulating layer, a first wiring layer in contact with the connection member and embedded in the first insulating layer, and a second wiring layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first wiring layer is embedded, and\n the first and second wiring layers are electrically connected to the semiconductor chip.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 90.0
- Lexical Diversity: 1.98077
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15941334', '15882440', '15928845', '15923308', '15663042']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9383914804967308
- 35 USC 102 Novelty (BERT): 0.5247030200629401
- Combined Prediction Score: 0.8970226344533517
- Mean Citation Score: 326.770886
- Max Citation Score: 347.41977
- Similarity Product: 300.28261489799024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test