PATENT CLAIM ANALYSIS

Application Number: 16410992
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "324000"]

Abstract:
Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

Claim (Index 6):
The memory cell of  claim 1  wherein the first and second regions are not a same composition as one another.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 100.0
- Lexical Diversity: 2.48214
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16102987', '15409412', '15975902', '15458572', '15933218']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9263080821705204
- 35 USC 102 Novelty (BERT): 0.49655784279278
- Combined Prediction Score: 0.8833330582327464
- Mean Citation Score: 239.027102
- Max Citation Score: 292.2234
- Similarity Product: 288.75825371811385

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test