PATENT CLAIM ANALYSIS

Application Number: 16034470
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["710", "306000"]

Abstract:
A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

Claim (Index 2):
The SoC of  claim 1 , further comprising:\n a graphic processor unit (GPU) connected to the first bus; and a memory controller connected to the first bus, wherein the controller is configured to reset, after isolation of the multi-core processor, the GPU and the memory controller.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 2.85714
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14588287', '10028804', '10426010', '14865005', '11744233']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6560743080974744
- 35 USC 102 Novelty (BERT): 0.468987063196564
- Combined Prediction Score: 0.6373655836073834
- Mean Citation Score: 155.875246
- Max Citation Score: 166.8787
- Similarity Product: 122.4963209807396

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test