PATENT CLAIM ANALYSIS

Application Number: 15924001
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-08
Patent Classification: ["257", "343000"]

Abstract:
A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

Claim (Index 14):
The transistor structure as claimed in  claim 13 , wherein the transistor device further comprises:\n a body region, located at one side of the gate structure in the substrate and having the first conductive type, wherein the second doped region and the fourth doped region are located in the body region; and a drift region, located at the other side of the gate structure in the substrate and having the second conductive type, wherein the third doped region is located in the drift region.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.89474
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15823606', '15251829', '15148090', '11047418', '11937502']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.910110732225402
- 35 USC 102 Novelty (BERT): 0.4883596986294053
- Combined Prediction Score: 0.8679356288658024
- Mean Citation Score: 202.782908
- Max Citation Score: 210.88443
- Similarity Product: 166.55614324953854

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test