PATENT CLAIM ANALYSIS

Application Number: 16135606
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "367000"]

Abstract:
A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Claim (Index 3):
A structure, comprising:\n a plurality of field effect transistor cells; and a diode disposed between a pair of adjacent ones of the cells.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 2.69643
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15469102', '14947197', '15279637', '12870600', '12242633']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9279545517027696
- 35 USC 102 Novelty (BERT): 0.561314257951179
- Combined Prediction Score: 0.8912905223276104
- Mean Citation Score: 334.498402
- Max Citation Score: 475.0706
- Similarity Product: 339.98227489032746

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test