PATENT CLAIM ANALYSIS

Application Number: 16233283
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "156000"]

Abstract:
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Claim (Index 11):
The PLL of  claim 10 , wherein:\n the digital loop filtered is configured to maintain its output value at the fixed output value upon the multiplexer being configured to provide the different reference clock; based on a predetermined time period after configuring the multiplexer to provide the different reference clock, reconfiguring the digital loop to filter to cause the output values from the digital loop filter to be dynamically generated by the digital loop filter based on the adder circuit output value.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.95652
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16227777', '16226938', '16218970', '12956498', '12874462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8018953476296098
- 35 USC 102 Novelty (BERT): 0.5220693137010629
- Combined Prediction Score: 0.773912744236755
- Mean Citation Score: 252.211654
- Max Citation Score: 322.83585
- Similarity Product: 250.82038690586683

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test