PATENT CLAIM ANALYSIS

Application Number: 15980111
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "329000"]

Abstract:
A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

Claim (Index 9):
The method of  claim 8 , wherein the dummy gate block has a thickness in a range of about 10 nm to about 50 nm.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 3.26087
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15416281', '15177362', '15450715', '15860957', '15846887']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9431836028063608
- 35 USC 102 Novelty (BERT): 0.5356354109680144
- Combined Prediction Score: 0.902428783622526
- Mean Citation Score: 374.614166
- Max Citation Score: 380.76883
- Similarity Product: 240.0100492665005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test