PATENT CLAIM ANALYSIS

Application Number: 15988375
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "024000"]

Abstract:
Semiconductor devices include a thin channel region formed on a buried insulator. A source and drain region is formed on the buried insulator, separated from the channel region by notches. A gate structure is formed on the thin channel region.

Claim (Index 16):
A semiconductor device, comprising:\n a buried insulator layer; an etch stop layer, formed directly on the buried insulator layer, comprising an undoped first semiconductor material; a thin channel region, formed directly on the etch stop layer, comprising a doped second semiconductor material that is different from the first semiconductor material; a source and drain region formed on the buried insulator, physically separated from the channel region by notches that are formed along a consistent crystal face of the respective channel region and source and drain regions; a dielectric layer formed in the notches to create a Coulomb blockade between the channel region and the source and drain regions; and a gate structure formed on the thin channel region.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 1.76
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15170448', '15921877', '15282349', '14585885', '14958171']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9186932216817496
- 35 USC 102 Novelty (BERT): 0.5055204657446396
- Combined Prediction Score: 0.8773759460880386
- Mean Citation Score: 245.850684
- Max Citation Score: 295.1066600000001
- Similarity Product: 242.31068792434817

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test