PATENT CLAIM ANALYSIS

Application Number: 15890943
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["375", "372000"]

Abstract:
An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.

Claim (Index 5):
The apparatus of  claim 4 , wherein the latency information comprises a CAS latency and a CAS write latency.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 1.70175
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15243651', '15139120', '13531341', '14285476', '13364198']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5256800757237258
- 35 USC 102 Novelty (BERT): 0.5391201576951229
- Combined Prediction Score: 0.5270240839208655
- Mean Citation Score: 258.267984
- Max Citation Score: 386.91202
- Similarity Product: 271.9893061966372

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test