PATENT CLAIM ANALYSIS

Application Number: 15968360
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-08
Patent Classification: ["257", "737000"]

Abstract:
Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Claim (Index 36):
The apparatus of  claim 35 , wherein the interconnects of a row from the plurality of rows are horizontally offset from interconnects of an adjacent row from the plurality of rows such that interconnects of the row are spaced from the interconnects of the adjacent row by at least the first pitch.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 1.20833
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15259980', '13865499', '15154770', '11459081', '15722983']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912322862433376
- 35 USC 102 Novelty (BERT): 0.5171898129549856
- Combined Prediction Score: 0.872809557485537
- Mean Citation Score: 134.29587199999995
- Max Citation Score: 139.3622
- Similarity Product: 64.04911463943124

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test