PATENT CLAIM ANALYSIS

Application Number: 15895094
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "206000"]

Abstract:
A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

Claim (Index 12):
A standard cell in a semiconductor die comprising:\n a P type diffusion region and an N type diffusion region, wherein the P type diffusion region is separated from the N type diffusion by an isolation region; a first gate and a second gate extending substantially parallel to each other and extending over the P type diffusion region and the N type diffusion region, thereby forming a first P MOS transistor, a second P MOS transistor, a first N MOS transistor, and a second N MOS transistor; a plurality of interconnect traces in a first metal layer extending substantially parallel to each other in a direction substantially perpendicular to the first, second, and third gates; a plurality of interconnect traces in a second metal layer extending substantially parallel to each other in a direction substantially perpendicular to the plurality of interconnect traces in the first metal layer; a cut region of the first and second gate separating the gate of the first P MOS transistor from the gate of the first N MOS transistor, and separating the gate of the second P MOS transistor from the gate of the second N MOS transistor; a first gate contact coupling the gate of the first P MOS transistor to a first interconnection trace in the first metal layer directly above the P type diffusion region, the first interconnect trace in the first layer coupled to a first interconnect trace in the second interconnect layer, the first interconnect trace in the second interconnect layer coupled to a second interconnect trace in the first interconnect layer directly above the N diffusion region, the second interconnect trace in the first interconnect layer coupled to a second gate contact coupled to the gate of the second N MOS transistor; and a third gate contact coupling the gate of the first N MOS transistor to a third interconnection trace in the first metal layer directly above the N type diffusion region, the third interconnect trace in the first layer coupled to a second interconnect trace in the second interconnect layer, the second interconnect trace in the second interconnect layer coupled to a fourth interconnect trace in the first interconnect layer directly above the P diffusion region, the fourth interconnect trace in the first interconnect layer coupled to a fourth gate contact coupled to the gate of the second P MOS transistor.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 88.0
- Lexical Diversity: 2.25
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13269545', '13970873', '10424319', '12821329', '11969854']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9149880812829184
- 35 USC 102 Novelty (BERT): 0.4815477969499768
- Combined Prediction Score: 0.8716440528496243
- Mean Citation Score: 205.41644
- Max Citation Score: 228.19536
- Similarity Product: 186.45769154156685

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test