PATENT CLAIM ANALYSIS

Application Number: 15944655
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["712", "228000"]

Abstract:
A processor architecture includes a register file hierarchy to implement virtual registers that provide a larger set of registers than those directly supported by an instruction set architecture to facilitate multiple copies of the same architecture register for different processing threads, where the register file hierarchy includes a plurality of hierarchy levels. The processor architecture further includes a plurality of execution units coupled to the register file hierarchy.

Claim (Index 3):
The processor architecture of  claim 2 , wherein a lower hierarchy level in the plurality of hierarchy levels supports higher bandwidth access to the plurality of execution units and a higher hierarchy level in the plurality of hierarchy levels supports lower bandwidth access to the plurality of execution units.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 91.0
- Lexical Diversity: 1.65116
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15357943', '12514303', '13428438', '15082359', '14194589']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5579345166728383
- 35 USC 102 Novelty (BERT): 0.5096392993568563
- Combined Prediction Score: 0.5531049949412402
- Mean Citation Score: 213.39831200000003
- Max Citation Score: 237.64006
- Similarity Product: 134.84271573471307

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test