PATENT CLAIM ANALYSIS

Application Number: 16017600
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "156000"]

Abstract:
A memory array includes a first memory cell and a second memory cell, each including a data storage element, a first access transistor coupled to the data storage element, and a second access transistor coupled to the data storage element. The memory array further includes two word lines configured to selectively enable access to the data storage element of the first memory cell through the two access transistors of the first memory cell respectively, two bit lines coupled to the two access transistors of the first memory cell respectively, two another word lines configured to selectively enable access to the data storage element of the second memory cell through the two access transistors of the second memory cell respectively, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.

Claim (Index 15):
The memory array according to  claim 14 , wherein the pre-charge voltage level is further determined by the first reference voltage.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 94.0
- Lexical Diversity: 4.07692
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13488432', '11015428', '14637297', '13595426', '13460487']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.80120726317154
- 35 USC 102 Novelty (BERT): 0.4799422505120043
- Combined Prediction Score: 0.7690807619055865
- Mean Citation Score: 174.60531400000005
- Max Citation Score: 176.32587
- Similarity Product: 118.96865530895772

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test