PATENT CLAIM ANALYSIS

Application Number: 16006107
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["327", "175000"]

Abstract:
A duty cycle corrector includes a delay chain, an edge detector, a falling edge shift (FES) controller, a plurality of falling edge modulator (FEM) cores, and a phase interpolator. The delay chain delays a first clock to generate a delay clock, and generates first and second sampling control signals. The edge detector samples the first clock and a second clock using the first and second sampling control signals to obtain first and second sampling signals. The FES controller determines a modulation direction and a modulation width based on the first and second sampling signals. The plurality of FEM cores first modulate the first edge of the first clock and second modulate the first edge of the delay clock using the modulation direction and the modulation width. The phase interpolator performs phase interpolation on the results of the first and second modulations.

Claim (Index 20):
The method of  claim 17 , wherein the first modulating and the second modulating include modulating the falling edge of the first clock in an opposite direction to the falling edge of the second clock.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 2.9434
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13078151', '11196581', '11148642', '12455572', '14803618']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.792598642471554
- 35 USC 102 Novelty (BERT): 0.4846607841062796
- Combined Prediction Score: 0.7618048566350266
- Mean Citation Score: 214.590178
- Max Citation Score: 225.43791
- Similarity Product: 172.03792371497693

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test