PATENT CLAIM ANALYSIS

Application Number: 15882521
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Claim (Index 1):
A method of forming a semiconductor structure, comprising:\n forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; covering a connection region with a patterned hard mask layer; applying and patterning a trimmable material layer over the alternating stack, wherein the patterned trimmable material layer covers a first memory array region located on one side of the connection region and a second memory array region located on another side of the connection region, and does not cover a center portion of an intermediate region between the first memory array region and the second memory array region, the intermediate region being adjacent to the connection region; forming a first terrace region adjoined to the first memory array region at one side of the intermediate region and a second terrace region adjoined to the second memory array region at another side of the intermediate region; removing the trimmable material layer and the patterned hard mask layer, wherein each of the insulating layers and the spacer material layers within the alternating stack continuously extends between the first and second memory array regions through the connection region; and forming first memory stack structures in the first memory array region and second memory stack structures in the second memory array region.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.26415
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15611220', '15877219', '15632983', '15488924', '15813579']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9378432086719442
- 35 USC 102 Novelty (BERT): 0.563654282392634
- Combined Prediction Score: 0.9004243160440132
- Mean Citation Score: 405.285566
- Max Citation Score: 476.46417
- Similarity Product: 351.65624740024214

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test