PATENT CLAIM ANALYSIS

Application Number: 15916703
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["327", "158000"]

Abstract:
According to one embodiment, in a semiconductor integrated circuit of a DLL circuit, in a delay chain, a plurality of delay elements are connected. A first detection circuit detects a group corresponding to a certain delay amount among a plurality of groups obtained by dividing the delay chain. A second detection circuit detects a delay element corresponding to the certain delay amount among a plurality of delay elements included in the detected group. The semiconductor integrated circuit detects the number of delay elements corresponding to one cycle of a first clock. The control circuit includes a second delay chain. The second delay chain has a configuration equivalent to the delay chain in the semiconductor integrated circuit. The control circuit outputs a second clock obtained by delaying the first clock by using the second delay chain according to the number of delay elements detected by the semiconductor integrated circuit.

Claim (Index 15):
A duty cycle correction circuit comprising:\n a first semiconductor integrated circuit having a first delay chain to which a plurality of delay elements are connected, and that detects the number of delay elements corresponding to one cycle of a first clock; a second semiconductor integrated circuit that detects the number of delay elements corresponding to a time width of a first level of the first clock transitioning between the first level and a second level; and a control circuit including a second delay chain having a configuration equivalent to the first delay chain in the first semiconductor integrated circuit, the control circuit delaying the first clock and outputting a second clock with duty being adjusted by using the second delay chain according to the number of delay elements detected by the first semiconductor integrated circuit and the number of delay elements detected by the second semiconductor integrated circuit, wherein the first semiconductor integrated circuit includes:\n a first detection circuit that detects a first group corresponding to a certain first delay amount among a plurality of first groups obtained by dividing the first delay chain; and \n a second detection circuit that detects a delay element corresponding to the certain first delay amount among the plurality of delay elements included in the detected first group, and \n wherein the second semiconductor integrated circuit includes:\n a third delay chain to which a plurality of delay elements are connected; \n a third detection circuit that detects a second group corresponding to a certain second delay amount among a plurality of second groups obtained by dividing the third delay chain; and \n a fourth detection circuit that detects a delay element corresponding to the certain second delay amount among the plurality of delay elements included in the detected second group.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 3.16
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13420866', '12493804', '13451131', '12493260', '12878080']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7552490047087005
- 35 USC 102 Novelty (BERT): 0.4498280790339695
- Combined Prediction Score: 0.7247069121412274
- Mean Citation Score: 157.51937800000005
- Max Citation Score: 174.2186
- Similarity Product: 152.4771006202936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test