PATENT CLAIM ANALYSIS

Application Number: 15908253
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["257", "204000"]

Abstract:
A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

Claim (Index 14):
The semiconductor device of  claim 8 , wherein each of the first and second logic cells further comprises: a first interconnection line disposed between the gate electrode and the internal interconnection line,\n wherein the first interconnection line extends in a second direction intersecting the first direction, and wherein a placement of the first interconnection line in the first logic cell is substantially the same as a placement of the first interconnection line in the second logic cell.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 88.0
- Lexical Diversity: 2.7
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15787244', '15870143', '15820053', '14505788', '15496015']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281595892682928
- 35 USC 102 Novelty (BERT): 0.493731015621616
- Combined Prediction Score: 0.884716731903625
- Mean Citation Score: 241.374664
- Max Citation Score: 263.48157000000003
- Similarity Product: 224.05212429946303

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test