PATENT CLAIM ANALYSIS

Application Number: 15949692
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-08
Patent Classification: ["711", "137000"]

Abstract:
Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Claim (Index 4):
The method of  claim 3 , wherein prefetching data associated with the third work unit includes:\n prefetching the data associated with the third work unit concurrently with flushing the first cache segment.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 91.0
- Lexical Diversity: 2.27536
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15949892', '11250054', '14701371', '14796167', '13712094']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4801106309855489
- 35 USC 102 Novelty (BERT): 0.5086789899683053
- Combined Prediction Score: 0.4829674668838246
- Mean Citation Score: 179.710804
- Max Citation Score: 240.94691
- Similarity Product: 162.46873854936004

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test