PATENT CLAIM ANALYSIS

Application Number: 16035135
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["365", "145000"]

Abstract:
Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

Claim (Index 16):
The method of  claim 9 , further comprising:\n setting a value of an indicator associated with the memory cell after a first flipping operation, wherein the determining is based at least in part on the value of the indicator.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 95.0
- Lexical Diversity: 2.29412
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15188890', '15641020', '16032398', '15426871', '15619158']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.810959488795325
- 35 USC 102 Novelty (BERT): 0.5095584425453551
- Combined Prediction Score: 0.7808193841703279
- Mean Citation Score: 276.126526
- Max Citation Score: 320.06738
- Similarity Product: 238.5999580207396

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test