PATENT CLAIM ANALYSIS

Application Number: 15914533
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "676000"]

Abstract:
A semiconductor device  1  includes a first drain terminal  4 , connected to a drain electrode of a first semiconductor chip, a first gate terminal  5 , connected to a gate electrode of the first semiconductor chip, a second drain terminal  6 , connected to a drain electrode of a second semiconductor chip, a second gate terminal  7 , connected to a gate electrode of the second semiconductor chip, a common source terminal  8 , connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin  9 , sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces)  43, 53, 63, 73 , and  83  substantially flush with an outer surface (lower surface)  9 b  of the sealing resin  9  and exposed from the outer surface  9 b.

Claim (Index 7):
The semiconductor device according to  claim 6 , wherein the first exposed surface of each terminal has a rectangular shape having four sides parallel to the four sides of the one surface, and\n if, with the first exposed surface of each drain terminal, a length of the side parallel to the first side is LD 1  and a length of the side parallel to the third side is LD 2 , and with the first exposed surface of each gate terminal, a length of the side that is parallel to the first side is LG 1  and a length of the side parallel to the third side is LG 2 , and with the first exposed surface of the source terminal, a length of the side that is parallel to the first side is LS 1  and a length of the side parallel to the third side is LS 2 , and an interval, along a direction along the first side, between the first exposed surface of the first drain terminal and the first exposed surface of the second drain terminal is d 1 , an interval, along a direction along the second side, between the first exposed surface of the first gate terminal and the first exposed surface of the common source terminal is d 2 , an interval, along the direction along the second side, between the first exposed surface of the second gate terminal and the first exposed surface of the common source terminal is d 3 , an interval, along a direction along the third side, between the first exposed surface of the first drain terminal and the first exposed surface of the first gate terminal is d 4 , and an interval, along a direction along the fourth side, between the first exposed surface of the second drain terminal and the first exposed surface of the second gate terminal is d 5 , the following formulae (a) and (b) are established.\n d 1= d 2= d 3= d 4= d 5\u2003\u2003(a) \n LS 2= LG 2\u2003\u2003(b)

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 3.03774
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12155479', '12759008', '10755375', '11349219', '10828262']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9091320696620452
- 35 USC 102 Novelty (BERT): 0.5023630783673066
- Combined Prediction Score: 0.8684551705325714
- Mean Citation Score: 206.342238
- Max Citation Score: 212.87192
- Similarity Product: 145.20992178380013

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test