PATENT CLAIM ANALYSIS

Application Number: 15883690
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "077000"]

Abstract:
A semiconductor device ( 1 ) is manufactured which includes a SiC epitaxial layer ( 28 ), a plurality of transistor cells ( 18 ) that are formed in the SiC epitaxial layer ( 28 ) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode ( 19 ) that faces a channel region ( 32 ) of the transistor cells ( 18 ) in which a channel is formed when the semiconductor device ( 1 ) is in an ON state, a gate metal ( 44 ) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode ( 19 ) while being physically separated from the gate electrode ( 19 ), and a built-in resistor ( 21 ) that is made of polysilicon and that is disposed below the gate metal ( 44 ) so as to electrically connect the gate metal ( 44 ) and the gate electron ( 19 ) together.

Claim (Index 49):
The semiconductor device according to  claim 46 , wherein the metal wiring is made of Cu.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 86.0
- Lexical Diversity: 2.31579
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15039725', '14010567', '14257451', '09926454', '15412785']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9254140338153148
- 35 USC 102 Novelty (BERT): 0.5177704244660197
- Combined Prediction Score: 0.8846496728803853
- Mean Citation Score: 212.413394
- Max Citation Score: 304.97375
- Similarity Product: 215.25797924309967

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test