PATENT CLAIM ANALYSIS

Application Number: 16009769
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "185180"]

Abstract:
A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Claim (Index 4):
The device according to  claim 3 , wherein\n in the interface chip,\n at least part of the second FIFOs are provided along a first direction, \n at least another part of the second FIFOs are provided along the first direction, and \n the first FIFO is provided between the part of the second FIFOs and the another part of the second FIFOs in a second direction different from the first direction.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.90625
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14844174', '15384714', '12198733', '10881022', '12801756']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7794723309304188
- 35 USC 102 Novelty (BERT): 0.504920394414173
- Combined Prediction Score: 0.7520171372787943
- Mean Citation Score: 198.959046
- Max Citation Score: 256.9766
- Similarity Product: 178.74720283286572

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test