PATENT CLAIM ANALYSIS

Application Number: 15985957
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "782000"]

Abstract:
A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.

Claim (Index 1):
A manufacturing method for semiconductor device comprising the steps of:\n (a) providing a semiconductor chip having a first front surface and a first rear surface which is located on the opposite side of the first front surface; (b) providing a lead frame which includes a chip mounting part having a second front surface and a second rear surface which is located on the opposite side of the second front surface; (c) after the step (a) and the step (b), applying a first bonding material to each of a plurality of first regions on the second front surface of the chip mounting part; (d) after the step (c), drying the first bonding material; (e) after the step (d), applying a second bonding material to a second region which is located between/among the respective first regions; (f) after the step (e), mounting the semiconductor chip over the chip mounting part in such a manner that the first rear surface of the semiconductor chip faces the second front surface of the chip mounting part with the first bonding material and the second bonding material being interposed; and (g) after the step (f), applying heat and pressure to the semiconductor chip and thereby bonding the first rear surface of the semiconductor chip, and the first bonding material and the second bonding material together, wherein the semiconductor chip has a first side which extends in a first direction, a second side which is located on the opposite side of the first side and extends in the first direction, a third side which extends in a second direction which intersects the first direction and a fourth side which is located on the opposite side of the third side and extends in the second direction in a planar view, wherein the semiconductor chip further has a first corner at which the first side and the third side intersect each other, a second corner at which the third side and the second side intersect each other, a third corner at which the second side and the fourth side intersect each other and a fourth corner at which the fourth side and the first side intersect each other in the planar view, and wherein after the step (f), part of each of the first corner, the second corner, the third corner and the fourth corner is located in each of the first regions in the planar view.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 93.0
- Lexical Diversity: 2.46429
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13639509', '12147676', '13196171', '14252740', '13490459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9026918594780228
- 35 USC 102 Novelty (BERT): 0.497485068742086
- Combined Prediction Score: 0.8621711804044291
- Mean Citation Score: 228.164784
- Max Citation Score: 243.84782
- Similarity Product: 191.5520238446605

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test