PATENT CLAIM ANALYSIS

Application Number: 15980288
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["327", "108000"]

Abstract:
The slew rate enhancement circuit includes: a first transistor located between a first power source and an eleventh node, the first transistor having a gate electrode coupled to the eleventh node, the first transistor being coupled as a current mirror to the first current source; a third current source having the other side coupled to a second power source lower than the first power source; a second transistor coupled between the first power source and the eleventh node; a third transistor coupled between the eleventh node and one side of the third current source; a fourth transistor coupled between the first power source and a twelfth node; and a fifth transistor coupled between the twelfth node and the one side of the third current source.

Claim (Index 14):
The slew rate enhancement circuit of  claim 8 , further comprising:\n a third switch coupled between the second power source and the twenty-second node; and a fourth switch located between the one side of the fourth current source and a common node of the thirteenth transistor and the fifteenth transistor.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 93.0
- Lexical Diversity: 3.19048
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11390443', '15495064', '12117180', '14933900', '13941356']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7773486542151455
- 35 USC 102 Novelty (BERT): 0.4803331210921124
- Combined Prediction Score: 0.7476471009028423
- Mean Citation Score: 227.849362
- Max Citation Score: 231.88031
- Similarity Product: 185.2827669395137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test