PATENT CLAIM ANALYSIS

Application Number: 16004009
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["327", "143000"]

Abstract:
Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

Claim (Index 19):
The integrated circuit of  claim 16 , further comprising a first logic gate coupled to an output of the first POR circuit and an output of the level shift latch circuitry, wherein the first logic gate provides the retention signal in the first voltage domain based on the output from the first POR circuit and the output from the level shift latch circuitry.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 2.80851
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15682327', '15490352', '15603252', '15823490', '15727382']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7528948151686423
- 35 USC 102 Novelty (BERT): 0.4709285772206115
- Combined Prediction Score: 0.7246981913738393
- Mean Citation Score: 165.767582
- Max Citation Score: 194.46217
- Similarity Product: 151.79215327146886

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test