PATENT CLAIM ANALYSIS

Application Number: 16100676
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "343000"]

Abstract:
In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.

Claim (Index 14):
The method of  claim 13 , further comprising:\n forming an electrically conductive runner on the fifth dielectric layer, wherein the second conductive via is integral with the electrically conductive runner.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 96.0
- Lexical Diversity: 1.61111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15191937', '15986433', '15279649', '15986942', '15192283']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9287471838771308
- 35 USC 102 Novelty (BERT): 0.5486020463218948
- Combined Prediction Score: 0.8907326701216072
- Mean Citation Score: 305.161798
- Max Citation Score: 408.88214
- Similarity Product: 341.543186898458

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test