PATENT CLAIM ANALYSIS

Application Number: 16027522
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "421000"]

Abstract:
An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

Claim (Index 15):
The integrated circuit of  claim 10 , wherein the buried dielectric layer comprises a plurality of sublayers of different dielectric materials.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 95.0
- Lexical Diversity: 2.41379
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15090000', '14301788', '14301765', '14301848', '15263425']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8768803992788612
- 35 USC 102 Novelty (BERT): 0.5148125270044518
- Combined Prediction Score: 0.8406736120514202
- Mean Citation Score: 261.53640200000007
- Max Citation Score: 322.03558
- Similarity Product: 299.25018130245684

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test