PATENT CLAIM ANALYSIS

Application Number: 15919788
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["714", "752000"]

Abstract:
According to one embodiment, a memory system comprises an encoder that encodes by a graph code and a data holding unit that holds data to be used in encoding. A check matrix of the graph code includes first to sixth submatrices, and the encoder produces a first vector obtained by multiplying an information word and the first submatrix, produces a second vector obtained by multiplying the information word and the third submatrix, produces a third vector obtained by multiplying the first vector and the fifth submatrix inverted in sign, produces a fourth vector obtained by adding the third vector and the second vector, produces a first parity obtained by multiplying the fourth vector and the data, produces a fifth vector obtained by multiplying the first parity and the second submatrix inverted in sign, and produces a second parity obtained by adding the fifth vector and the first vector.

Claim (Index 5):
The memory system according to  claim 1 , wherein one or more component codes among a plurality of component codes forming the graph code are Bose-Chaudhuri-Hocquenghem (BCH) codes,\n wherein the encoder comprises: at least a corresponding number of shift registers to generator polynomials of the one or more BCH codes; a selector that distributes the information word to the shift registers; a multiplier; an adder; and a code word memory that stores the information word, the first parity, and the second parity, wherein the shift registers include a first shift register group formed of a plurality of shift registers and a second shift register group formed of a plurality of other shift registers, wherein the selector inputs the information word stored in the code word memory to the first shift register group, wherein the first shift register group calculates the first vector in response to input of the information word by the selector, wherein the code word memory stores the first vector calculated by the first shift register group, wherein the selector inputs the first vector stored in the code word memory to the second shift register group, wherein the second shift register group calculates the second and third vectors and the fourth vector in response to input of the first vector by the selector, wherein the multiplier calculates the fourth vector calculated by the second shift register group by the for-encoding data, thereby calculating the first parity, wherein the code word memory stores the first parity calculated by the multiplier, wherein the selector inputs the first parity stored in the code word memory to the first shift register group, wherein the first shift register group calculates the fifth vector in response to input of the first parity by the selector, wherein the adder adds the fifth vector calculated by the first shift register group and the first vector stored in the code word memory, thereby calculating the second parity, and wherein the code word memory stores the second parity calculated by the adder.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 3.16
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14400834', '15654492', '10724280', '13755222', '13697576']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2751039479201825
- 35 USC 102 Novelty (BERT): 0.4843412433956617
- Combined Prediction Score: 0.2960276774677304
- Mean Citation Score: 181.61502
- Max Citation Score: 193.85873
- Similarity Product: 143.8880305640984

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test