PATENT CLAIM ANALYSIS

Application Number: 16214201
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "312000"]

Abstract:
A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Claim (Index 6):
The method of  claim 1 , wherein the N-type work function adjustment layer comprises TiAl, TiCAl, TiNAl, or TiSiAl.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 2.53191
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15489768', '15916729', '14928595', '15272197', '16039085']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9267896927792122
- 35 USC 102 Novelty (BERT): 0.5503033384588064
- Combined Prediction Score: 0.8891410573471716
- Mean Citation Score: 274.768938
- Max Citation Score: 405.94333
- Similarity Product: 368.9287047132969

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test