PATENT CLAIM ANALYSIS

Application Number: 16197871
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "189050"]

Abstract:
A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

Claim (Index 10):
An apparatus comprising:\n one or more memory banks configured to store first data and second data; a first data path coupled to the one or more memory banks configured to transfer the first data; a second data path coupled to the one or more memory banks configured to transfer the second data; a first latch configured to gate the first data path based on a clock signal in the semiconductor device; a second latch configured to gate the second data path based on an inverted clock signal; a first set of logic gates that receives and combines outputs of the first latch and the second latch and provides the combined outputs of the first latch and the second latch to a first transistor coupled to a positive power supply; a third latch configured to gate the first data path based on the clock signal; a fourth latch configured to gate the second data path based on the inverted clock signal; a second set of logic gates that receives and combines outputs of the third latch and the fourth latch and provides the combined outputs of the third latch and the fourth latch to a second transistor coupled to a negative power supply; and interface circuitry coupled to the one or more memory banks, the first latch, and the second latch, wherein the interface circuitry is configured to:\n send a first instruction to the one or more memory banks to transmit the first data on the first data path; \n send a second instruction to the one or more memory banks to transmit the second data on the second data path; \n output first gated data based on the clock signal; and \n output second gated data based on the inverted clock signal.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 98.0
- Lexical Diversity: 2.97619
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15652986', '09938206', '15850744', '11824440', '15691394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7482511082307264
- 35 USC 102 Novelty (BERT): 0.5358649467996393
- Combined Prediction Score: 0.7270124920876176
- Mean Citation Score: 219.970498
- Max Citation Score: 376.78958
- Similarity Product: 339.953522025888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test