PATENT CLAIM ANALYSIS

Application Number: 15884109
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["710", "313000"]

Abstract:
The present disclosure generally relates to a Modular PCIe Unit (MPU), which is a single-lane PCI Express endpoint that can act as either a Stand-Alone Single-Lane or as a (one) Lane in a Multilane Endpoint Unit, composed by cascaded-MPUs. The MPU will include a PCIe link, a PCIe transition, a SoC specific and a PCIe phy that are all unique to the individual MPU. The MPUs are scalable in that a single MPU may be used or, if more MPUs are desired for higher performance, additional MPUs, each of which can be unique, added to create the Multilane Endpoint Unit.

Claim (Index 16):
The memory system of  claim 15 , wherein the interconnection bus is coupled to the first means at a location disposed between the first phy and the first means for sequencing data packets.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 86.0
- Lexical Diversity: 1.71642
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13242110', '11831887', '12034645', '15726566', '13844280']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6842790173323419
- 35 USC 102 Novelty (BERT): 0.476217046156
- Combined Prediction Score: 0.6634728202147077
- Mean Citation Score: 153.969148
- Max Citation Score: 164.93951
- Similarity Product: 114.249198904413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test