PATENT CLAIM ANALYSIS

Application Number: 16236783
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Claim (Index 16):
The device of  claim 11  further comprising:\n a contact etch stop layer comprising:\n a vertical leg contacting a sidewall of the second gate spacer; and \n a horizontal leg connected to a bottom end of the vertical leg, wherein the horizontal leg has a bottom surface substantially coplanar with a bottom end of the second gate spacer.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 2.60976
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15221123', '15859863', '14739294', '16222610', '15347196']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9201023377774132
- 35 USC 102 Novelty (BERT): 0.496999006646394
- Combined Prediction Score: 0.8777920046643112
- Mean Citation Score: 248.394706
- Max Citation Score: 286.49527
- Similarity Product: 257.960763128525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test