PATENT CLAIM ANALYSIS

Application Number: 15919525
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189080"]

Abstract:
There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Claim (Index 1):
A semiconductor integrated circuit device comprising:\n a cell array including:\n a plurality of memory cells arranged in a matrix and each including: a holding circuit which has a plurality of MOSFETs and a pair of input/output nodes and operates with a voltage difference between a first voltage and a second voltage as an operating voltage; and a pair of transfer MOSFETs which are coupled to the input/output nodes respectively and whose gates receive a selection signal; \n a plurality of word lines arranged in respective rows of the matrix and each coupled to gates of pairs of transfer MOSFETs in a plurality of memory cells arranged in a corresponding row; and \n a plurality of bit line pairs arranged in respective columns of the matrix and each coupled to pairs of transfer MOSFETs in a plurality of memory cells arranged in a corresponding column; \n a peripheral circuit for selecting a word line from among the word lines and selecting a bit line pair from among the bit line pairs; and a voltage control circuit, for generating the first voltage, which changes a voltage value of the first voltage so as to decrease the voltage difference, in response to a unique ID generation instruction, and then changes the voltage value of the first voltage so as to increase the voltage difference.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.46377
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14334790', '15239410', '15797135', '15465300', '15000027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.799804356631416
- 35 USC 102 Novelty (BERT): 0.4964695623312993
- Combined Prediction Score: 0.7694708772014044
- Mean Citation Score: 252.503604
- Max Citation Score: 298.44708
- Similarity Product: 282.2532478727889

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test