PATENT CLAIM ANALYSIS

Application Number: 15763970
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["714", "764000"]

Abstract:
A computer device comprises a first processing device; a plurality of memory circuits, a first one of which comprises one or more other processing devices; a data bus coupling the first processing device to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processing device and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting the first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Claim (Index 9):
The computing device of  claim 8 , wherein a plurality of least significant bits of the first address is identical to a plurality of least significant bits of one of the second addresses.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 2.55932
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10097499', '15551418', '11394949', '15428719', '14265270']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3137672684448884
- 35 USC 102 Novelty (BERT): 0.4974357592101729
- Combined Prediction Score: 0.3321341175214168
- Mean Citation Score: 188.390398
- Max Citation Score: 190.32498
- Similarity Product: 112.45394467967036

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test