PATENT CLAIM ANALYSIS

Application Number: 15968360
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-08
Patent Classification: ["257", "737000"]

Abstract:
Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Claim (Index 35):
The apparatus of  claim 32 , wherein:\n the plurality of interconnects define a plurality of rows of interconnects; the interconnects of the plurality of rows are horizontally spaced according to a first pitch; and the interconnects of the plurality of rows are vertically spaced according to a second pitch that is less than the first pitch.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 1.20833
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15259980', '13865499', '15154770', '11459081', '15722983']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9142501384334264
- 35 USC 102 Novelty (BERT): 0.4946764915003261
- Combined Prediction Score: 0.8722927737401165
- Mean Citation Score: 134.29587199999995
- Max Citation Score: 139.3622
- Similarity Product: 81.4206836884737

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test