PATENT CLAIM ANALYSIS

Application Number: 15872100
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["710", "309000"]

Abstract:
Systems and methods for providing a partitioned interconnect slot for inter-processor operation. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a processor comprising a first core and a second core; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to enable an Input/Output (I/O) device to communicate directly with the first core and the second core utilizing a single interconnect slot.

Claim (Index 18):
The method of  claim 17 , further comprising reducing latency of communication between (a) the first and second cores and (b) the NVM bridge adapter.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 1.61818
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14604746', '15073012', '14279118', '15826922', '14615451']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6756129844739883
- 35 USC 102 Novelty (BERT): 0.504083437995823
- Combined Prediction Score: 0.6584600298261718
- Mean Citation Score: 215.363508
- Max Citation Score: 224.13646
- Similarity Product: 127.68277994796873

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test