PATENT CLAIM ANALYSIS

Application Number: 16150012
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-01
Patent Classification: ["345", "506000"]

Abstract:
One embodiment provides for a general-purpose graphics processing unit comprising multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution, a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity, and a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.

Claim (Index 14):
The method as in  claim 11 , additionally comprising scheduling threads of the warp to multiple processing elements at sub-warp granularity, wherein the multiple processing elements are to complete a first sub-warp of threads and execute a second sub-warp of threads after the first sub-warp of threads completes.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.0
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15477038', '15477022', '15493233', '15494773', '15477027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6295738362487182
- 35 USC 102 Novelty (BERT): 0.5093265439840037
- Combined Prediction Score: 0.6175491070222467
- Mean Citation Score: 267.623414
- Max Citation Score: 279.26727
- Similarity Product: 213.94517112998489

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test