PATENT CLAIM ANALYSIS

Application Number: 15942065
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["710", "110000"]

Abstract:
A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

Claim (Index 14):
The method of  claim 12 , wherein the internal connections has only one level wire crossing among each other.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 3.30612
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12119396', '14871706', '12823515', '12119377', '10054362']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6798353517161502
- 35 USC 102 Novelty (BERT): 0.4906201244946891
- Combined Prediction Score: 0.6609138289940041
- Mean Citation Score: 163.264296
- Max Citation Score: 165.51263
- Similarity Product: 101.05250082412482

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test