PATENT CLAIM ANALYSIS

Application Number: 16245307
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["438", "396000"]

Abstract:
A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

Claim (Index 1):
A semiconductor device, comprising:\n a substrate including an active region extending in a direction; a conductive line crossing the active region; and a contact plug disposed on the active region and on one side of the conductive line, the contact plug includes a plurality of grains, wherein the contact plug includes a first contact plug and a second contact plug on the first contact plug, wherein an average grain size of the first contact plug is greater than an average gain size of the second contact plug.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.04348
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15603668', '15071452', '14290620', '15916957', '11098648']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8343542849315078
- 35 USC 102 Novelty (BERT): 0.5115402053047756
- Combined Prediction Score: 0.8020728769688346
- Mean Citation Score: 226.98163800000003
- Max Citation Score: 290.22284
- Similarity Product: 237.9036719883371

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test