PATENT CLAIM ANALYSIS

Application Number: 15950610
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "185110"]

Abstract:
A memory device with a plurality of memory block may include a plurality of memory cells constituting a memory blocks, and two or more select transistors coupled to the plurality of memory cells constituting the memory block and configured to select the memory block, the two or more select transistors having different threshold voltages from one another.

Claim (Index 5):
The memory device according to  claim 4 , wherein:\n gates of the first, third, fifth, and seventh drain select transistors are coupled to a first drain select line, gates of the second, fourth, sixth, and eighth drain select transistors are coupled to a second drain select line, gates of the first, third, fifth, and seventh source select transistors are coupled to a first source select line, and gates of the second, fourth, sixth, and eighth source select transistors are coupled to a second source select line.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 1.875
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15060726', '15873069', '15648681', '15148123', '14691263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.784388469298667
- 35 USC 102 Novelty (BERT): 0.5028101191229709
- Combined Prediction Score: 0.7562306342810974
- Mean Citation Score: 225.527866
- Max Citation Score: 272.6365
- Similarity Product: 211.6340194234252

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test