PATENT CLAIM ANALYSIS

Application Number: 16015762
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-08
Patent Classification: ["345", "691000"]

Abstract:
The present disclosure provides a display panel, a display device and a driving method of a display panel, aiming to lower power consumption of display devices. The display panel operates in P pixel charging sub-phases, and P is a number of rows of pixels. Every two sequential pixel charging sub-phases form one pixel charging phase. In one pixel charging sub-phase of each pixel charging phase, switch group elements of each driving unit are switched on in a first sequence, and in the other pixel charging sub-phase of each pixel charging phase, the switch group elements of each driving unit are switched on in a second sequence. The first sequence and the second sequence are reversed. In the present disclosure, 1≤P, 1≤N, and P and N are positive integers. The above display panel is applicable to display devices.

Claim (Index 11):
The display panel according to  claim 10 , wherein each of the at least four switch group elements comprises a second thin film transistor and a third thin film transistor, a first terminal of the second thin film transistor and a first terminal of the third thin film transistor are electrically connected to a first terminal of the switch group element, and a second terminal of the second thin film transistor and a second terminal of the third thin film transistor are electrically connected to a second terminal of the switch group element,\n wherein the display panel further comprises at least four second clock signal lines, an x th  second clock signal line is electrically connected to a control terminal of an x th  second thin film transistor in each of the N driving units, x is 1, 2, . . . , or M, where 1\u2264M and M is a positive integer; in one pixel charging sub-phase of each pixel charging phase, the at least four second clock signal lines sequentially provide enable signals in the first sequence, so that second thin film transistors of each of the N driving units are sequentially switched on in the first sequence, and in the other pixel charging sub-phase of each pixel charging phase, the at least four second clock signal lines sequentially provide enable signals in the second sequence, so that second thin film transistors of each of the N driving units are sequentially switched on in the second sequence, wherein the display panel further comprises at least four third clock signal lines, a y th  third clock signal line is electrically connected to a control terminal of a y th  third thin film transistor in each of the N driving units, y is 1, 2, . . . , or M; in one pixel charging sub-phase of each pixel charging phase, the at least four third clock signal lines sequentially provide enable signals in the first sequence, so that third thin film transistors of each of the N driving units are sequentially switched on in the first sequence, and in the other pixel charging sub-phase of each pixel charging phase, the at least four third clock signal lines sequentially provide enable signals in the second sequence, so that third thin film transistors of each of the N driving units are sequentially switched on in the second sequence, and wherein the at least four third clock signal lines provide switch-off signals in a period from a 1 st  pixel charging sub-phase to a (P/2) th  pixel charging sub-phase of the P pixel charging sub-phases, and the at least four second clock signal lines provide the switch-off signal in a period from a (P/2+1) th  pixel charging sub-phase to a P th  pixel charging sub-phase of the P pixel charging sub-phases.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 2.59322
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15994937', '15974699', '15505103', '14777525', '14316284']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6862478005610879
- 35 USC 102 Novelty (BERT): 0.4965565997138751
- Combined Prediction Score: 0.6672786804763667
- Mean Citation Score: 239.924928
- Max Citation Score: 268.8938
- Similarity Product: 223.5128617405653

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test