PATENT CLAIM ANALYSIS

Application Number: 15898119
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["365", "148000"]

Abstract:
A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

Claim (Index 18):
The method of  claim 17 , wherein when the memory cell transitions to the third resistance state, the memory cell cannot transition back to either the first or second resistance state.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 3.5122
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15435082', '15216520', '15730398', '14219534', '14631182']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7721037893772131
- 35 USC 102 Novelty (BERT): 0.5043191716815019
- Combined Prediction Score: 0.745325327607642
- Mean Citation Score: 189.111888
- Max Citation Score: 217.84395
- Similarity Product: 134.1767974552989

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test