PATENT CLAIM ANALYSIS

Application Number: 16504248
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.

Claim (Index 1):
An integrated circuit comprising:\n a first plurality of logic tiles and a second plurality of logic tiles, wherein the logic tiles of the first plurality of logic tiles are different from the logic tiles of the second plurality of logic tiles and wherein each logic tile of the first plurality of logic tiles and the second plurality of logic tiles includes:\n at least one input clock path, wherein the input clock path includes circuitry which is configurable to receive a clock signal, \n a plurality of output clock paths, wherein each output clock path includes circuitry which is configurable to transmit a tile output clock signal to one or more neighboring logic tiles, and \n tile clock generation circuitry, coupled to the input clock path, configurable to generate a tile clock, having a skew, wherein the skew between the tile clocks of each logic tile of the plurality of logic tiles is zero; and \n wherein:\n the first plurality of logic tiles includes a first logic tile to receive a first external clock signal at an input of a first input clock path thereof, wherein each logic tile of a first plurality of logic tiles is configurable to generate its tile clock using (i) the first external clock signal received by the first logic tile or (ii) a delayed version of the first external clock signal received from one of the plurality of output clock paths of a logic tile of the first plurality of logic tiles, wherein at least one of the logic tiles of the first plurality of logic tiles, in operation, generates its tile clock using a delayed version of the first external clock signal received from one of the plurality of output clock paths of a different logic tile of the first plurality of logic tiles, and \n the second plurality of logic tiles includes a second logic tile to receive a second external clock signal at an input of a first input clock path thereof, wherein each logic tile of a second plurality of logic tiles is configurable to generate its tile clock using (i) the second external clock signal received by the second logic tile or (ii) a delayed version of the second external clock signal received from one of the plurality of output clock paths of a logic tile of the second plurality of logic tiles, wherein at least one of the logic tiles of the second plurality of logic tiles, in operation, generates its tile clock using a delayed version of the second external clock signal received from one of the plurality of output clock paths of a different logic tile of the second plurality of logic tiles; and \n timing circuitry, external to the first plurality of logic tiles and a second plurality of logic tiles and electrically connected to the first input clock paths of at least the first logic tile and the second logic tile, to generate the first external clock signal and the second external clock signal, wherein the first external clock and second external clock signal have the same clock frequency and zero skew with respect to each other.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.375
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15996430', '16009656', '14712864', '15347045', '14972553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7061591541161995
- 35 USC 102 Novelty (BERT): 0.5804808522881877
- Combined Prediction Score: 0.6935913239333983
- Mean Citation Score: 431.059484
- Max Citation Score: 486.68964000000005
- Similarity Product: 441.07751289289

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test