PATENT CLAIM ANALYSIS

Application Number: 15984586
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["438", "479000"]

Abstract:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Claim (Index 1):
A method of preparing a semiconductor-on-insulator device, the method comprising:\n forming a charge trapping layer on a front surface layer of a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a bulk region between the front and back surfaces, and a central plane of the single crystal semiconductor handle substrate between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of 100 Ohm-cm and further wherein the charge trapping layer comprises one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; forming a semiconductor oxide layer on the charge trapping layer, wherein the semiconductor oxide layer has a thickness of at least about 0.1 micrometers; and bonding the semiconductor oxide layer to a dielectric layer on a front surface layer of a single crystal semiconductor donor substrate to thereby prepare a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor donor substrate and the other of which is a back surface of the single crystal semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor donor substrate, and a central plane of the single crystal semiconductor donor substrate between the front and back surfaces of the single crystal semiconductor donor substrate, wherein the single crystal semiconductor donor substrate comprises a cleave plane and the dielectric layer on the front surface layer of the single crystal semiconductor donor substrate.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 93.0
- Lexical Diversity: 1.97143
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15526798', '15435428', '16077176', '16077142', '15526640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8954088252095893
- 35 USC 102 Novelty (BERT): 0.548399152428122
- Combined Prediction Score: 0.8607078579314426
- Mean Citation Score: 403.164596
- Max Citation Score: 413.68033
- Similarity Product: 364.573504594636

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test