PATENT CLAIM ANALYSIS

Application Number: 15997837
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["333", "117000"]

Abstract:
The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

Claim (Index 7):
The method of  claim 5 , wherein the wafer is a silicon wafer.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 94.0
- Lexical Diversity: 3.23913
- Patent Class: 333.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14885393', '15668931', '13974659', '12542958', '15659877']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8626159465679438
- 35 USC 102 Novelty (BERT): 0.5432761837759849
- Combined Prediction Score: 0.8306819702887479
- Mean Citation Score: 315.7559080000001
- Max Citation Score: 424.9303
- Similarity Product: 205.5905212411046

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test