PATENT CLAIM ANALYSIS

Application Number: 15907570
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185110"]

Abstract:
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.

Claim (Index 1):
An apparatus, comprising:\n a plurality of non-volatile memory cells including a group of connected memory cells, the group of connected memory cells is a block of memory cells sharing a common set of word lines across the block, the block of memory cells includes multiple sub-block of memory cells, each sub-block of the multiple sub-blocks has its own set of one or more selection lines with respect to other sub-blocks of the block of memory cells; an erase circuit connected to the memory cells and configured to erase the group of connected memory cells by applying an erase signal to the group of connected memory cells; and an erase speed circuit configured to adjust an erase speed for a subset of the group of connected memory cells by adjusting voltages on the selection lines.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 1.51515
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15337522', '15630389', '15191150', '15151951', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8019440300333426
- 35 USC 102 Novelty (BERT): 0.4765971276021498
- Combined Prediction Score: 0.7694093397902233
- Mean Citation Score: 226.306854
- Max Citation Score: 232.60359
- Similarity Product: 187.75466815579173

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test