PATENT CLAIM ANALYSIS

Application Number: 16107036
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Claim (Index 8):
The semiconductor device according to  claim 7 ,\n wherein the non-volatile memory cell further includes a second gate electrode extending in the second direction, and being formed to cover an upper surface and a side surface of a second part of the first projecting unit through a second gate insulating film, wherein the second gate electrode is formed adjacent to the first gate electrode, and wherein the first silicide layer and the second silicide layer are formed in a manner that the first part and the second part are sandwiched therebetween in the first direction.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 96.0
- Lexical Diversity: 2.14286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16036324', '15482239', '15879257', '15626092', '15961334']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9332636891106484
- 35 USC 102 Novelty (BERT): 0.5171307519582081
- Combined Prediction Score: 0.8916503953954045
- Mean Citation Score: 291.9861420000001
- Max Citation Score: 322.3297
- Similarity Product: 263.4565741942286

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test