PATENT CLAIM ANALYSIS

Application Number: 16244002
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["327", "175000"]

Abstract:
Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

Claim (Index 4):
The clock distribution circuitry as claimed in  claim 1 , wherein:\n in the first buffer pair, and the second buffer pair, the second buffer is connected in series after the first buffer in the propagation direction; and the first buffer pair is connected in series with the second buffer pair so that the first and second clock paths are part of the same combined clock path.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 99.0
- Lexical Diversity: 2.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16244025', '13295875', '13930662', '11101958', '11671383']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7800356548966868
- 35 USC 102 Novelty (BERT): 0.4901109424473799
- Combined Prediction Score: 0.7510431836517562
- Mean Citation Score: 192.673962
- Max Citation Score: 248.65811
- Similarity Product: 196.3498587561697

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test