PATENT CLAIM ANALYSIS

Application Number: 16375282
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-07
Patent Classification: ["257", "774000"]

Abstract:
The semiconductor device  100  comprises a first semiconductor element  113  provided on a face on one side of a flat plate shaped interconnect component  101,  an insulating resin  119  covering a face of a side where the first semiconductor element  113  of the interconnect component  101  is provided and a side face of the first semiconductor element  113,  and a second semiconductor element  111  provided on a face on the other side of the interconnect component  101.  The interconnect component  101  has a constitution where an interconnect layer  103,  a silicon layer  105  and an insulating film  107  are sequentially formed. The interconnect layer  103  has a constitution where the interconnect layer  103  has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element  113  is electrically connected with the second semiconductor element  111  through the conductive component.

Claim (Index 1):
A semiconductor device comprising:\n a wiring substrate having a first surface, a second surface opposite the first surface, and a plurality of wirings; a first semiconductor element mounted on the first surface of the wiring substrate through a plurality of first electrodes; a second semiconductor element mounted on the first surface of the wiring substrate through a plurality of second electrodes, the second semiconductor element being arranged next to the first semiconductor element; a silicon element embedded in the wiring substrate such that the silicon element is not exposed from the second surface of the wiring substrate; and a plurality of electrode terminals formed on the second surface of the wiring substrate, wherein the first semiconductor element is electrically connected with one of the plurality of electrode terminals through a first part of the plurality of wirings, without passing through each of the silicon element and any conductive materials located outside of the wiring substrate, wherein the second semiconductor element is electrically connected with another one of the plurality of electrode terminals through a second part of the plurality of wirings, without passing through each of the silicon element and any conductive materials located outside of the wiring substrate, wherein the silicon element is electrically connected with the first semiconductor element through a third part of the plurality of wirings, and electrically connected with the second semiconductor element through a fourth part of the plurality of wirings, wherein, in cross-section view, a thickness of the silicon element is less than a thickness of the wiring substrate, and wherein the silicon element is arranged in the wiring substrate such that the silicon element is overlapped with each of the first semiconductor element and the second semiconductor element.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 100.0
- Lexical Diversity: 2.96154
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14524718', '13495494', '12169930', '11159157', '11094152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9092091289662498
- 35 USC 102 Novelty (BERT): 0.5303589547235207
- Combined Prediction Score: 0.871324111541977
- Mean Citation Score: 298.12808200000006
- Max Citation Score: 335.58084
- Similarity Product: 259.76110882397177

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test