PATENT CLAIM ANALYSIS

Application Number: 16502933
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["716", "106000"]

Abstract:
A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Claim (Index 10):
The method according to  claim 8 , wherein identifying assertations that are missing from the assertion description file includes expanding a signal that is declared unknown and displaying the expansion as multiple nodes in the graph, each having a value that is a subset of unknown.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.04615
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15253517', '13433909', '14031949', '11936775', '14674651']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3419909561187956
- 35 USC 102 Novelty (BERT): 0.5582740587213413
- Combined Prediction Score: 0.3636192663790502
- Mean Citation Score: 224.465052
- Max Citation Score: 465.47177
- Similarity Product: 403.34209055180486

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test