PATENT CLAIM ANALYSIS

Application Number: 16022540
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["257", "066000"]

Abstract:
A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Claim (Index 1):
A memory device that includes a plurality of memory cells, wherein at least one of the memory cells comprises:\n a channel region; a floating gate adjacent to the channel region along a first side, wherein a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction of the channel region; a control gate adjacent to the floating gate along an opposing second side of the floating gate, wherein the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate; and a dielectric layer disposed between the control gate and the floating gate, wherein the dielectric layer follows the tapered edge along the floating gate and forms a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 2.61667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14808475', '15252090', '13153964', '14140215', '14144442']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9202654603080864
- 35 USC 102 Novelty (BERT): 0.4789753437591515
- Combined Prediction Score: 0.876136448653193
- Mean Citation Score: 182.97255
- Max Citation Score: 187.5822
- Similarity Product: 141.36771544797418

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test