PATENT CLAIM ANALYSIS

Application Number: 15919492
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "185110"]

Abstract:
According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.

Claim (Index 9):
The memory system according to  claim 1 , wherein\n the memory device comprises a plurality of word lines, the plurality of word lines including the first word line and the second word line, e, and the plurality of word lines and insulating layers are stacked alternately in a first direction, and a size of the first cell transistor in a second direction is smaller than a size of the second cell transistor in the second direction, the second direction being substantially orthogonal to the first direction.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.55
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15691799', '15868718', '15916551', '15639411', '15346713']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8147188815421751
- 35 USC 102 Novelty (BERT): 0.4870811830101306
- Combined Prediction Score: 0.7819551116889707
- Mean Citation Score: 190.232202
- Max Citation Score: 218.5317
- Similarity Product: 153.0815365039229

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test