PATENT CLAIM ANALYSIS

Application Number: 15895837
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["375", "362000"]

Abstract:
A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

Claim (Index 13):
The serializer of  claim 10 , wherein the pre-buffer stage includes:\n a first pre-buffer configured to receive the first clock signal and the first signal, and output the first delayed signal; a second pre-buffer configured to receive the second clock signal and the second signal, and output the second delayed signal; a third pre-buffer configured to receive the third clock signal and the third signal, and output the third delayed signal; and a fourth pre-buffer configured to receive the fourth clock signal and the fourth signal, and output the fourth delayed signal.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 88.0
- Lexical Diversity: 2.51351
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15855567', '11850754', '12165171', '14882942', '15366345']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.503606657856378
- 35 USC 102 Novelty (BERT): 0.492184670620498
- Combined Prediction Score: 0.50246445913279
- Mean Citation Score: 196.609306
- Max Citation Score: 216.4241
- Similarity Product: 154.3832546279669

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test