PATENT CLAIM ANALYSIS

Application Number: 15870315
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.

Claim (Index 18):
The semiconductor package structure of  claim 17 , further comprising a third conductive layer and a fourth conductive layer, wherein:\n the second insulating layer has an upper surface and a lower surface, and defines a second through hole extending through the second insulating layer, the second conductive layer is disposed on the upper surface of the second insulating layer and extends into the second through hole of the second insulating layer to form a second conductive via, the third insulating layer has an upper surface and a lower surface, and defines a third through hole extending through the third insulating layer, the third conductive layer is disposed on the upper surface of the third insulating layer and extends into the third through hole of the third insulating layer to form a third conductive via, the third conductive layer is electrically connected to the second conductive layer through the second conductive via, the fourth insulating layer has an upper surface and a lower surface, and defines a fourth through hole extending through the fourth insulating layer, the fourth conductive layer is disposed on the upper surface of the fourth insulating layer and extends into the fourth through hole of the fourth insulating layer to form a fourth conductive via, and the fourth conductive layer is electrically connected to the third conductive layer through the third conductive via.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 4.025
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15665289', '15608733', '15222873', '15209777', '14328668']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9185121535547064
- 35 USC 102 Novelty (BERT): 0.4811392182870798
- Combined Prediction Score: 0.8747748600279438
- Mean Citation Score: 228.236612
- Max Citation Score: 233.52968
- Similarity Product: 196.04527345211508

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test