PATENT CLAIM ANALYSIS

Application Number: 16054472
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["257", "336000"]

Abstract:
A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.

Claim (Index 18):
The method of  claim 17 , wherein the providing of the substrate comprises:\n forming a first conductivity type buried layer on the substrate; forming a second conductivity type buried layer on the first conductivity type buried layer; and forming a first conductivity type drift region and a second conductivity type body region on the second conductivity type buried layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 3.07692
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12891485', '12406048', '10443782', '10925035', '11676613']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9268554387710162
- 35 USC 102 Novelty (BERT): 0.5109100265383102
- Combined Prediction Score: 0.8852608975477456
- Mean Citation Score: 234.35962400000005
- Max Citation Score: 249.81653
- Similarity Product: 153.1099798975581

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test