PATENT CLAIM ANALYSIS

Application Number: 15911894
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["323", "271000"]

Abstract:
Implementations of on-chip electrical regulation devices may include: a positive power domain electrically coupled with a negative power domain through a power mesh including two or more loads. The positive power domain, negative power domain, or both the positive power domain and negative power domain may each include a power domain rail. The power domain rail may include a resistance distributed along a length of the power domain rail. The distributed resistance may be electrically coupled with one or more transistors also distributed along the power domain rail. Each of the one or more transistors, in combination with the distributed resistance, may be configured to dissipate electrical power along the length of the power domain rail to reduce a voltage across the positive power domain, negative power domain, or both the positive power domain and the negative power domain to a desired operating voltage at the power mesh.

Claim (Index 15):
An on-chip electrical regulation system comprising:\n a positive power domain electrically coupled with a negative power domain through a power mesh comprising two or more loads; wherein the positive power domain, the negative power domain, or both the positive power domain and the negative power domain comprise a power domain rail comprising a plurality of resistors distributed along a length of the power domain rail, the distributed plurality of resistors electrically coupled directly with a plurality of transistors also distributed along the length of the power domain rail; wherein each of the plurality of transistors, in combination with the distributed plurality of resistors, are configured to generate using open loop control a substantially constant voltage drop across the two or more loads of the power mesh across the length of the power domain rail; wherein the power mesh comprises a plurality of interdigitated metal tracks electrically coupled with the two or more loads; and wherein the plurality of transistors are comprised on the plurality of interdigitated metal tracks.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 3.07692
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14833805', '10841454', '10842149', '13018379', '15440704']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7083960042032442
- 35 USC 102 Novelty (BERT): 0.4612865887166811
- Combined Prediction Score: 0.6836850626545878
- Mean Citation Score: 166.177706
- Max Citation Score: 171.49953
- Similarity Product: 135.15858609143794

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test