PATENT CLAIM ANALYSIS

Application Number: 15777582
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "091000"]

Abstract:
A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip welding wire region and an external electrode region connected with each other. The chip welding wire region is composed of multiple conductive lines, wherein the central conductive line located in the central position of the chip welding wire region is a straight line section. The conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, so that the entire chip welding wire region forms a circular area. The array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides. The entire chip welding wire region can also form a rectangular area.

Claim (Index 1):
A die-bonding substrate, comprising a substrate, and a conductive line layer and array chips provided on the substrate, characterized in that, the conductive line layer includes a chip welding wire region and an external electrode region, which are electrically connected with each other; and that the chip welding wire region is composed of multiple conductive lines;\n wherein the central conductive line located in the central position of the chip welding wire region is a straight line section, and is the longest line section; the conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, the farther a conductive line lies away from the central conductive line, the shorter its straight line section is, and the longer its arc section is, so that the entire chip welding wire region forms a circular area; the array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides; or wherein the conductive lines are straight line sections arranged parallel to one another, so that the entire chip welding wire region forms a rectangular area; the array chips are arranged inside the rectangular area, and are electrically connected with the conductive lines arranged at both sides.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.39062
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15782007', '13312237', '15399769', '15927458', '14561946']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.911974728589003
- 35 USC 102 Novelty (BERT): 0.5025699384401892
- Combined Prediction Score: 0.8710342495741217
- Mean Citation Score: 201.738766
- Max Citation Score: 237.97736
- Similarity Product: 155.8190498878479

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test