PATENT CLAIM ANALYSIS

Application Number: 15915796
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["341", "158000"]

Abstract:
Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

Claim (Index 32):
The processor of  claim 26 , further comprising additional bypass circuits, wherein each of the first bypass circuit and the additional bypass circuits is associated with a bit of resolution of the ADC.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.34375
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15901294', '15484987', '15484965', '15484949', '15652710']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5973099928442038
- 35 USC 102 Novelty (BERT): 0.5299602894457389
- Combined Prediction Score: 0.5905750225043573
- Mean Citation Score: 263.23034
- Max Citation Score: 274.03528
- Similarity Product: 134.6768466301823

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test