PATENT CLAIM ANALYSIS

Application Number: 15918351
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "185220"]

Abstract:
According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.

Claim (Index 10):
The device according to  claim 9 ,\n wherein the second verify level of the threshold voltage is a verify level higher by one or two stages or more than the first verify level of the threshold voltage in the three or more different verify levels of threshold voltages.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.34848
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15253520', '15247916', '13053796', '15175806', '13237291']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.820064910345429
- 35 USC 102 Novelty (BERT): 0.5038946060134929
- Combined Prediction Score: 0.7884478799122354
- Mean Citation Score: 236.59183
- Max Citation Score: 273.1492
- Similarity Product: 182.11814635596275

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test