PATENT CLAIM ANALYSIS

Application Number: 15941225
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "190000"]

Abstract:
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a semiconductor substrate and a plurality of fins on the semiconductor substrate; forming an isolation structure on the semiconductor substrate, between adjacent fins and with a top surface lower than the top surfaces of the fins; forming a gate structure across of the fins by covering portions of top and side surfaces of the fins; forming a sidewall material layer to cover the gate structure and the fins; etching the sidewall material layer to form gate sidewall spacers on side surfaces of the gate structure and shadowing sidewall spacers on portions of side surfaces of the fins adjacent to the isolation structure; and performing an ion implantation process on the fins using the gate sidewall spacers and the shadowing sidewall spacers as a mask to form lightly doped regions in the fins.

Claim (Index 20):
The semiconductor structure according to  claim 18 , wherein:\n the stress layers are one or more of U-shaped and \u03a3-shaped.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.49206
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15909285', '13940283', '15397081', '14554168', '15398817']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9318021961524896
- 35 USC 102 Novelty (BERT): 0.5111298198406607
- Combined Prediction Score: 0.8897349585213068
- Mean Citation Score: 274.21479600000004
- Max Citation Score: 282.78534
- Similarity Product: 197.8740373879909

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test