PATENT CLAIM ANALYSIS

Application Number: 16047976
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["716", "102000"]

Abstract:
Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.

Claim (Index 11):
The computer-implemented method of  claim 8  wherein the determined functional clocking components are associated with corresponding components in the hardware description of the clock network.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 95.0
- Lexical Diversity: 2.11538
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14568613', '11151043', '12343415', '13324880', '12218107']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3403333844191021
- 35 USC 102 Novelty (BERT): 0.4443203092392896
- Combined Prediction Score: 0.3507320769011209
- Mean Citation Score: 138.923614
- Max Citation Score: 153.52829
- Similarity Product: 121.75331212203504

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test