PATENT CLAIM ANALYSIS

Application Number: 15744990
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["382", "124000"]

Abstract:
Provided is a fingerprint identification panel comprising multiple first electrode strips, multiple second electrode strips, a scanning device, a sensing signal providing device and an identification device, wherein the first electrode strips and the second electrode strips are insulated from and intersected with each other; the scanning device is configured to provide driving signals to the plurality of first electrode strips in turn, the sensing signal providing device is configured to provide sensing signals to the second electrode strips, and a capacitor is formed between each first electrode strip and a second electrode strip adjacent thereto—; the plurality of second electrode strips are connected with the identification device, and transmit signals that reflect quantities of the capacitors to the identification device, the identification device is configured to determine a morphology of a fingerprint based on the signals.

Claim (Index 24):
The fingerprint identification panel of  claim 23 , wherein the scanning device comprises a clock signal line, a trigger signal input terminal and a reset signal input terminal, each shift register comprises a clock signal terminal, a signal input terminal, a low level signal terminal, a storage capacitor, a plurality of transistors, a reset terminal and a signal output terminal, and the plurality of transistors comprise a pull-up transistor, an input transistor, a pull-down transistor and a pull-down control transistor, wherein\n the clock signal terminal is connected with the clock signal line; a first electrode of the input transistor is connected with the signal input terminal, and a gate of the input transistor is connected with the first electrode of the input transistor; a gate of the pull-up transistor is connected with a second electrode of the input transistor, a first electrode of the pull-up transistor is connected with the clock signal terminal, and a second electrode of the pull-up transistor is connected with the signal output terminal; a first terminal of the storage capacitor is connected with the gate of the pull-up transistor, and a second terminal of the storage capacitor is connected with the second electrode of the pull-up transistor; a gate of the pull-down transistor and a gate of the pull-down control transistor are connected and both are connected with the reset terminal of the shift register, a first electrode of the pull-down transistor is connected with the signal output terminal, and a second electrode of the pull-down transistor is connected with the low level signal terminal; a first electrode of the pull-down control transistor is connected with the second electrode of the input transistor, and a second electrode of the pull-down control transistor is connected with the low level signal terminal; the signal input terminal of the shift register of a first stage is connected with the trigger signal input terminal, and the signal input terminal of each of the shift registers of the remaining stages is connected with the signal output terminal of the shift register of a previous stage; and the reset terminal of the shift register of a last stage is connected with the reset signal input terminal, and the reset terminal of each of the shift registers of the remaining stages is connected with the signal output terminal of the shift register of a next stage.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 86.0
- Lexical Diversity: 2.64286
- Patent Class: 382.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15303225', '15204489', '15121897', '15562570', '15761749']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3586113622913692
- 35 USC 102 Novelty (BERT): 0.4910735455931936
- Combined Prediction Score: 0.3718575806215516
- Mean Citation Score: 203.99711
- Max Citation Score: 221.89453
- Similarity Product: 162.32130434425952

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test