PATENT CLAIM ANALYSIS

Application Number: 16123665
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

Claim (Index 5):
The method of  claim 4 , wherein the inner gate structure includes an inner gate dielectric layer formed on the inner bottom spacer and the inner wall of the tubular vertical fin.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 2.04762
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15195498', '15199352', '15798886', '16046273', '15425158']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9411660152978244
- 35 USC 102 Novelty (BERT): 0.5449966912599832
- Combined Prediction Score: 0.9015490828940405
- Mean Citation Score: 366.40712600000006
- Max Citation Score: 435.7016
- Similarity Product: 249.4763506544113

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test