PATENT CLAIM ANALYSIS

Application Number: 16011539
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["365", "189020"]

Abstract:
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Claim (Index 12):
The memory system of  claim 11 , further comprising a continuity module, wherein second primary data port is coupled to the second primary data link bypassing the continuity module.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 94.0
- Lexical Diversity: 1.54167
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15262741', '15610001', '15260880', '15745396', '15522182']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7808834754940849
- 35 USC 102 Novelty (BERT): 0.5061771832655344
- Combined Prediction Score: 0.7534128462712298
- Mean Citation Score: 224.227558
- Max Citation Score: 279.89938
- Similarity Product: 186.38427751773

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test