PATENT CLAIM ANALYSIS

Application Number: 16039400
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["365", "226000"]

Abstract:
A memory device has a plurality of power rails, including: a first power rail for transmitting a high power voltage, a second power rail for transmitting a low power voltage, a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied. When power gating is applied, supply of the power voltage to the fourth power rail is blocked.

Claim (Index 5):
The memory device of  claim 1 , further comprising:\n a second PG switch connected between the first power rail and the fourth power rail; and a third PG switch connected between the second power rail and the fourth power rail.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 3.07843
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15959344', '16039404', '15366198', '15968297', '14198955']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8035117497908317
- 35 USC 102 Novelty (BERT): 0.5162565388396877
- Combined Prediction Score: 0.7747862286957173
- Mean Citation Score: 228.89987
- Max Citation Score: 325.0992
- Similarity Product: 221.86233956680297

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test