PATENT CLAIM ANALYSIS

Application Number: 15911709
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "574000"]

Abstract:
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

Claim (Index 7):
The transistor of  claim 6 , further including:\n a further N-type doped well formed in the N-type doped well of the collector; a third silicide layer on top of a more heavily doped N-type region of the further N-type doped well; wherein more heavily doped N-type region is shallow trench isolated from the epitaxial N-type doped region of the collector.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 2.1746
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15450114', '10379169', '14059531', '10581127', '12627794']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9172575189362864
- 35 USC 102 Novelty (BERT): 0.5336504371295583
- Combined Prediction Score: 0.8788968107556135
- Mean Citation Score: 276.511968
- Max Citation Score: 315.9996
- Similarity Product: 174.2130057952881

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test