PATENT CLAIM ANALYSIS

Application Number: 16027889
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "221000"]

Abstract:
A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

Claim (Index 20):
The method as recited in  claim 19 , further comprising forming source and drain regions, wherein the first dielectric layer remains on the silicon layer to protect against fin erosion up to the step of forming source and drain regions.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.24138
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15220150', '14800290', '14794562', '15058865', '12614906']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8932445683315299
- 35 USC 102 Novelty (BERT): 0.5754047543081507
- Combined Prediction Score: 0.861460586929192
- Mean Citation Score: 427.021876
- Max Citation Score: 512.3114
- Similarity Product: 367.89418112937216

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test