PATENT CLAIM ANALYSIS

Application Number: 16010714
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-07
Patent Classification: ["438", "158000"]

Abstract:
The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.

Claim (Index 10):
The manufacturing method for a thin film transistor according to  claim 7 , wherein in the first photoresist ashing and the second photoresist ashing, an ashing gas is O 2 .

Metadata:
- Claim Count in Document: 4.0
- Percentile: 94.0
- Lexical Diversity: 2.92727
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13270423', '15529506', '14764307', '12784759', '14795578']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8663073228954632
- 35 USC 102 Novelty (BERT): 0.5238794526485497
- Combined Prediction Score: 0.8320645358707719
- Mean Citation Score: 287.9383400000001
- Max Citation Score: 296.7822
- Similarity Product: 198.8126799173356

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test