PATENT CLAIM ANALYSIS

Application Number: 16154659
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "773000"]

Abstract:
Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.

Claim (Index 5):
The method of  claim 1  wherein the molding includes:\n attaching the semiconductor substrate of the first die to a temporary carrier; \n molding the mold material over the semiconductor substrate and the temporary carrier; and \n thinning the mold material to expose a first surface of the semiconductor substrate and a second surface of the mold material, wherein the first surface is adjacent the second surface.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 97.0
- Lexical Diversity: 2.53488
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15438691', '15229651', '15960960', '14264699', '14264584']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9206733005651474
- 35 USC 102 Novelty (BERT): 0.4745647761063059
- Combined Prediction Score: 0.8760624481192634
- Mean Citation Score: 185.666416
- Max Citation Score: 211.30542000000003
- Similarity Product: 179.31163203147057

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test