PATENT CLAIM ANALYSIS

Application Number: 15866309
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "059000"]

Abstract:
A transistor array panel according to an exemplary embodiment includes a substrate, and a first transistor and a second transistor positioned on the substrate. Each of the first transistor and the second transistor includes: a first electrode; a second electrode overlapping the first electrode; a spacing member positioned between the first electrode and the second electrode; a semiconductor layer extending along a side wall of the spacing member; and a gate electrode overlapping the semiconductor layer. A thickness of the spacing member of the first transistor is larger than a thickness of the spacing member of the second transistor.

Claim (Index 20):
The method of  claim 12 , further comprising:\n forming a planarization layer covering the first and second transistors; and forming a pixel electrode connected to the second electrode of the first transistor.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 2.7
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15344084', '12472979', '14184361', '14468472', '12753615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9212235254213808
- 35 USC 102 Novelty (BERT): 0.5056104460159357
- Combined Prediction Score: 0.8796622174808364
- Mean Citation Score: 252.310594
- Max Citation Score: 257.46878
- Similarity Product: 170.35595293851136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test