PATENT CLAIM ANALYSIS

Application Number: 15966637
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "401000"]

Abstract:
A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a first fill pinch off between the fin structures separated by a first pitch; and forming a material stack of a silicon containing layer, and a dielectric layer over the plurality of fin structures, wherein the dielectric provides a second fill pinch off between fin structures separated by a second pitch. The silicon containing layer is converted into an oxide material layer. The second dielectric that provides the second fill pinch off is removed, and an opening is etched in a remaining silicon containing layer exposed by removing the second fill pinch off. An underlying gate cut region is etched in the gate structure using the opening in the remaining portion of the silicon containing layer.

Claim (Index 20):
The semiconductor device of  claim 19 , wherein the gate cut trench is filled with an interlevel dielectric material.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.66071
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15966664', '15295277', '15487685', '15634307', '15620095']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9346235454860212
- 35 USC 102 Novelty (BERT): 0.5331294213981194
- Combined Prediction Score: 0.894474133077231
- Mean Citation Score: 312.9592340000001
- Max Citation Score: 366.71826
- Similarity Product: 285.45495951137065

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test