PATENT CLAIM ANALYSIS

Application Number: 16235284
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["324", "521000"]

Abstract:
A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.

Claim (Index 20):
A voltage regulator system, comprising:\n a plurality of power stages, each power stage comprising:\n one or more power transistor switches configured to output a phase current for the power stage; \n one or more power transistor gate drivers configured to turn the one or more power transistor switches off and on; \n fault detection circuitry configured to detect one or more faults in the power stage, including:\n positive and negative overcurrent faults in which the phase current exceeds a positive or negative current limit; \n an overtemperature fault in which the temperature of the power stage exceeds a temperature limit; \n a phase fault in the power transistor output stage; \n a boot supply under-voltage fault in which a voltage of a boot capacitor coupled to the one or more power transistor gate drivers is below a target boot voltage level; and \n a supply under-voltage fault in which a supply voltage of the power stage is below a target supply voltage level; and \n \n reporting circuitry configured to monitor and report information of the power stage, including:\n report temperature information for the power stage in a first nominal range at a first pin of the power stage when no faults are detected; \n report phase current information for the power stage in a second nominal range at a second pin of the power stage when no faults are detected; and \n report any of the faults in an out-of-band range outside the first nominal range at the first pin and/or in an out-of-band range outside the second nominal range at the second pin, so that each type of fault which the fault detection circuitry is configured to detect has a unique fault signature at the first and the second pins; \n \n a controller comprising: a first pin coupled to the first pin of each power stage and configured to receive aggregate temperature information from the plurality of power stages, the aggregate temperature information indicating the highest temperature reported by all of the power stages; a plurality of second pins, each second pin of the controller coupled to the second pin of one of the power stages and configured to receive phase current information from that power stage; control circuitry configured to control operation of the power stages; detection circuitry configured to detect signal levels at the first and the second pins of the controller, wherein the aggregate temperature information is reported to the controller at the first pin of the controller in a first nominal range and the phase current information is reported to the controller at each of the second pins of the controller in a second nominal range; and fault analysis circuitry configured to identify a type of fault reported to the controller and the power stage that reported the fault based on the detected signal levels at the first and the second pins of the controller and further based on state information accessible by the controller, each fault type reported to the controller having a unique fault signature at the first and the second pins of the controller which is outside at least one of the first and the second nominal ranges.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.54839
- Patent Class: 324.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15647048', '14255079', '16107528', '11926475', '11102603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4951419249138061
- 35 USC 102 Novelty (BERT): 0.6124355521891827
- Combined Prediction Score: 0.5068712876413437
- Mean Citation Score: 252.754948
- Max Citation Score: 533.5884
- Similarity Product: 525.8780085388183

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test