PATENT CLAIM ANALYSIS

Application Number: 16042927
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["326", "101000"]

Abstract:
A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.

Claim (Index 10):
The semiconductor structure of  claim 1 , wherein the vertical transport logic circuit cell comprises a NAND2 logic circuit such that the first logic gate is a first NAND gate and the second logic gate is a second NAND gate.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 3.27027
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15046863', '15464696', '10648474', '12338632', '11090116']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6787886612789665
- 35 USC 102 Novelty (BERT): 0.4773739069809959
- Combined Prediction Score: 0.6586471858491695
- Mean Citation Score: 181.869966
- Max Citation Score: 208.79659
- Similarity Product: 160.78718454122188

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test