PATENT CLAIM ANALYSIS

Application Number: 16386202
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "368000"]

Abstract:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

Claim (Index 12):
The integrated circuit structure of  claim 11 , wherein each of the first gate structure and the second gate structure further comprises an insulating cap on the gate electrode and on and the sidewalls of the high-k gate dielectric layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 100.0
- Lexical Diversity: 3.01923
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15859352', '15859353', '15859354', '15859327', '15859412']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9318722760532372
- 35 USC 102 Novelty (BERT): 0.5400865550828504
- Combined Prediction Score: 0.8926937039561984
- Mean Citation Score: 248.608586
- Max Citation Score: 287.37112
- Similarity Product: 237.8686261628341

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test