PATENT CLAIM ANALYSIS

Application Number: 15949044
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-07
Patent Classification: ["327", "541000"]

Abstract:
A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Claim (Index 1):
A core power detection circuit, arranged to execute power detection in an input/output (I/O) control system to generate a core power detection signal for controlling the I/O control system, the I/O control system operating according to a plurality of supply voltages with respect to a first reference voltage, the core power detection circuit comprising:\n a reference power bias circuit, arranged to generate a second reference voltage according to a first supply voltage of the plurality of supply voltages, wherein the reference power bias circuit comprises:\n a group of voltage-division components, coupled between a first supply voltage wire and a reference voltage wire, each voltage-division component within the group of voltage-division components being an active component having at least three terminals, said at least three terminals comprising two terminals through which the group of voltage-division components are connected in series to form a serial connection between the first supply voltage wire and the reference voltage wire, said at least three terminals further comprising another terminal differing from the two terminals, said another terminal differing from the two terminals being electrically and directly connected to the reference voltage wire for one of the group of voltage-division components that is closest to the reference voltage wire along a connection path on the serial connection, or being electrically and directly connected to either the second reference voltage or the reference voltage wire for one of the group of voltage-division components that is not closest to the reference voltage wire along the connection path on the serial connection, wherein the first supply voltage wire and the reference voltage wire are arranged to conduct the first supply voltage and the first reference voltage, respectively, and a voltage on a terminal between two voltage-division components of the group of voltage-division components is utilized as the second reference voltage; and \n a comparison circuit, coupled to the reference power bias circuit, arranged to execute a comparison operation according to at least a part of a second supply voltage of the plurality of supply voltages and the second reference voltage to generate a third reference voltage, wherein the second supply voltage is less than the first supply voltage, and the comparison circuit comprises:\n a first group of Field Effect Transistors (FETs), coupled between the first supply voltage wire and the reference voltage wire, wherein the first group of FETs comprises:\n a first P-type FET and a first N-type FET, wherein source terminals of the first P-type FET and the first N-type FET are coupled to the first supply voltage wire and the reference voltage wire, respectively, drain terminals of the first P-type FET and the first N-type FET are coupled to each other, a gate terminal of the first P-type FET is coupled to the terminal between the two voltage-division components to receive the second reference voltage, the first N-type FET is coupled to a second supply voltage wire and the reference voltage wire via a gate terminal and a source terminal of the first N-type FET, respectively, and the second supply voltage wire is arranged to conduct the second supply voltage; \n \n wherein the core power detection circuit utilizes the third reference voltage or a derivative of the third reference voltage as the core power detection signal, and a configuration of the core power detection circuit makes the core power detection signal indicate if the second supply voltage is in a ready state to allow a partial circuit of the I/O control system to operate when the second supply voltage is in the ready state.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 91.0
- Lexical Diversity: 2.78846
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14397750', '10952425', '12154285', '15694847', '12610750']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7637064350603233
- 35 USC 102 Novelty (BERT): 0.4682746150835434
- Combined Prediction Score: 0.7341632530626454
- Mean Citation Score: 186.561646
- Max Citation Score: 195.6875
- Similarity Product: 156.48089382052422

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test