PATENT CLAIM ANALYSIS

Application Number: 16038197
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "326000"]

Abstract:
A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.

Claim (Index 7):
The semiconductor memory device according to  claim 1  further comprising:\n a first source/drain doping region disposed in the main surface of the substrate and adjacent to the first single spacer structure; and \n a second source/drain doping region disposed in the main surface of the substrate and adjacent to the second single spacer structure.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 95.0
- Lexical Diversity: 3.04545
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13873681', '14721970', '10907829', '15048236', '15043571']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9109039153814192
- 35 USC 102 Novelty (BERT): 0.479539121423555
- Combined Prediction Score: 0.8677674359856327
- Mean Citation Score: 180.42124
- Max Citation Score: 187.2861
- Similarity Product: 137.31589379734396

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test