PATENT CLAIM ANALYSIS

Application Number: 15923064
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["365", "185020"]

Abstract:
A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

Claim (Index 9):
The memory device of  claim 1 , wherein:\n the set of NAND strings comprises an additional row of NAND strings at the one distance from a second edge of the plurality of word line layers, opposite the first edge; and the control circuit is configured to program the additional row of NAND strings concurrently with the programming of the one row of NAND strings.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 1.87143
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15437718', '15430299', '15889519', '15615972', '15678683']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.818863973700397
- 35 USC 102 Novelty (BERT): 0.493688434184297
- Combined Prediction Score: 0.786346419748787
- Mean Citation Score: 241.340228
- Max Citation Score: 280.57614
- Similarity Product: 235.41314432034017

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test