PATENT CLAIM ANALYSIS

Application Number: 16033377
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "303000"]

Abstract:
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

Claim (Index 31):
A memory cell comprising:\n first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions, the second transistor having third and fourth source/drain regions, and the third transistor having fifth and sixth source/drain regions; wherein the memory cell includes a pillar of semiconductor material extending through the second and third transistors, and which includes the third, fourth, fifth and sixth source/drain regions as well as channel regions of the second and third transistors; a first bitline under the second transistor and electrically coupled with the first source/drain region; a second bitline above the third transistor and electrically coupled with the sixth source/drain region; a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor; and wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 3.44681
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16006301', '15664183', '15664217', '15664143', '15664161']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9272256879883134
- 35 USC 102 Novelty (BERT): 0.5175050525418958
- Combined Prediction Score: 0.8862536244436716
- Mean Citation Score: 301.80616999999995
- Max Citation Score: 329.5861
- Similarity Product: 266.2007727313995

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test