PATENT CLAIM ANALYSIS

Application Number: 15741753
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "059000"]

Abstract:
The present application discloses A thin film transistor (TFT), including: a substrate; a source-drain layer comprising a source electrode and a drain electrode over the substrate; and an active layer comprising a poly-Si pattern and an amorphous-Si pattern having contact with the poly-Si pattern over the substrate. The amorphous-Si pattern is between the poly-Si pattern and the source-drain layer; the source electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in a direction substantially perpendicular to a surface of the substrate; and the drain electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in the direction substantially perpendicular to the surface of the substrate.

Claim (Index 8):
The TFT according to  claim 1 , further comprising a gate electrode, wherein an orthogonal projection of the poly-Si pattern on the substrate substantially overlaps with an orthogonal projection of the gate electrode.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.56522
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15704588', '12753732', '15309949', '15809673', '15521471']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9248296367065044
- 35 USC 102 Novelty (BERT): 0.4985953954545574
- Combined Prediction Score: 0.8822062125813096
- Mean Citation Score: 246.863866
- Max Citation Score: 264.90216000000004
- Similarity Product: 202.9868575473548

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test