PATENT CLAIM ANALYSIS

Application Number: 15969234
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "777000"]

Abstract:
The present invention ultra-low loss high energy density dielectric layers having femtosecond (10 −15  sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.

Claim (Index 5):
The high-speed semiconductor chip stack of  claim 1 , wherein the capacitive dielectric material comprises a thermodynamically stable perovskite electroceramic.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 1.35417
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15958706', '15881164', '11479159', '14268082', '13216192']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9204118721975828
- 35 USC 102 Novelty (BERT): 0.4862968108628234
- Combined Prediction Score: 0.8770003660641068
- Mean Citation Score: 181.370446
- Max Citation Score: 212.47585
- Similarity Product: 160.49449314935802

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test