PATENT CLAIM ANALYSIS

Application Number: 16133404
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-06
Patent Classification: ["257", "040000"]

Abstract:
A method of fabricating a display panel may include forming an oxide semiconductor pattern on a base layer including a first region and a second region, etching first, second, and third insulating layers to form a first groove that overlaps the second region, forming electrodes on the third insulating layer, forming a fourth insulating layer on the third insulating layer to cover the electrodes, thermally treating the fourth insulating layer, forming an organic layer to cover the fourth insulating layer, and forming an organic light emitting diode on the organic layer.

Claim (Index 1):
A method of fabricating a display panel, comprising:\n forming a silicon semiconductor pattern on a base layer including a first region and a second region that is extended from the first region, the silicon semiconductor pattern overlapping the first region; forming a first control electrode on the silicon semiconductor pattern, the first control electrode overlapping the silicon semiconductor pattern with a first insulating layer interposed therebetween; forming a second control electrode to overlap the first region and to be spaced apart from the first control electrode with a second insulating layer interposed therebetween; forming an oxide semiconductor pattern on the second control electrode to overlap the second control electrode with a third insulating layer interposed therebetween; etching the first, second, and third insulating layers to form a first contact hole and a second contact hole exposing at least a portion of the silicon semiconductor pattern and a first groove that overlaps the second region; forming on the third insulating layer a first input electrode and a first output electrode that are connected to the silicon semiconductor pattern through the first and second contact holes, and a second input electrode and a second output electrode that are connected to the oxide semiconductor pattern; forming a fourth insulating layer on the third insulating layer to cover the first input electrode, the first output electrode, the second input electrode, and the second output electrode; thermally treating the fourth insulating layer; forming an organic layer to cover the fourth insulating layer; and forming on the organic layer an organic light emitting diode that is connected to the first output electrode.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 2.32558
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15923507', '14506061', '15654485', '15271504', '15297640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9013890807233964
- 35 USC 102 Novelty (BERT): 0.4909831673349367
- Combined Prediction Score: 0.8603484893845506
- Mean Citation Score: 218.501642
- Max Citation Score: 230.82271
- Similarity Product: 186.0572049974984

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test