PATENT CLAIM ANALYSIS

Application Number: 16123396
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "206000"]

Abstract:
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Claim (Index 21):
A semiconductor device comprising:\n a first conductivity type first MIS transistor electrically connected between a first node with which a first potential is supplied and a second node; a second conductivity type first MIS transistor electrically connected between the second node and a third node with which a second potential different from the first potential is supplied; a second conductivity type second MIS transistor electrically connected between the second node and the third node in parallel with the second conductivity type first MIS transistor; a first conductivity type second MIS transistor electrically connected between the first node and the fourth node; a second conductivity type third MIS transistor electrically connected between the third node and the fourth node; a second conductivity type fourth MIS transistor electrically connected between the third node and the fourth node in parallel with the second conductivity type third MIS transistor; a second conductivity fifth MIS transistor electrically connected between the second node and the fifth node; a second conductivity type sixth MIS transistor electrically connected between the fourth node and the sixth node; a first conductivity type first well region; a first conductivity type second well region; and a second conductivity type well region arranged between the first conductivity type first well region and the first conductivity type second well region, wherein the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor are arranged in a first active region, wherein the second conductivity type second MIS transistor is arranged in a second active region which is separated from the first active region, and which is arranged next to the first active region, wherein the second conductivity type third MIS transistor is arranged in a third active region, wherein the second conductivity type fourth MIS transistor and the second conductivity type sixth MIS transistor are arranged in a fourth active region which is separated from the third active region, and which is arranged next to the third active region, wherein the first, second, third and fourth active regions are arranged in a first direction, and arranged in sequence, and separated from one another, wherein, in plan view, the first active region and the second active region are arranged in the first conductivity type first well region, wherein, in plan view, the third active region and the fourth active region are arranged in the first conductivity type second well region, wherein a gate electrode of the second conductivity type fifth MIS transistor is comprised of a first part of a first gate wiring which is extended in the first direction, and which is arranged over the first active region, wherein a gate electrode of the second conductivity type first MIS transistor is comprised of a second part of a second gate wiring which is extended in the first direction, and which is arranged over the first active region and the second active region, wherein a gate electrode of the second conductivity type second MIS transistor is comprised of a third part of the second gate wiring, wherein a gate electrode of the second conductivity type third MIS transistor is comprised of a fourth part of a third gate wiring which is extended in the first direction, and which is arranged over the third active region and the fourth active region, wherein a gate electrode of the second conductivity type fourth MIS transistor is comprised of a fifth part of the third gate wiring, wherein a gate electrode of the second conductivity type sixth MIS transistor is comprised of a sixth part of a fourth gate wiring which is extended in the first direction, and which is arranged over the fourth active region, wherein a length of the first active region in a second direction crossing to the first direction is longer than a length of the second active region in the second direction, and wherein a length of the fourth active region in the second direction is longer than a length of the third active region in the second direction.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 97.0
- Lexical Diversity: 2.69767
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15616633', '13559461', '14921038', '15165651', '14579898']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9491364028569884
- 35 USC 102 Novelty (BERT): 0.6503453707633556
- Combined Prediction Score: 0.919257299647625
- Mean Citation Score: 631.436662
- Max Citation Score: 645.56445
- Similarity Product: 592.3872392548532

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test