PATENT CLAIM ANALYSIS

Application Number: 16125786
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2020-01
Patent Classification: ["365", "156000"]

Abstract:
A memory array and a semiconductor chip are provided. The memory array includes memory cells, each includes: first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. A source/drain of the first pull-up transistor is coupled to a source/drain of the first pull-down transistor. A source/drain of the second pull-up transistor is coupled to a source/drain of the second pull-down transistor. Gates of the second pull-up and pull-down transistors are coupled to the first node. Gates of the first pull-up and pull-down transistors are coupled to the second node. The first and second pass-gate transistors are respectively coupled to the first and second nodes. The first and second pull-up transistors respectively include a first active structure having a bottom portion including a strained semiconductor material and a top portion including an unstrained semiconductor material. The first active structures continuously extend across the memory array.

Claim (Index 16):
A semiconductor chip, comprising:\n a logic array, comprising a plurality of logic cells, wherein each of the plurality of logic cells comprises a first active structure over a substrate, the first active structure has a bottom portion and a top portion over the bottom portion, the top portion of the first active structure comprises a strained semiconductor material, the bottom portion of the first active structure comprises an unstained semiconductor material, and the first active structures of adjacent logic cells are connected with each other to continuously extend across the logic array; and a memory array, comprising a plurality of SRAM cells, wherein each of the plurality of SRAM cells comprises a second active structure over the substrate, the second active structure has a bottom portion and a top portion over the bottom portion, the top portion of the second active structure comprises a strained semiconductor material, the bottom portion of the second active structure comprises an unstrained semiconductor material, and the second active structures of adjacent SRAM cells are connected with each other to continuously extend across the memory array.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 3.32653
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14671587', '14690068', '14104835', '13328685', '14486293']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8004949936671719
- 35 USC 102 Novelty (BERT): 0.4906254760364734
- Combined Prediction Score: 0.7695080419041022
- Mean Citation Score: 231.53286799999995
- Max Citation Score: 241.14894
- Similarity Product: 168.55645431460977

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test