PATENT CLAIM ANALYSIS

Application Number: 15964290
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["711", "122000"]

Abstract:
Maintaining multiple cache areas in a storage device having multiple processors includes loading data into a first local cache in response to a first processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the first local cache is accessible to the first subset of the processors and is inaccessible to other processors, loading data into a second local cache in response to a second processor of the second subset of the processors performing a read operation to the specific portion of non-volatile storage, where the second local cache is accessible to the second subset of the processors and is inaccessible to other processors, and loading data into a global cache in response to one of the processors performing a write operation to the specific portion of non-volatile storage, where the global cache is accessible to all the processors.

Claim (Index 11):
A non-transitory computer readable medium containing software that maintains multiple cache areas in a storage device having multiple processors, the software comprising:\n executable code that loads data from a specific portion of non-volatile storage into a first local cache area in response to a first processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, wherein the first local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and is inaccessible to a third subset of the processors that is different than the first subset of the processors and the second subset of the processors; executable code that loads data from the specific portion of non-volatile storage into a second local cache area in response to a second processor of the second subset of the processors performing a read operation to the specific portion of non-volatile storage, wherein the second local cache area is different from the first local cache area and wherein the second local cache area is accessible to the second subset of the processors and is inaccessible to the first subset of the processors and the third subset of the processors; and executable code that loads data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors and to the third subset of processors.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 3.78049
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15964315', '11729722', '15279787', '11729707', '11729716']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5286159024631358
- 35 USC 102 Novelty (BERT): 0.5481824795270505
- Combined Prediction Score: 0.5305725601695273
- Mean Citation Score: 273.16778400000004
- Max Citation Score: 416.5423
- Similarity Product: 351.69273507537844

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test