PATENT CLAIM ANALYSIS

Application Number: 15987706
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "506000"]

Abstract:
Disclosed is a method for fabricating a semiconductor device with intra-die variation control. In one embodiment, a method for fabricating a semiconductor device includes: depositing a first dielectric layer on a semiconductor substrate die; patterning a conductive layer on the first dielectric layer to create at least one device region and at least one dummy pattern region, wherein the at least one device region comprises a plurality of first conductive patterns and the at least one dummy pattern region comprises a plurality of second conductive patterns to control intra-die variation.

Claim (Index 16):
A method for fabricating a semiconductor device comprising:\n forming at least one conductive feature on a semiconductor substrate die; depositing a first dielectric layer on the semiconductor substrate die; depositing a conductive layer on the first dielectric layer; patterning the conductive layer on the first dielectric layer to create at least one device region and at least one dummy pattern region, wherein the at least one device region comprises a plurality of first conductive patterns and the at least one dummy pattern region comprises a plurality of second conductive patterns to control intra-die variation; and annealing the semiconductor substrate die with the plurality of first conductive patterns in the at least one device region and the plurality of second conductive patterns in the at least one dummy pattern region, wherein a ratio between a first area and a second area in the at least one dummy pattern region is 40-90%, wherein the first area is a total area of the first dielectric layer covered by the plurality of second conductive patterns and the second area is a total area of the first dielectric layer without the plurality of second conductive patterns, and wherein a variation of resistance values of the plurality of first conductive patterns in the at least one device region after annealing is in a range of \u00b110%.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 93.0
- Lexical Diversity: 2.18182
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15225024', '14995017', '11281030', '13344137', '12417394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9047343238212644
- 35 USC 102 Novelty (BERT): 0.4532715800210348
- Combined Prediction Score: 0.8595880494412416
- Mean Citation Score: 133.94834799999998
- Max Citation Score: 146.54822
- Similarity Product: 119.95928025973558

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test