PATENT CLAIM ANALYSIS

Application Number: 15908449
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "185030"]

Abstract:
According to one embodiment, a semiconductor memory device includes memory cells, a word line, bit lines, and a controller. The word line is connected to the memory cells. Each of the lines is connected to the memory cells. In a program operation, while applying a program voltage to the word line, the controller applies a first voltage to a bit line connected to memory cells to which a first data is to be written, applies a second voltage lower than the first voltage to a bit line connected to memory cells to which a second data is to be written, and applies a third voltage lower than the second voltage to a bit line connected to memory cells to which a third data is to be written.

Claim (Index 15):
The device of  claim 1 , wherein\n the plurality of memory cells is set to have a fourth threshold voltage higher than the third threshold voltage in a case of storing fourth data as the plurality of bits of data, set to have a fifth threshold voltage higher than the fourth threshold voltage in a case of storing fifth data as the plurality of bits of data, and set to have a sixth threshold voltage higher than the fifth threshold voltage in a case of storing sixth data as the plurality of bits of data, in the program, the controller applies a second program voltage higher than the first program voltage after applying the first program voltage, and while applying the second program voltage, applies a fourth voltage higher than the first voltage to each of the set of the bit lines connected to the memory cells to which the first data is to be written, the set of the bit lines connected to the memory cells to which the second data is to be written, and the set of the bit lines connected to the memory cells to which the third data is to be written, applies a fifth voltage lower than the fourth voltage to bit lines connected to memory cells to which the fourth data is to be written, applies a sixth voltage lower than the fifth voltage to bit lines connected to memory cells to which the fifth data is to be written, and applies a seventh voltage lower than the sixth voltage to bit lines connected to memory cells to which the sixth data is to be written.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 3.475
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15174114', '15695470', '14474307', '15700864', '15061967']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8187812481561623
- 35 USC 102 Novelty (BERT): 0.4788903319200394
- Combined Prediction Score: 0.78479215653255
- Mean Citation Score: 226.22265
- Max Citation Score: 239.73666
- Similarity Product: 199.7152425945032

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test