PATENT CLAIM ANALYSIS

Application Number: 15923282
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185290"]

Abstract:
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Claim (Index 10):
A method for controlling a memory system,\n the memory system comprising:\n a controller chip configured to send\n a first operation command, \n a second operation command, \n a status inquiry command, \n a suspend command, and \n a resume command; and \n \n a memory chip configured to perform\n a first operation upon receipt of the first operation command, \n a second operation upon receipt of the second operation command, \n a status output upon receipt of the status inquiry command, \n a suspend upon receipt of the suspend command, \n a resume upon receipt of the suspend command, \n \n the method including:\n sending the first operation command from the controller chip to cause the memory chip to perform the first operation, \n during the first operation is performed, sending the suspend command from the controller chip to cause the memory chip to suspend the first operation, \n after the first operation is suspended, sending the status inquiry command from the controller chip to cause the memory chip to send status information to the controller chip, \n after the status information to the controller chip is received, sending the second operation command from the controller chip to cause the memory chip to perform the second operation, \n after the second operation has been finished, sending the resume command from the controller chip to cause the memory chip to resume the first operation.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 90.0
- Lexical Diversity: 2.63265
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15074190', '15361778', '14748351', '14093108', '13425818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8125648231913883
- 35 USC 102 Novelty (BERT): 0.4843713835566459
- Combined Prediction Score: 0.779745479227914
- Mean Citation Score: 230.67682
- Max Citation Score: 258.88852
- Similarity Product: 218.1093117486573

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test