PATENT CLAIM ANALYSIS

Application Number: 16030853
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["349", "043000"]

Abstract:
A method for manufacturing a BOA liquid crystal display panel is provided. The BOA liquid crystal display panel is structured to have a TFT entirely located on a first black matrix and further, a second black matrix is arranged between the TFT and the passivation protection layer such that the second black matrix and the first black matrix completely enclose the TFT to block light emitting from a backlight module located under an array substrate in a direction toward an active layer and also to block reflecting light irradiating the active layer from lateral sides and a top side to better prevent light irradiating the active layer of the TFT for preventing photo leakage current, ensuring stable performance of the TFT device, and improving image displaying quality. The method helps overcome the issue of photo leakage current induced by backlighting irradiating the active layer of the TFT.

Claim (Index 4):
The method according to  claim 2  comprising the following steps:\n (1) providing a lower substrate, coating a layer of black resin on the lower substrate, using a first mask to subject the black resin to patterning treatment so as to form the first black matrix; \n (2) sputtering-coating or vapor-depositing a metal film on the first black matrix and the lower substrate and using a second mask to subject the metal film to patterning treatment so as to form the source/drain terminals located on the first black matrix; \n (3) successively depositing a semiconductor film and an insulation film on the source/drain terminals and the first black matrix through chemical vapor deposition and then sputtering-coating or vapor-depositing another metal film, and using a third mask to simultaneously subject said another metal film, the insulation film, and the semiconductor film to patterning treatment so as to form the active layer, a gate insulation layer, and a gate terminal that are sequentially formed on the source/drain terminals and the first black matrix, \n wherein the source/drain terminals, the active layer, the gate insulation layer, and the gate terminal constitute the TFT; \n (4) coating another layer of black resin on the TFT and the lower substrate and using the first mask to subject said another layer of the black resin to patterning treatment to form the second black matrix such that the second black matrix and the first black matrix completely enclose the TFT; \n (5) depositing a passivation protection layer on the second black matrix and the lower substrate through chemical vapor deposition and using a fourth mask to subject the passivation protection layer to patterning treatment to form a via extending through the passivation protection layer and the second black matrix so as to expose a portion of the source/drain terminals; \n (6) depositing an indium tin oxide (ITO) film on the passivation protection layer and using a fifth mask to subject the ITO film to patterning treatment so as to form a pixel electrode, in such a way that the pixel electrode is set in contact with the source/drain terminals through the via thereby completing the manufacture of the array substrate; and \n (7) providing an upper substrate and sequentially forming a color resist layer and a common electrode layer on the upper substrate to complete the manufacture of the CF substrate, and \n then, laminating the array substrate and the CF substrate together, filling liquid crystal molecules between the array substrate and the CF substrate to form a liquid crystal layer, and subjecting the array substrate and the CF substrate to packaging.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.9125
- Patent Class: 349.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14778085', '15529508', '14423128', '15441246', '15441245']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.833330235873875
- 35 USC 102 Novelty (BERT): 0.5630243659261549
- Combined Prediction Score: 0.806299648879103
- Mean Citation Score: 338.54115
- Max Citation Score: 455.76462
- Similarity Product: 342.06936881027696

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test