PATENT CLAIM ANALYSIS

Application Number: 15889928
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["365", "193000"]

Abstract:
When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.

Claim (Index 14):
The semiconductor device according to  claim 13 ,\n wherein during the second adjustment period, the control circuit determines as a writing result for left edge inspection on an effective window of the write data a writing result of the write data obtained when a delay amount larger than the first delay amount stored in the storage unit by k\u00d7\u0394D is set as a delay amount of the delay adjustment circuit, wherein the control circuit obtains one or more writing results for the left edge inspection by sequentially reducing k from N (\u22652) until a writing result for left edge inspection on the write data is incorrect, wherein during the second adjustment period, the control circuit determines as a writing result for right edge inspection on an effective window of the write data a writing result of the write data obtained when a delay amount smaller than the second delay amount stored in the storage unit by k\u00d7\u0394D is set as a delay amount of the delay adjustment circuit, wherein the control circuit obtains one or more writing results for the right edge inspection by sequentially reducing k from N (\u22652) until a writing result for right edge inspection on the write data is incorrect, and wherein the control circuit corrects at least one of the first delay amount, the second delay amount, and the third delay amount stored in the storage unit or none of them based on one or more writing results for the left edge inspection and one or more writing results for the left edge inspection.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 88.0
- Lexical Diversity: 2.18868
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15360404', '14369501', '12596535', '11505328', '13272856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8021997866591926
- 35 USC 102 Novelty (BERT): 0.4696577068208475
- Combined Prediction Score: 0.7689455786753581
- Mean Citation Score: 168.60554
- Max Citation Score: 172.85379
- Similarity Product: 127.05150473486243

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test