PATENT CLAIM ANALYSIS

Application Number: 15903507
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["327", "211000"]

Abstract:
In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Claim (Index 16):
The sequential circuit of  claim 11 , wherein the combinational logic comprises:\n an inverter configured to invert the voltage of the first node, a first PMOS transistor having one end connected to the first connection node in response to an output value of the inverter, a second PMOS transistor configured to connect other end of the first PMOS transistor of the combinational logic to the power supply terminal in response to the data; a third PMOS transistor configured to connect the one end of the first PMOS transistor of the combinational logic to the power supply terminal in response to an inverted version of a scan enable signal; a fourth PMOS transistor configured to connect the first connection node to the power supply terminal in response to the voltage of the second node; a first NMOS transistor configured to connect the second connection node to the first connection node in response to the output value of the inverter; a second NMOS transistor having one end connected to the first connection node in response to the data; a third NMOS transistor configured to connect other end of the second NMOS transistor of the combinational logic to the second connection node in response to the inverted scan enable signal; and a fourth NMOS transistor configured to connect the ground terminal to the second connection node in response to the voltage of the second node.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 88.0
- Lexical Diversity: 4.41935
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15254272', '15663852', '13440007', '14873634', '13049427']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7702472609263655
- 35 USC 102 Novelty (BERT): 0.5710584937223834
- Combined Prediction Score: 0.7503283842059674
- Mean Citation Score: 301.87892
- Max Citation Score: 444.85358
- Similarity Product: 420.0930785933042

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test