PATENT CLAIM ANALYSIS

Application Number: 15893197
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["345", "093000"]

Abstract:
Fault-tolerant liquid crystal displays are delineated for avionics systems. At least some example embodiments are methods including providing an avionics display full screen on the LCD, the providing being implemented by driving source signal lines of the LCD by way of a first source driver circuit through a first set of FETs; driving gate signal lines of the LCD by way of a first gate driver circuit through a second set of FETs; preventing back biasing of a second source driver circuit by electrically isolating the source signal lines from the second source driver circuit; and preventing back biasing of a second gate driver circuit by electrically isolating the gate signal lines from the second gate driver circuit.

Claim (Index 8):
A fault-tolerant liquid crystal display (LCD) for avionic systems, comprising:\n an LCD comprising a panel glass, source signal lines, and gate signal lines; a first driver circuit comprising a first source driver circuit coupled to the source signal lines, and a first gate driver circuit coupled to the gate signal lines; a first plurality of field effect transistors (FETs) disposed directly on the panel glass, the first plurality of FETs electrically coupled between the first source driver circuit and the source signal lines; a second plurality of FETs disposed directly on the panel glass, the second plurality of FETs electrically coupled between the first gate driver circuit and the gate signal lines; a second driver circuit distinct from the first driver circuit, the second driver circuit comprising a second source driver circuit coupled to the source signal lines, and a second gate driver circuit coupled to the gate signal lines; a third plurality of FETs disposed directly on the panel glass, the third plurality of FETs electrically coupled between the second source driver circuit and the source signal lines; a fourth plurality of FETs disposed directly on the panel glass, the fourth plurality of FETs electrically coupled between the second gate driver circuit and the gate signal lines; a control circuit electrically coupled to the first, second, third, and fourth plurality of FETs, the control circuit configured to implement a first mode in which the first driver circuit is electrically coupled to the source signal lines and the gate signal lines by way of the first and second plurality of FETs, and the second driver circuit is electrically isolated from the source signal lines and the gate signal lines by way of the third and fourth plurality of FETs; and the control circuit being configured to implement a second mode in which the first driver circuit is electrically isolated from the source signal lines and the gate signal lines by way of the first and second plurality of FETs, and the second driver circuit is electrically coupled to the source signal lines and the gate signal lines by way of the third and fourth plurality of FETs.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 88.0
- Lexical Diversity: 2.38462
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15266556', '13182457', '11780216', '14963880', '11371925']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6366691826783191
- 35 USC 102 Novelty (BERT): 0.4746237000539174
- Combined Prediction Score: 0.620464634415879
- Mean Citation Score: 179.04276000000004
- Max Citation Score: 190.88214
- Similarity Product: 146.9167818920159

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test