PATENT CLAIM ANALYSIS

Application Number: 16402343
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "401000"]

Abstract:
Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.

Claim (Index 15):
The semiconductor device of  claim 14 , further comprising a self-aligned contact cap over the gate conductor.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 100.0
- Lexical Diversity: 2.20588
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15841887', '16244493', '15841933', '15495237', '15705888']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9275623870535662
- 35 USC 102 Novelty (BERT): 0.5214343999826725
- Combined Prediction Score: 0.8869495883464767
- Mean Citation Score: 270.98269600000003
- Max Citation Score: 315.6484
- Similarity Product: 212.9502406369448

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test