PATENT CLAIM ANALYSIS

Application Number: 15975556
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["710", "107000"]

Abstract:
Memory devices having a reduced global data patch footprint and associated systems and methods. In some embodiments, a memory device is provided, comprising (a) a memory array including first and second sets of memory banks, (b) lower data terminals, (c) upper data terminals, and (d) an input/output (I/O) circuit including an internal data bus. The internal data bus can include a first plurality of global data lines in communication the first set of memory banks, a second plurality of global data lines in communication with the second set of memory banks, a third plurality of global data lines in communication with the first and second pluralities of global data lines, and a fourth plurality of global data lines in communication with the first and second pluralities of global data lines. The third plurality of global data lines is configured to bidirectionally transfer data to and from the lower terminals, and the fourth plurality of global data lines is configured to bidirectionally transfer data to and from the upper terminals.

Claim (Index 18):
A method for operating a memory device, the method comprising:\n electrically coupling an internal data bus of an input/output circuit to lower data terminals and upper data terminals of the memory device, the internal data bus including\u2014\n a first plurality of global data lines in communication with one or more memory banks of the memory device, \n a second plurality of global data lines in communication with one or more of the memory banks, \n a third plurality of global data lines in communication with the first plurality and the second plurality of global data lines, wherein individual lines of the third plurality of global data lines are configured to bidirectionally transfer data, and \n a fourth plurality of global data lines in communication with the first plurality and the second plurality of global data lines, wherein individual lines of the fourth plurality of global data lines are configured to bidirectionally transfer data; and \n transferring data on the third plurality of global data lines (a) from one or more of the memory banks to the lower and/or upper terminals through the first and/or second plurality of global data lines, and (b) from the lower and/or upper terminals to one or more of the memory banks through the first and/or second plurality of global data lines; and transferring data on the fourth plurality of global data lines (a) from one or more of the memory banks to the lower and/or upper terminals through the first and/or second plurality of global data lines, and (b) from the lower and/or upper terminals to one or more of the memory banks through the first and/or second plurality of global data lines, wherein: transferring the data on the third plurality of global data lines and/or transferring the data on the fourth plurality of global data lines includes transferring the data according to a staggered firing scheme to separate transition of corresponding signals in time.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 3.09677
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15974587', '13629328', '15681151', '14106811', '10750156']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6532721737232514
- 35 USC 102 Novelty (BERT): 0.4724836085773497
- Combined Prediction Score: 0.6351933172086612
- Mean Citation Score: 153.614336
- Max Citation Score: 162.22773999999995
- Similarity Product: 114.32926511303064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test