PATENT CLAIM ANALYSIS

Application Number: 15958847
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["438", "113000"]

Abstract:
A semiconductor package has a semiconductor chip on a wiring board, sealed with a sealant. A semiconductor package substrate is formed with V grooves along division lines from a resin layer side by use of a V blade. The wiring board is divided along the V grooves into individual semiconductor packages, while forming an inclined surface and a vertical surface at each package side surface. A shield layer is formed on the package upper surface and the package side surfaces. In this instance, the aspect ratio at the vertical surface side of the package interval is controlled, whereby an appropriate shield layer is formed on the package upper surface and the package inclined surfaces, thereby securing a shielding effect, and the shield layer is formed in a thin form on the package vertical surfaces and on the groove bottom between the packages, thereby restraining generation of burs.

Claim (Index 2):
A method of manufacturing a semiconductor package, the semiconductor package obtained by dividing a semiconductor package substrate having a plurality of semiconductor chips which are mounted in a plurality of regions on a wiring board partitioned by a plurality of intersecting division lines and which are sealed with a sealant, the semiconductor package substrate being divided along the division lines, the method comprising:\n a dividing step of dividing the semiconductor package substrate along the division lines, and forming each side surface of each semiconductor package with an inclination or step such that outer shape size of the semiconductor package becomes larger than that at an upper surface of the sealant of the semiconductor package on route from the: upper surface toward a lower surface of the sealant; a semiconductor package aligning step of aligning the divided individual semiconductor packages in such a manner that the adjacent semiconductor packages are spaced by a predetermined interval X mm from each other, and holding a wiring board side of the aligned semiconductor packages on a holding jig or adhering the wiring board side onto a support member; a shield layer forming step of forming a shield layer on side surfaces of the semiconductor packages and an upper surface of the sealant from a conductive material supplied from above the sealant; and a picking-up step of picking up the semiconductor package formed with the shield layer, after the shield layer forming step is conducted, wherein where side surface length from a lower end of the inclination or step of the semiconductor package to the holding jig or the support member is Y mm, then the inclination or step, the side surface length Y mm, the predetermined interval X mm, and the shield layer forming conditions are so set as to obtain such an aspect ratio Y/X that at the time of formation of the shield layer, the shield layer is formed on the side surfaces but the amount of the shield layer formed on a bottom surface between the semiconductor packages is reduced.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 2.27143
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15845803', '15721118', '15879082', '15431171', '14482378']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.860570492398671
- 35 USC 102 Novelty (BERT): 0.4984773077186695
- Combined Prediction Score: 0.8243611739306709
- Mean Citation Score: 228.95612000000003
- Max Citation Score: 277.5685
- Similarity Product: 232.34758645251392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test