PATENT CLAIM ANALYSIS

Application Number: 15872124
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["375", "233000"]

Abstract:
A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Claim (Index 16):
A device configured to simultaneously generate a plurality of complementary sets of bias levels comprising:\n a first bias level generator, comprising:\n a receiver comprising a plurality of inputs each configured to receive a respective one of a reference signal, an adjustment signal, a first feedback signal, and a second feedback signal and a plurality of outputs configured to transmit a set of output signals based on the reference signal, the adjustment signal, the first feedback signal, and the second feedback signal; \n an amplifier comprising at least one input configured to receive the set of output signals from the receiver, wherein the operational amplifier is configured to generate the first feedback signal based on the set of output signals; and \n a current mirror configured to receive the first feedback signal and generate the second feedback signal, a first bias value, and a second bias value based on the first feedback signal, wherein the current mirror comprises a first output configured to transmit the first bias value; and \n a voltage divider coupled to the first output, wherein the voltage divider is configured to receive the first bias value and to interpolate a subset of bias levels between a first bias level and a second bias level to generate a plurality of bias levels, wherein the voltage divider comprises a second output configured to supply a selected bias level of the plurality of bias levels and transmit the selected bias level as a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 2.77083
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15872140', '15864972', '15716162', '15716132', '15841144']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.484271067970704
- 35 USC 102 Novelty (BERT): 0.5219708975163306
- Combined Prediction Score: 0.4880410509252667
- Mean Citation Score: 249.96935
- Max Citation Score: 344.20184
- Similarity Product: 302.3930053240872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test