PATENT CLAIM ANALYSIS

Application Number: 16032804
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["370", "351000"]

Abstract:
This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.

Claim (Index 7):
The method according to  claim 6  wherein the plurality of SR signals are generated by the SA-L pipeline.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 2.48529
- Patent Class: 370.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14493018', '13893796', '14265037', '14789401', '13219339']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5576226341364543
- 35 USC 102 Novelty (BERT): 0.522995607660886
- Combined Prediction Score: 0.5541599314888974
- Mean Citation Score: 244.619626
- Max Citation Score: 263.9142
- Similarity Product: 144.31332290461063

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test