PATENT CLAIM ANALYSIS

Application Number: 16167903
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "231000"]

Abstract:
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Claim (Index 14):
The integrated circuit of  claim 13 , further comprising:\n a second PMOS transistor having a second PMOS gate and a second PMOS active area, wherein the first PMOS active area has a width that is smaller than the second PMOS active area and the first PMOS gate has a long side dimension less than a long side dimension of the second PMOS gate; and a gate extension with a gap between a first edge of the gate extension and the first PMOS gate and a second opposite edge aligned with an edge of the second PMOS gate.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 1.66667
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14576659', '15409842', '14584348', '11849798', '13288664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8629319423884702
- 35 USC 102 Novelty (BERT): 0.52190217587575
- Combined Prediction Score: 0.8288289657371982
- Mean Citation Score: 255.28350200000008
- Max Citation Score: 318.36716
- Similarity Product: 201.1656806117821

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test