PATENT CLAIM ANALYSIS

Application Number: 15933291
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["365", "189050"]

Abstract:
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Claim (Index 2):
The device of  claim 1 , wherein the first data path comprises two latches and the second data path comprises three latches.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.30769
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15377981', '15159452', '14203416', '15182117', '15182109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8202799846856633
- 35 USC 102 Novelty (BERT): 0.5704785810806445
- Combined Prediction Score: 0.7952998443251614
- Mean Citation Score: 374.1944
- Max Citation Score: 488.11862
- Similarity Product: 372.7968801218283

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test