PATENT CLAIM ANALYSIS

Application Number: 15859931
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["708", "522000"]

Abstract:
An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X≤J and F<Y≤K. In response to the MAP instruction, the instruction decoder is configured to control the processing circuitry to perform a rearrangement operation to rearrange the portions of at least one of the first operand and the second operand to form transformed first and second operands so that the E×F products that are required to be summed are aligned with a number of columns of adders within the adder array. Further, the adder array is controlled in dependence on the transformed first and second operands to add the required E×F products using the number of columns of adders within the adder array. Further, the rearrangement performed by the rearrangement operation is controlled in dependence on the parameter such that at least one column of adders used when the parameter indicates the first number of MAP operations is reused when the parameter indicates a second number of MAP operations different to the first number. This provides a particularly area and power efficient implementation for handling MAP operations.

Claim (Index 10):
An apparatus as claimed in  claim 1 , wherein when a plurality of multiply-and-accumulate-products operations are determined from the parameter, the instruction decoder is responsive to a restriction parameter to selectively disable performance of a subset of the plurality of multiply-and-accumulate-products operations by the processing circuitry.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 86.0
- Lexical Diversity: 2.61475
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15494946', '15494911', '14748817', '15224176', '13936576']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5078384367414407
- 35 USC 102 Novelty (BERT): 0.5782751236291203
- Combined Prediction Score: 0.5148821054302086
- Mean Citation Score: 355.915768
- Max Citation Score: 513.22687
- Similarity Product: 356.5274505799222

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test