PATENT CLAIM ANALYSIS

Application Number: 16250343
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-10
Patent Classification: ["711", "100000"]

Abstract:
A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Claim (Index 20):
A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which are partitioned into a plurality of partitions including a first partition and a second partition, and a second memory module used as a cache, the memory controlling device comprising:\n a memory controller that accesses the first memory module and the second memory module; a lookup logic that includes a plurality of ways and manages tag information of a plurality of cache lines of the second memory module, each way including a plurality of sets which correspond to the plurality of cache indices, respectively, and the plurality of cache indices corresponding to the plurality of cache lines, respectively; and a cache controller that splits an address of a request into at least a target cache index and a target tag, and determines whether the request is a cache hit or a cache miss by referring to the lookup logic based on the target cache index and the target tag, wherein in a case where the request is the cache miss, the cache controller:\n when the request is a read request, a write to the first partition is in progress, and the read request targets to the second partition, instructs the memory controller to read target data of the read request from the first memory module; and \n when the request is a write request and no empty cache line exists in the second memory module, detects a target way among the plurality of ways in a target set corresponding to the target cache index among the plurality of sets in one clock cycle, selects a cache line of the target way in the target set as a victim cache line, and instructs the memory controller to write victim data of the victim cache line to the first memory module and to write target data of the write request to the victim cache line.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 99.0
- Lexical Diversity: 2.2
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12035398', '13629172', '15398775', '14253785', '12901452']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.52766411708505
- 35 USC 102 Novelty (BERT): 0.4987649094479425
- Combined Prediction Score: 0.5247741963213393
- Mean Citation Score: 237.64096
- Max Citation Score: 244.80775
- Similarity Product: 170.6172775171548

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test