PATENT CLAIM ANALYSIS

Application Number: 16046730
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.

Claim (Index 4):
The 3D NAND memory cell of  claim 1 , wherein the plurality of vertical dielectric layers comprise a tunneling layer, a charge-trapping layer, and a blocking layer.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 95.0
- Lexical Diversity: 1.77143
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15934730', '15056510', '15250185', '15215080', '15008744']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.937517865327662
- 35 USC 102 Novelty (BERT): 0.5076037507832923
- Combined Prediction Score: 0.8945264538732249
- Mean Citation Score: 288.9059220000001
- Max Citation Score: 297.85376
- Similarity Product: 258.8698437657165

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test