PATENT CLAIM ANALYSIS

Application Number: 15888071
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "347000"]

Abstract:
A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.

Claim (Index 24):
A method of fabricating a metal-oxide-silicon (MOS) transistor exhibiting enhanced mobility of channel electrons, the method including:\n forming a channel region between a source region and a drain region in a semiconductor substrate such that first and second contact regions of said source region and said drain region are respectively disposed adjacent to the upper surface of the semiconductor substrate; forming first and second nickel monosilicide (NiSi) structures on said source region and said drain region, respectively, such that said first and second NiSi structures are exposed on said upper surface of the semiconductor substrate; and forming a stressing stack across the source region and the drain region such that said stressing stack generates a tensile stress in said channel region, wherein forming said stressing stack consists essentially of:\n forming a first dielectric layer having a first hydrogen content over the upper surface of the semiconductor substrate such that respective portions of said first dielectric layer contact said first and second NiSi structures, and such that said first dielectric layer includes a first residual stress that applies a first tensile stress component on said channel region; \n performing a plasma treatment of said first dielectric layer in a nitrogen atmosphere before forming said second dielectric layer; and \n forming a second dielectric layer having a second hydrogen content on an upper surface of the first dielectric layer such that said second dielectric layer includes a second residual stress that applies a second tensile stress component on said channel region, \n wherein said first hydrogen content of said first dielectric layer is at least 10 percent lower than said second hydrogen content of said second dielectric layer, and wherein said first residual stress of said first dielectric layer is lower than said second residual stress of said second dielectric layer such that said first tensile stress component is at least 20 percent lower than said second tensile stress component.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 88.0
- Lexical Diversity: 1.975
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13520618', '10849689', '10799788', '13034902', '11119522']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.925272968595216
- 35 USC 102 Novelty (BERT): 0.483095995338254
- Combined Prediction Score: 0.8810552712695198
- Mean Citation Score: 218.3841
- Max Citation Score: 237.48834
- Similarity Product: 203.96093023655533

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test