PATENT CLAIM ANALYSIS

Application Number: 15927478
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["711", "106000"]

Abstract:
Various implementations described herein are directed to an integrated circuit having a cache with memory components that store data with multiple addresses. The integrated circuit may include a controller that communicates with the cache to provide directives to the cache. The integrated circuit may include a refresh circuit that interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing. The refresh circuit may further employ the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.

Claim (Index 15):
The integrated circuit of  claim 14 , wherein the commands or instructions comprise a cache invalidation command or instruction that is used as a memory unmap command or instruction that is related to a deallocation operation or a trim operation.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.09091
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['09641519', '11198709', '15636565', '10334374', '11198708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5123981246243857
- 35 USC 102 Novelty (BERT): 0.4604050133332689
- Combined Prediction Score: 0.5071988134952741
- Mean Citation Score: 120.065202
- Max Citation Score: 121.77955
- Similarity Product: 89.57758848188818

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test