PATENT CLAIM ANALYSIS

Application Number: 15965590
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-06
Patent Classification: ["257", "738000"]

Abstract:
A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

Claim (Index 16):
A semiconductor package comprising:\n a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a plurality of redistribution layers disposed on different levels in the insulating member in the stacking direction, each of the plurality of redistribution layers having a redistribution via, and the plurality of redistribution layers including at least a first redistribution layer adjacent to the first surface and a second redistribution layer adjacent to the second surface; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; a support member disposed on the first surface of the connection member and having a cavity in which the semiconductor chip is accommodated; an encapsulant disposed on the first surface of the connection member and encapsulating the support member and the semiconductor chip; a passivation layer disposed on the second surface of the connection member; underbump metallurgy (UBM) pads disposed on the passivation layer; and UBM vias connecting the second redistribution layer to the UBM pads through the passivation layer and having a non-circular cross section, wherein the redistribution via of the second redistribution layer is disposed to overlap the UBM pad and not to overlap the UBM via in the stacking direction.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.96078
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15913429', '15923308', '15802131', '15962867', '15946109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9322864340671656
- 35 USC 102 Novelty (BERT): 0.5343816638605714
- Combined Prediction Score: 0.8924959570465063
- Mean Citation Score: 355.34241000000014
- Max Citation Score: 374.25208
- Similarity Product: 317.0645910943889

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test