PATENT CLAIM ANALYSIS

Application Number: 15859895
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "659000"]

Abstract:
Provided is a semiconductor package having high electric reliability. The semiconductor package includes a lower sub-semiconductor package including a lower semiconductor chip and a lower mold layer on the lower semiconductor chip and having a mold via hole, an upper sub-semiconductor package including an upper semiconductor chip, a filling layer that is between the lower sub-semiconductor package and the upper sub-semiconductor package, a connection via in the mold via hole that penetrates the lower mold layer and the filling layer and electrically connects the lower sub-semiconductor package to the upper sub-semiconductor package. The filling layer includes an extending part of the filling layer that extends into the mold via hole of the filling layer from a portion having a higher level than a top surface of the lower mold layer.

Claim (Index 3):
The semiconductor package of  claim 2 , wherein the filling layer comprises a protruding part that protrudes farther than the side surface of the lower sub-semiconductor package and/or the side surface of the upper sub-semiconductor package in a same direction.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 2.89362
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14531994', '15392275', '13243704', '15806618', '14504972']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9148440930575372
- 35 USC 102 Novelty (BERT): 0.5096630546223504
- Combined Prediction Score: 0.8743259892140186
- Mean Citation Score: 242.16214200000005
- Max Citation Score: 245.61641
- Similarity Product: 168.9352279031676

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test