PATENT CLAIM ANALYSIS

Application Number: 15918659
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "355000"]

Abstract:
A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

Claim (Index 17):
The semiconductor integrated circuit device according to  claim 13 ,\n wherein the first diode is arranged between the logic block and the pad lead part, and wherein the second diode is arranged between the pad lead part and the first transistor.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.17143
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13910891', '14953319', '14461163', '13654415', '12635675']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91689368206661
- 35 USC 102 Novelty (BERT): 0.5655766474280861
- Combined Prediction Score: 0.8817619786027578
- Mean Citation Score: 301.23762
- Max Citation Score: 445.21854
- Similarity Product: 339.9057682855225

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test