PATENT CLAIM ANALYSIS

Application Number: 15933949
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "351000"]

Abstract:
Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.

Claim (Index 3):
The method of  claim 1 , further comprising the step of:\n forming shallow trench isolation (STI) regions in the substrate between the fins.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.17742
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14880659', '15640766', '15713975', '15783029', '15663133']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9301888875668904
- 35 USC 102 Novelty (BERT): 0.5237232228023972
- Combined Prediction Score: 0.889542321090441
- Mean Citation Score: 324.9786220000001
- Max Citation Score: 337.6734600000001
- Similarity Product: 226.323401995318

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test