PATENT CLAIM ANALYSIS

Application Number: 16140053
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-06
Patent Classification: ["365", "222000"]

Abstract:
A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.

Claim (Index 16):
A memory system comprising:\n at least one semiconductor memory device; and a memory controller configured to transmit one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to the at least one semiconductor memory device during a refresh period, wherein the at least one semiconductor memory device includes: a memory cell array including a plurality of bank arrays each including a plurality of memory cell rows each including a plurality of dynamic memory cells; and a refresh control circuit configured to perform a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, wherein, for each of the one or more command pairs, the memory controller is configured to sequentially transmit during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps, wherein when the memory controller transmits an all-bank self-refresh command with the self-refresh entry command to the semiconductor memory device, the refresh control circuit performs the refresh operation on all of the bank arrays, and wherein when the memory controller transmits a per-bank self-refresh command with the self-refresh entry command to the semiconductor memory device in the self-refresh mode, the refresh control circuit performs the refresh operation on each of the bank arrays.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.85185
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14793749', '15065211', '15194784', '14858140', '13720998']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8304976049579703
- 35 USC 102 Novelty (BERT): 0.5308946983803601
- Combined Prediction Score: 0.8005373143002092
- Mean Citation Score: 346.570112
- Max Citation Score: 392.89798
- Similarity Product: 295.6456824576545

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test