PATENT CLAIM ANALYSIS

Application Number: 16353711
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["341", "142000"]

Abstract:
In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

Claim (Index 14):
An analog-to-digital converter, comprising:\n a quantizer, comprising:\n a main comparator set comprising:\n a first comparator having a first input coupled to receive an error signal, a second input coupled to receive a first reference signal, and an output coupled to output a first bit of a first digitized error signal; and \n a second comparator having a first input coupled to receive the error signal, a second input coupled to receive a second reference signal, and an output coupled to output a second bit of the first digitized error signal; and \n \n an auxiliary comparator set comprising:\n a third comparator having a first input coupled to receive the error signal, a second input coupled to receive a third reference signal, and an output coupled to output a first bit of a second digitized error signal; and \n a fourth comparator having a first input coupled to receive the error signal, a second input coupled to receive a fourth reference signal, and an output coupled to output a second bit of the second digitized error signal; \n \n a main digital-to-analog converter (DAC) coupled to the quantizer, the main DAC configured to receive the first digitized error signal, and an auxiliary DAC coupled to the quantizer, the auxiliary DAC configured to receive the second digitized error signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.19643
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15628462', '12568811', '13562729', '15935045', '13600559']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5377397133734487
- 35 USC 102 Novelty (BERT): 0.5314123898773303
- Combined Prediction Score: 0.5371069810238369
- Mean Citation Score: 241.66738
- Max Citation Score: 331.5819
- Similarity Product: 277.0101155065298

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test