PATENT CLAIM ANALYSIS

Application Number: 16127894
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["365", "156000"]

Abstract:
A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.

Claim (Index 6):
A memory circuit comprising:\n a first inverter circuit including a first input terminal, a first output terminal, a first p-channel MOS transistor in which a source terminal is connected to a first power supply line and a gate terminal is connected to the first input terminal, and a first n-channel MOS transistor in which a source terminal is connected to a second power supply line, a drain terminal is connected to a drain terminal of the first p-channel MOS transistor, and a gate terminal is connected to the first input terminal; a second inverter circuit including a second input terminal connected to the first output terminal, a second output terminal connected to the first input terminal, a second p-channel MOS transistor in which a source terminal is connected to the first power supply line and a gate terminal is connected to the second input terminal, and a second n-channel MOS transistor in which a source terminal is connected to the second power supply line, a drain terminal is connected to a drain terminal of the second p-channel MOS transistor, and a gate terminal is connected to the second input terminal; a first capacitor having a first terminal and a second terminal, the first terminal being connected to the first output terminal and the second input terminal, and the second terminal being connected to a first wiring line; a third n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the first terminal of the first capacitor, the other of the source terminal and the drain terminal is connected to a second wiring line, and a gate terminal is connected to a third wiring line; a second capacitor having a third terminal and a fourth terminal, the third terminal being connected to the second output terminal and the first input terminal, and the fourth terminal being connected to the first wiring line; and a fourth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the third terminal of the second capacitor, the other of the source terminal and the drain terminal is connected to a fourth wiring line, and a gate terminal is connected to the third wiring line.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 3.30233
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13360904', '12889881', '13774668', '15478237', '14932254']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8097285446457718
- 35 USC 102 Novelty (BERT): 0.4824522856832539
- Combined Prediction Score: 0.77700091874952
- Mean Citation Score: 252.638442
- Max Citation Score: 259.87628
- Similarity Product: 219.9788683903217

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test