PATENT CLAIM ANALYSIS

Application Number: 16010536
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["716", "103000"]

Abstract:
An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

Claim (Index 8):
The method according to  claim 6 , wherein identifying the flip-flop comprises sequentially traversing the original RTL model.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 2.37313
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15387958', '14675307', '14675356', '15822241', '14634446']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3753413375359544
- 35 USC 102 Novelty (BERT): 0.5070609844627109
- Combined Prediction Score: 0.3885133022286301
- Mean Citation Score: 242.174262
- Max Citation Score: 298.1948
- Similarity Product: 165.6488201417446

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test