PATENT CLAIM ANALYSIS

Application Number: 15988453
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["257", "076000"]

Abstract:
Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

Claim (Index 11):
A semiconductor device structure comprising a lateral GaN (gallium nitride) power transistor comprising:\n a substrate comprising a device area of the transistor; a nitride semiconductor layer formed on the device area of the substrate, the nitride semiconductor layer comprising a GaN heterostructure defining active regions for a plurality of transistor sections of a multi-section transistor; a first level of on-chip metallization (M1), M1 being patterned to define source, drain and gate finger electrodes of each transistor section and a gate bus; for each section, the gate bus comprising a first portion formed on an inactive region along a first edge of the active region, and second portions of the gate bus extending from the first portion of the gate bus and formed on inactive regions between active regions of each section; in each section, the source and drain finger electrodes being arranged as an array with the gate finger electrodes running in channel regions between adjacent source and drain finger electrodes, and the gate finger electrodes being interconnected to adjacent second portions of the gate bus; an overlying second level of on-chip metallization (M2), M2 being patterned to define for each section a contact structure comprising a drain pad and first and second source contact areas, in each section the drain pad extending over a central part of the active region, and the first and second source contact areas being located each side of the drain pad; an intermetal dielectric layer provided between the first and second level metallization layers M1 and M2; the drain pad being interconnected by conductive micro-vias through the intermetal dielectric layer to underlying drain finger electrodes; and the first and second source contact areas being interconnected to the source finger electrodes.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 1.83908
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15704458', '15078023', '15027012', '14568507', '15032824']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9137441423716696
- 35 USC 102 Novelty (BERT): 0.535804647397411
- Combined Prediction Score: 0.8759501928742438
- Mean Citation Score: 304.91698800000006
- Max Citation Score: 361.3031
- Similarity Product: 283.4305892924845

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test