PATENT CLAIM ANALYSIS

Application Number: 16103475
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-04
Patent Classification: ["323", "312000"]

Abstract:
A sense resistor is placed in series with an output capacitor of a buck converter. The buck converter operates in a discontinuous mode such that there is a dead time in each switching cycle. A control circuit senses a voltage across the sense resistor and thereby generates a first signal I CS . The control circuit detects an offset voltage in I CS , where the offset voltage is the voltage of I CS  during the dead time in a first switching cycle. The control circuit level shifts the entire I CS  by the offset voltage, thereby generating a second signal I CLS . I CLS  has the same waveform as the waveform of the inductor current. In a second cycle, I CLS  is used to determine when to turn off the main switch and when the start of the dead time occurs. I CLS  and the offset voltage are used together to determine when to turn the main switch on.

Claim (Index 20):
The power converter circuit of  claim 16 , wherein the integrated circuit comprises no digital processor that fetches and executes any processor-executable instructions from any memory.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 96.0
- Lexical Diversity: 2.31507
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15693494', '14474132', '14607684', '13444308', '13332343']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7525168744004452
- 35 USC 102 Novelty (BERT): 0.522883365851245
- Combined Prediction Score: 0.7295535235455253
- Mean Citation Score: 254.621162
- Max Citation Score: 355.0163
- Similarity Product: 333.7970223091364

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test