PATENT CLAIM ANALYSIS

Application Number: 16015789
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["708", "523000"]

Abstract:
An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

Claim (Index 3):
The arithmetic processing device according to  claim 1 , wherein a number of arithmetic circuits corresponds to a number of columns of the third data.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 3.46667
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15782881', '15651651', '15618444', '15710433', '15090722']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4727866748715699
- 35 USC 102 Novelty (BERT): 0.5308527087317645
- Combined Prediction Score: 0.4785932782575893
- Mean Citation Score: 258.08194
- Max Citation Score: 338.82944
- Similarity Product: 247.1368951575852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test