PATENT CLAIM ANALYSIS

Application Number: 15966664
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "401000"]

Abstract:
A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a first fill pinch off between the fin structures separated by a first pitch; and forming a material stack of a silicon containing layer, and a dielectric layer over the plurality of fin structures, wherein the dielectric provides a second fill pinch off between fin structures separated by a second pitch. The silicon containing layer is converted into an oxide material layer. The second dielectric that provides the second fill pinch off is removed, and an opening is etched in a remaining silicon containing layer exposed by removing the second fill pinch off. An underlying gate cut region is etched in the gate structure using the opening in the remaining portion of the silicon containing layer.

Claim (Index 1):
A method of forming a semiconductor device comprising:\n providing at least two regions of fin structures, wherein the fin structures within each of the at least two regions has a first pitch of separation and a second pitch of separation is present between adjacent regions; forming a gate structure over the fin structures extending across the at least two regions, wherein the gate structure provides a first fill pinch off between the fin structures separated by the first pitch; forming a material stack of a first dielectric layer, a semiconductor containing layer, and a second dielectric layer; removing the second dielectric layer that provides the second fill pinch off; etching an opening in the semiconductor containing layer exposed by removing the second fill pinch off; etching an exposed portion of the first dielectric layer using the opening in the remaining portion of the semiconductor containing layer as a second etch mask; and etching the gate cut region of the gate structure using the etched first dielectric layer as a gate cut region etch mask.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 91.0
- Lexical Diversity: 2.66071
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15295277', '15966637', '15241898', '15634307', '15345595']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9319952722855356
- 35 USC 102 Novelty (BERT): 0.5587776143309867
- Combined Prediction Score: 0.8946735064900808
- Mean Citation Score: 328.613002
- Max Citation Score: 428.99582
- Similarity Product: 405.0486646845436

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test