PATENT CLAIM ANALYSIS

Application Number: 15778156
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["716", "110000"]

Abstract:
Disclosed is a method for performing netlist comparison based on a pin connection relationship of a component, comprising the steps: acquiring a schematic diagram netlist file generated by a schematic diagram, and acquiring a PCB netlist file generated by a PCB; reading a network in the schematic diagram netlist file, forming a netlist connection relationship corresponding to each network into a schematic diagram array, all schematic diagram arrays forming a schematic diagram array set; reading a network in the PCB netlist file, forming a netlist connection relationship corresponding to each network into a PCB array, all PCB arrays forming a PCB array set; and comparing the schematic diagram array set with the PCB array set, and outputting differences between the two array sets. The present disclosure merely compares the connection relationship of components. With regard to the condition where a pin connection relationship of an element does not change but a network name changes, occurring during the conversion of different pieces of EDA software, and the present disclosure can effectively guarantee the accuracy of a connection after a schematic diagram and a PCB network are converted. The present disclosure can be widely applied to netlist comparison systems of pin connection relationships of various EDA software components.

Claim (Index 4):
The method of  claim 3 , wherein the step S 331  further comprises:\n S 3311 , reading the schematic diagram arrays in the schematic diagram array subset one by one; \n S 3312 , determining whether all the schematic diagram arrays in the schematic array subset have been read; if yes, then the method will end; otherwise, the method proceeds to S 3313 ; \n S 3313 , comparing an i-th schematic diagram array in the schematic diagram array subset with a k-th PCB array in the PCB array subset, and determining whether there is an intersection of the pins of the components; if there is an intersection, writing the non-intersecting component pins into the result file and clearing two arrays with intersections, and then the method proceeds to step S 3314 ; otherwise the method proceeds to S 3315 ; \n S 3314 , letting i=i+1, and returning to step S 3312 ; and \n S 3315 , determining whether all the PCB arrays have been read; if yes, then writing the component pins with no intersection into the result file, letting i=i+1, and returning to step S 3312 .

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.56322
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10064035', '12650346', '14482296', '10975151', '14829550']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3046046383149767
- 35 USC 102 Novelty (BERT): 0.4900982642177002
- Combined Prediction Score: 0.3231540009052491
- Mean Citation Score: 166.428186
- Max Citation Score: 184.73268
- Similarity Product: 110.10452299997806

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test