PATENT CLAIM ANALYSIS

Application Number: 15962867
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-06
Patent Classification: ["257", "668000"]

Abstract:
A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.

Claim (Index 18):
A semiconductor package comprising:\n a first connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package, including an insulating member and a first redistribution layer embedded in the insulating member, and having holes formed in the second surface to be connected to portions of the first redistribution layer; a semiconductor chip having an active surface having connection electrodes disposed thereon, and an inactive surface opposing the active surface in the stacking direction and disposed on the first connection member, the inactive surface facing the second surface of the first connection member; an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip; and a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer through the holes of the first connection member, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias, wherein an area of a surface of at least one of the through-vias adjacent to the first redistribution layer is smaller than an area of a surface of the at least one of the through-vias adjacent to the wiring pattern.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 3.28889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15946109', '15958699', '15962577', '15941334', '15413713']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9400979784508092
- 35 USC 102 Novelty (BERT): 0.529411162403095
- Combined Prediction Score: 0.8990292968460377
- Mean Citation Score: 360.775098
- Max Citation Score: 365.86963
- Similarity Product: 313.25362264607725

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test