PATENT CLAIM ANALYSIS

Application Number: 15947222
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["341", "154000"]

Abstract:
Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.

Claim (Index 14):
The DAC circuit of  claim 13 , wherein a second portion of the first termination impedance path is coupled in shunt with a second portion of the second termination impedance path.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 2.26154
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15586848', '13791536', '14214341', '10641658', '15668088']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.622661046127601
- 35 USC 102 Novelty (BERT): 0.5004423418536068
- Combined Prediction Score: 0.6104391757002016
- Mean Citation Score: 232.25793400000003
- Max Citation Score: 243.58247000000003
- Similarity Product: 186.0003270638573

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test