PATENT CLAIM ANALYSIS

Application Number: 16105142
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["341", "110000"]

Abstract:
This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.

Claim (Index 9):
A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising:\n an operational amplifier a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; and a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; wherein the DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 96.0
- Lexical Diversity: 2.26667
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15005392', '14371786', '15237767', '14158299', '11879675']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6219285230271339
- 35 USC 102 Novelty (BERT): 0.5042567113578619
- Combined Prediction Score: 0.6101613418602068
- Mean Citation Score: 262.00874200000004
- Max Citation Score: 281.5637
- Similarity Product: 236.81988201456664

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test