PATENT CLAIM ANALYSIS

Application Number: 15994075
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["323", "313000"]

Abstract:
There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.

Claim (Index 4):
The reference voltage circuit according to  claim 1 , wherein the depletion type transistor and the enhancement type transistor are connected through a current mirror circuit.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 93.0
- Lexical Diversity: 1.74468
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13196983', '11724940', '13416619', '14183897', '12813004']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7368456362425891
- 35 USC 102 Novelty (BERT): 0.4610623954367411
- Combined Prediction Score: 0.7092673121620043
- Mean Citation Score: 159.632276
- Max Citation Score: 164.78038
- Similarity Product: 130.0365939609575

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test