PATENT CLAIM ANALYSIS

Application Number: 15901432
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["711", "206000"]

Abstract:
Memory systems that can predict a physical address associated with a logical address, and methods for use therewith, are described herein. In one aspect, the memory system predicts a physical address for a logical address that follows a sequence of random logical addresses. The predicted physical address could be a physical location where the data for the logical address is predicted to be stored. In some cases, the host data can be returned without accessing a management table. The predicted physical address is not required to be the location of the data to be returned to the host for the logical address. In one aspect, the memory system predicts a physical address at which information is stored that may be used to ultimately provide the data for the logical address, such as a location in the management table.

Claim (Index 7):
The apparatus of  claim 6 , wherein the one or more control circuits are further configured to:\n read at the first physical address and the at least one selected additional physical address in parallel.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 88.0
- Lexical Diversity: 2.38095
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15636496', '15853868', '13896328', '13867770', '15183813']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5535086985959009
- 35 USC 102 Novelty (BERT): 0.5065580481623951
- Combined Prediction Score: 0.5488136335525503
- Mean Citation Score: 223.212566
- Max Citation Score: 232.15106
- Similarity Product: 139.5039570659852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test