PATENT CLAIM ANALYSIS

Application Number: 16041460
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "043000"]

Abstract:
According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Claim (Index 1):
A semiconductor memory comprising:\n a bit line; a source line; a member extending in a first direction from the bit line to the source line and including an oxide semiconductor layer, a first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction electrically disconnected from the bit line, the oxide semiconductor layer including a first portion, second portion, and third portion arranged in order from the second end to the first end; first, second and third conductive layers disposed along the first direction, the first conductive layer facing the first portion and including a first material, the second conductive layer facing the second portion and including a second material different from the first material, and the third conductive layer facing the third portion including the second material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the first portion; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 95.0
- Lexical Diversity: 2.95833
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15704643', '16041577', '15705457', '13752726', '15253244']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.895838454232322
- 35 USC 102 Novelty (BERT): 0.5055235994166022
- Combined Prediction Score: 0.85680696875075
- Mean Citation Score: 208.05105
- Max Citation Score: 288.4918
- Similarity Product: 260.57001539460424

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test