PATENT CLAIM ANALYSIS

Application Number: 15987089
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "316000"]

Abstract:
In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

Claim (Index 16):
The semiconductor device of  claim 15 , further comprising a residual polysilicon layer disposed over the isolation insulating layer at the transition area.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.86792
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15267954', '15725000', '12020744', '11045850', '11848382']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8923565022004043
- 35 USC 102 Novelty (BERT): 0.5078055953637518
- Combined Prediction Score: 0.853901411516739
- Mean Citation Score: 186.028024
- Max Citation Score: 248.32974
- Similarity Product: 174.3700227424621

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test