PATENT CLAIM ANALYSIS

Application Number: 16041455
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "130000"]

Abstract:
Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.

Claim (Index 13):
An electronic memory device, comprising:\n a first array of memory cells configured in a cross point architecture, the first array spanning a plurality of sections, the first array of memory cells coupled with a corresponding first plurality of first access lines oriented in a first direction and with a corresponding second plurality of second access lines oriented in a second direction that is different than the first direction; a second array of memory cells configured in the cross point architecture, the second array spanning the plurality of sections, wherein the first array overlies the second array, the second array of memory cells coupled with a corresponding third plurality of third access lines oriented in the first direction and with a corresponding fourth plurality of fourth access line oriented in the second direction; a first plurality of plate lines oriented in the first direction, each plate line of the first plurality of plate lines coupled with a corresponding plurality of memory cells of the first array within a first respective section of the plurality of sections; a second plurality of plate lines oriented in the first direction, each plate line of the second plurality of plate lines coupled with a corresponding plurality of memory cells of the second array within a second respective section of the plurality of sections; and a third plate line oriented in the first direction and spanning two or more sections of the plurality of sections, the third plate line coupled with one or more plate lines of the first plurality of plate lines.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.84706
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15469865', '15434395', '15434401', '15969302', '15690895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8073073490230865
- 35 USC 102 Novelty (BERT): 0.5308170185596903
- Combined Prediction Score: 0.779658315976747
- Mean Citation Score: 257.87404000000004
- Max Citation Score: 379.70767
- Similarity Product: 303.4810409295511

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test