PATENT CLAIM ANALYSIS

Application Number: 16418502
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["711", "154000"]

Abstract:
A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Claim (Index 5):
The stacked memory device of  claim 1 , wherein the local sub process corresponds to data decoding to decompress compressed data and the global sub process corresponds to data combining to generate frame data by combining a plurality of decompressed data portions.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.66667
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15617450', '16038269', '14803119', '16185453', '15450588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5119782621258026
- 35 USC 102 Novelty (BERT): 0.553717014321322
- Combined Prediction Score: 0.5161521373453545
- Mean Citation Score: 269.699244
- Max Citation Score: 417.0998
- Similarity Product: 304.3597995827437

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test