PATENT CLAIM ANALYSIS

Application Number: 15942837
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["365", "185210"]

Abstract:
A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.

Claim (Index 1):
A sensing circuit connected with a non-volatile memory, the sensing circuit comprising:\n a sensing stage comprising a voltage clamp, a first P-type transistor and a first N-type transistor, wherein an input terminal of the voltage clamp receives a first power supply voltage, an output terminal of the voltage clamp generates a second power supply voltage, a source terminal of the first P-type transistor receives the second power supply voltage, a gate terminal of the first P-type transistor receives a cell current from a selected circuit of the non-volatile memory, a drain terminal of the first N-type transistor is connected with a drain terminal of the first P-type transistor, a gate terminal of the first N-type transistor receives a first bias voltage, and a source terminal of the first N-type transistor receives a ground voltage; a reference current generator comprising a second N-type transistor, wherein a drain terminal of the second N-type transistor is connected with the gate terminal of the first P-type transistor, a gate terminal of the second N-type transistor receives a reference voltage, and a source terminal of the second N-type transistor receives the ground voltage; an inverter, wherein an input terminal of the inverter is connected with the drain terminal of the first P-type transistor; and a latch having an input terminal connected with an output terminal of the inverter, wherein in a sensing period, the latch generates a data signal to indicate a storage state of the selected cell, wherein in the sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 91.0
- Lexical Diversity: 3.22727
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13909187', '14487578', '10665019', '12817175', '11401933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8194204529766647
- 35 USC 102 Novelty (BERT): 0.4876156413217342
- Combined Prediction Score: 0.7862399718111717
- Mean Citation Score: 247.131172
- Max Citation Score: 275.72736000000003
- Similarity Product: 238.2959751196289

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test