PATENT CLAIM ANALYSIS

Application Number: 16049013
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "328000"]

Abstract:
In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

Claim (Index 8):
The semiconductor device of  claim 7 , wherein each of the underlying layers have a substantially uniform thickness above the fin structure.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 2.85106
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15481672', '16036888', '14749602', '15707682', '15428798']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9299483074150072
- 35 USC 102 Novelty (BERT): 0.5236313611808756
- Combined Prediction Score: 0.889316612791594
- Mean Citation Score: 271.55676200000005
- Max Citation Score: 330.09128
- Similarity Product: 236.0440213542509

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test