PATENT CLAIM ANALYSIS

Application Number: 16085423
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["327", "566000"]

Abstract:
A battery management chip circuit on the basis of an SOI process. The battery management chip circuit comprises a high-voltage multiplexer MUX, a voltage reference circuit, a Sigma-delta ADC (comprising an analog modulator and a digital filter), an SPI communication circuit, a function control circuit and a voltage value register. The battery management chip circuit is integrated on the basis of an SOI high-voltage process, and particularly, high-voltage MOS transistors adopted by the battery management chip circuit are high-voltage MOS device units on the basis of the SOI process. In addition, the present invention highlights the design of interface circuit-chopper circuit of the high-voltage multiplexer MUX and the Sigma-delta ADC, so as to describe the advantages such as decrease of difficulty of circuit design and reduction of layout area brought about when the present invention adopts the SOI process design and tape-out.

Claim (Index 9):
The battery management chip circuit on the basis of the SOI process according to any one of  claim 1 , characterized in that the battery management chip circuit comprises an interface circuit of an analog modulator input, the interface circuit comprises: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first diode, a second diode, a first capacitor and a second capacitor integrated on the basis of the SOI process, wherein source ends of the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are connected with positive electrodes of the first diode and the second diode and are connected with an input voltage, a gate electrode of the first MOS transistor, a gate electrode of the fourth MOS transistor and a drain electrode of the third MOS transistor are connected with a negative electrode of the first diode and a negative electrode of the first capacitor, and gate electrodes of the second MOS transistor and the third MOS transistor and a drain electrode of the fourth MOS transistor are connected with a negative electrode of the second diode and a negative electrode of the second capacitor, and positive electrodes of the first capacitor and the second capacitor are respectively connected with non-overlapping complementary clock signals; and drain electrodes of the first MOS transistor and the second MOS transistor are respectively used as output ends of the circuit.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 99.0
- Lexical Diversity: 2.16667
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11034938', '11866693', '09466934', '15408200', '11922197']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.792469633539076
- 35 USC 102 Novelty (BERT): 0.5002823365269257
- Combined Prediction Score: 0.763250903837861
- Mean Citation Score: 215.352828
- Max Citation Score: 222.82744
- Similarity Product: 138.02577660962106

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test