PATENT CLAIM ANALYSIS

Application Number: 16200630
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["708", "503000"]

Abstract:
A processor comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and at least one three-dimensional memory (3D-M) array. The 3D-M array stores at least a portion of a look-up table (LUT) for a non-arithmetic function, while the ALC performs arithmetic operations on the LUT data.

Claim (Index 9):
The processor according to  claim 1 , wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.46512
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15591205', '16186571', '16059023', '16121653', '15450017']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4758196836368998
- 35 USC 102 Novelty (BERT): 0.51757803862581
- Combined Prediction Score: 0.4799955191357908
- Mean Citation Score: 239.089374
- Max Citation Score: 298.51584
- Similarity Product: 225.6071717024231

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test