PATENT CLAIM ANALYSIS

Application Number: 15954665
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["714", "718000"]

Abstract:
A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode. Logic BIST circuits complete a test with the LBIST mode, at a stage where the second scan test has completed.

Claim (Index 7):
A semiconductor device which is configured with one semiconductor chip, comprising:\n a memory circuit unit which includes a memory circuit and an interface for test for the memory circuit; a logic circuit which includes a memory pre-stage logic circuit issuing an instruction for accessing to the memory circuit and a memory post-stage logic circuit to which read data from the memory circuit is input, and performs a predetermined logical operation; a memory BIST (Built In Self Test) circuit which tests the memory circuit; and a logic BIST circuit which tests the logic circuit and the memory BIST circuit, wherein the memory circuit includes:\n a first scan flip flop circuit for bypass which has a function for bypassing an input and/or an output of the memory circuit, and selectively latches an input signal for the memory circuit or a scan-in signal, and \n a path switch circuit which transmits an output signal of the first scan flip flop circuit for bypass to the memory BIST circuit and the memory post-stage logic circuit, when it is set to a first test mode, transmits an output signal of the first scan flip flop circuit for bypass to the memory post-stage logic circuit, when it is set to a second test mode, and transmits an output signal of the memory circuit to the memory BIST circuit.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.75
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11603085', '15220427', '11626574', '10086214', '14072295']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2814978867124321
- 35 USC 102 Novelty (BERT): 0.5095596270566802
- Combined Prediction Score: 0.304304060746857
- Mean Citation Score: 261.310006
- Max Citation Score: 279.22342000000003
- Similarity Product: 196.40905336491107

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test