PATENT CLAIM ANALYSIS

Application Number: 15912282
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185180"]

Abstract:
A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.

Claim (Index 18):
The method according to  claim 14 , wherein the power supply protection circuit further includes a first resistor electrically connected in series with the third transistor between the second pad and the first node.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 5.31034
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15700892', '15690257', '13553746', '11477741', '13610426']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8306398721199679
- 35 USC 102 Novelty (BERT): 0.4916406035974778
- Combined Prediction Score: 0.7967399452677189
- Mean Citation Score: 194.967956
- Max Citation Score: 263.97635
- Similarity Product: 204.916457616508

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test