PATENT CLAIM ANALYSIS

Application Number: 15918675
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["711", "158000"]

Abstract:
Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Claim (Index 21):
A system for managing priority to a memory subsystem, comprising:\n a first level memory access handling unit configured to generate memory access requests in accordance with corresponding instructions originating from multiple levels of a computing system architecture, the multiple levels comprising at least an application level, a network level, an operating system level, and a micro-architectural level, wherein the first level memory access handling unit is of a higher level of the computing system architecture relative to the memory subsystem, and the instructions generated by the multiple levels have associated priority indicators assigned in accordance with prioritization schemes respectively associated with the multiple levels, the priority indicators comprising first priority indicators assigned to a first subset of the instructions originating at the application level based on user-defined application priorities, second priority indicators assigned to a second subset of the instructions originating at the network level based on a determination of whether the instructions originate from the network level or an internal level, and third priority indicators assigned to a third subset of the instructions originating at the operating system level based on a determination of whether the third subset of the instructions are associated with an interrupt at the operating system level; and a memory controller unit of the memory subsystem configured to receive the memory access requests and the priority indicators, and to assign respective memory access priorities of the memory access requests based on the priority indicators.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 90.0
- Lexical Diversity: 1.85366
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14497619', '12886050', '14565255', '12317836', '13586708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4683953751177219
- 35 USC 102 Novelty (BERT): 0.5048748016376069
- Combined Prediction Score: 0.4720433177697105
- Mean Citation Score: 187.144694
- Max Citation Score: 311.73532
- Similarity Product: 307.4018516342688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test