PATENT CLAIM ANALYSIS

Application Number: 15742038
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["257", "043000"]

Abstract:
An etch stop layer (ESL) thin-film transistor (TFT) substrate includes an active layer including a channel zone and two opposite side zones that are made conducting through treatment with plasma doping so that a distance between the two side zones is a width of the channel zone that is smaller than a distance between a source electrode and a drain electrode in electrical connection with the two opposite side zones respectively, so as to make a relatively small actual channel length. Such a relatively small actual channel length provides the TFT with an excellent electrical conduction property and has an advantage of increasing a source-drain current.

Claim (Index 6):
An etch stop layer (ESL) thin-film transistor (TFT) substrate fabrication method, comprising the following steps:\n Step S 1 : providing a backing plate, forming a gate electrode on the backing plate through deposition and patterning, forming a gate insulation layer on the gate electrode and the backing plate through deposition and patterning, forming an active layer on the gate insulation layer through deposition and patterning at a location above and corresponding to the gate electrode; wherein the active layer is formed of a material that comprises a metal oxide semiconductor; Step S 2 : forming a protection layer on the active layer through patterning, wherein the protection layer corresponds to and covers a middle area of the active layer to expose two opposite side zones of the active layer, subjecting the two opposite side zones of the active layer that are exposed outside the protection layer to plasma doping treatment to increase electrical conductivity of the two side zones to respectively form a source contact zone and a drain contact zone, wherein the middle area of the active layer that is covered by the protection layer forms a channel zone, and removing the protection layer; and Step S 3 : forming an etch stop layer on the active layer and the gate insulation layer through deposition and patterning, such that the etch stop layer is provided with a first via and a second via formed therein and respectively corresponding to the source contact zone and the drain contact zone of the active layer, forming a source electrode and a drain electrode on the etch stop layer through deposition and patterning, wherein the source electrode and the drain electrode are respectively set in contact engagement with the source contact zone and the drain contact zone through the first via and the second via; wherein the channel zone has a width that is smaller than a distance between the source electrode and the drain electrode.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 1.68657
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14764169', '14759198', '15441245', '15441246', '14777744']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9227689149775874
- 35 USC 102 Novelty (BERT): 0.4904925528347943
- Combined Prediction Score: 0.8795412787633081
- Mean Citation Score: 252.276518
- Max Citation Score: 262.00964
- Similarity Product: 223.2470489222002

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test