PATENT CLAIM ANALYSIS

Application Number: 15904488
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["327", "310000"]

Abstract:
Embodiments of the present invention provide computer system for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Claim (Index 2):
A method for balancing out voltages, comprises:\n receiving a total voltage from a voltage supply pin; dividing the total voltage into two different voltages, wherein:\n a first voltage is greater than half of the total voltage, and \n a second voltage is less than or equal to half of the total voltage; \n sending the first voltage to a group of inverters of a first layer and an n-type channel field effect transistor (NFET) of the first layer, wherein the group of inventors of the first layer consists of: a first inverter, a second inverter, and a third inverter; sending the second voltage to a decoupling resistor, and a group of inventors of a second layer, and an NFET of the second layer, wherein the group of inventors of the second layer consists of: a first inverter, a second inverter, and a third inverter; responsive to sending the first voltage and the second voltage, powering the first inverter, the second inverter, and the third inverter of the second layer through the decoupling resistor during a typical operation of a circuit; monitoring for an electric static discharge (ESD) event; responsive to detecting an ESD event powering the first inverter, the second inverter, and the third inverter of the second layer through a first p-type channel field effect transistor (PFET) during the ESD event; generating a third voltage at a midpoint node, wherein the third voltage is half of the total voltage during the ESD event and wherein the midpoint node is a common region shared between the NFET of the first layer and the NFET of the second layer; powering the first inverter, the second inverter, and the third inverter of the second layer through the resistor during a typical operation of a circuit; and powering the first inverter, the second inverter, and the third inverter of the second layer through a first p-type channel field effect transistor (PFET) during an electric static discharge (ESD) event.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.46
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15713731', '15444519', '11865820', '11738336', '12127245']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7776037393071347
- 35 USC 102 Novelty (BERT): 0.4905810863248356
- Combined Prediction Score: 0.7489014740089048
- Mean Citation Score: 201.615942
- Max Citation Score: 269.95163
- Similarity Product: 251.36171639271743

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test