PATENT CLAIM ANALYSIS

Application Number: 15925200
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["714", "729000"]

Abstract:
Electronic scan circuitry includes a decompressor ( 510 ), a plurality of scan chains ( 520. i ) fed by the decompressor ( 510 ), a scan circuit ( 502, 504 ) coupled to the plurality of scan chains ( 520. i ) to scan them in and out, a masking circuit ( 590 ) fed by the scan chains ( 520. i ), and a scannable masking qualification circuit ( 550, 560, 580 ) coupled to the masking circuit ( 590 ), the masking qualification circuit ( 550, 560, 580 ) scannable by scan-in of bits by the decompressor ( 510 ) along with scan-in of the scan chains ( 520. i ), and the scannable masking qualification circuit ( 550, 560, 580 ) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit ( 590 ). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Claim (Index 1):
An electronic scan circuitry comprising:\n (a) decompressor circuitry having a serial data input line and parallel data output lines; (b) scan chains, each scan chain having a scan chain input coupled to one parallel data output line and having a scan chain output; (c) first masking circuitry having first masking inputs coupled to a first group of the scan chain outputs, the first masking circuitry including:\n (i) first gates, each first gate having a first input connected to a first masking input, a second input coupled to a first qualify line, a third input, and a first masking output; and \n (ii) first registers coupled in series, each first register having a serial input and an output connected to the third input of a first gate; \n (d) second masking circuitry having second masking inputs coupled to a second group of the scan chain outputs, the second masking circuitry including:\n (i) second gates, each second gate having a first input connected to a second masking input, a second input coupled to a second qualify line separate from the first qualify line, a third input, and a second masking output; and \n (ii) second registers coupled in series with the first registers, each second register having a serial input and an output connected to a third input of the second gates; and \n (e) compactor circuitry having parallel compactor inputs coupled to the first masking outputs and the second masking outputs, and having a serial compactor output.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 3.2037
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14944971', '12904303', '14487538', '14743720', '12938939']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3480516381708261
- 35 USC 102 Novelty (BERT): 0.621972341108179
- Combined Prediction Score: 0.3754437084645614
- Mean Citation Score: 476.75566
- Max Citation Score: 560.9474
- Similarity Product: 549.9131580287457

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test