PATENT CLAIM ANALYSIS

Application Number: 16118598
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["365", "185050"]

Abstract:
According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Claim (Index 17):
The device according to  claim 16 , wherein the plurality of coupling parts of the even-numbered steps are arranged to descend by two steps from one end of the coupling region toward a center along the first direction, and the plurality of coupling parts of the odd-numbered steps are arranged to descend by the two steps from another end of the coupling region toward the center along the first direction.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 2.95122
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15433451', '15951314', '15890894', '15457201', '15646780']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7747364793183567
- 35 USC 102 Novelty (BERT): 0.479201734947613
- Combined Prediction Score: 0.7451830048812823
- Mean Citation Score: 181.275662
- Max Citation Score: 185.3627
- Similarity Product: 137.77214384195207

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test