PATENT CLAIM ANALYSIS

Application Number: 15963440
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["385", "014000"]

Abstract:
An active optoelectronic optical engine layer is assembled on a SOI silicon substrate side, including multiple VCSEL input ports and multiple PD output ports. Each passive straight silicon waveguide terminated with two 45 degree reflectors is fabricated on the silicon-on-oxide surface of the SOI substrate to form an optical path to transmit optical signals from the VCSEL lasers to photodetectors. The active and passive sides are designed and developed as an on-chip optical interconnect module to carry high-speed electrical traces, Improved RF performance is achieved. A method of fabricating the device is disclosed as: on the substrate surface, patterning a plurality of conductive lines and the optical engine has an emitter (VCSEL) and a receiver (PD); on the SOI device layer, patterning a straight portion and two 45 degree end reflectors as the silicon waveguide and align the two 45 degree end reflectors with active optical devices VCSEL and PD.

Claim (Index 17):
A method of fabricating an optical interconnect apparatus, comprising:\n providing a silicon substrate having two substantially parallel first and second surfaces: depositing an insulating layer on the first surface; patterning a plurality of conductive lines on the insulating layer; growing bonding pillars or solder bumps and coating with Au/Ni for flip chip to mount active optical devices such as a vertical cavity surface emitting laser (VCSEL) and a photodetector (PD); turning the silicon substrate over to work on second surface; patterning a straight portion of the silicon waveguide on the second silicon surface; patterning two 45 degree end reflectors on the straight portion of the silicon waveguide, wherein the patterning comprises variable exposure intensity in lithography process, wherein the two 45 degree end reflectors are aligned with active optical devices VCSEL and PD; removing excess silicon outside the silicon waveguide to expose the oxide layer; and depositing a layer of oxide on the waveguide.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 1.92941
- Patent Class: 385.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15963665', '15963780', '15963815', '15963030', '15963014']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8331992902781737
- 35 USC 102 Novelty (BERT): 0.5363855027265139
- Combined Prediction Score: 0.8035179115230078
- Mean Citation Score: 324.317172
- Max Citation Score: 384.9688
- Similarity Product: 348.1544898720742

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test