PATENT CLAIM ANALYSIS

Application Number: 16204841
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-06
Patent Classification: ["327", "175000"]

Abstract:
Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

Claim (Index 6):
The semiconductor device of  claim 5 , wherein the clock distortion calibration circuitry is configured to convert the trim value into the one or more biasing voltages and/or biasing currents using biasing circuitry.

Metadata:
- Claim Count in Document: 71.0
- Percentile: 98.0
- Lexical Diversity: 2.59322
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15848796', '14155775', '13598513', '11443813', '16179349']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7775797310021347
- 35 USC 102 Novelty (BERT): 0.5329096652640267
- Combined Prediction Score: 0.7531127244283239
- Mean Citation Score: 229.572484
- Max Citation Score: 373.51465
- Similarity Product: 371.3361950941026

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test