PATENT CLAIM ANALYSIS

Application Number: 15944080
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["716", "053000"]

Abstract:
Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

Claim (Index 20):
A method, comprising:\n decomposing a layout of a semiconductor chip into a plurality of intended circuit layout patterns; determining, for the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources, wherein determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on at least two or more of: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern; applying a scoring formula based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns; ranking the plurality of intended circuit layout patterns based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both; and outputting at least a portion of ranking information to facilitate influence or control over a semiconductor fabrication process.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 91.0
- Lexical Diversity: 2.60811
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15709856', '15066280', '14991330', '12770903', '11202591']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3183173341473176
- 35 USC 102 Novelty (BERT): 0.4526670708050395
- Combined Prediction Score: 0.3317523078130898
- Mean Citation Score: 145.114134
- Max Citation Score: 175.98882
- Similarity Product: 135.88043846649884

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test