PATENT CLAIM ANALYSIS

Application Number: 16116816
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "197000"]

Abstract:
Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Claim (Index 2):
The semiconductor structure of  claim 1 , wherein the semiconductor substrate has a first conductivity type, and the one or more semiconductor regions have a second conductivity type, opposite the first conductivity type.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 96.0
- Lexical Diversity: 2.01515
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15658252', '15588011', '15727159', '14958873', '12002358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9363583657336304
- 35 USC 102 Novelty (BERT): 0.6001201688540383
- Combined Prediction Score: 0.9027345460456712
- Mean Citation Score: 356.195084
- Max Citation Score: 560.69165
- Similarity Product: 453.49441463090784

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test