PATENT CLAIM ANALYSIS

Application Number: 15991020
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["327", "156000"]

Abstract:
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Claim (Index 18):
A phase-locked loop circuit, comprising:\n a counter-based time-to-digital converter circuit to determine a count value corresponding to a time between corresponding edges of a reference clock and a feedback clock; an analog phase-locked loop to generate a second clock responsive to a count value from the counter-based time-to-digital converter; and a frequency divider to receive the second clock and to generate the feedback clock at a reduced frequency from a frequency of the second clock; wherein the counter-based time-to-digital converter circuit includes a plurality of flip-flops that are to be clocked using the second clock.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 93.0
- Lexical Diversity: 2.625
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15183752', '10839201', '15675160', '12018770', '13380392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7747006461023715
- 35 USC 102 Novelty (BERT): 0.4575538440906188
- Combined Prediction Score: 0.7429859659011964
- Mean Citation Score: 171.15700599999997
- Max Citation Score: 173.64496
- Similarity Product: 144.25037350971218

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test