PATENT CLAIM ANALYSIS

Application Number: 15935313
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["708", "204000"]

Abstract:
A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2 ew-1 −1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a first shifter operable to receive a first significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a first output, wherein min{(ew−1), bitwidth(iw−2−s y )}≤k≤(ew−1) where s y =1 for a signed floating point number and s y =0 for an unsigned floating point number; an inverting unit configured to invert the bit values of the exponent; a second shifter coupled to the inverting unit configured to receive a second significand input comprising a contiguous set of the most significant bits of the significand and configured to right-shift the input by a number of bits equal to the value represented by the p least significant bits of the inverted exponent to generate a second output, wherein min{(ew−1),bitwidth(fw)}≤p≤(ew−1); and a multiplexer coupled to the first and second shifters and configured to: receive a first input comprising a contiguous set of bits of the first output and a second input comprising a contiguous set of bits of the second output; and output the first input if the most significant bit of the exponent is equal to one; and output the second input if the most significant bit of the exponent is equal to zero.

Claim (Index 18):
The binary logic circuit as claimed in  claim 1 , wherein the binary logic circuit further comprises exception-handling circuitry configured to output an exception result in response to detecting an exception condition from a set of exception conditions comprising at least one of: i) E>B+iw\u22121\u2212s y ; ii) E\u2264B\u2212fw, where s y =1 for a signed number and s y =0 for an unsigned number; and the binary logic circuit further comprises an output multiplexer configured to multiplex between the exception result and the output from the multiplexer coupled to the first and second shifters.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 90.0
- Lexical Diversity: 3.2
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15935345', '11740711', '11840323', '13284125', '11019097']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4409832637605414
- 35 USC 102 Novelty (BERT): 0.6869948808888211
- Combined Prediction Score: 0.4655844254733693
- Mean Citation Score: 441.289368
- Max Citation Score: 855.43805
- Similarity Product: 648.2452291035115

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test