PATENT CLAIM ANALYSIS

Application Number: 16192019
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["710", "110000"]

Abstract:
A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

Claim (Index 9):
A system on chip (SoC) comprising:\n a first master; a second master; an interface configured to provide communication between an external device and the first master and/or communication between the external device and the second master; and a semaphore circuit configured to detect a first access request from the first master and/or a second access request from the second master, and to grant the first access request or the second access request, wherein the semaphore circuit is configured to predict a time when one of the first master and the second master occupies the interface, and configured to schedule the other of the first master and the second master.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.93023
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15899877', '14877653', '13137349', '11608239', '15247366']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.643766768073886
- 35 USC 102 Novelty (BERT): 0.555257673116288
- Combined Prediction Score: 0.6349158585781263
- Mean Citation Score: 275.768334
- Max Citation Score: 422.95874
- Similarity Product: 357.5096105472207

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test