PATENT CLAIM ANALYSIS

Application Number: 15976315
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "145000"]

Abstract:
Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS −V G  hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS  states at V G =0.

Claim (Index 1):
A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 93.0
- Lexical Diversity: 1.77632
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12860253', '15594807', '13137566', '12856962', '13396272']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7733244931782005
- 35 USC 102 Novelty (BERT): 0.4948280971973228
- Combined Prediction Score: 0.7454748535801128
- Mean Citation Score: 165.774406
- Max Citation Score: 186.89499
- Similarity Product: 107.47960006580116

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test