PATENT CLAIM ANALYSIS

Application Number: 15985563
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["375", "376000"]

Abstract:
Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M−x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

Claim (Index 11):
A system comprising:\n a first clock module configured to generate a reference clock signal; a first digital-to-time converter configured to adjust the reference clock signal in accordance with a first control signal and to generate an adjusted reference clock output signal; a time-to-digital converter configured to receive, as a first input signal, the adjusted reference clock output signal from the first digital-to-time converter; a second clock module configured to generate an output high-frequency clock signal based on an output from the time-to-digital converter; a feedback module configured to receive the output high-frequency clock signal and to generate a derived signal based on the output high-frequency clock signal; a second digital-to-time converter configured to adjust the derived signal in accordance with a second control signal and to provide the adjusted derived signal, as a second input signal, to the time-to-digital converter; and a control module configured to generate the first and second control signals, wherein the first and second control signals are centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the first and second control signals are respectively defined as (M+x) and (M\u2212x).

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 1.88764
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12978221', '15370796', '15869854', '15625449', '15170882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4593307234648249
- 35 USC 102 Novelty (BERT): 0.5129123621693827
- Combined Prediction Score: 0.4646888873352807
- Mean Citation Score: 265.01081200000004
- Max Citation Score: 291.6605
- Similarity Product: 227.6908247984052

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test