PATENT CLAIM ANALYSIS

Application Number: 15747111
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "368000"]

Abstract:
Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.

Claim (Index 20):
The method of  claim 13 , further comprising:\n forming a backside strain inducing layer over the channel region exposed by the strain enhancement opening.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 86.0
- Lexical Diversity: 2.12069
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13539463', '13168711', '13886939', '11506986', '15677855']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9107805878861596
- 35 USC 102 Novelty (BERT): 0.4908307502516845
- Combined Prediction Score: 0.8687856041227122
- Mean Citation Score: 187.349716
- Max Citation Score: 193.40054
- Similarity Product: 127.95695460100174

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test