PATENT CLAIM ANALYSIS

Application Number: 15916193
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["711", "149000"]

Abstract:
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Claim (Index 15):
The DRAM device of  claim 13 , wherein the data links corresponding to each one of said memory arrays are sixteen in number.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 90.0
- Lexical Diversity: 2.04918
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15169331', '14305799', '12820973', '14449610', '12627769']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5301727619642805
- 35 USC 102 Novelty (BERT): 0.4982128261520114
- Combined Prediction Score: 0.5269767683830536
- Mean Citation Score: 217.57258199999995
- Max Citation Score: 248.19466
- Similarity Product: 179.07862580681683

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test