PATENT CLAIM ANALYSIS

Application Number: 15987113
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["712", "220000"]

Abstract:
A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.

Claim (Index 3):
The apparatus according to  claim 2 , wherein the control circuitry is configured to start counting the delay in accessing information from the storage circuitry in response to an access request for information from said storage circuitry missing in a predetermined storage level of the storage circuitry.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 1.86567
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12149772', '12511620', '15464574', '11051979', '14947030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5964118493160855
- 35 USC 102 Novelty (BERT): 0.4837608628475382
- Combined Prediction Score: 0.5851467506692308
- Mean Citation Score: 172.83793400000005
- Max Citation Score: 183.67879
- Similarity Product: 125.30490685046492

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test