PATENT CLAIM ANALYSIS

Application Number: 15965606
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["438", "478000"]

Abstract:
Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method includes providing a film stack containing a Si layer, a SiGe layer, and a Ge layer positioned between the Si layer and the SiGe layer, and selectively removing the Ge layer by etching that is selective to the Si layer and the SiGe layer, thereby forming an opening between the Si layer and the SiGe layer. According to another embodiment, the method providing a film stack containing alternating Si and Ge layers, and selectively removing the Ge layers by etching that is selective to the Si layers. According to another embodiment, the method includes providing a film stack containing a plurality of alternating SiGe and Ge layers, and selectively removing the plurality of Ge layers by etching that is selective to the SiGe layers.

Claim (Index 19):
The method of  claim 16 , wherein the thermal or plasma-assisted halogen-based gas phase etching includes Cl 2 , F 2 , ClF 3 , or a combination thereof.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 3.4375
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12865517', '14511715', '14969833', '14880659', '15450756']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.880254683120405
- 35 USC 102 Novelty (BERT): 0.5135324608936596
- Combined Prediction Score: 0.8435824608977305
- Mean Citation Score: 261.41267000000005
- Max Citation Score: 277.9924
- Similarity Product: 182.8585013298273

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test