PATENT CLAIM ANALYSIS

Application Number: 16207081
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["257", "295000"]

Abstract:
A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

Claim (Index 13):
The semiconductor device of  claim 2 , further comprising:\n a first conductive layer disposed over the first ferroelectric layer; and a second conductive layer disposed over the second ferroelectric layer.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 3.4878
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15640127', '16049013', '15447679', '15796154', '15481672']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8893483967933796
- 35 USC 102 Novelty (BERT): 0.4842254060020947
- Combined Prediction Score: 0.8488360977142512
- Mean Citation Score: 163.016672
- Max Citation Score: 211.646
- Similarity Product: 172.25267332792282

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test