PATENT CLAIM ANALYSIS

Application Number: 15920562
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "759000"]

Abstract:
Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

Claim (Index 17):
The method of  claim 14 , wherein the second set of conductors and the second grid pattern of electrical contacts is fabricated in a second BEOL dielectric layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 2.90566
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15456758', '15456769', '15793130', '12146546', '15837774']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920175815780406
- 35 USC 102 Novelty (BERT): 0.4754456348684539
- Combined Prediction Score: 0.8757027976892108
- Mean Citation Score: 176.12813599999996
- Max Citation Score: 180.69688
- Similarity Product: 137.8461957230854

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test