PATENT CLAIM ANALYSIS

Application Number: 16023546
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["257", "530000"]

Abstract:
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Claim (Index 33):
A memory array, comprising:\n a substrate; and at least two memory devices, each comprising:\n a first gate conductor disposed over a first gate dielectric structure on the substrate; \n a second gate conductor disposed over a second gate dielectric structure on the substrate, the second gate conductor comprising an L shape including a vertical portion adjacent to the first gate conductor and a horizontal portion on an opposite side of the vertical portion from the first gate conductor; and \n an inter-gate dielectric structure disposed between the first gate conductor and the second gate conductor; \n a spacer disposed on a sidewall of the horizontal portion of the second gate conductor and on a sidewall of an opposite side of the first gate conductor from the second gate conductor; \n a doped region in the substrate adjacent to the opposite side of the first gate conductor from the second gate conductor; \n a contact electrically coupled to the doped region; and \n an insulating material disposed over the substrate between the contact and the spacer on the sidewall of the first gate conductor, \n wherein the insulating material comprises no voids, \n wherein a first memory device and a second memory device are disposed such that the horizontal portion of the second gate conductor of the first memory device is adjacent to the horizontal portion of the second gate conductor of the second memory device.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 94.0
- Lexical Diversity: 2.42373
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15433848', '14450727', '15606255', '14612191', '15711075']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9022042926031446
- 35 USC 102 Novelty (BERT): 0.5155865599101321
- Combined Prediction Score: 0.8635425193338433
- Mean Citation Score: 246.414734
- Max Citation Score: 314.1221
- Similarity Product: 285.97811827093363

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test