PATENT CLAIM ANALYSIS

Application Number: 16102317
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["438", "183000"]

Abstract:
A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.

Claim (Index 17):
The semiconductor device of  claim 16 , wherein a material of the first gate dielectric region is different from that of the first spacer dielectric region.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 96.0
- Lexical Diversity: 3.16
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14809158', '15449582', '15068409', '15699643', '15846887']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.862422078933207
- 35 USC 102 Novelty (BERT): 0.5039039468168157
- Combined Prediction Score: 0.8265702657215679
- Mean Citation Score: 184.429322
- Max Citation Score: 227.11765
- Similarity Product: 146.7810376957476

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test