PATENT CLAIM ANALYSIS

Application Number: 16011963
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["327", "141000"]

Abstract:
Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Claim (Index 14):
The IC of  claim 11 , wherein the delay model is further configured to account for an internal delay of the IC.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 94.0
- Lexical Diversity: 1.6875
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15906160', '15064663', '12978221', '15170882', '15674985']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7605742179738497
- 35 USC 102 Novelty (BERT): 0.5091411193317118
- Combined Prediction Score: 0.735430908109636
- Mean Citation Score: 228.39578
- Max Citation Score: 239.41965
- Similarity Product: 152.25635037115217

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test