PATENT CLAIM ANALYSIS

Application Number: 15891395
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["716", "106000"]

Abstract:
A method for circuit design automation includes appending a non-synthesizable input having a unique identifier to HDL code that specifies a physical input of the circuit. For the physical components in the circuit to which a signal from the physical input is to propagate, corresponding non-synthesizable components are appended, having respective identifiers assigned responsively to the unique identifier of the non-synthesizable input, to the HDL code that specifies the physical components. The design is verified by simulating operation of the circuit using the HDL code, including both the physical and non-synthesizable inputs and components. After verifying the design, a netlist synthesis tool automatically generates a netlist of the circuit including the physical inputs and components while omitting the non-synthesizable inputs and components.

Claim (Index 9):
The apparatus according to  claim 8 , wherein the non-synthesizable input and components are preceded in the HDL code by a translate-off command.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 88.0
- Lexical Diversity: 2.25862
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12397298', '09846092', '10976643', '11684156', '11948551']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3687622622138707
- 35 USC 102 Novelty (BERT): 0.4814100160324343
- Combined Prediction Score: 0.3800270375957271
- Mean Citation Score: 207.559324
- Max Citation Score: 217.20276
- Similarity Product: 139.51540667241812

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test