PATENT CLAIM ANALYSIS

Application Number: 16049256
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "500000"]

Abstract:
An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.

Claim (Index 5):
The method of  claim 4 , wherein the SiN layer or the SiC layer is 200 to 800 A thick and has a 50 to 500 megapascal (Mpa) compressive stress.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 1.71429
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15857234', '15478615', '12555162', '15071725', '13945435']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9117029454725032
- 35 USC 102 Novelty (BERT): 0.5102680019958739
- Combined Prediction Score: 0.8715594511248402
- Mean Citation Score: 147.035052
- Max Citation Score: 170.37573
- Similarity Product: 89.14425393710911

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test