PATENT CLAIM ANALYSIS

Application Number: 15871374
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "289000"]

Abstract:
Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×10 21 /cm 3  or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

Claim (Index 15):
The semiconductor device of  claim 11 , wherein top surfaces of the source/drain assembly comprise a V-shaped groove and at least one of surfaces forming the V-shaped groove is a (311) crystal surface.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.08696
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15351739', '15051056', '14662697', '14547190', '14330306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927002719534854
- 35 USC 102 Novelty (BERT): 0.48900758852317
- Combined Prediction Score: 0.8832032064336858
- Mean Citation Score: 231.013816
- Max Citation Score: 235.78609
- Similarity Product: 187.3287020917773

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test