PATENT CLAIM ANALYSIS

Application Number: 15779442
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "401000"]

Abstract:
Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

Claim (Index 13):
The device of  claim 11 , wherein the Group IV material is a PMOS or NMOS structure.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.1
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15525183', '15525164', '13340937', '15043935', '12646477']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9002307936575427
- 35 USC 102 Novelty (BERT): 0.4960153571354152
- Combined Prediction Score: 0.8598092500053299
- Mean Citation Score: 152.36727800000003
- Max Citation Score: 156.49112
- Similarity Product: 99.73030062885285

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test