PATENT CLAIM ANALYSIS

Application Number: 15906366
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["257", "773000"]

Abstract:
A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.

Claim (Index 5):
The semiconductor device structure of  claim 4 , wherein a first distance between a first of the non-uniformly spaced contact structures over and in contact with the first of the at least three steps and a second of the non-uniformly spaced contact structures over and in contact with the second of the at least three steps is less than a second distance between the second of the non-uniformly spaced contact structures and a second of the non-uniformly spaced contact structures over and in contact with the third of the at least three steps.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 88.0
- Lexical Diversity: 1.64
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14837978', '15606415', '15271924', '13932551', '14877997']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303090623544892
- 35 USC 102 Novelty (BERT): 0.5057019494103051
- Combined Prediction Score: 0.8878483510600709
- Mean Citation Score: 234.75997200000003
- Max Citation Score: 256.53903
- Similarity Product: 175.72850219758453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test