PATENT CLAIM ANALYSIS

Application Number: 15745548
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["257", "072000"]

Abstract:
A array substrate comprises: a substrate including a display area and a peripheral wiring area, wherein active switches, pixel units and signal lines are disposed in the display area, the pixel units are coupled to the active switches, the active switches are coupled to the signal lines, and the signal lines include gate lines and source lines, each pixel unit includes a first subpixel and a second subpixel are coupled to different gate lines, and coupled to a common source line, input interface of the gate lines is disposed in the wiring area; a gate driving module disposed in the wiring area and including output interfaces; connecting lines disposed between the input interfaces and the output interfaces, wherein the connecting lines include wiring line groups and jumper line groups, a sequence of signals of jumper line groups is different from a sequence of signals of wiring line groups.

Claim (Index 17):
An array substrate, comprising:\n a substrate including a display area and a peripheral wiring area of the display area, wherein a plurality of active switches, a plurality of pixel units and a plurality of signal lines are disposed in the display area, and the plurality of pixel units are electrically coupled to the plurality of active switches respectively, and the plurality of active switches are electrically coupled to the plurality of signal lines respectively, and the plurality of signal lines include a plurality of gate lines and a plurality of source lines, wherein each pixel unit includes a first subpixel and a second subpixel, the first subpixel and the second subpixel are electrically coupled to different gate lines respectively through corresponding active switches, the first subpixel and the second subpixel are electrically coupled to a common source line, a plurality of input interfaces of the plurality of gate lines are disposed in the wiring area, and the plurality of input interfaces include a first input interface and a second input interface; a gate driving module disposed in the wiring area, the gate driving module including a plurality of output interfaces, control signals outputted from the gate driving module according to the line layout sequence of the plurality of output interfaces, and the plurality of output interfaces include a first output interface and a second output interface; and a plurality of connecting lines disposed between the plurality of input interfaces and the plurality of output interfaces, so that the plurality of input interfaces are electrically coupled to the plurality of output interfaces respectively; wherein the plurality of connecting lines include a plurality of wiring line groups and a plurality of jumper line groups, the plurality of wiring line groups and the plurality of jumper line groups are disposed to be interlaced, the plurality of jumper line groups include a two-wiring line combination, the two-wiring line combination includes a first wiring line and a second wiring line; the first wiring line electrically couple between the first output interface and the second input interface, the second wiring line electrically couple between the second output interface and the first input interface, the second wiring line is disposed in a turning line, a straight line, a curve line, or a slanted line, the first wiring line is disposed in a jumper line, a sequence of input signals are contrary to a sequence of output signals for the two-wiring line combination, and a sequence of the control signals outputted from the plurality of output interfaces are different from a sequence of the control signals received by the plurality of input interfaces.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.94545
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12085529', '14296063', '12526700', '15745550', '13517872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916906907733572
- 35 USC 102 Novelty (BERT): 0.4661435634496307
- Combined Prediction Score: 0.8718305733051779
- Mean Citation Score: 193.805564
- Max Citation Score: 195.40915
- Similarity Product: 165.2310837943137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test