PATENT CLAIM ANALYSIS

Application Number: 15915823
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185110"]

Abstract:
In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.

Claim (Index 19):
The flash memory according to  claim 17 , wherein the second level shifter is configured to shift a maximum voltage value and a minimum voltage value of an external access signal to a pre-selected value based on an operation mode of the flash memory.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 90.0
- Lexical Diversity: 2.14634
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15432228', '14961643', '10486638', '13323868', '11436701']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8008110607029771
- 35 USC 102 Novelty (BERT): 0.5615671489745963
- Combined Prediction Score: 0.7768866695301391
- Mean Citation Score: 270.908968
- Max Citation Score: 470.39362
- Similarity Product: 358.3233413153648

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test