PATENT CLAIM ANALYSIS

Application Number: 15978235
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["326", "039000"]

Abstract:
An integrated circuit comprising a first memory array and programmable/configurable logic circuitry including a plurality of logic tiles wherein each logic tile includes a perimeter, a plurality of external I/O disposed in an I/O layout on the perimeter, wherein the I/O layout of each tile is identical. Each external I/O is configurable as an external I/O to connect to and communicate with external circuitry, or a memory I/O to point-to-point connect to memory located adjacent thereto, or an unused I/O. The first memory array is physically adjacent to a first logic tile on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and point-to-point connected to the memory I/O. In operation, circuitry of the first logic tile is configured to read data from and write data to the first memory array via the memory I/O.

Claim (Index 8):
An integrated circuit comprising:\n programmable/configurable logic circuitry having a periphery, the programmable/configurable logic circuitry includes: a plurality of logic tiles, configured in an array having a plurality of rows and a plurality of columns of logic tiles; a first plurality of memory arrays, wherein at least one memory array of the first plurality of memory arrays is (i) physically located between each logic tile of successive rows of logic tiles and (i) associated with at least one logic tile of a row of the successive rows; wherein each logic tile of the plurality of logic tiles includes:\n an interconnect network including a plurality of multiplexers, \n a plurality of interconnect I/O to connect to the interconnect network and one or more interconnect I/O of one or more other logic tiles of the plurality of logic tiles, \n a perimeter, \n a plurality of memory I/O, disposed in an I/O layout on the perimeter of the logic tile, configurable to point-to-point connect to memory, wherein the I/O layout of the memory I/O of each logic tile is identical, and \n circuitry, electrically coupled to the memory I/O and configurable to read data from and write data to memory; and \n wherein:\n each memory array of the first plurality of memory arrays is (i) physically located adjacent a first portion of the perimeter of the associated logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and (ii) point-to-point connected to the memory I/O located on a first portion of the perimeter of the associated logic tile, and \n the circuitry of each logic tile which is electrically coupled to the memory I/O located on the first portion of the perimeter of the logic tile is configured to read data from and write data to the associated memory array during operation of the programmable/configurable logic circuitry.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 93.0
- Lexical Diversity: 2.59016
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15239958', '15975037', '14972553', '14712864', '15347045']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7171372955502289
- 35 USC 102 Novelty (BERT): 0.5883158985750483
- Combined Prediction Score: 0.7042551558527108
- Mean Citation Score: 390.231684
- Max Citation Score: 530.7966
- Similarity Product: 459.77001955515146

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test