PATENT CLAIM ANALYSIS

Application Number: 15898671
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "343000"]

Abstract:
A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.

Claim (Index 13):
The device of  claim 1  comprises an epitaxial layer formed on the substrate, the epitaxial layer serves as a surface substrate for the device region.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.06349
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14808991', '15872939', '15137018', '15640613', '15898669']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9270481046272137
- 35 USC 102 Novelty (BERT): 0.5045806391549675
- Combined Prediction Score: 0.884801358079989
- Mean Citation Score: 236.994976
- Max Citation Score: 244.54065
- Similarity Product: 163.0383427684486

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test