PATENT CLAIM ANALYSIS

Application Number: 16238682
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "185290"]

Abstract:
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Claim (Index 1):
A non-volatile semiconductor memory device comprising:\n a memory cell array comprising a plurality of memory cells, and a plurality of word-lines connected to gates of the memory cells; and a control circuit configured to perform an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level, the memory cell array comprising: a semiconductor substrate; a first semiconductor layer extending in a direction perpendicular to the semiconductor substrate, and functioning as a body of a memory cell; a charge accumulation layer operative to accumulate charges; and a first conductive layer sandwiching the charge accumulation layer with the first semiconductor layer, and functioning as a gate of the memory cell and a word-line, the control circuit performing the first write operation to the plurality of memory cells, and when the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing a first function operation except for the erase operation and the first write operations, the control circuit performs the first function operation during the first write operations.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.63265
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13425818', '14748351', '14093108', '15074190', '15361778']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7584698176579125
- 35 USC 102 Novelty (BERT): 0.4473411026334114
- Combined Prediction Score: 0.7273569461554625
- Mean Citation Score: 181.44724
- Max Citation Score: 190.44243
- Similarity Product: 183.86605864581588

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test