PATENT CLAIM ANALYSIS

Application Number: 15986307
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-07
Patent Classification: ["257", "360000"]

Abstract:
An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.

Claim (Index 8):
An ESD protection circuit assembly, comprising:\n an I/O circuit comprising a power I/O unit and a signal I/O unit, said power I/O unit comprising a high-voltage power termination pad, a high-voltage ground termination pad and a second power line electrically connected to said high-voltage ground termination pad, said signal I/O unit comprising a plurality of signal transmission termination pads and a plurality of signal transmission lines respectively electrically connected to said signal transmission termination pads; and an electrostatic discharge clamp circuit comprising a P-type substrate, at least three low voltage P-type structures arranged on the P-type substrate and connected in series, a plurality of low voltage N-type wells formed on a top side of said P-type substrate and said at least three low voltage P-type structures each comprises a first P-type heavily doped area and a second P-type heavily doped area formed in each said low voltage N-type well, said first P-type heavily doped area and said second P-type heavily doped area are isolated from each other through a part of said low voltage N-type wells, said first P-type heavily doped area of the first said low voltage P-type structure being electrically connected to said signal transmission termination pad through said signal transmission line, said second P-type heavily doped area of the last said low voltage P-type structure being electrically connected to said high-voltage ground termination pad through said second power line to provide an ESD current discharge path.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 93.0
- Lexical Diversity: 2.12698
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15986245', '12628188', '13216016', '13556219', '10711673']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9224235163868428
- 35 USC 102 Novelty (BERT): 0.5490001403210933
- Combined Prediction Score: 0.8850811787802679
- Mean Citation Score: 300.69648
- Max Citation Score: 417.50394
- Similarity Product: 336.46449977059007

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test