PATENT CLAIM ANALYSIS

Application Number: 16230717
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["375", "233000"]

Abstract:
An equalizer circuit includes: an addition circuit configured to add an input signal and a compensation signal; a comparison circuit configured to compare an output signal of the addition circuit; a plurality of first latch circuits configured to hold an output signal of the comparison circuit, the plurality of first latch circuits being connected in cascade; a selection circuit configured to select and output one of output signals of the comparison circuit and the plurality of first latch circuits; a second latch circuit configured to hold an output signal of the selection circuit; and a digital analog conversion circuit configured to generate the compensation signal, based on an output signal of the second latch circuit.

Claim (Index 14):
The reception circuit according to  claim 11 , wherein\n a total number of latch circuits obtained by totaling the plurality of first latch circuits and the second latch circuits is equal to the number of taps in the equalizer circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.88372
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15132824', '14202751', '11303941', '16209616', '11672270']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4699850681540701
- 35 USC 102 Novelty (BERT): 0.5032671566570823
- Combined Prediction Score: 0.4733132770043713
- Mean Citation Score: 220.43529400000003
- Max Citation Score: 225.41048
- Similarity Product: 156.90333039238453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test