PATENT CLAIM ANALYSIS

Application Number: 15897109
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["330", "006000"]

Abstract:
A signal amplifying system having an oscillator and an amplifying circuit. The oscillator has a first resistor with a first resistance R 1  and a first capacitor with a first capacitance C 1 , and generates an oscillating signal having a frequency f which equals to k1/(R 1 *C 1 ), k1 is a first proportional parameter. The amplifying circuit has an input terminal to receive an input signal and amplifies the input signal under the control of the oscillating signal. The amplifying circuit has a second resistor with a second resistance R 2  and a second capacitor with a second capacitance C 2 . The amplifying circuit has a −3 dB bandwidth W −3 dB  which equals to k2/(R 2 *C 2 ), k2 is a second proportional parameter. In this signal amplifying system, the product of the first resistance R 1  and the first capacitance C 1  is proportional to the product of the second resistance R 2  and the second capacitance C 2.

Claim (Index 3):
The signal amplifying system of  claim 2 , wherein the first bias transistor has a first terminal, a second terminal and a control terminal, the first terminal of the first bias transistor is coupled to a power supply, and wherein the second resistor has a first terminal coupled to the second terminal of the first bias transistor, and a second terminal coupled to the control terminal of the first bias transistor; and wherein the bias circuit further comprises:\n a second bias transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the power supply, the control terminal is coupled to the second terminal of the first bias transistor; a third bias transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the second resistor, the second terminal is coupled to a reference ground; a fourth bias transistor having a first terminal coupled to the second terminal of the second bias transistor, a second terminal coupled to the reference ground, and a control terminal coupled to the control terminal of the third bias transistor and the first terminal of the fourth bias transistor; a fifth bias transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the reference ground, and the control terminal is coupled to the control terminal of the fourth bias transistor; a sixth bias transistor having a first terminal coupled to the power supply, a second terminal coupled to the first terminal of the fifth bias transistor, and a control terminal coupled to the second terminal of the sixth bias transistor; and a seventh bias transistor having a first terminal coupled to the power supply, a control terminal coupled to the control terminal of the sixth bias transistor, and a second terminal configured to provide the bias current IB; wherein the first, third, fourth, fifth and sixth bias transistors have the same gate width to length ratio, the gate width to length ratios of the second and seventh bias transistors are proportional to the gate width to length ratio of the first bias transistor.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 3.15789
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14576535', '11858137', '13424283', '11775105', '13664679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7579329554636529
- 35 USC 102 Novelty (BERT): 0.4680602213360202
- Combined Prediction Score: 0.7289456820508897
- Mean Citation Score: 172.237652
- Max Citation Score: 178.8198
- Similarity Product: 156.14707998969553

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test