PATENT CLAIM ANALYSIS

Application Number: 15988140
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "154000"]

Abstract:
A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.

Claim (Index 13):
A dual-rail memory device comprising:\n a bit line; a complementary bit line; a memory cell coupled to the bit line or the complementary bit line, the memory cell further coupled to a word line; a precharge circuit comprising a first portion coupled between the bit line and the complementary bit line and a second portion coupled between the bit line and the complementary bit line; and a control circuit configured to, in response to an access request,\n increase a voltage of the bit line or the complementary bit line by deactivating the first portion and activating the second portion, \n deactivate the second portion after increasing the voltage of the bit line, and \n activate the word line after deactivating the second portion.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 1.67647
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14045589', '15296567', '13271353', '13337761', '12687571']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8063183584976994
- 35 USC 102 Novelty (BERT): 0.5107313009818363
- Combined Prediction Score: 0.776759652746113
- Mean Citation Score: 260.17701600000004
- Max Citation Score: 326.63013
- Similarity Product: 253.1185238535476

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test