PATENT CLAIM ANALYSIS

Application Number: 16160366
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "009000"]

Abstract:
Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.

Claim (Index 14):
The FET device of  claim 1 , further comprising:\n a gate dielectric separating the SiGe nanowires from the gate, wherein the gate dielectric is selected from the group consisting of: hafnium oxide and lanthanum oxide.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 97.0
- Lexical Diversity: 1.89394
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15640782', '14880659', '15640766', '13550861', '12731241']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9366865658224408
- 35 USC 102 Novelty (BERT): 0.5705470675820298
- Combined Prediction Score: 0.9000726159983996
- Mean Citation Score: 406.176862
- Max Citation Score: 479.0893
- Similarity Product: 396.83557790562514

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test