PATENT CLAIM ANALYSIS

Application Number: 15920002
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "738000"]

Abstract:
A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Claim (Index 14):
A method of producing a semiconductor die formed on a substrate, the method comprising:\n forming a first circuit block on the substrate; forming a second circuit block on the substrate; segmenting the semiconductor die into a first power mesh and an electrically isolated second power mesh, the first power mesh electrically coupled to the first circuit block and configured to supply power to the first circuit block, and the second power mesh electrically connected to the second circuit block and configured to supply power to the second circuit block; communicatively coupling a first plurality of external circuit connections to the first circuit block, such that the first plurality of external circuit connections is communicatively isolated from the second circuit block; communicatively coupling a second plurality of external circuit connections to the second circuit block such that the second plurality of external circuit connections is communicatively isolated from the first circuit block; connecting the first power mesh to one or more first signal pins, the one or more first signal pins configured to receive one or more external signals; and connecting the second power mesh to one or more second signal pins, the one or more second signal pins configured to receive one or more external signals.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 90.0
- Lexical Diversity: 3.42857
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14686666', '10884055', '12625457', '10164495', '10301200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9129607093148188
- 35 USC 102 Novelty (BERT): 0.4582017475961588
- Combined Prediction Score: 0.8674848131429528
- Mean Citation Score: 164.183052
- Max Citation Score: 168.39426
- Similarity Product: 139.88330178331017

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test