PATENT CLAIM ANALYSIS

Application Number: 15976653
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "773000"]

Abstract:
A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a smaller elastic modulus than the metal layer or layer stack over a temperature range.

Claim (Index 13):
The semiconductor device of  claim 12 , wherein the stress relieving layer or layer stack covers the entire main surface of the semiconductor body over which the stress relieving layer or layer stack is disposed.

Metadata:
- Claim Count in Document: 49.0
- Percentile: 93.0
- Lexical Diversity: 2.81633
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15581204', '14902001', '12182283', '10689386', '11858554']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9190574781921004
- 35 USC 102 Novelty (BERT): 0.4946256914254006
- Combined Prediction Score: 0.8766142995154306
- Mean Citation Score: 186.575842
- Max Citation Score: 190.80104
- Similarity Product: 126.14448702427865

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test