PATENT CLAIM ANALYSIS

Application Number: 15863581
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. The method also includes forming a stacked structure on a bottom and sidewall of the opening and on a top of the interlayer dielectric layer. In addition, the method includes removing at least a first portion of the stacked structure from the top of the interlayer dielectric layer. Further, the method includes performing an annealing treatment on the base substrate, and forming a gate structure by filling the opening with a metal layer.

Claim (Index 11):
The method according to  claim 1 , wherein:\n removing the first portion of the stacked structure from the top of the interlayer dielectric layer includes a dry etching process.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 2.36538
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15799706', '15494607', '13737966', '13861584', '14305969']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9247523558885156
- 35 USC 102 Novelty (BERT): 0.4985105560662845
- Combined Prediction Score: 0.8821281759062926
- Mean Citation Score: 221.06246
- Max Citation Score: 240.70537
- Similarity Product: 173.28929371692956

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test