PATENT CLAIM ANALYSIS

Application Number: 16192767
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "329000"]

Abstract:
Provided is a method for fabricating a semiconductor device, which includes the following steps. First, a substrate having at least one transistor is provided. A first insulation layer is formed to cover the transistor. The first insulation layer is patterned to form at least one opening, wherein a part of the transistor is exposed by the opening. At last, an epitaxy is formed in the opening to cover the part of the transistor.

Claim (Index 8):
The method of  claim 1 , wherein the transistor is a vertical silicon pillar with a drain electrode at the top of the vertical silicon pillar, a source electrode at the bottom of the vertical silicon pillar, and a gate electrode substantially at the middle of the vertical silicon pillar, wherein the drain electrode is the part exposed by the opening and covered by the epitaxy.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.86364
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12728596', '13211249', '14288167', '13547318', '13271446']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92024022183357
- 35 USC 102 Novelty (BERT): 0.4853387110775323
- Combined Prediction Score: 0.8767500707579663
- Mean Citation Score: 181.857708
- Max Citation Score: 189.984
- Similarity Product: 135.59134232711793

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test