PATENT CLAIM ANALYSIS

Application Number: 16432257
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["708", "655000"]

Abstract:
A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Claim (Index 7):
The processor of  claim 5 , wherein the performed division includes Euclidean division and processor is configured to perform the sign assignment by negating the quotient without negating the remainder.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.4
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15142047', '15198070', '12708180', '14315940', '12379447']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4138523474444249
- 35 USC 102 Novelty (BERT): 0.5691049451633531
- Combined Prediction Score: 0.4293776072163177
- Mean Citation Score: 248.529154
- Max Citation Score: 449.0924
- Similarity Product: 317.6365531955242

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test