PATENT CLAIM ANALYSIS

Application Number: 16295620
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["365", "185110"]

Abstract:
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Claim (Index 1):
A memory device, comprising:\n a plurality of block units each including a plurality of blocks, each block including a plurality of memory strings, each memory string including a first transistor, a first memory cell transistor, a second memory cell transistor, and a second; a plurality of first select gate lines, each of the first select gate lines connected to a gate of a corresponding one of the first transistors in each block unit; a plurality of second select gate lines, each of the second select gate lines connected to a gate of a corresponding one of the second transistors in each block unit; a plurality of first word lines, each of the first word lines connected to gates of the first memory cell transistors of a corresponding one of the blocks in each block unit; a plurality of second word lines, each of the second word lines connected to gates of the second memory cell transistor of a corresponding one of the blocks in each block unit; a plurality of transfer transistors, each first select gate line, each second select gate line, each first word line, and each second word line respectively having one end of a transfer transistor connected thereto; a plurality of block decoders having a selection signal output line respectively connected to gates of the transfer transistors connected to one of the block units; and a voltage supply circuit having voltage supply lines connected to another end of the transfer transistor respectively connected to the first select gate lines and the second select gate lines of each of the block units.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 99.0
- Lexical Diversity: 2.61667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15984834', '13784512', '15497928', '15151883', '14688664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8297961060437995
- 35 USC 102 Novelty (BERT): 0.5335581063640119
- Combined Prediction Score: 0.8001723060758207
- Mean Citation Score: 358.02829800000006
- Max Citation Score: 388.68323
- Similarity Product: 383.0215989077258

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test