PATENT CLAIM ANALYSIS

Application Number: 16012957
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "401000"]

Abstract:
A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.

Claim (Index 17):
The device of  claim 16 , wherein directing the parasitic current flow to the source reduces overall parasitic current effects in the device.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.5283
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15267646', '15264688', '15378680', '15895077', '15444617']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9295136636445838
- 35 USC 102 Novelty (BERT): 0.5535367752356136
- Combined Prediction Score: 0.8919159748036868
- Mean Citation Score: 366.51862
- Max Citation Score: 421.70535
- Similarity Product: 285.1438493966103

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test