PATENT CLAIM ANALYSIS

Application Number: 16397547
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["365", "230030"]

Abstract:
A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.

Claim (Index 1):
A circuit for generating a varying pulse width clock signal which varies with an address of a memory cell, the circuit comprising:\n a plurality of transistors each having a different word line configurations, different effective RC constant and different discharging time; a sub-address of the address of the memory cell with the plurality of bits,\n wherein each of the plurality of transistors is individually addressed by one of the plurality of bits of the sub-address, \n wherein the source of each of the plurality of transistors is electrically connected to a second supply voltage Vss; \n a first transistor, wherein the source of the first transistor is electrically connected to the drain of each of the plurality of transistors; a second transistor, wherein the source of the second transistor is electrically connected to a first supply voltage Vdd; a third transistor, wherein the drain of the drain of the first transistor and the drain of the second transistor are electrically connected to the gate of the third transistor, wherein the source of the third transistor is electrically connected to the first supply voltage Vdd; a fourth transistor, wherein the drain of the third transistor and the drain of the fourth transistor are electrically connected, wherein the gate of the fourth transistor is driven by an external clock signal CLK; a delay element, wherein the output of the delay element is electrically connected to the gate of the first transistor and the gate of the second transistor; a fifth transistor, wherein the source of the fifth transistor is electrically connected to the first supply voltage Vdd, wherein the delay element is also electrically connected to the drain of the fifth transistor, wherein the gate of the fifth transistor is electrically connected to the drain of the third transistor and the drain of the fourth transistor; and a sixth transistor, wherein the source of the sixth transistor is electrically connected to the first supply voltage Vdd, wherein the gate of the sixth transistor is electrically connected to the gate of the fifth transistor, wherein the drain of the sixth transistor drives the varying pulse width clock signal GCKP.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 100.0
- Lexical Diversity: 1.77419
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15860767', '15611332', '13610859', '15214253', '15629489']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7774364844972166
- 35 USC 102 Novelty (BERT): 0.4933033082424323
- Combined Prediction Score: 0.7490231668717382
- Mean Citation Score: 191.81145
- Max Citation Score: 269.1757
- Similarity Product: 213.818072297591

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test