PATENT CLAIM ANALYSIS

Application Number: 16121237
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2018-12
Patent Classification: ["327", "382000"]

Abstract:
An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

Claim (Index 1):
An apparatus, comprising:\n an analog circuit including a pair of analog circuit input nodes and a pair of analog circuit output nodes; and a mismatch reduction circuit including:\n a first mismatch reduction circuit input node; \n a first mismatch reduction circuit output node; \n a phase controller configured to time one or more pairs of even and odd phases; \n an input switch coupled to the phase controller and configured to electrically connect the first mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase of the one or more pairs of even and odd phases and to electrically connect the first mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase of the one or more pairs of even and odd phases; and \n an output switch coupled to the phase controller and configured to electrically connect a first node of the pair of analog circuit output nodes to the first mismatch reduction circuit output node during each even phase of the one or more pairs of even and odd phases and to electrically connect a second node of the pair of analog circuit output nodes to the first mismatch reduction circuit output node during each odd phase of the one or more pairs of even and odd phases.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 4.36111
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15482020', '15863487', '10894982', '10750508', '15391599']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7456780408346251
- 35 USC 102 Novelty (BERT): 0.5217988149134469
- Combined Prediction Score: 0.7232901182425072
- Mean Citation Score: 196.511574
- Max Citation Score: 344.7252
- Similarity Product: 340.6389942910909

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test