PATENT CLAIM ANALYSIS

Application Number: 16447829
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["326", "081000"]

Abstract:
Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

Claim (Index 3):
The depletion mode buried channel conductor insulator semiconductor field effect transistor as claimed in  claim 1 , wherein said source, said drain, said channel are located in a well of second conductivity type semiconductor material that corresponds to said back-gate doping and said back gate doping is located in a well of first conductivity type semiconductor material.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 100.0
- Lexical Diversity: 2.46809
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16173271', '15543801', '15954202', '10324485', '12996067']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7399764329042897
- 35 USC 102 Novelty (BERT): 0.6159996571446297
- Combined Prediction Score: 0.7275787553283237
- Mean Citation Score: 411.499936
- Max Citation Score: 555.81885
- Similarity Product: 544.1984531362832

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test