PATENT CLAIM ANALYSIS

Application Number: 15921337
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["341", "118000"]

Abstract:
An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.

Claim (Index 7):
The A/D converter according to  claim 6 , wherein\n the digital error correction circuit generates the output digital code by a determination result based on the high-order M bits of the input digital code, the low-order N bits of the input digital code, and the redundant bits output from the successive approximation control circuit.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.03509
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15197447', '14587825', '13186059', '13036429', '10976610']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6519453264619544
- 35 USC 102 Novelty (BERT): 0.5280294866830532
- Combined Prediction Score: 0.6395537424840643
- Mean Citation Score: 309.59075800000005
- Max Citation Score: 337.6368
- Similarity Product: 276.9553510457039

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test