PATENT CLAIM ANALYSIS

Application Number: 15872610
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "394000"]

Abstract:
Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.

Claim (Index 15):
The method of  claim 11 , further comprising recessing the recessed surfaces of the semiconductor substrate, wherein the recessing of the recessed surfaces of the semiconductor substrate is performed after removing the additional dielectric spacer material layer from the recessed surfaces and prior to the forming of the counter doped semiconductor layer.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 86.0
- Lexical Diversity: 1.90476
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15727310', '15834380', '15802067', '15005665', '15802021']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9424317919465912
- 35 USC 102 Novelty (BERT): 0.5513882378541768
- Combined Prediction Score: 0.90332743653735
- Mean Citation Score: 433.26454
- Max Citation Score: 465.0944
- Similarity Product: 297.2381233730316

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test