PATENT CLAIM ANALYSIS

Application Number: 15772410
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

Claim (Index 3):
The shift register circuitry according to  claim 1 , at least further comprising a pull-down control circuit, a first pull-down circuit, and a second pull-down circuit;\n wherein the plurality of output circuits comprise at least a first output circuit and a second output circuit; wherein the input circuit is coupled to the input signal terminal, a first voltage terminal, a first pull-up point and a second pull-up point, and is configured to couple the first voltage terminal to the first pull-up point and the second pull-up point, under the control of the voltage at the input signal terminal; wherein the first output circuit is coupled to a first clock signal terminal and a first output signal terminal, and is configured to couple the first clock signal terminal to the first output signal terminal, under the control of a voltage at the first pull-up point; wherein the second output circuit is coupled to a second clock signal terminal and a second output signal terminal, and is configured to couple the second clock signal terminal to the second output signal terminal, under the control of a voltage at the second pull-up point; wherein the pull-down control circuit is coupled to a third voltage terminal, a third clock signal terminal, the first pull-up point, the second pull-up point, and the pull-down point, and is configured to selectively couple the pull-down point to one of the third voltage terminal and the third clock signal terminal, under the control of voltages at the third clock signal terminal, the first pull-up point and the second pull-up point; wherein the first pull-down circuit is coupled to the pull-down point, the third voltage terminal, the first pull-up point and the first output signal terminal, and is configured to couple the first pull-up point and the first output signal terminal to the third voltage terminal, under the control of a voltage at the pull-down point; and wherein the second pull-down circuit is coupled to the pull-down point, the third voltage terminal, the second pull-up point, and the second output signal terminal, and is configured to couple the second pull-up point and the second output signal terminal to the third voltage terminal, under the control of the voltage at the pull-down point.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.97778
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15680452', '15232095', '15761749', '15780157', '15750679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7004218480044586
- 35 USC 102 Novelty (BERT): 0.5063158055721692
- Combined Prediction Score: 0.6810112437612297
- Mean Citation Score: 288.8553100000001
- Max Citation Score: 305.9340200000001
- Similarity Product: 261.34308318040263

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test