PATENT CLAIM ANALYSIS

Application Number: 15980767
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["326", "008000"]

Abstract:
A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line. The harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and a sense amplifier having a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit.

Claim (Index 19):
A physically unclonable function (PUF) device comprising:\n a plurality of PUF cells, configured to generate an output, wherein each of the plurality of PUF cells comprising: an enable/disable complementary metal oxide semiconductor (CMOS) differential logic circuit (ECDL), comprising a first transistor, a second transistor, and a sense amplifier, wherein the sense amplifier comprising a first pair, a second pair and a bias transistor,\n the first pair forms an inverter circuit comprising a third transistor and a fourth transistor, and the second pair forms an inverter circuit comprising a fifth transistor and a sixth transistor, \n the third transistor and the fifth transistor are IO devices, wherein the IO devices use a predetermined voltage to power the PUF cells, \n the IO devices are selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and \n a pulse evaluation circuit, programmable to generate a pulse evaluation signal coupled to a control terminal of the second transistor, wherein after the pulse evaluation signal is stopped, the sense amplifier is enabled to translate difference between a bit line and the complementary bit line.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 2.82432
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15288342', '15288382', '12938477', '14667665', '15598293']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6307546509089613
- 35 USC 102 Novelty (BERT): 0.4904921435360839
- Combined Prediction Score: 0.6167284001716736
- Mean Citation Score: 223.4088
- Max Citation Score: 237.08208
- Similarity Product: 183.1013460607338

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test