PATENT CLAIM ANALYSIS

Application Number: 16038063
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "203000"]

Abstract:
Apparatuses and methods for reducing rots address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

Claim (Index 11):
An apparatus including:\n a sense amplifier configured to, during a precharge phase and in response to an isolation signal, decouple a first gut node of the sense amplifier from a first digit line and decouple a second gut node of the sense amplifier from a second digit line after the first gut node and the second gut nodes have been precharged to a precharge voltage; and a decoder circuit configured to transition from an activation phase to the precharge phase in response to a precharge command, wherein during the precharge phase, the decoder circuit is configured to set the isolation signal to cause the sense amplifier to decouple the first gut node from the first digit line and decouple the second gut node from the second digit line after the first gut node and the second gut node are precharged to the precharge voltage, wherein the decoder circuit is further configured to transition from the precharge phase to a subsequent activation phase in response to receipt of an activate command, wherein, during the activation phase, the decoder circuit is further configured to cause the sense amplifier to perform a threshold voltage compensation operation to bias the first and second digit lines based on a threshold voltage difference between at least two circuit components of the sense amplifier and, after the threshold voltage compensation operation, to cause the sense amplifier to sense a data state of a memory cell coupled to one of the first or second digit lines.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 95.0
- Lexical Diversity: 2.66667
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16017826', '16009806', '16013618', '15591015', '12399757']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.847031774884074
- 35 USC 102 Novelty (BERT): 0.5482981584765296
- Combined Prediction Score: 0.8171584132433196
- Mean Citation Score: 359.086276
- Max Citation Score: 446.5499
- Similarity Product: 324.5967414179802

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test