PATENT CLAIM ANALYSIS

Application Number: 15953514
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-08
Patent Classification: ["341", "158000"]

Abstract:
A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.

Claim (Index 16):
The method of  claim 15 , wherein the control signal couples to a gate terminal of each of the P-type MOSFET and the N-type MOSFET, and when the SAR ADC is disabled, the control signal deactivates the P-type MOSFET and activates the N-type MOSFET.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 91.0
- Lexical Diversity: 2.79245
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15191966', '14423681', '12925916', '15135073', '14182222']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6095406395377244
- 35 USC 102 Novelty (BERT): 0.5061412514620918
- Combined Prediction Score: 0.5992007007301612
- Mean Citation Score: 210.056498
- Max Citation Score: 221.95267
- Similarity Product: 146.14320260096432

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test