PATENT CLAIM ANALYSIS

Application Number: 15917206
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "365000"]

Abstract:
FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET transistor is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the in and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second oxide isolation layer has a thickness greater than a thickness of the first isolation layer.

Claim (Index 4):
A P-N junction comprising:\n a first P-type FinFET; a first N-type FinFET disposed adjacent the first P-type FinFET; and a first isolation layer laterally separating the first N-type FinFET from the adjacent the first P-type FinFET transistor, the first isolation layer having a first thickness and a first width; and a second isolation laterally disposed adjacent the first N-type FinFET, the second isolation layer having a second thickness and a second width, the first thickness at least twice the second thickness, and the first width greater than the second width.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.06
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15197949', '15133832', '14668227', '12933414', '13063504']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916866923901351
- 35 USC 102 Novelty (BERT): 0.4868134336525387
- Combined Prediction Score: 0.8738615748764699
- Mean Citation Score: 222.49514200000004
- Max Citation Score: 229.68054
- Similarity Product: 178.23504765277505

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test