PATENT CLAIM ANALYSIS

Application Number: 15876216
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "296000"]

Abstract:
A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

Claim (Index 10):
The semiconductor device according to  claim 1 , wherein the gate comprises a tungsten layer and TiN liner layer, wherein the TiN liner layer is disposed between the tungsten layer and the first gate dielectric layer and between the tungsten layer and the second gate dielectric layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 3.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14937056', '12343035', '12167231', '11641845', '15189478']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9195486170583842
- 35 USC 102 Novelty (BERT): 0.4797708120553545
- Combined Prediction Score: 0.8755708365580812
- Mean Citation Score: 174.73296399999995
- Max Citation Score: 177.31088
- Similarity Product: 129.01488008857726

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test