PATENT CLAIM ANALYSIS

Application Number: 16012858
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["341", "126000"]

Abstract:
A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.

Claim (Index 7):
The multi-Nyquist zone digital-to-analog device of  claim 6  wherein the D/A stage comprises:\n a deinterleaver having a signal input to accept the digital input signal, a clock input to accept the first clock signal, and an output to supply N deinterleaved digital values; \n a bank of N digital-to-analog converters (DACs), each DAC having a signal input to accept a corresponding deinterleaved digital value, a clock input to accept the second clock signal, and a signal output to supply a corresponding deinterleaved analog value; \n wherein the upsampling stage comprises:\n a bank of N first sample-and-hold (S/H) circuits, each first S/H circuit having an input to accept a corresponding deinterleaved analog value, a control port to accept the second clock signal, and an output to supply a corresponding sampled analog value; \n a delay-locked loop having an input to accept the second clock signal, and an output to supply the N phases of the clock frequency; \n a bank of N current impulse (CI) DACs, each CI DAC having an input to accept a corresponding sampled analog value, a control port to accept the second clock signal, and an output to supply a corresponding impulse signal; \n a bank of N second S/H circuits, each second S/H circuit having an input to accept a corresponding impulse signal, a control port to accept a corresponding second clock phase, and an output to supply a corresponding sampled impulse signal; and, \n an interleaver having an input to accept the N sampled impulse signals and an output to supply the analog output signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.64516
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15787298', '15964186', '15673228', '14750203', '14927077']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6212010826990606
- 35 USC 102 Novelty (BERT): 0.6485715876037809
- Combined Prediction Score: 0.6239381331895327
- Mean Citation Score: 415.783656
- Max Citation Score: 626.922
- Similarity Product: 556.8097279028892

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test