PATENT CLAIM ANALYSIS

Application Number: 15938207
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["257", "751000"]

Abstract:
An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for fabricating the structure is described.

Claim (Index 15):
The method as recited in  claim 10 , wherein the first high modulus layer in the first level is different than the second high modulus layer in the second level, and each high modulus layer is selected according to the ILD in the respective level.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 2.15942
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15938155', '15387120', '15806027', '14574430', '11317042']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9219490654369528
- 35 USC 102 Novelty (BERT): 0.5396804489997851
- Combined Prediction Score: 0.883722203793236
- Mean Citation Score: 237.372654
- Max Citation Score: 386.1332
- Similarity Product: 253.30914002971645

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test