PATENT CLAIM ANALYSIS

Application Number: 15864865
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "337000"]

Abstract:
An LDMOS device includes a handle portion having a buried dielectric layer and a semiconductor layer thereon doped a second dopant type. A drift region doped a first type is within the semiconductor layer providing a drain extension. A gate stack includes a gate electrode on a gate dielectric layer on respective sides of a junction with the drift region. A DWELL region is within the semiconductor layer. A source region doped the first type is within the DWELL region. A drain region doped the first type is within the drift region. A first partial buried layer doped the second type is in a first portion of the drift region including under the gate electrode. A second partial buried layer doped the first type is in a second portion of the drift region including under the drain.

Claim (Index 27):
The device of  claim 19 , further comprising a source region within said substrate, wherein a portion of said body region and a portion of said drift region are located between said source region and said drain region.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 3.29545
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15009017', '15257243', '14974951', '15362962', '14671572']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9285993422926688
- 35 USC 102 Novelty (BERT): 0.5688578821504335
- Combined Prediction Score: 0.8926251962784452
- Mean Citation Score: 354.969948
- Max Citation Score: 560.2277
- Similarity Product: 337.09599048864845

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test