PATENT CLAIM ANALYSIS

Application Number: 15916241
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["257", "326000"]

Abstract:
A semiconductor device of the present invention includes: an element isolation part which is disposed between fins and whose height is lower than the height of each fin; a memory gate electrode placed over the fins and the element isolation part with a memory gate insulating film having a charge storage part in between; and a control gate electrode disposed in line with the memory gate electrode. The height of the element isolation part below the memory gate electrode is higher than the height of the element isolation part below the control gate electrode. A mismatch between electron injection and hole injection is improved, rewriting operation speed is accelerated, and reliability is enhanced by making the height of the element isolation part below the memory gate electrode higher than the height of the element isolation part below the control gate electrode as mentioned above.

Claim (Index 13):
The manufacturing method for a semiconductor device according to  claim 12 ,\n wherein the first film at the step (d) is formed by thermal oxidation, and wherein the isolation insulating film at the step (b) is formed by CVD.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 2.45161
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15669814', '12910788', '15914837', '15879257', '15482239']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9189044558910155
- 35 USC 102 Novelty (BERT): 0.5137777581264771
- Combined Prediction Score: 0.8783917861145617
- Mean Citation Score: 271.457866
- Max Citation Score: 287.96863
- Similarity Product: 227.25367113701336

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test