PATENT CLAIM ANALYSIS

Application Number: 16050094
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "410000"]

Abstract:
A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Claim (Index 20):
A semiconductor device, comprising:\n a gate dielectric layer located over a substrate, wherein the gate dielectric layer includes a material having a dielectric constant that is greater than a dielectric constant of SiO 2 ; a capping layer located over the gate dielectric layer, wherein the capping layer includes a rare earth oxide material; a gate electrode located over the capping layer, wherein the gate electrode includes one or more metal material, wherein an upper portion of the gate electrode is at least as wide as a lower portion of the gate electrode; and fluorine-containing particles disposed over the substrate.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 95.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15420580', '15235899', '15642559', '13438451', '13328382']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9104851123117716
- 35 USC 102 Novelty (BERT): 0.4934569048985047
- Combined Prediction Score: 0.8687822915704448
- Mean Citation Score: 189.532452
- Max Citation Score: 252.965
- Similarity Product: 200.83977286100392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test