PATENT CLAIM ANALYSIS

Application Number: 15923864
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "003000"]

Abstract:
Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Claim (Index 30):
The method of  claim 22  wherein the structure is a third assembly, and wherein the forming of the structure comprises:\n forming first trenches within a mass of the first semiconductor material; the first trenches extending along the second direction; a base of the first semiconductor material remaining under the first trenches; the first trenches having sidewalls along the semiconductor material walls; \n forming insulative steps along bottoms of the first trenches; \n forming the second conductive material within the first trenches and over the insulative steps; the second conductive material being configured as conductive beams having upwardly-opening container shapes; \n forming the insulative regions within the first trenches and over the conductive beams; \n forming the first conductive lines to extend across the insulative regions and across the semiconductor material walls; \n forming second trenches between the first conductive lines; the second trenches extending into the semiconductor material walls to a level which is above a top level of the upwardly-opening container-shaped conductive beams; \n forming an insulative mass which fills the second trenches and covers the first conductive lines; the insulative mass having an upper surface comprising a first dielectric bonding material; a first assembly comprising the insulative mass, the first semiconductor material, the first conductive lines and the conductive beams; \n forming a second assembly comprising a second dielectric bonding material over the second semiconductor material; \n inverting the first assembly and bonding the first dielectric bonding material with the second dielectric bonding material to form the dielectric bonding region, and to form the third assembly to comprise the first assembly bonded to the second assembly through the dielectric bonding region; wherein an upper surface of the third assembly comprises the base of the first semiconductor material; and \n polishing said upper surface of the third assembly to remove the base of the first semiconductor material.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 2.86792
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14226643', '15064002', '15650274', '15391604', '13765643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8592220433324332
- 35 USC 102 Novelty (BERT): 0.4944687836927086
- Combined Prediction Score: 0.8227467173684608
- Mean Citation Score: 219.374328
- Max Citation Score: 225.80673
- Similarity Product: 158.16828977211176

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test