PATENT CLAIM ANALYSIS

Application Number: 16149261
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-01
Patent Classification: ["365", "185120"]

Abstract:
Memory devices include a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line.

Claim (Index 16):
The memory device of  claim 11 , further comprising a data latch connected to a node between the first transistor and the second transistor.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 97.0
- Lexical Diversity: 2.13636
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16021306', '15019175', '16021250', '15191786', '15692565']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8013892090687249
- 35 USC 102 Novelty (BERT): 0.4935350890476038
- Combined Prediction Score: 0.7706037970666129
- Mean Citation Score: 252.319582
- Max Citation Score: 297.2899
- Similarity Product: 280.262533200407

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test