PATENT CLAIM ANALYSIS

Application Number: 16183603
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["712", "008000"]

Abstract:
The present disclosure provides a data read-write scheduler and a reservation station for vector operations. The data read-write scheduler suspends the instruction execution by providing a read instruction cache module and a write instruction cache module and detecting conflict instructions based on the two modules. After the time is satisfied, instructions are re-executed, thereby solving the read-after-write conflict and the write-after-read conflict between instructions and guaranteeing that correct data are provided to a vector operations component. Therefore, the subject disclosure has more values for promotion and application.

Claim (Index 9):
The data write scheduler of  claim 8 , wherein the write instruction cache unit is further configured to:\n update the status of the vector write instruction to indicate that the vector write instruction is to be transmitted based on a determination that a new vector write instruction enters a queue of the write instruction cache unit, update the status of the vector write instruction to indicate that the vector write instruction is transmittable based on a determination that the dependent vector read instruction is being executed or has been executed, transmit the vector write instruction and update the status of the vector write instruction to indicate that the vector write instruction is being executed based on a determination\n that an immediately preceding vector write instruction has been transmitted, and \n that a previous status of the vector write instruction indicates that the vector write instruction is transmittable, \n update the status of the vector write instruction to indicate that the vector write instruction is transmitted after the write requests of the vector write instruction have been transmitted by the write control module, and update the status of the vector write instruction to indicate that the vector write instruction is executed based on a determination that all of the write requests of the vector write instruction have been processed by the on-chip RAM, and that the feedback is received from the on-chip RAM.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 98.0
- Lexical Diversity: 1.64912
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16183612', '16039605', '14335029', '12082971', '14575103']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.622300481663604
- 35 USC 102 Novelty (BERT): 0.5689051837848663
- Combined Prediction Score: 0.6169609518757302
- Mean Citation Score: 299.440904
- Max Citation Score: 464.2825
- Similarity Product: 408.1009174361825

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test