PATENT CLAIM ANALYSIS

Application Number: 15954133
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "369000"]

Abstract:
A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

Claim (Index 17):
A semiconductor structure for constructing a transistor having reduced parasitic contact resistance, the semiconductor structure comprising:\n a first device disposed over a semiconductor structure; a second device disposed adjacent the first device, the first and second devices separated from each other by a sidewall trench isolation (STI) structure; an interlayer dielectric (ILD) disposed over the first and second devices; recesses disposed within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device; a first dielectric layer disposed over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers disposed over the source/drain regions of the second device; and an epitaxial layer disposed over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 91.0
- Lexical Diversity: 2.83019
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15437840', '15804215', '15914096', '15455659', '15466358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9283921532130724
- 35 USC 102 Novelty (BERT): 0.5226021346892847
- Combined Prediction Score: 0.8878131513606937
- Mean Citation Score: 317.786384
- Max Citation Score: 342.77057
- Similarity Product: 269.0637716981709

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test