PATENT CLAIM ANALYSIS

Application Number: 15922541
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "368000"]

Abstract:
A semiconductor device includes a first substrate having a first surface and a second surface opposite to the first surface, a shallow trench isolation in the first substrate, the shallow trench isolation having a first depth, the first depth being a distance from a bottom of the shallow trench isolation to the first surface of the first substrate, a transistor on the first surface of the first substrate, a first dielectric cap layer covering the first surface of the first substrate, a first interconnect structure on the first dielectric cap layer, a carrier substrate bonded to the first substrate through the first dielectric cap layer, a second dielectric cap layer on the second surface of the first substrate; and a through silicon via extending through the second dielectric cap layer, the shallow trench isolation, and the first dielectric cap layer, and connected to the first interconnect structure.

Claim (Index 8):
An electronic apparatus comprising:\n a semiconductor device; and an electronic component assembly coupled to the semiconductor device; wherein the semiconductor device is formed by the following steps:\n providing a first substrate; \n from a first surface of the first substrate, forming a shallow trench isolation in the first substrate, the shallow trench isolation having a pad layer at a first depth, the first depth being a distance from a bottom of the shallow trench isolation to the first surface of the first substrate; \n forming at least one transistor on the first surface of the first substrate, the at least one transistor having a source/drain region at a seven depth, the seventh depth being a distance from the bottom of the source/drain region to the first surface of the first substrate; \n forming a first dielectric cap layer covering the first surface of the first substrate; \n forming a first interconnect structure on the first dielectric cap layer; \n providing a carrier substrate; \n bonding the carrier substrate to the first substrate through the first dielectric cap layer; \n from a second surface of the first substrate opposite to the first surface, thinning the first substrate to the first depth to expose a surface of the pad layer; \n after thinning the first substrate from the second surface, removing a portion of the first substrate from the second surface below the at least one transistor to a fifth depth lower than the first depth using a wet etching process, the fifth depth being a distance from the second surface to the first surface of the first substrate after removing the portion of the first substrate from the second surface below the at least one transistor, the fifth depth being greater than the seventh depth; \n forming a second dielectric cap layer on the second surface of the first substrate covering the exposed surface of the pad layer of the shallow trench isolation and the portion of the first substrate below the at least one transistor having the fifth depth below the first depth; \n forming a through silicon via (TSV), the TSV running through the second dielectric cap layer, the shallow trench isolation, and the first dielectric cap layer, and connected to the first interconnect structure; and \n forming a second interconnect structure on the second dielectric cap layer connected to the through silicon via.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 3.80952
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14996091', '11950001', '13732806', '13191540', '14084597']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916690477557958
- 35 USC 102 Novelty (BERT): 0.5110776652038939
- Combined Prediction Score: 0.8761291963225515
- Mean Citation Score: 242.9231
- Max Citation Score: 324.79672
- Similarity Product: 315.2479510157633

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test