PATENT CLAIM ANALYSIS

Application Number: 15915147
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Claim (Index 5):
The memory system of  claim 2 , wherein the memory controller sets memory blocks by grouping the corresponding pages of the respective memory banks using one physical block address.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 90.0
- Lexical Diversity: 1.92105
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15726460', '15618597', '15426298', '13954135', '11771531']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.563708308014167
- 35 USC 102 Novelty (BERT): 0.5038950565305792
- Combined Prediction Score: 0.5577269828658082
- Mean Citation Score: 240.388434
- Max Citation Score: 265.9842
- Similarity Product: 188.7978694397449

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test