PATENT CLAIM ANALYSIS

Application Number: 15864371
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["708", "603000"]

Abstract:
An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

Claim (Index 16):
The arithmetic logic unit of  claim 14 , wherein the first logic circuit is configured so that the output of first and second AND gates are the two inputs of a first OR gate, and the output of the first OR gate is a first input to a third AND gate and the output of a NAND gate is connected as one input to a second OR gate and the output of the second OR gate is the second input to the third AND gate, and the output of the third AND gate is connected as the first input to an Exclusive OR gate.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.73913
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10893163', '10406046', '10035033', '11506283', '11760553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4869733689785501
- 35 USC 102 Novelty (BERT): 0.5086371202818369
- Combined Prediction Score: 0.4891397441088788
- Mean Citation Score: 248.514394
- Max Citation Score: 261.6972
- Similarity Product: 188.6591490840912

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test