PATENT CLAIM ANALYSIS

Application Number: 15982934
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "077000"]

Abstract:
In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.

Claim (Index 12):
The power semiconductor device of  claim 1 , wherein the conductive gate electrode includes at least one of doped polysilicon, a metal and a silicide.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 93.0
- Lexical Diversity: 3.05769
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15158214', '15858406', '15275184', '14744958', '13600184']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9363953693618308
- 35 USC 102 Novelty (BERT): 0.5622500581662375
- Combined Prediction Score: 0.8989808382422715
- Mean Citation Score: 318.130824
- Max Citation Score: 438.38507
- Similarity Product: 396.0601726832669

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test