PATENT CLAIM ANALYSIS

Application Number: 15865858
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["365", "230030"]

Abstract:
Disclosed is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform an erase characteristic check operation and an erase operation on the plurality of memory blocks. The semiconductor memory device also includes a control logic configured to control the peripheral circuit to perform the erase characteristic check operation and the erase operation, determine whether each of the plurality of memory blocks has a normal erase characteristic or an overerase characteristic according to a result of the erase characteristic check operation for each of the plurality of memory blocks, and set an erase voltage of the erase operation.

Claim (Index 11):
The semiconductor memory device of  claim 9 , wherein the control logic controls the peripheral circuit to perform a program operation of programming the data in a plurality of CAM Cells of the selected memory block.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 86.0
- Lexical Diversity: 2.68085
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15642606', '15340957', '15641485', '15263773', '15259262']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8035049729553225
- 35 USC 102 Novelty (BERT): 0.5128046378993086
- Combined Prediction Score: 0.7744349394497212
- Mean Citation Score: 276.798678
- Max Citation Score: 289.53802
- Similarity Product: 200.4405677724886

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test