PATENT CLAIM ANALYSIS

Application Number: 15777086
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "296000"]

Abstract:
Embodiments of the present disclosure describe an integrated circuit that may include a first transistor on a first side of a semiconductor substrate and a second transistor on a second side of the semiconductor substrate, wherein the second side is opposite and parallel to the first side. In embodiments, the integrated circuit may further include a first capacitor positioned on the first side of the semiconductor substrate and coupled to the first transistor to form a first memory cell, and a second capacitor positioned on the second side of the semiconductor substrate and coupled to the second transistor to form a second memory cell.

Claim (Index 14):
The method  claim 13  wherein the first and second transistors each includes a source region and a drain region with a gate length between the source region and the drain region and wherein the method further includes forming the first transistor with a first gate length and forming the second transistor with a second gate length that is the same as the first gate length.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.94595
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15213529', '15240799', '10245283', '14434559', '13348142']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8976558170727102
- 35 USC 102 Novelty (BERT): 0.462371543600848
- Combined Prediction Score: 0.854127389725524
- Mean Citation Score: 134.33673399999998
- Max Citation Score: 138.54886000000002
- Similarity Product: 111.3735079321158

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test