PATENT CLAIM ANALYSIS

Application Number: 15913819
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["716", "121000"]

Abstract:
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Claim (Index 7):
The method as recited in  claim 5 , wherein the first index distance is zero and the second index distance is zero.

Metadata:
- Claim Count in Document: 58.0
- Percentile: 90.0
- Lexical Diversity: 2.5283
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12497052', '14605946', '13540529', '15243748', '14040590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4764716970210201
- 35 USC 102 Novelty (BERT): 0.5217784748419054
- Combined Prediction Score: 0.4810023748031087
- Mean Citation Score: 387.149236
- Max Citation Score: 401.93552
- Similarity Product: 201.4103457541848

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test