PATENT CLAIM ANALYSIS

Application Number: 16250290
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["710", "110000"]

Abstract:
A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

Claim (Index 12):
A method of operating a memory module including a master memory device, slave memory devices, a back channel bus coupling the master memory device to the slave memory devices, and an external command/address bus coupling the memory module to an external device, the method comprising:\n generating, by the master device, a back channel clock signal; outputting, by the master device, the back channel clock signal through the back channel bus to the slave memory devices; receiving, by the master memory device, device information from each of the slave memory devices through the back channel bus; determining, by the master memory device, which of the slave memory devices need refreshing based on the device information received from each of the slave memory devices; generating, by the master memory device, a refresh command in accordance with a result of the determining that at least one of the slave memory devices need refreshing; outputting, by the master memory device, the refresh command through the back channel bus to the at least one of the slave memory devices that were determined to need refreshing; and receiving, by the master memory device and/or by one of the slave memory devices, an external command and address from the external device through the external command/address bus, wherein, upon receiving the refresh command, the slave memory devices start executing the refresh command at substantially same time with reference to the back channel clock signal.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 99.0
- Lexical Diversity: 2.88889
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14976865', '15691828', '14959773', '14959003', '14083033']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6240819962281412
- 35 USC 102 Novelty (BERT): 0.5581159548586664
- Combined Prediction Score: 0.6174853920911938
- Mean Citation Score: 245.250434
- Max Citation Score: 426.78226
- Similarity Product: 368.6478722172666

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test