PATENT CLAIM ANALYSIS

Application Number: 16244025
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["327", "175000"]

Abstract:
Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.

Claim (Index 2):
The clock distribution circuitry according to  claim 1 , wherein the control circuitry comprises low-pass filter circuitry, configured to receive the output clock signal or another clock signal from along the clock path and to output the measurement signal, the measurement signal being indicative of a DC-level of the output clock signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 99.0
- Lexical Diversity: 2.72881
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16244002', '16008640', '13392638', '16008678', '14207751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7958069237307358
- 35 USC 102 Novelty (BERT): 0.4948616330718948
- Combined Prediction Score: 0.7657123946648517
- Mean Citation Score: 235.526696
- Max Citation Score: 262.1823
- Similarity Product: 204.41754913494583

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test