PATENT CLAIM ANALYSIS

Application Number: 16217122
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["345", "213000"]

Abstract:
A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Claim (Index 6):
A display device comprising:\n a plurality of pixels a plurality of scanning signal lines supplying a scanning signal to the plurality of pixels respectively, a driving circuit sequentially applying the scanning signal from one ends of the plurality of scanning signal lines, a plurality of output circuits outputting the scanning signal to the plurality of scanning signal lines, and including a first output circuit and a second output circuit, a first clock signal line supplying a first clock signal to a first output circuit, and a second clock signal line supplying a second clock signal to a second output circuit, wherein the first output circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein the first transistor has a gate connecting to a first node, an input electrode connecting the first clock signal line, and an output electrode connecting to the first scanning signal line, wherein the first node becomes an active potential during an output period including a period in which the scanning signal is applied to the corresponding scanning signal line, wherein the second transistor has a gate applying the second clock, an input electrode connecting an inactive potential, and an output electrode connecting the first node. wherein the third transistor has a gate applying the second clock, an input electrode connecting the inactive potential, and an output electrode connecting the scanning signal line, wherein the fourth transistor has a gate applying an output of the second output circuit and an input electrode connecting the inactive potential and an output electrode connecting the first node, wherein the fifth transistor has a gate connecting the first node and an output electrode connecting the second node and an input electrode applying the second clock, and wherein the second clock signal has an active potential at the time of termination of the output period and the inactive potential during the output period of the first output circuit.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 3.02128
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14883338', '15358209', '14161723', '15097414', '16172003']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6435279306811045
- 35 USC 102 Novelty (BERT): 0.5311878007548041
- Combined Prediction Score: 0.6322939176884744
- Mean Citation Score: 310.1011220000001
- Max Citation Score: 354.85666000000015
- Similarity Product: 325.79178423243303

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test