PATENT CLAIM ANALYSIS

Application Number: 15890595
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A memory device includes a memory including first and second pages in first and second banks, respectively, an address decoder mapping command addresses to physical addresses. The memory device further includes circuitry configured to maintain a status indicating a most recently written page, decode received command sequences including command addresses and implementing an operation including (i) responsive to receiving a command sequence including a read command address that is pre-configured for reading data, causing the address decoder to map the read command address to one of the first and second pages selected according to the status, and (ii) responsive to receiving a second command sequence including a write command address that is pre-configured for writing data, causing the address decoder to map the write command address to one of the first and second pages selected according to the status.

Claim (Index 1):
A memory device, comprising:\n a memory configured with pages, the pages including a first set of pages including a first page in a first bank and a second page in a second bank; an address decoder that maps received command addresses to physical addresses of pages and banks of the memory; and control circuitry configured to maintain a status indicating a most recently written page of the first set of pages, to decode received command sequences that comprise the command addresses, to execute operations identified in the command sequences, and to implement an operation including:\n responsive to receiving a first command sequence including a read command address that is pre-configured for reading data from the first set of pages, causing the address decoder to map the read command address to one of the first page in the first bank and the second page in the second bank selected in response to the status; and \n responsive to receiving a second command sequence including a write command address that is pre-configured for writing to the first set of pages, causing the address decoder to map the write command address to one of the first page in the first bank and the second page in the second bank selected in response to the status.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 2.43548
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15868896', '15290339', '12113709', '12093661', '14852890']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5295395451889333
- 35 USC 102 Novelty (BERT): 0.490219392686954
- Combined Prediction Score: 0.5256075299387354
- Mean Citation Score: 209.347564
- Max Citation Score: 219.74057
- Similarity Product: 152.84903296964168

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test