PATENT CLAIM ANALYSIS

Application Number: 15980635
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "139000"]

Abstract:
In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.

Claim (Index 18):
A method of manufacturing a semiconductor device comprising:\n a step of forming a trench on an upper surface of a semiconductor substrate including a first semiconductor layer of a first conductivity type; a step of forming a trench insulating film on an inner surface of the trench; a step of forming a trench electrode inside the trench on which the trench insulating film is formed; a step of forming, on the semiconductor substrate, a floating layer of a second conductivity type placed on the first semiconductor layer and where a lower end of the trench electrode reaches, a barrier layer of the first conductivity type placed on the floating layer, a second semiconductor layer of the second conductivity type placed on the barrier layer, and a third semiconductor layer of the first conductivity type placed on the second semiconductor layer in such a way that the third semiconductor layer, the second semiconductor layer and the barrier layer are separated from the first semiconductor layer by the floating layer; a step of forming a through groove running through an inter-layer insulating layer formed on the semiconductor substrate; and a step of forming, on the inter-layer insulating layer, a line layer connecting to the second semiconductor layer through the through groove.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 93.0
- Lexical Diversity: 2.95918
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15955819', '15706403', '13470473', '15411268', '15145712']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916436311634624
- 35 USC 102 Novelty (BERT): 0.4798712537175078
- Combined Prediction Score: 0.8727798058429124
- Mean Citation Score: 214.4679
- Max Citation Score: 226.38156
- Similarity Product: 187.5992021981192

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test