PATENT CLAIM ANALYSIS

Application Number: 16103475
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-04
Patent Classification: ["323", "312000"]

Abstract:
A sense resistor is placed in series with an output capacitor of a buck converter. The buck converter operates in a discontinuous mode such that there is a dead time in each switching cycle. A control circuit senses a voltage across the sense resistor and thereby generates a first signal I CS . The control circuit detects an offset voltage in I CS , where the offset voltage is the voltage of I CS  during the dead time in a first switching cycle. The control circuit level shifts the entire I CS  by the offset voltage, thereby generating a second signal I CLS . I CLS  has the same waveform as the waveform of the inductor current. In a second cycle, I CLS  is used to determine when to turn off the main switch and when the start of the dead time occurs. I CLS  and the offset voltage are used together to determine when to turn the main switch on.

Claim (Index 1):
A method comprising:\n (a) using an analog amplifier to amplify a voltage signal between a first input terminal and a second input terminal thereby generating a first analog signal, wherein the voltage signal is a voltage signal across a resistor during first and second switching cycles of a buck converter; (b) using an offset detector to detect an offset voltage in the first analog signal; (c) using a level shift circuit to level shift the first analog signal by the offset voltage thereby generating a second analog signal, wherein the second analog signal is a level-shifted version of the first analog signal; (d) detecting when the second analog signal exhibits a first characteristic during the second switching cycle; (e) in response to the detecting of (d) deasserting a first output signal onto a first output terminal, wherein the deasserting of the first output signal causes a main switch to turn off during the second switching cycle; (f) detecting when the second analog signal exhibits a second characteristic during the second switching cycle; (g) in response to the detecting of (f) asserting a second output signal onto a second output terminal; (h) receiving an input trigger signal onto an input terminal, wherein the input trigger signal is received during the second switching cycle; and (i) in response to the receiving of (h) asserting the first output signal, wherein the asserting of the first output signal causes the main switch to turn on at the end of the second switching cycle.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 96.0
- Lexical Diversity: 2.31507
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15693494', '14474132', '14607684', '13444308', '13332343']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7295257556728937
- 35 USC 102 Novelty (BERT): 0.5200127881987926
- Combined Prediction Score: 0.7085744589254835
- Mean Citation Score: 254.621162
- Max Citation Score: 355.0163
- Similarity Product: 349.4312293200314

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test