PATENT CLAIM ANALYSIS

Application Number: 15896365
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "189050"]

Abstract:
According to one embodiment, a semiconductor memory device includes: a first memory cell; a first latch circuit; and a second latch circuit. The first latch circuit and the second latch circuit are associated with the first memory cell. When the semiconductor memory device receives, from an external device, a first address designating one of the first latch circuit and the second latch circuit and a read command for data of the first memory cell, data is read from the first memory cell and the read data is held in the one of the first latch circuit and the second latch circuit corresponding to the first address.

Claim (Index 15):
A semiconductor memory device comprising:\n a first memory cell capable of storing data; and a first latch circuit associated with the first memory cell, wherein when first operation information for designating an operation and a read command for reading data in the first memory cell are received from an external device, data is read from the first memory cell, an operation based on the first operation information is executed for the read data, and a result of the operation is held in the first latch circuit.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 88.0
- Lexical Diversity: 2.9
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15455419', '15459294', '14023187', '14918036', '15195560']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7621406821517602
- 35 USC 102 Novelty (BERT): 0.4984771294493242
- Combined Prediction Score: 0.7357743268815167
- Mean Citation Score: 216.198756
- Max Citation Score: 238.50389
- Similarity Product: 163.85913266777575

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test