PATENT CLAIM ANALYSIS

Application Number: 15767666
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["327", "109000"]

Abstract:
Provided is a technique for a stably operable complementary single ended push pull (SEPP) circuit. A buffer circuit includes the following: an NPN transistor and a PNP transistor that constitute a complementary SEPP circuit; a first resistor; a second resistor; a first load element having one end connected to a gate of a semiconductor switching element and another end connected to a base of the NPN transistor; and a second load element having one end connected to the gate of the semiconductor switching element and another end connected to a base of the PNP transistor.

Claim (Index 5):
The buffer circuit according to  claim 4 ,\n wherein the one end of the resistor, which is the first load element, is connected not to the gate, but to a first connection point at which the emitter of the NPN transistor is connected to the first resistor, and wherein the one end of the resistor, which is the second load element, is connected not to the gate, but to a second connection point at which the emitter of the PNP transistor is connected to the second resistor.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.21277
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14897392', '13028675', '10805040', '15671932', '10713140']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.797618569895166
- 35 USC 102 Novelty (BERT): 0.4954412156773551
- Combined Prediction Score: 0.7674008344733849
- Mean Citation Score: 239.923036
- Max Citation Score: 263.54007
- Similarity Product: 204.78538704028847

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test