PATENT CLAIM ANALYSIS

Application Number: 15927688
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

Claim (Index 18):
The method of  claim 17 , wherein each of the drain regions contacts a top end of a respective drain select level channel portions and a respective one of the memory level channel portion.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 90.0
- Lexical Diversity: 2.22222
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15354067', '15888714', '15818146', '15876884', '15906109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9341545608550608
- 35 USC 102 Novelty (BERT): 0.5653252530031597
- Combined Prediction Score: 0.8972716300698705
- Mean Citation Score: 412.425296
- Max Citation Score: 473.56152
- Similarity Product: 317.10673420497886

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test