PATENT CLAIM ANALYSIS

Application Number: 15905020
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "185180"]

Abstract:
According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.

Claim (Index 17):
The semiconductor memory device according to  claim 16 , wherein the first circuit is directly connected to the second circuit by the first bus.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 88.0
- Lexical Diversity: 3.12821
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14015980', '10409120', '11531082', '13152692', '12040155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.790563605172591
- 35 USC 102 Novelty (BERT): 0.4783814900892707
- Combined Prediction Score: 0.7593453936642591
- Mean Citation Score: 136.933304
- Max Citation Score: 139.8387
- Similarity Product: 88.77515191944836

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test