PATENT CLAIM ANALYSIS

Application Number: 16000196
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["710", "108000"]

Abstract:
A fault-tolerant process control system includes a first and second master process controller, each including a first and second serial communication engine. A first bus switch couples the first serial communication engine to a shared SPI bus and a second bus switch couples the second communication engine to shared SPI bus. The shared SPI bus transmits SPI signals received from the first serial communication engine when the first bus switch is enabled to a first target device, and transmits SPI signals received from the second serial communication engine when the second bus switch is enabled to a second target device. An arbiter block receives a select control signal from the master process controllers and is coupled to both the first and second bus switch for single bus switch selection so that only one master process controller is granted access to the shared SPI bus.

Claim (Index 1):
A fault-tolerant process control system, comprising:\n a first master process controller including a first processor including first memory and a first serial communication engine; at least a second master process controller connected in parallel to said first master process controller including a second processor including second memory and a second serial communication engine; a first bus switch coupling said first serial communication engine to a shared Serial Peripheral Interface (SPI) bus including a plurality of SPI lines and a second bus switch coupling said second serial communication engine to said shared SPI bus, wherein said shared SPI bus transmits SPI signals received from said first serial communication engine when said first bus switch is enabled to at least a first target device, and transmits SPI signals received from said second serial communication engine when said second bus switch is enabled to at least a second target device, and an arbiter block having an input coupled to receive a select control signal from both said first and second master process controllers that is coupled to both said first bus switch and to said second bus switch for single bus switch selection, wherein at any time only one of said first master process controller and said second master process controller is granted access to said shared SPI bus.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 94.0
- Lexical Diversity: 2.77778
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13569309', '13453169', '15995303', '12057326', '11096941']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6676642084983512
- 35 USC 102 Novelty (BERT): 0.4906672376134313
- Combined Prediction Score: 0.6499645114098592
- Mean Citation Score: 199.449456
- Max Citation Score: 250.1249
- Similarity Product: 190.6544117736101

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test