PATENT CLAIM ANALYSIS

Application Number: 15889161
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["257", "775000"]

Abstract:
A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction.

Claim (Index 1):
A semiconductor memory device, comprising:\n a semiconductor substrate; bit line structures disposed on the semiconductor substrate, wherein each of the bit line structures is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction; storage node contacts disposed on the semiconductor substrate, wherein each of the storage node contacts is disposed between two of the bit line structures disposed adjacent to each other in the second direction; and isolation structures disposed on the semiconductor substrate, wherein each of the isolation structures is disposed between two of the bit line structures disposed adjacent to each other in the second direction, each of the storage node contacts is disposed between two of the isolation structures disposed adjacent to each other in the first direction, and each of the isolation structures comprises two first portions and a second portion disposed between the two first portions in the second direction, wherein each of the first portions is elongated in the first direction and partially disposed between one of the bit line structures disposed adjacent to the isolation structure and one of the storage node contacts disposed adjacent to the isolation structure in the second direction, wherein each of the first portions is disposed between the second portion and one of the bit line structures disposed adjacent to the isolation structure in the second direction.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 88.0
- Lexical Diversity: 3.52273
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15479294', '15458946', '15590023', '13732353', '15859756']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9193856558422278
- 35 USC 102 Novelty (BERT): 0.5027064342427645
- Combined Prediction Score: 0.8777177336822815
- Mean Citation Score: 243.45493
- Max Citation Score: 293.6077
- Similarity Product: 251.5775209718228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test