PATENT CLAIM ANALYSIS

Application Number: 15983621
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "676000"]

Abstract:
A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.

Claim (Index 1):
A semiconductor device package, comprising:\n a die pad comprising a die attach surface and an outer surface opposite the die attach surface; a semiconductor die mounted on the die attach surface; an encapsulant material that encapsulates the semiconductor die and exposes the outer surface of the die pad at an upper side of the encapsulant material; a first lead that directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material that is opposite the upper side; and a second lead that is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material that is opposite the first sidewall, and bends towards the lower side of the encapsulant material; wherein a first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall wherein an area of the die pad is larger than the semiconductor die, and wherein the semiconductor die is mounted on the die pad such that semiconductor die is completely contained within an outer periphery of the die pad.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.92
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10847955', '10702274', '13714023', '11123463', '15727725']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9225968937804369
- 35 USC 102 Novelty (BERT): 0.4867307150906096
- Combined Prediction Score: 0.8790102759114541
- Mean Citation Score: 244.872988
- Max Citation Score: 263.69894
- Similarity Product: 238.05700413837792

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test