PATENT CLAIM ANALYSIS

Application Number: 16064454
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "072000"]

Abstract:
A semiconductor device ( 1001 ) includes a first thin film transistor ( 201 ) including a first semiconductor layer ( 3 A), a gate insulating layer ( 5 ), a first gate electrode ( 7 A) provided on the gate insulating layer ( 5 ), and first source and drain electrodes ( 8 A), ( 9 A), the first semiconductor layer ( 3 A) including a first channel region ( 30 A) and a first high-density impurity region ( 33 s A), ( 33 d A) containing an impurity of a first conductivity type. The first channel region ( 30 A) includes a first channel portion ( 31 A) and a second channel portion ( 32 A) located between the first channel portion and the first high-density impurity region. The first channel portion ( 31 A) contains an impurity of a second conductivity type that is different from the first conductivity type at a density higher than that in the second channel portion ( 32 A) and the impurity of the first conductivity type at a density substantially equal to that in the second channel portion ( 32 A).

Claim (Index 15):
A method for manufacturing a semiconductor device including at least one first thin film transistor and at least one second thin film transistor having a different conductivity type from the first thin film transistor, the method comprising:\n (a) a step for forming, on a substrate, a first semiconductor layer in a form of an island to serve as an active region of the first thin film transistor and a second semiconductor layer in a form of an island to serve as an active region of the second thin film transistor; (b) a step for forming a gate insulating layer covering the first and second semiconductor layers; (c) a step for forming a first gate electrode to overlap with a region to serve as a channel region in the first semiconductor layer with the gate insulating layer interposed therebetween and forming a second gate electrode to overlap with a region to serve as a channel region in the second semiconductor layer with the gate insulating layer interposed therebetween; (d) a step for doping a region in the first semiconductor layer not covered with the first gate electrode with an impurity of a first conductivity type to form a first high-density impurity region; and (e) a step for doping a region in the second semiconductor layer not covered with the second gate electrode with an impurity of a second conductivity type to form a second high-density impurity region, further comprising: between the step (a) and the step (c), a channel doping step (f 1 ) for doping a part of a region to serve as the channel region in the first semiconductor layer with the impurity of the second conductivity type to form a first channel portion in the first semiconductor layer, wherein, in the region to serve as the channel region in the first semiconductor layer, a region not doped with the impurity of the second conductivity type in the step (f 1 ) becomes a second channel portion, and wherein the second channel portion in the first semiconductor layer contains the impurity at a density that is substantially equal to a density of the impurity in the channel region in the second semiconductor layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 3.27692
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15569283', '11305212', '13125774', '14119407', '10913415']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913953904979168
- 35 USC 102 Novelty (BERT): 0.5126884714479749
- Combined Prediction Score: 0.8738273616260487
- Mean Citation Score: 287.183196
- Max Citation Score: 298.70758
- Similarity Product: 245.6989106219649

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test