PATENT CLAIM ANALYSIS

Application Number: 16074450
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["438", "618000"]

Abstract:
A technique, comprising: forming a stack comprising a semiconductor layer for providing the semiconductor channels of one or more transistors, and an insulator layer; and patterning the stack so as to form in a single process both: (i) one or more interconnection holes for connecting a conductor level on one side of the stack to a conductor level on the opposite side of the stack; and (ii) one or more leakage reduction trenches for reducing leakage paths via the semiconductor between conductor elements on one side of the stack.

Claim (Index 14):
The method according to  claim 12 , wherein the leakage reduction holes function solely to reduce leakage paths via the semiconductor between conductor elements on one side of the stack.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 96.0
- Lexical Diversity: 1.88679
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15327263', '15100527', '15502795', '10557623', '13631595']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8652352501404174
- 35 USC 102 Novelty (BERT): 0.5036116707697506
- Combined Prediction Score: 0.8290728922033507
- Mean Citation Score: 197.984556
- Max Citation Score: 245.11081
- Similarity Product: 169.06991861112652

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test