PATENT CLAIM ANALYSIS

Application Number: 15886539
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "329000"]

Abstract:
Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

Claim (Index 13):
The method of  claim 1 , wherein the first polymer spacers are removed by ashing.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 88.0
- Lexical Diversity: 2.51613
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15853822', '15863000', '15713975', '15843318', '15853769']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.934212407154866
- 35 USC 102 Novelty (BERT): 0.5505273139610699
- Combined Prediction Score: 0.8958438978354863
- Mean Citation Score: 392.80018
- Max Citation Score: 424.95676
- Similarity Product: 252.8569338359213

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test