PATENT CLAIM ANALYSIS

Application Number: 16025429
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-10
Patent Classification: ["365", "185170"]

Abstract:
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Claim (Index 13):
A nonvolatile semiconductor memory device, comprising:\n a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series, the nonvolatile memory cells including a first memory cell provided at one end side of the memory string, a second memory cell provided at the other end side of the memory string, and memory cells for data storage provided between the first memory cell and the second memory cell in the memory string, the first memory cell and the second memory cell being not used for data storage; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to perform a pre-program operation before an erasing operation for the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block, the control circuit being configured to execute the erasing operation by applying an erasing voltage to the NAND cell units in the block, and to execute the pre-program operation by applying a certain pre-program voltage to the memory cells for data storage in the NAND cell units, and by applying a voltage different from the certain pre-program voltage to the first memory cell and the second memory cell in the NAND cell units, at least one of the first memory cell and the second memory cell including two or more memory cells not used for data storage which are to be applied with the voltage different from the certain pre-program voltage.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 3.35556
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14945569', '14066875', '12878624', '15345585', '14295923']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8694626669514257
- 35 USC 102 Novelty (BERT): 0.6207989943440689
- Combined Prediction Score: 0.8445962996906899
- Mean Citation Score: 613.5389680000002
- Max Citation Score: 618.4624
- Similarity Product: 526.8788711812973

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test