PATENT CLAIM ANALYSIS

Application Number: 16029607
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Claim (Index 11):
The dynamic decode circuit according to  claim 1 , wherein the decoder comprises a plurality of decode transistors, wherein the decode transistors are configured to cause the first node to be in a first state based on input signals being in a first input signal state and the evaluation clock signal being active, wherein the decode transistors are configured to cause the first node to be in a second state based on the input signals being in a second input signal state other than the first input signal state and the evaluation clock signal being active.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 1.43243
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16029577', '15613185', '15796819', '16029604', '15274322']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7896151052669859
- 35 USC 102 Novelty (BERT): 0.5796483319870533
- Combined Prediction Score: 0.7686184279389927
- Mean Citation Score: 483.02547
- Max Citation Score: 489.0524
- Similarity Product: 480.199723985672

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test