PATENT CLAIM ANALYSIS

Application Number: 15913131
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185080"]

Abstract:
An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

Claim (Index 5):
The apparatus of  claim 1 , wherein the host interface includes a DMA chip select line activated by the processor when the parallel data bus is available, wherein the hybrid controller is configured to, in response to activation of the DMA chip select line, perform DMA cache data transfers including one or more of a DRAM preload, an update of one or more pages of NVM, and a read or write of cache metadata.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 2.32203
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15199802', '15252594', '15287022', '15294547', '12054310']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7934217751677999
- 35 USC 102 Novelty (BERT): 0.6265163685227375
- Combined Prediction Score: 0.7767312345032936
- Mean Citation Score: 344.183196
- Max Citation Score: 628.20465
- Similarity Product: 518.5789767092407

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test