PATENT CLAIM ANALYSIS

Application Number: 15868955
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "298000"]

Abstract:
A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

Claim (Index 11):
The DRAM device with an embedded flash memory according to  claim 10 , wherein the first transistor comprises a first gate oxide layer, the second transistor comprises a second gate oxide layer, wherein a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.48649
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13332259', '13135220', '12259032', '11050988', '12576231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922955016934893
- 35 USC 102 Novelty (BERT): 0.4877877024173208
- Combined Prediction Score: 0.8794382854831357
- Mean Citation Score: 194.978674
- Max Citation Score: 203.99953
- Similarity Product: 147.39877310542107

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test