PATENT CLAIM ANALYSIS

Application Number: 15777829
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-07
Patent Classification: ["257", "072000"]

Abstract:
An array substrate and a manufacturing method thereof, and display panel are disclosed. The array substrate includes a substrate, a thin film transistor disposed on the substrate and a common electrode disposed on a side of the thin film transistor away from the substrate. The common electrode includes a first hollowed-out portion. An active layer of the thin film transistor includes a source electrode region, a drain electrode region and a channel region. An orthographic projection of the first hollowed-out portion on the substrate at least covers an orthographic projection of the channel region on the substrate.

Claim (Index 16):
The manufacturing method according to  claim 15 , wherein, the forming the insulating layer, the common electrode, the passivation layer and the pixel electrode which are sequentially on the side of the thin film transistor away from the substrate by using the patterning process for three times specifically comprises:\n forming the insulating film layer on the substrate on which the thin film transistor has been formed; forming a common electrode film layer comprising the third via hole by using the patterning process for one time on the substrate on which the insulating film layer has been formed; etching a part of the insulating film layer located right below the third via hole by using a dry etching to form the insulating layer comprising the first via hole; forming the passivation layer comprising the second via hole and the second hollowed-out portion by using the patterning process for one time on the substrate on which the insulating layer and the common electrode film layer have been formed; forming the pixel electrode, of which the orthographic projection on substrate does not overlap with the orthographic projection of the first hollowed-out portion on the substrate, by using the patterning process for one time on the substrate on which the passivation layer has been formed, and forming the first hollowed-out portion in the common electrode film layer, thereby forming the common electrode including the third via hole and the first hollowed-out portion.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 93.0
- Lexical Diversity: 2.44186
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16080207', '15807451', '15750984', '15529495', '15568155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9291014504047626
- 35 USC 102 Novelty (BERT): 0.5199889534535288
- Combined Prediction Score: 0.8881902007096392
- Mean Citation Score: 305.86805
- Max Citation Score: 318.64468
- Similarity Product: 207.66328929896832

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test