PATENT CLAIM ANALYSIS

Application Number: 16054963
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-01
Patent Classification: ["257", "197000"]

Abstract:
A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.

Claim (Index 18):
The method of manufacturing the semiconductor structure according to  claim 12 , further comprising:\n forming a space on a sidewall of the emitter.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 96.0
- Lexical Diversity: 2.89362
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16053657', '14048131', '14525545', '15264885', '15205430']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9203587547387913
- 35 USC 102 Novelty (BERT): 0.5272334425063252
- Combined Prediction Score: 0.8810462235155445
- Mean Citation Score: 268.319022
- Max Citation Score: 345.42758
- Similarity Product: 223.6802248249316

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test