PATENT CLAIM ANALYSIS

Application Number: 15860266
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["320", "107000"]

Abstract:
The present disclosure provides a power adapter, an electronic device and a charging apparatus. In the process of charging a battery in a conventional charge mode after the power adapter is powered on, the power adapter carries out quick charge inquiry communication with the electronic device when an output current value of the power adapter is within a conventional current range for a preset time interval; after the electronic device sends a quick charge command to the power adapter, the power adapter adjusts the output voltage according to the battery voltage information fed back by the electronic device; and when the output voltage meets a voltage requirement for quick charge preset by the electronic device, the power adapter adjusts the output current and the output voltage for charging the battery in a quick charge mode.

Claim (Index 14):
The electronic device of  claim 12 , further comprising:\n a battery connector, a main controller, a thirteenth capacitor, a thirty-sixth resistor, a thirty-seventh resistor, a fourteenth capacitor, a first Schottky diode, a second Schottky diode, a fifteenth capacitor, a thirty-eighth resistor, a thirty-ninth resistor, a fortieth resistor, a third NPN triode, a fourth NMOS transistor and a fifth NMOS transistor; wherein, the battery connector is coupled to an electrode of the battery; a first pin and a second pin of the battery connector are jointly grounded; a first ground pin and a second ground pin of the battery connector are jointly grounded; a first input/output pin of the main controller is coupled to a seventh pin and an eighth pin of the battery connector; a second input/output pin, a seventh input/output pin, an eighth input/output pin and a ninth input/output pin of the main controller are coupled to a sixth pin, a fifth pin, a fourth pin and a third pin of the battery connector respectively; an analog ground pin and a ground pin of the main controller are both grounded; a first vacant pin and a second vacant pin of the main controller are suspended; a power pin of the main controller and a first terminal of the thirteenth capacitor are both coupled to the seventh pin and the eighth pin of the battery connector; a fourth input/output pin and an eleventh input/output pin of the main controller are configured to perform data communication with the electronic device; the thirty-sixth resistor is coupled between the fourth input/output pin and the power pin of the main controller; the sixth input/output pin and the twelfth input/output pin of the main controller are coupled to a first communication terminal and a second communication terminal of the main control circuit in the power adapter respectively; a first terminal of the thirty-seventh resistor and a first terminal of the thirty-eighth resistor are jointly coupled to a tenth input/output terminal of the main controller; a second terminal of the thirty-seventh resistor is coupled to the power pin of the main controller; a second terminal of the thirty-eighth resistor is coupled to a base electrode of the third NPN triode; a fifth input/output terminal of the main controller is coupled to a first terminal of the fourteenth capacitor; a second terminal of the fourteenth capacitor and a cathode of the first Schottky diode are jointly coupled to an anode of the second Schottky diode; a first terminal of the thirty-ninth resistor and a first terminal of the fifteenth capacitor are jointly coupled to a cathode of the second Schottky diode; each of a second terminal of the thirty-ninth resistor, a first terminal of the fortieth resistor and a collector electrode of the third NPN triode is coupled to a gate electrode of the fourth NMOS transistor and a gate electrode of the fifth NMOS transistor; a second terminal of the fortieth resistor and a second terminal of the fifteenth capacitor are jointly grounded; a source electrode of the fourth NMOS transistor is coupled to an anode of the first Schottky diode, and also coupled to a seventh pin and an eighth pin of the battery connector; a drain electrode of the fourth NMOS transistor is coupled to a drain electrode of the fifth NMOS transistor; a source electrode of the fifth NMOS transistor is coupled to the communication interface of the electronic device; an emitter electrode of the third NPN triode is coupled to an anode of the third Schottky diode, and a cathode of the third Schottky diode is grounded.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.50877
- Patent Class: 320.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15113973', '15596009', '15596884', '15115203', '15115251']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7492120355975537
- 35 USC 102 Novelty (BERT): 0.5323452658906743
- Combined Prediction Score: 0.7275253586268657
- Mean Citation Score: 351.751086
- Max Citation Score: 371.28656
- Similarity Product: 324.55356558557514

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test