PATENT CLAIM ANALYSIS

Application Number: 15925762
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189050"]

Abstract:
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Claim (Index 13):
A semiconductor device comprising:\n a logic circuit including a first data input node for receiving a data signal and a clock input node for receiving a clock signal such that the logic circuit stores the data signal in response to a transition of the clock signal; and a first data buffer including a first data output node coupled to the first data input node of the logic circuit, for outputting the data signal, wherein the logic circuit includes a first transistor comprised of a fin type field-effect transistor, wherein the first transistor has a gate electrode comprised of a first gate wiring for the first data input node, wherein the first gate wiring is formed on a first projection semiconductor layer, wherein the first projection semiconductor layer extends along a first direction, and the first gate wiring extends along a second direction perpendicular to the first direction, wherein the first data buffer includes a second transistor comprised of a fin type field-effect transistor, wherein the second transistor has a drain electrode comprised of a first local wiring for the first data output node, wherein the first local wiring is formed on a second projection semiconductor layer, wherein the second projection semiconductor layer extends along the first direction, and the first local wiring extends along the second direction, wherein a path of the data signal from the first data output node to the first data input node comprises a plurality of wirings which are in a same layer as the first gate wiring and the first local wiring, and wherein, in plan view, a length of the path of the data signal from the first data output node to the first data input node is longer than a length of a straight path from the first local wiring to the first gate wiring along the first direction.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.53333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15211298', '15607599', '15841950', '14944262', '11320751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7841380757778548
- 35 USC 102 Novelty (BERT): 0.4925319317832921
- Combined Prediction Score: 0.7549774613783985
- Mean Citation Score: 213.51475
- Max Citation Score: 289.29242
- Similarity Product: 254.5909503263712

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test