PATENT CLAIM ANALYSIS

Application Number: 15964245
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["326", "016000"]

Abstract:
A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.

Claim (Index 11):
The method according to  claim 1 , wherein a second receive register is implemented on a third interface pin, the second receive register reading out whether the first signal is received at the third interface pin, the third interface pin being allocated to the first interface pin if the first signal is received at the third interface pin.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 2.34615
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13839282', '11935096', '13168414', '15291113', '11189308']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6237110546095959
- 35 USC 102 Novelty (BERT): 0.4643028009409722
- Combined Prediction Score: 0.6077702292427335
- Mean Citation Score: 138.089846
- Max Citation Score: 143.38312
- Similarity Product: 109.99020499786852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test