PATENT CLAIM ANALYSIS

Application Number: 16022704
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Claim (Index 12):
The package according to  claim 10 , wherein a bottom size of the first via portion is substantially equivalent to a bottom size of the second via portion, and orthogonal projections of the first via portion and the second via portion overlap with each other in a concentric way.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 3.02778
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15688817', '15693950', '15157220', '14447426', '15859123']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921881380245606
- 35 USC 102 Novelty (BERT): 0.5103498535570449
- Combined Prediction Score: 0.8807282275767498
- Mean Citation Score: 217.664304
- Max Citation Score: 267.35162
- Similarity Product: 184.8655681502557

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test