PATENT CLAIM ANALYSIS

Application Number: 15859988
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "676000"]

Abstract:
A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.

Claim (Index 14):
The multi-chip package of power semiconductor of  claim 13 , wherein each of the power semiconductor chips further comprises:\n a gate bump formed between the gate segment and the gate electrode; a source bump formed between the source segment and the source electrode; and a drain bump formed between the drain segment and the drain contact.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 3.51351
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13288108', '15398453', '14673347', '11288103', '13293194']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9106301106519988
- 35 USC 102 Novelty (BERT): 0.5026940294495036
- Combined Prediction Score: 0.8698365025317494
- Mean Citation Score: 215.02736600000003
- Max Citation Score: 227.8725
- Similarity Product: 162.35809140086175

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test