PATENT CLAIM ANALYSIS

Application Number: 16403864
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Claim (Index 8):
A semiconductor device comprising:\n an integrated circuit die, the integrated circuit die having a front-side and a backside; molding compound adjacent sidewalls of the integrated circuit die; a first layer extending over the molding compound; an adhesive material interposed between the integrated circuit die and the first layer; and a through via extending through the molding compound and the first layer, a smallest width of the through via in the molding compound being greater than a largest width of the through via in the first layer, wherein the through via protrudes from the first layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 100.0
- Lexical Diversity: 1.89583
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15805683', '14743451', '14696198', '14723857', '16390138']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9337529789925988
- 35 USC 102 Novelty (BERT): 0.554170379198763
- Combined Prediction Score: 0.8957947190132152
- Mean Citation Score: 290.54948
- Max Citation Score: 355.89865
- Similarity Product: 333.6147429106802

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test