PATENT CLAIM ANALYSIS

Application Number: 16033154
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["323", "271000"]

Abstract:
A current balance method used in multi-phase switching converters, including: generating an error amplifying signal based on a reference voltage signal and a feedback voltage signal indicative of an output voltage of the multi-phase converter; generating a first and second voltage signals respectively indicative of output currents of a first and second switching circuits; generating an average voltage signal indicative of the average value of the first and second voltage signals; generating a first adjusting voltage signal based on the average voltage signal and the first voltage signal; comparing a sum of the error amplifying signal and the first adjusting voltage signal with a first current sensing signal indicative of the current flowing through a transistor in the first switching circuit, to provide a first comparison signal; and generating a first control signal based on the first comparison signal to control the transistor.

Claim (Index 8):
The multi-phase switching converter of  claim 6 , wherein the first logic circuit comprises:\n a first on-time control circuit configured to generate a first on-time control signal; a first flip flop having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first comparing circuit, the second input terminal is coupled to the first on-time control circuit to receive the first on-time control signal, and wherein based on the first comparison signal and the first on-time control signal, the first flip flop generates the first control signal at the output terminal; and a first phase lock loop circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first flip flop, the second input terminal is configured to receive a first frequency dividing signal, the output terminal is coupled to the first on-time control circuit, and wherein the first phase lock loop circuit adjusts the first on-time control signal based on the first control signal and the first frequency dividing signal.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 95.0
- Lexical Diversity: 2.92308
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15846142', '15387621', '14585645', '15389390', '14548180']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7501862251437444
- 35 USC 102 Novelty (BERT): 0.4862396257378538
- Combined Prediction Score: 0.7237915652031555
- Mean Citation Score: 206.970012
- Max Citation Score: 223.28291
- Similarity Product: 164.69551701375718

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test