PATENT CLAIM ANALYSIS

Application Number: 15948569
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["711", "130000"]

Abstract:
Techniques for managing multi-level memory and coherency using a unified page granular controller can simplify software programming of both file system handling for persistent memory and parallel programming of host and accelerator and enable better software utilization of host processors and accelerators. As part of the management techniques, a line granular controller cooperates with a page granular controller to support both fine grain and coarse grain coherency and maintain overall system inclusion property. In one example, a controller to manage coherency in a system includes a memory data structure and on-die tag cache to store state information to indicate locations of pages in a memory hierarchy and an ownership state for the pages, the ownership state indicating whether the pages are owned by a host processor, owned by an accelerator device, or shared by the host processor and the accelerator device. The controller can also include logic to, in response to a memory access request from the host processor or the accelerator to access a cacheline in a page in a state indicating ownership by a device other than the requesting device, cause the page to transition to a state in which the requesting device owns or shares the page.

Claim (Index 9):
The apparatus of  claim 6 , wherein:\n the logic is to cause the information to be stored to the hardware storage, to a structure in near memory, and to a structure in the far memory; wherein the hardware storage is to store the information for recently accessed pages, the structure in the near memory is to store information for pages allocated to the near memory cache, and the structure in the far memory is to store information for all memory pages; and wherein the information to be stored in the hardware storage, the structure in the near memory, and the structure in the far memory is to indicate locations in the near memory cache for far memory pages and the ownership state.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.19792
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13921844', '15825880', '13447462', '13447445', '12775511']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5308242956163324
- 35 USC 102 Novelty (BERT): 0.5019540116630812
- Combined Prediction Score: 0.5279372672210073
- Mean Citation Score: 182.759096
- Max Citation Score: 194.60368
- Similarity Product: 114.03700744468686

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test