PATENT CLAIM ANALYSIS

Application Number: 16049624
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["719", "312000"]

Abstract:
Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

Claim (Index 1):
A method of acknowledging a completion of a transaction of data via an inter-processor communication (IPC) link between a first independently operable processor apparatus and a second independently operable processor apparatus, the method comprising:\n reading, by the second independently operable processor apparatus, a first data structure representative of the data, wherein the first data structure is written by the first independently operable processor apparatus to a first data array located in a shared memory structure; retrieving the data from the shared memory structure based at least on the reading of the first data structure from the first data array, wherein the retrieved data corresponds to the first data structure; transmitting the retrieved data corresponding to the first data structure via an apparatus associated with the second independently operable processor apparatus; subsequent to the transmitting of the data, writing, by the second independently operable processor apparatus, a second data structure to a second data array located in the shared memory structure, wherein the second data structure comprises information associated with the transmitting of the data and being readable by the first independently operable processor apparatus, thereby optimizing signaling of the completion of the transaction of data between the first and second independently operable processor apparatus, wherein the signaling of the completion comprises enabling the first independently operable processor apparatus to check for the second data structure at a time interval that is dynamically altered to be smaller or larger based at least on (i) a number of transactions, and (ii) a threshold number of transactions; and causing the first independently operable processor apparatus to read the second data structure from the second data array.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 1.93902
- Patent Class: 719.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15984153', '15865638', '14879030', '15011291', '15721200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.539332380689064
- 35 USC 102 Novelty (BERT): 0.5144042687203417
- Combined Prediction Score: 0.5368395694921918
- Mean Citation Score: 260.273578
- Max Citation Score: 303.18237
- Similarity Product: 221.83908321547688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test