PATENT CLAIM ANALYSIS

Application Number: 15871746
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "379000"]

Abstract:
Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

Claim (Index 6):
The multi-chip package of  claim 5 , further comprising:\n a thermal pad; a third die that includes at least one of a controller circuit or a driver circuit; wherein the second die and the third die are disposed on the thermal pad.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14965697', '15019275', '14955037', '14071403', '13301699']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9120049656886758
- 35 USC 102 Novelty (BERT): 0.5556276765247347
- Combined Prediction Score: 0.8763672367722818
- Mean Citation Score: 259.184664
- Max Citation Score: 430.00027
- Similarity Product: 316.4286061182535

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test