PATENT CLAIM ANALYSIS

Application Number: 16510688
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-11
Patent Classification: ["257", "401000"]

Abstract:
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Claim (Index 10):
A computing device, comprising:\n a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:\n an NMOS device comprising a first fin, the first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion, the lower fin portion having a first side and a second side; \n a PMOS device comprising a second fin, the second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion, the lower fin portion having a first side and a second side, wherein the first side of the lower fin portion of the second fin faces the second side of the lower fin portion of the first fin; \n a first dielectric portion comprising silicon and oxygen, the first dielectric portion directly on the second side of the lower fin portion of the first fin; \n a second dielectric portion comprising silicon and oxygen, the second dielectric portion directly the first side of the lower fin portion of the second fin; \n an insulating layer comprising nitrogen, the insulating layer over the first dielectric portion and over the second dielectric portion, and the insulating layer continuous over the first dielectric portion and the second dielectric portion; \n a dielectric fill material directly on the insulating layer; \n a first gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over a first portion of the dielectric fill material; and \n a second gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, the second gate electrode over a second portion the dielectric fill material.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.70175
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16103430', '14779936', '15122796', '15859352', '14780218']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9277760752892464
- 35 USC 102 Novelty (BERT): 0.5429982572751597
- Combined Prediction Score: 0.8892982934878377
- Mean Citation Score: 312.0530500000001
- Max Citation Score: 399.1398
- Similarity Product: 348.9299110016584

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test