PATENT CLAIM ANALYSIS

Application Number: 16213842
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["710", "113000"]

Abstract:
Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Claim (Index 36):
A device, comprising:\n an arbiter circuit for atomic memory operations, wherein the arbiter circuit is configured to control access for a plurality of hardware processors to a shared system memory; and a data storage register connected to the arbiter circuit; wherein, responsive to detection of an atomic memory operation at an address of the shared system memory from a given one of the plurality of hardware processors, the arbiter circuit is configured to perform an atomic memory operation procedure, wherein to perform the atomic memory operation procedure the arbiter circuit is configured to:\n establish an indicator of an active atomic memory operation at the address; \n block subsequent memory operations from the plurality of hardware processors to the address of the atomic memory operation while the indicator of the active atomic memory operation is set; \n issue one or more memory operations to the shared system memory to perform the atomic memory operation; and \n clear the indicator of the active atomic memory operation, responsive to an acknowledgment of the one or more memory operations from the shared system memory; and \n allow subsequent memory operations from the plurality of hardware processors to the address of the atomic memory operation to proceed to the shared system memory.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 98.0
- Lexical Diversity: 2.89091
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15085977', '15256590', '11171155', '15256588', '13192104']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6469980556335806
- 35 USC 102 Novelty (BERT): 0.6156912061445396
- Combined Prediction Score: 0.6438673706846765
- Mean Citation Score: 261.435396
- Max Citation Score: 571.94135
- Similarity Product: 524.31653614811

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test