PATENT CLAIM ANALYSIS

Application Number: 15874099
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

Claim (Index 1):
A three-dimensional semiconductor device comprising:\n an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction; contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure; bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and arranged as a periodic array of bit lines having a bit line pitch along the first horizontal direction; and a pair of wall-shaped via structures extending through the alternating stack, and laterally extending along the first horizontal direction, wherein the at least five rows of memory stack structures are located between pair of wall-shaped via structures.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.16667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15174030', '15354116', '15337235', '15635321', '15017961']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239048544404216
- 35 USC 102 Novelty (BERT): 0.5476997018910658
- Combined Prediction Score: 0.886284339185486
- Mean Citation Score: 310.3296400000001
- Max Citation Score: 406.54224
- Similarity Product: 370.6384822119999

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test