PATENT CLAIM ANALYSIS

Application Number: 15892463
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["327", "536000"]

Abstract:
A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Claim (Index 2):
The bias regulator circuit of  claim 1 , the voltage divider further including:\n a third resistive element having a first terminal coupled to the NMOS bias voltage node and a second terminal coupled to the first node.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 88.0
- Lexical Diversity: 3.16667
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14840257', '10672793', '13754267', '11119130', '13196633']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7871522212722235
- 35 USC 102 Novelty (BERT): 0.4730316531476138
- Combined Prediction Score: 0.7557401644597626
- Mean Citation Score: 195.39971
- Max Citation Score: 199.53568
- Similarity Product: 157.69277668073656

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test