PATENT CLAIM ANALYSIS

Application Number: 16125786
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2020-01
Patent Classification: ["365", "156000"]

Abstract:
A memory array and a semiconductor chip are provided. The memory array includes memory cells, each includes: first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. A source/drain of the first pull-up transistor is coupled to a source/drain of the first pull-down transistor. A source/drain of the second pull-up transistor is coupled to a source/drain of the second pull-down transistor. Gates of the second pull-up and pull-down transistors are coupled to the first node. Gates of the first pull-up and pull-down transistors are coupled to the second node. The first and second pass-gate transistors are respectively coupled to the first and second nodes. The first and second pull-up transistors respectively include a first active structure having a bottom portion including a strained semiconductor material and a top portion including an unstrained semiconductor material. The first active structures continuously extend across the memory array.

Claim (Index 11):
A memory array, comprising a plurality of memory cells, each of the plurality of memory cells comprises:\n a first pull-up transistor and a first pull-down transistor, wherein a source/drain of the first pull-up transistor is electrically coupled to a source/drain of the first pull-down transistor at a first node; a second pull-up transistor and a second pull-down transistor, wherein a source/drain of the second pull-up transistor is electrically coupled to a source/drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor are electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor are electrically coupled to the second node; a first pass-gate transistor and a first dummy transistor, electrically coupled to the first node; and a second pass-gate transistor and a second dummy transistor, electrically coupled to the second node, wherein the first dummy transistor, the second dummy transistor, the first pull-up transistor and the second pull-up transistor are transistors of the same conductive type, and a work function of gates of the first dummy transistor and the second dummy transistor is higher or lower than a work function of gates of the first pull-up transistor and the second pull-up transistor.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 3.32653
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14671587', '14690068', '14104835', '13328685', '14486293']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8040513261562712
- 35 USC 102 Novelty (BERT): 0.4660762746800271
- Combined Prediction Score: 0.7702538210086468
- Mean Citation Score: 231.53286799999995
- Max Citation Score: 241.14894
- Similarity Product: 226.9516065122044

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test