PATENT CLAIM ANALYSIS

Application Number: 15743617
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["345", "212000"]

Abstract:
The present disclosure provides a GOA unit circuit, a method for driving the same, and a GOA circuit. The GOA unit circuit comprises a first input sub-circuit, a pull-up sub-circuit, a first pull-down sub-circuit, a reset sub-circuit, a second input sub-circuit, a noise control sub-circuit, a first de-noising sub-circuit, and a second de-noising sub-circuit. The first pull-down sub-circuit is connected to an output signal terminal, a first clock control signal terminal and a discharge signal terminal, a discharge signal provided by the discharge signal terminal is at a high level higher than that of an input signal provided by the input signal terminal, and the first pull-down sub-circuit is configured to discharge the output signal terminal under the control of the first clock control signal and the discharge signal, to pull down a potential at the output signal terminal to a low level. The GOA unit circuit is configured to drive gate lines of a display apparatus.

Claim (Index 14):
A Gate Driver on Array (GOA) circuit, comprising a plurality of cascaded GOA unit circuits according to  claim 1 , wherein\n a discharge signal terminal of a previous stage of GOA unit circuit is connected to a pull-up node of any stage subsequent to the previous stage of GOA unit circuit; first clock control signal terminals and second clock control signal terminals of odd stages of GOA unit circuits are connected to a first group of clock signal input lines; and in each of various odd stages of GOA unit circuits, an output signal terminal of a previous stage of GOA unit circuit is connected to an input signal terminal of a next stage of GOA unit circuit, a reset signal terminal of the previous stage of GOA unit circuit is connected to an output signal terminal of the next stage of GOA unit circuit, and an input signal provided by an input signal terminal of a first stage of GOA unit circuit and a reset signal provided by a reset signal terminal of a last stage of GOA unit circuit are provided by a system; and first clock control signal terminals and second clock control signal terminals of even stages of GOA unit circuit are connected to a second group of clock signal input lines; and in each of various even stages of GOA unit circuits, an output signal terminal of a previous stage of GOA unit circuit is connected to an input signal terminal of a next stage of GOA unit circuit, a reset signal terminal of the previous stage of GOA unit circuit is connected to an output signal terminal of the next stage of GOA unit circuit, and an input signal provided by an input signal terminal of a first stage of GOA unit circuit and a reset signal provided by a reset signal terminal of a last stage of GOA unit circuit are provided by the system.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 3.10714
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15682740', '16066827', '15741742', '14787934', '15529613']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6968314932285488
- 35 USC 102 Novelty (BERT): 0.5388641421343818
- Combined Prediction Score: 0.681034758119132
- Mean Citation Score: 343.007954
- Max Citation Score: 393.1922
- Similarity Product: 321.57755828562983

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test