PATENT CLAIM ANALYSIS

Application Number: 16018970
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "329000"]

Abstract:
Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.

Claim (Index 15):
The method of  claim 14 , further comprising:\n removing the first OPL; forming a second OPL over the cap layer, the isolation dielectric material and in the preliminary gate contact opening; and forming an anti-reflective coating (ARC) layer over the second OPL.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 94.0
- Lexical Diversity: 2.74576
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15790216', '15592172', '15274087', '15971191', '15424937']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9305724351981384
- 35 USC 102 Novelty (BERT): 0.5280495038968128
- Combined Prediction Score: 0.8903201420680058
- Mean Citation Score: 331.688032
- Max Citation Score: 353.7876
- Similarity Product: 227.7926723499298

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test