PATENT CLAIM ANALYSIS

Application Number: 16123262
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["438", "586000"]

Abstract:
A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.

Claim (Index 8):
The method as claimed in  claim 1 , wherein the ion-implanting process includes forming an ion-implanted region under surfaces of the dummy gate structure and the preliminary second interlayer insulation pattern.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 97.0
- Lexical Diversity: 3.02174
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15171120', '13302080', '13252621', '15361516', '15080706']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8663915193873042
- 35 USC 102 Novelty (BERT): 0.5296839025363161
- Combined Prediction Score: 0.8327207577022054
- Mean Citation Score: 293.060546
- Max Citation Score: 328.0662200000001
- Similarity Product: 238.4370310578872

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test