PATENT CLAIM ANALYSIS

Application Number: 15922901
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["326", "080000"]

Abstract:
An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.

Claim (Index 17):
The method of  claim 14 , further comprising:\n coupling a three-state gate to the input terminal for receiving the input signal, wherein the three-state gate comprises third and fourth PMOS transistors, and fifth and sixth NMOS transistors, all connected in series between the first supply voltage and ground, and wherein gate terminals of the fourth PMOS transistor and the fifth NMOS transistor are respectively coupled with output terminals of the second inverter and the first inverter; coupling a latch with an output of the three-state gate, wherein the latch is connected between the second supply voltage and ground; and coupling the output inverter to an output terminal of the latch, wherein the output terminal is connected between the second supply voltage and ground.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 1.94444
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15857214', '15687781', '15826273', '15872230', '14658353']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6711474841458819
- 35 USC 102 Novelty (BERT): 0.481095629500727
- Combined Prediction Score: 0.6521422986813664
- Mean Citation Score: 218.193646
- Max Citation Score: 224.65376
- Similarity Product: 170.31852573488237

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test