PATENT CLAIM ANALYSIS

Application Number: 16033816
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-05
Patent Classification: ["327", "434000"]

Abstract:
A semiconductor device includes a first internal circuit coupled to first and second voltage terminals for receiving first and second voltages; a second internal circuit coupled to the first and second voltage terminals for receiving the first and second voltages; a first power gating circuit coupled between at least one of the first and second voltage terminals and the first internal circuit, the first power gating circuit being suitable for disconnecting at least one of the first and second voltages based on a first mode signal in a first mode; a second power gating circuit coupled between at least one of the first and second voltage terminals and the second internal circuit, the second power gating circuit being suitable for disconnecting at least one of the first and second voltages based on an integrated mode signal in the first mode and a second mode; and a control circuit suitable for generating the first mode signal and the integrated mode signal.

Claim (Index 19):
The operating method of  claim 17 , wherein the first mode includes a deep-sleep mode, and the second mode includes a power-down mode.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 95.0
- Lexical Diversity: 4.175
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14616824', '16021801', '13867314', '15701020', '11969968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7779883439894631
- 35 USC 102 Novelty (BERT): 0.5090592492351333
- Combined Prediction Score: 0.7510954345140302
- Mean Citation Score: 186.539712
- Max Citation Score: 195.6299
- Similarity Product: 101.42194717679024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test