PATENT CLAIM ANALYSIS

Application Number: 15957615
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "319000"]

Abstract:
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

Claim (Index 14):
A method of forming a memory device, comprising:\n forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface; forming a memory cell on a first fin of the plurality of fins, by:\n forming spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions, \n forming a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, \n forming a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, \n forming a control gate that extends along and is insulated from the floating gate, and \n forming an erase gate that extends along and is insulated from the source region; \n forming a logic device on a second fin of the plurality of fins, by:\n forming spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the logic source and drain regions, and \n forming a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the second fin; \n wherein the first and second fins are formed as a single continuous fin.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 3.07692
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15295022', '15945161', '15933124', '15050309', '15489548']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9151001764269208
- 35 USC 102 Novelty (BERT): 0.5278030869260646
- Combined Prediction Score: 0.8763704674768351
- Mean Citation Score: 313.718762
- Max Citation Score: 340.4594
- Similarity Product: 281.73303023023607

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test