PATENT CLAIM ANALYSIS

Application Number: 15918659
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "355000"]

Abstract:
A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

Claim (Index 11):
A semiconductor integrated circuit device comprising a semiconductor chip, the semiconductor chip comprising:\n a core region including logic circuits having semiconductor elements; an I/O region arranged around the core region; a plurality of I/O pads formed in the I/O region; and a plurality of I/O parts formed in the I/O region and disposed along an edge of the semiconductor chip, each of the I/O parts coupled with an associated one of the I/O pads, the I/O parts each comprising:\n an output buffer block including an output buffer to function as an interface for output of signal to the outside, the output buffer including a first transistor and a second transistor; \n a logic block configured to control the output buffer; and \n a pad lead part disposed between the logic block and the first transistor, and coupled to the associated one of the I/O pads, \n wherein, in each of the I/O parts:\n in plan view, the logic block, the pad lead part, the first transistor and the second transistor are arranged in this order starting from a position closer to a center of the semiconductor chip toward the edge of the semiconductor chip, \n the pad lead part is coupled with a connection part of a drain terminal of the first transistor and a drain terminal of the second transistor, \n in the first transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, \n in the second transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 2.17143
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13910891', '14953319', '14461163', '13654415', '12635675']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9072766278933162
- 35 USC 102 Novelty (BERT): 0.5638915902044519
- Combined Prediction Score: 0.8729381241244297
- Mean Citation Score: 301.23762
- Max Citation Score: 445.21854
- Similarity Product: 344.47237738427634

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test