PATENT CLAIM ANALYSIS

Application Number: 16042910
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["712", "222000"]

Abstract:
The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

Claim (Index 31):
A method for operating first and second specialized processing blocks that are arranged in a bidirectional cascade chain to generate a double-precision floating-point sum, comprising:\n receiving, at a first processing circuit, a first subset of a first double-precision floating-point number and a first subset of a second double-precision floating-point number; determining, using the first subset of the first double-precision floating-point number and the first subset of the double-precision floating-point number whether the first double-precision floating-point number or the second double-precision floating-point number is larger; generating, using the first processing circuit, a control signal indicating that the first double-precision floating-point number is larger than the second double-precision floating-point number; generating, using the first processing circuit, a data signal indicating shifted values of the first or second double-precision floating-point number, and a first partial sum that is based at least in part on the first subset of the first double-precision floating-point number and the first subset of the second double-precision floating-point number; receiving a second subset of the first double-precision floating-point number and a second subset of the second double-precision floating-point number at a second processing circuit; and generating, using the second processing circuit, a carry signal and a second partial sum that is based at least in part on the second subset of the first double-precision floating-point number and the second subset of the second double-precision floating-point number.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.26923
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15367205', '15367208', '16039029', '15242923', '15270153']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6820579867421379
- 35 USC 102 Novelty (BERT): 0.6193360322514959
- Combined Prediction Score: 0.6757857912930738
- Mean Citation Score: 498.582776
- Max Citation Score: 607.45935
- Similarity Product: 530.6650503296256

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test