PATENT CLAIM ANALYSIS

Application Number: 16266604
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-10
Patent Classification: ["326", "038000"]

Abstract:
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Claim (Index 13):
The multi-chip system of  claim 11 , wherein an additional plurality of chips are mounted on the routing layer, and electrically coupled with the interfacing bar with routing in the routing layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 99.0
- Lexical Diversity: 1.52941
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14040223', '13646477', '14977645', '15499557', '15816360']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.663230412544888
- 35 USC 102 Novelty (BERT): 0.4567565238172901
- Combined Prediction Score: 0.6425830236721283
- Mean Citation Score: 122.76851000000002
- Max Citation Score: 142.67065
- Similarity Product: 110.90725899280012

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test