PATENT CLAIM ANALYSIS

Application Number: 15887702
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["324", "538000"]

Abstract:
A method of bondwire integrity testing a packaged IC includes forcing a pin current or pin voltage level sufficient to forward bias a parasitic diode at a plurality of pins relative to a selected reference pin. The pins are connected to bond pads (BPs) on the IC by a bondwire. The bond pads coupled to a diffusion of a first type that forms the parasitic diode (D) with a region doped the second type coupled to a bondpad wirebonded to the reference pin. The resulting pin voltages or pin currents at measured, and present pin-pin relationships are determined. The present pin-pin relationships are compared to stored pin-pin relationship data for a device design of the IC. Results from the comparing are used to determine whether any present pin-pin relationships are significantly different as compared to the stored pin-pin relationships to identify a bondwire problem for at least one pin.

Claim (Index 10):
A test system testing a packaged integrated circuit (IC) device, comprising:\n a processor coupled to control a power supply including a voltage source or a current source that is switchably connected to a contactor for contacting pins of said packaged IC including a plurality of pins and a selected common reference pin, said plurality of pins each connected to bond pads on said IC by a bondwire that are coupled to a diffusion of a first doping type, said diffusions forming a parasitic diode with a region doped a second doping type coupled to a bond pad wirebonded to said reference pin; said voltage source or said current source for forcing at least one pin current level or at least one pin voltage level for forward biasing said parasitic diodes relative to said reference pin;\n a voltage or current monitor coupled to said processor for measuring resulting respective pin voltages or respective pin currents for said plurality of pins, and \n said processor with an associated memory for determining a bondwire integrity for said plurality of pins including:\n determining present pin-pin relationships from said respective pin voltages or said respective pin currents; \n comparing said present pin-pin relationships to stored pin-pin relationship data for a device design of said IC device in said associated memory that provides relationships between said plurality of pins, and \n utilizing results from said comparing to determine whether any of said present pin-pin relationships are significantly different as compared to said stored pin-pin relationships to identify an additional bonding resistance for at least one of said plurality of pins.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 88.0
- Lexical Diversity: 1.90476
- Patent Class: 324.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15857234', '11034093', '10397402', '11033202', '15337821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5165865432428676
- 35 USC 102 Novelty (BERT): 0.4864171157684447
- Combined Prediction Score: 0.5135696004954253
- Mean Citation Score: 188.010862
- Max Citation Score: 206.57361
- Similarity Product: 149.8140396399701

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test