PATENT CLAIM ANALYSIS

Application Number: 15906890
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["257", "326000"]

Abstract:
A memory device comprises electrode layers stacked in a stacking direction. Semiconductor pillars penetrate the electrode layers in the stacking direction. First wirings are disposed above the plurality of electrode layers at a first level. Each first wiring is electrically connected to a semiconductor pillar. A second wiring is disposed above the plurality of electrode layers at the first level. The second wiring is insulated from semiconductor pillars. The second wiring and the first wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction. A width of the second wiring the second direction is equal to a width of each first wiring. A spacing distance between the second wiring and a nearest first wiring is greater than a spacing interval between adjacent first wirings.

Claim (Index 17):
A memory device, comprising:\n a source line layer; a plurality of word line layers stacked on the source line in a stacking direction; a plurality of memory holes penetrating the plurality of word line layers in the stacking direction and reaching the source line layer, each memory hole including a semiconductor pillar covered with a memory film; a plurality of bit line wirings disposed above the plurality of word line layers in the stacking direction at a first level, each bit line wiring being electrically connected to at least one semiconductor pillar in the plurality of memory holes; and a dummy bit line wiring disposed above the plurality of word line layers in the stacking direction at the first level, the dummy bit line wiring being electrically insulated from the plurality of memory holes, wherein the dummy bit line wiring and the plurality of bit line wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction intersecting the first and stacking directions, a width of the dummy bit line wiring in the second direction is equal to a width of each bit line wirings in the plurality of bit line wirings in the second direction, and a spacing distance along the second direction between the dummy bit line wiring and a nearest bit line wiring in the plurality of bit line wirings is greater than a spacing interval along the second direction between adjacent bit line wirings in the plurality of bit line wirings.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 2.58929
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15906423', '15855186', '12705231', '14687177', '13401113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.910338088727835
- 35 USC 102 Novelty (BERT): 0.4735347762724183
- Combined Prediction Score: 0.8666577574822933
- Mean Citation Score: 175.594106
- Max Citation Score: 190.95038
- Similarity Product: 149.7955316387141

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test