PATENT CLAIM ANALYSIS

Application Number: 15895321
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["326", "038000"]

Abstract:
A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.

Claim (Index 7):
The PLU of  claim 2 , wherein:\n a first transistor is configured to couple the first RHL with a power supply in response to the first power gating cell being active; a second transistor is configured to couple the second RHL with the power supply in response to the second power gating cell being active; a third transistor is configured to couple the third RHL with the power supply in response to the third power gating cell being active; and a fourth transistor is configured to couple the LUT with the power supply in response to the fourth power gating cell being active.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 88.0
- Lexical Diversity: 2.0303
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['09754632', '14458456', '14089238', '14890911', '15224224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6739448625638828
- 35 USC 102 Novelty (BERT): 0.4842164877004782
- Combined Prediction Score: 0.6549720250775424
- Mean Citation Score: 170.86310399999996
- Max Citation Score: 185.4701
- Similarity Product: 124.5434977825284

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test