PATENT CLAIM ANALYSIS

Application Number: 15980073
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["345", "208000"]

Abstract:
Provided are an organic light-emitting display panel and an organic display device, the organic light-emitting display panel includes: a display region and at least one peripheral circuit region; the peripheral circuit region is provided with shift registers cascaded in stages and clock signal lines of at least two different types, the number of clock signal lines in at least one of the different types is not less than 2, clock signals of one type of the clock signal lines are the same, clock signals of different types of the clock signal lines are different; the clock signal lines each is electrically connected to a clock signal input terminal of one of the shift registers, the shift registers each is configured to output a gate driving signal according to the clock signal in the clock signal line electrically connected to the input terminal of one of the shift registers.

Claim (Index 7):
The organic light-emitting display panel according to  claim 1 , wherein\n each stage of the shift registers comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor; wherein a gate electrode of the first transistor is configured as a first clock signal terminal of the each stage of the shift registers, a first electrode of the first transistor is configured as a trigger signal inputting terminal of the each stage of the shift registers, and a second electrode of the first transistor is electrically connected to a first electrode of the second transistor; wherein a gate electrode of the second transistor is electrically connected to the gate electrode of the first transistor, and a second electrode of the second transistor is electrically connected to a second electrode of the fourth transistor; wherein a gate electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and a first electrode of the third transistor is electrically connected to a second power signal terminal, a second electrode of the third transistor is electrically connected to a first node; wherein a gate electrode of the fourth transistor is configured as a second clock signal terminal of the shift register, a first electrode of the fourth transistor is electrically connected to a second electrode of the fifth transistor; wherein a gate electrode of the fifth transistor is electrically connected to the first node, and a first electrode of the fifth transistor is electrically connected to a first power signal terminal; wherein a gate electrode of the sixth transistor is electrically connected to the second electrode of the fourth transistor, a first electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor, and a second electrode of the sixth transistor is electrically connected to the first node; wherein a gate electrode of the seventh transistor is electrically connected to the first electrode of the third transistor, a first electrode of the seventh transistor is electrically connected to the second electrode of the second transistor, and a second electrode of the seventh transistor is electrically connected to a second node; wherein a gate electrode of the eighth transistor is electrically connected to the first node, a first electrode of the eighth transistor is electrically connected to the first electrode of the fifth transistor, and a second electrode of the eighth transistor is configured as a driving signal outputting terminal; wherein a gate electrode of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the gate electrode of the fourth transistor, and a second electrode of the ninth transistor is electrically connected to the second electrode of the eighth transistor; wherein a first electrode of the first capacitor is electrically connected to the first electrode of the fifth transistor, and a second electrode of the first capacitor is electrically connected to the gate electrode of the eighth transistor; and wherein a first electrode of the second capacitor is electrically connected to the second node, and a second electrode of the second capacitor is electrically connected to the second electrode of the ninth transistor.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 93.0
- Lexical Diversity: 2.75439
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14302383', '15598217', '11411473', '11683143', '12873936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6493958523529617
- 35 USC 102 Novelty (BERT): 0.4947156196647019
- Combined Prediction Score: 0.6339278290841357
- Mean Citation Score: 240.864192
- Max Citation Score: 250.55896
- Similarity Product: 213.3275905844927

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test