PATENT CLAIM ANALYSIS

Application Number: 16226938
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "159000"]

Abstract:
A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

Claim (Index 2):
The PLL of  claim 1 , wherein the circuit including the finite state machine also includes a delay circuit to generate a feedback clock divider reset signal that is a delayed version of a reference clock divider reset signal, wherein the feedback clock divider reset signal resets the feedback clock divider and the reference clock divider reset signal resets the programmable reference clock divider.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 98.0
- Lexical Diversity: 2.29231
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16101009', '16227777', '12111541', '14700695', '12550393']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8103885283715007
- 35 USC 102 Novelty (BERT): 0.4978593933968913
- Combined Prediction Score: 0.7791356148740397
- Mean Citation Score: 251.626852
- Max Citation Score: 258.00763
- Similarity Product: 193.0860291354793

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test