PATENT CLAIM ANALYSIS

Application Number: 16017308
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["375", "316000"]

Abstract:
A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.

Claim (Index 4):
The receiver of  claim 2 , wherein the clock divider is further configured to divide a quadrature version of the sampling clock signal to form a quadrature divided clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 1.74286
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13235628', '15346434', '15959104', '11005465', '12372946']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5257577559055827
- 35 USC 102 Novelty (BERT): 0.5057785766496613
- Combined Prediction Score: 0.5237598379799906
- Mean Citation Score: 234.881726
- Max Citation Score: 247.64339
- Similarity Product: 166.03080644922912

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test