PATENT CLAIM ANALYSIS

Application Number: 16036751
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "154000"]

Abstract:
Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline. The integrated circuit may include a write driver coupled to the bitline for writing data to the bitcell. The write driver may have an inverter and a clamping device that are arranged to clamp current after data has been written to the bitcell.

Claim (Index 15):
An integrated circuit, comprising:\n a first device coupled between multiple terminals, wherein the first device operates to clamp current between the multiple terminals based on a first activation signal; and a second device coupled between the multiple terminals, the first device and a bias voltage source, wherein the second device operates to generate the first activation signal based on the bias voltage, and wherein the second device operates to activate the first device with the first activation signal based on a second activation signal received from one terminal of the multiple terminals.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 95.0
- Lexical Diversity: 1.63158
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15960475', '13784830', '15760681', '15393552', '15823490']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7870886265891689
- 35 USC 102 Novelty (BERT): 0.4627474424258183
- Combined Prediction Score: 0.7546545081728339
- Mean Citation Score: 183.23022
- Max Citation Score: 196.55577
- Similarity Product: 161.4387108944821

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test