PATENT CLAIM ANALYSIS

Application Number: 16103391
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["358", "001130"]

Abstract:
A photoelectric conversion device includes a pixel array including one or more linear array, each including plural linearly-arranged pixels; and plural memory circuits, each including plural memory cells. The plural pixels in the pixel array are connected one-to-one to the plural memory cells of the plural memory circuits. Each of the plural pixels alternately outputs a photoelectric conversion value indicating an electric voltage generated in accordance with a light amount of an incident light entering the pixel, and a reset value indicating a reference charge of the pixel, to the memory cell corresponding to the pixel. Each of the plural memory cells temporarily stores the photoelectric conversion value and the reset value output from the pixel corresponding to the memory cell. Each of the plural memory circuits outputs the photoelectric conversion values and the reset values stored in the plural memory cells of the memory circuit, in a predetermined order.

Claim (Index 14):
The photoelectric conversion device according to  claim 12 ,\n wherein the plurality of memory circuits configure a first circuit group, arranged along a longitudinal direction of the linear array, wherein the plurality of amplifiers configure a second circuit group, arranged along the longitudinal direction of the linear array, wherein the plurality of analog/digital converters configure a third circuit group, arranged along the longitudinal direction of the linear array, wherein the plurality of pixel value calculators configure a fourth circuit group, arranged along the longitudinal direction of the linear array, wherein the first to fourth circuit groups are arranged so as to become more distant from the pixel array, in this order, in a direction orthogonal to the longitudinal direction of the linear array, wherein the pixel array and the first to fourth circuit groups have first end portions and second end portions corresponding to both ends of the linear array, wherein the first timing generator includes a third timing generator and a fourth timing generator which are each configured so as to generate the same timing signal, wherein the third timing generator and the fourth timing generator operate in synchronization with each other, wherein the third timing generator is connected to the first end portions of the pixel array and of the first to fourth circuit groups, wherein the fourth timing generator is connected to the second end portions of the pixel array and of the first to fourth circuit groups, and wherein a length of a signal line from the third timing generator to the first end portions of the pixel array and of the first to fourth circuit groups, is the same as a length of a signal line from the fourth timing generator to the second end portions of the pixel array and of the first to fourth circuit groups.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 96.0
- Lexical Diversity: 2.63934
- Patent Class: 358.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14499534', '11119697', '12676562', '13773121', '11860192']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5618699179545712
- 35 USC 102 Novelty (BERT): 0.5037619012167106
- Combined Prediction Score: 0.5560591162807852
- Mean Citation Score: 229.13582
- Max Citation Score: 236.66711
- Similarity Product: 159.6248110118359

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test