PATENT CLAIM ANALYSIS

Application Number: 15927481
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["438", "382000"]

Abstract:
A method of forming a target layer in semiconductor fabrication is disclosed that includes steps of forming a first layer by performing a first process at least one time and forming a second layer by performing a second process at least one time, wherein the first process may include supplying a first source gas, supplying a second source gas several times, and supplying an inert gas several times.

Claim (Index 17):
The method of  claim 11 , wherein the forming of the electrode pattern comprises:\n forming a first insulating layer on the first conductive line, the first insulating layer comprising a first trench exposing a top surface of the first conductive line; depositing the electrode layer to partially fill the first trench and to cover inner side surfaces and a bottom surface of the first trench; depositing a spacer layer to partially fill the first trench; forming a second insulating layer to fill a remaining portion of the first trench; and patterning the electrode layer, the spacer layer, and the second insulating layer to form a second trench crossing the first trench.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 1.89474
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15227334', '14970105', '15700154', '15160264', '13775496']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8514047121272461
- 35 USC 102 Novelty (BERT): 0.4851678319341494
- Combined Prediction Score: 0.8147810241079364
- Mean Citation Score: 186.848788
- Max Citation Score: 213.36049
- Similarity Product: 160.69283163172602

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test