PATENT CLAIM ANALYSIS

Application Number: 15949774
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["365", "156000"]

Abstract:
A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.

Claim (Index 12):
The write assist circuit of  claim 11 , wherein the first switchable conductive path includes:\n a gate electrode of the eighth NMOS transistor is connected to the power-supply voltage.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 91.0
- Lexical Diversity: 3.28889
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12958402', '14677991', '11750052', '13025872', '13901614']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8108999156898965
- 35 USC 102 Novelty (BERT): 0.4818267510639044
- Combined Prediction Score: 0.7779925992272972
- Mean Citation Score: 200.852354
- Max Citation Score: 212.45723
- Similarity Product: 154.9700601657355

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test