PATENT CLAIM ANALYSIS

Application Number: 16166000
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["712", "220000"]

Abstract:
A processor comprising: an execution unit for executing a respective thread in each of a repeating sequence of time slots; and a plurality of context register sets, each comprising a respective set of registers for representing a state of a respective thread. The context register sets comprise a respective worker context register set for each of the number of time slots the execution unit is operable to interleave, and at least one extra context register set. The worker context register sets represent the respective states of worker threads and the extra context register set being represents the state of a supervisor thread. The processor is configured to begin running the supervisor thread in each of the time slots, and to enable the supervisor thread to then individually relinquish each of the time slots in which it is running to a respective one of the worker threads.

Claim (Index 1):
A processor comprising:\n an execution unit arranged to execute a respective thread in each of a repeating sequence of different time slots, the sequence consisting of a plural number of time slots in which the execution logic is operable to interleave execution of the respective threads; and a plural number of context register sets, each comprising a respective set of registers for representing a respective state of a respective thread, wherein the context register sets comprise a respective worker context register set for each of the number of time slots the execution unit is operable to interleave in said sequence and at least one extra context register set, such that the number of context register sets is at least one greater than the number of time slots the execution unit is operable to interleave, the worker context register sets being arranged to represent the respective states of respective worker threads which perform computation tasks, and the extra context register set being arranged to represent the state of a supervisor thread which schedules execution of the tasks performed by the worker threads; wherein the processor is configured to begin running the supervisor thread in each of the time slots, and to enable the supervisor thread to then individually relinquish each of the time slots in which it is running to a respective one of the worker threads.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 2.62712
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15885955', '15886099', '15886185', '15886138', '12605201']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6284478964748471
- 35 USC 102 Novelty (BERT): 0.5503871504629482
- Combined Prediction Score: 0.6206418218736571
- Mean Citation Score: 325.325886
- Max Citation Score: 439.8989
- Similarity Product: 334.54817999645473

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test