PATENT CLAIM ANALYSIS

Application Number: 16000582
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "175000"]

Abstract:
In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.

Claim (Index 10):
The duty cycle controller of  claim 7 , wherein the delay circuit further comprises:\n a delay loop controller configured to output a signal to the unit delay circuit obtained by operating the output clock signal and a delayed feedback clock signal output from the unit delay circuit; and a loop counter configured to determine whether the predetermined delay time has elapsed since the output clock signal was input according to the delayed feedback clock signal, and configured to determine the predetermined loop count.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.7
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12400495', '13563863', '13420459', '13098154', '14810900']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8066671956569046
- 35 USC 102 Novelty (BERT): 0.4944443514809253
- Combined Prediction Score: 0.7754449112393066
- Mean Citation Score: 262.21605200000005
- Max Citation Score: 270.6687
- Similarity Product: 220.4396925213039

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test