PATENT CLAIM ANALYSIS

Application Number: 16012366
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "222000"]

Abstract:
A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.

Claim (Index 8):
The integrated circuit as recited in  claim 1 , wherein the high-priority transaction comprises executing a command to power down at least a portion of the memory controller.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.85965
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15353150', '12955112', '10982277', '15802781', '15785918']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7798778594547009
- 35 USC 102 Novelty (BERT): 0.5137393270202298
- Combined Prediction Score: 0.7532640062112538
- Mean Citation Score: 221.644532
- Max Citation Score: 237.2273
- Similarity Product: 132.659737609154

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test