PATENT CLAIM ANALYSIS

Application Number: 15925023
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["365", "185330"]

Abstract:
To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.

Claim (Index 1):
A reference voltage generation circuit comprising:\n a first MOS transistor including a first source terminal, a first drain terminal, and a first gate terminal in a floating state; a second MOS transistor including a second gate terminal connected to the first gate terminal, a second source terminal, a second drain terminal, and a second bulk terminal, the second source terminal, the second drain terminal, and the second bulk terminal being connected to the first source terminal and being connected to each other; a third MOS transistor including a third source terminal, a third drain terminal, and a third gate terminal in a floating state; a fourth MOS transistor including a fourth gate terminal connected to the third gate terminal, a fourth source terminal, a fourth drain terminal, and a fourth bulk terminal, the fourth source terminal, the fourth drain terminal, and the fourth bulk terminal being connected to the third drain terminal and being connected to each other; a first power source terminal; and a second power source terminal configured to have a lower voltage than a voltage of the first power source terminal when the first MOS transistor and the third MOS transistor are N-channel MOS transistors, and to have a higher voltage than the voltage of the first power source terminal when the first MOS transistor and the third MOS transistor are P-channel MOS transistors, wherein the first drain terminal is connected to the first power source terminal, the third source terminal is connected to the second power source terminal, and the first source terminal is connected to the third drain terminal; or wherein the third drain terminal is connected to the first power source terminal, the first source terminal is connected to the second power source terminal, and the first drain terminal is connected to the third source terminal.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 1.84444
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11526057', '15140639', '12792295', '13867055', '10484578']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7998468335599518
- 35 USC 102 Novelty (BERT): 0.495971780506255
- Combined Prediction Score: 0.7694593282545821
- Mean Citation Score: 228.707224
- Max Citation Score: 233.39963
- Similarity Product: 146.8596755191034

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test