PATENT CLAIM ANALYSIS

Application Number: 15955013
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["716", "134000"]

Abstract:
Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Claim (Index 15):
The method of  claim 14 , wherein adjusting a delay to the clock signal comprises:\n stepping through a range of delay of the adjustable delay element, wherein the range of delay corresponds to one half a data bit time.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.10256
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14339224', '15138142', '14059366', '14335681', '14516763']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3753794391340256
- 35 USC 102 Novelty (BERT): 0.5238240300540006
- Combined Prediction Score: 0.3902238982260232
- Mean Citation Score: 238.49645
- Max Citation Score: 386.63943
- Similarity Product: 258.0248584090233

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test