PATENT CLAIM ANALYSIS

Application Number: 15981928
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["257", "330000"]

Abstract:
A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

Claim (Index 24):
The device of  claim 21 , wherein the interface is the only interface along which the upper portion of the vertical channel and the lower portion of the vertical channel meet,\n the interface extends no higher than a plane level with the top surface of the substrate, and at least part of the inner surface of the sidewall of the lower channel and part of the top surface of the lower channel constitute the interface.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 93.0
- Lexical Diversity: 2.14545
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15514239', '15639733', '14831449', '14725476', '13800872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9286469365909034
- 35 USC 102 Novelty (BERT): 0.5150758121043283
- Combined Prediction Score: 0.8872898241422459
- Mean Citation Score: 250.361496
- Max Citation Score: 260.1696
- Similarity Product: 152.75686902923584

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test