PATENT CLAIM ANALYSIS

Application Number: 15871059
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "750000"]

Abstract:
A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

Claim (Index 3):
The semiconductor device of  claim 2 , further comprising:\n a bit line disposed on the pad.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 2.79487
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14995586', '14151288', '13949447', '15832756', '13229136']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9182814967042524
- 35 USC 102 Novelty (BERT): 0.5038582956608815
- Combined Prediction Score: 0.8768391765999155
- Mean Citation Score: 247.168702
- Max Citation Score: 250.33192000000005
- Similarity Product: 177.90887508090978

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test