PATENT CLAIM ANALYSIS

Application Number: 16249482
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["365", "185030"]

Abstract:
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claim (Index 7):
The non-volatile memory device of  claim 1 , wherein the command data, the address data, the write data and the read data are transferred in synchronization with one of rising and falling edges of the clock input signal when the non-volatile memory device is in a single data rate implementation.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.20339
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15937937', '15345552', '15868219', '13867437', '14984303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8397483306686844
- 35 USC 102 Novelty (BERT): 0.5533541541103548
- Combined Prediction Score: 0.8111089130128515
- Mean Citation Score: 405.235218
- Max Citation Score: 421.07736
- Similarity Product: 384.3384882402564

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test