PATENT CLAIM ANALYSIS

Application Number: 15938812
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["257", "365000"]

Abstract:
Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Claim (Index 20):
The IC device of  claim 19 , further comprising:\n an isolation feature disposed over the substrate and adjacent to the first and second fins, wherein the second ILD layer extends through an upper portion of the isolation feature.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 90.0
- Lexical Diversity: 2.51613
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13231750', '15882905', '15592899', '14940841', '14739233']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8936011047894915
- 35 USC 102 Novelty (BERT): 0.4903138387319398
- Combined Prediction Score: 0.8532723781837364
- Mean Citation Score: 176.818888
- Max Citation Score: 180.96541
- Similarity Product: 125.83214978358627

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test