PATENT CLAIM ANALYSIS

Application Number: 16102391
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-07
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

Claim (Index 2):
The semiconductor package according to  claim 1 , wherein in a central region of the lower chip, the centerline of one of the pillars and the centerline of one of the pads are aligned with each other, and\n in the peripheral region of the lower chip, an amount of the offset between the centerline of the pillar of the bump and the centerline of the corresponding one of the pads to which the bump is bonded varies among the bumps and the corresponding ones of the pads bonded to each other.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 96.0
- Lexical Diversity: 2.65217
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12907028', '15493096', '13188554', '15943072', '10424096']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9300825528621676
- 35 USC 102 Novelty (BERT): 0.4962726969244733
- Combined Prediction Score: 0.8867015672683983
- Mean Citation Score: 252.506064
- Max Citation Score: 268.55466
- Similarity Product: 225.5512519743061

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test