PATENT CLAIM ANALYSIS

Application Number: 15862859
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["711", "103000"]

Abstract:
A memory system includes: a memory device suitable for including a plurality of pages where data are stored and a plurality of memory blocks including the pages; and a controller suitable for receiving a plurality of commands from a host, performing command operations in response to the commands in the memory blocks, updating map data for the memory blocks according to the command operations being performed, and registering information on the map data in a data table for each of the memory blocks.

Claim (Index 5):
The memory system of  claim 4 ,\n wherein the controller calculates the loading time and the scanning time based on the number of the map segments included in the map data of each of the memory blocks, the map segment list of the map segments, and the number of the valid addresses included in each of the map segments, and wherein the map data, the map segments, and the valid addresses of the first memory blocks have a least size, and the first memory blocks have a valid addresses distribution of a maximal locality distribution or continuity/sequence distribution.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 86.0
- Lexical Diversity: 2.02273
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15407046', '15603519', '15406320', '15701624', '15448781']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5758714484859166
- 35 USC 102 Novelty (BERT): 0.5172445336238816
- Combined Prediction Score: 0.5700087569997132
- Mean Citation Score: 268.91025
- Max Citation Score: 282.5156
- Similarity Product: 163.26867630038262

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test