PATENT CLAIM ANALYSIS

Application Number: 16057979
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["341", "144000"]

Abstract:
In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Claim (Index 1):
A method, comprising:\n receiving a device clock signal; generating a synchronization (SYSREF) clock signal at least partially according to the device clock signal; generating a shifted clock signal at least partially according to the device clock signal; sampling, by a latch, the SYSREF clock signal using the shifted clock signal; and outputting the sampled SYSREF clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.675
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15673166', '15395489', '16036221', '14452535', '13799384']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5453368758813177
- 35 USC 102 Novelty (BERT): 0.4770268411324325
- Combined Prediction Score: 0.5385058724064292
- Mean Citation Score: 148.5166258
- Max Citation Score: 216.39505
- Similarity Product: 193.451433681804

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test