PATENT CLAIM ANALYSIS

Application Number: 16016132
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "154000"]

Abstract:
A data-processing device, such as a memory device, includes a signal generator configured to transmit an enable-signal, and a plurality of circuit elements arranged in an array of plurality of rows spaced along a direction, each of the plurality of the circuit elements configured to receive the enable-signal from the signal generator and to input and output data as a result of receiving the enable-signal. The device also includes an input/out (I/O) interface operatively connected to the plurality of circuit elements and located to propagate data from the I/O interface to the circuit elements in a first direction relative to the direction in which the rows are spaced and receive data propagated from the circuit elements to the I/O interface in a second direction relative to the first direction. The signal generator maintains the direction of enable-signal propagation relative to the direction of data propagation regardless of the direction of data propagation.

Claim (Index 11):
A memory device, comprising:\n a plurality of memory cells, each configured to input data in a WRITE operation and output data in a READ operation, the memory cells being arranged in an array of plurality of rows sequentially arranged along a first direction, each of the rows including at least one of the memory cells, a signal generator including a plurality of signal generator modules sequentially arrange in a second direction, each configured to supply an input/output (I/O) enable-signal to a respective one of the rows of memory cells to enable the input and output of data, the signal generator further including a pulse signal generator located and adapted to propagate an enable-signal along a direction that is the same or opposite to the second direction to the plurality of signal generator modules to sequentially enable the signal generator modules to supply the respective I/O enable-signal; and an input/out (I/O) interface located proximate one side of the array, operatively connected to the plurality of memory cells, and configured to propagate data from the I/O interface to the memory cells in the first direction in the WRITE operation and to receive data propagated from the memory cells to the I/O interface in a third direction that is opposite to the first direction in the READ operation; the signal generator and the array being mutually arranged to propagate the enable-signal to the plurality of signal generator modules in a direction that bears same directional relationship to the first direction in the WRITE operation as it does to the second direction in the READ operations.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 94.0
- Lexical Diversity: 2.77586
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10455601', '12543256', '12715742', '10766428', '12703354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7751335723921718
- 35 USC 102 Novelty (BERT): 0.455536334282731
- Combined Prediction Score: 0.7431738485812278
- Mean Citation Score: 148.113496
- Max Citation Score: 167.18492
- Similarity Product: 134.22155440693618

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test