PATENT CLAIM ANALYSIS

Application Number: 16279719
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["327", "270000"]

Abstract:
A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

Claim (Index 5):
The asynchronous clock signal generator circuit of  claim 1 , wherein the flip-flop is configured to latch the output of the counter at the rising edge of the clock signal and the digital filter circuit is configured to accumulate the output of the subtractor circuit at the falling edge of the clock signal.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 99.0
- Lexical Diversity: 2.86792
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15658272', '14856432', '11819070', '14626441', '14106269']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7854611476844632
- 35 USC 102 Novelty (BERT): 0.5211704118963169
- Combined Prediction Score: 0.7590320741056485
- Mean Citation Score: 208.2435
- Max Citation Score: 342.3559
- Similarity Product: 282.10050690442915

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test