PATENT CLAIM ANALYSIS

Application Number: 16011308
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "190000"]

Abstract:
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Claim (Index 1):
An integrated circuit structure, comprising:\n a channel structure above a semiconductor fin above a substrate comprising silicon, the channel structure comprising a Group III-V material; a gate structure on a top surface, along sidewall surfaces, and on a bottom surface of the channel structure, the gate structure further in a trench below the bottom surface of the channel structure, the gate structure comprising:\n a gate dielectric layer on the top surface, along the sidewall surfaces, and on the bottom surface of the channel structure, the gate dielectric layer further along sidewalls and a bottom of the trench, and the gate dielectric layer comprising hafnium and oxygen; and \n a conductive layer on the gate dielectric layer on the top surface, along the sidewall surfaces, and on the bottom surface of the channel structure, and further on the gate dielectric layer along the sidewalls and the bottom of the trench, the conductive layer comprising a metal nitride; \n a source structure at a first side of the channel structure; and \n a drain structure at a second side of the channel structure opposite the first side, wherein the gate structure has a depth into the semiconductor fin deeper than a depth of the source structure and the drain structure.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.2381
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13749139', '15134093', '14821561', '15135262', '13629154']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9197409838050332
- 35 USC 102 Novelty (BERT): 0.5123645608259907
- Combined Prediction Score: 0.879003341507129
- Mean Citation Score: 275.11944000000005
- Max Citation Score: 304.9434
- Similarity Product: 233.001640166688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test