PATENT CLAIM ANALYSIS

Application Number: 15777829
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-07
Patent Classification: ["257", "072000"]

Abstract:
An array substrate and a manufacturing method thereof, and display panel are disclosed. The array substrate includes a substrate, a thin film transistor disposed on the substrate and a common electrode disposed on a side of the thin film transistor away from the substrate. The common electrode includes a first hollowed-out portion. An active layer of the thin film transistor includes a source electrode region, a drain electrode region and a channel region. An orthographic projection of the first hollowed-out portion on the substrate at least covers an orthographic projection of the channel region on the substrate.

Claim (Index 4):
The array substrate according to  claim 1 , wherein, the array substrate further comprises an insulating layer disposed between the thin film transistor and the common electrode, and a passivation layer and a pixel electrode which are sequentially disposed on a side of the common electrode away from the substrate, wherein, the insulating layer comprises a first via hole, the passivation layer comprises a second via hole and a second hollowed-out portion, and an orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the first hollowed-out portion on the substrate,\n the common electrode further comprises a third via hole; the orthographic projection of the first hollowed-out portion on the substrate overlaps with an orthographic projection of the second hollowed-out portion on the substrate; an orthographic projection of the first via hole on the substrate, an orthographic projection of the second via hole on the substrate and an orthographic projection of the third via hole on the substrate are overlapped with each other, a size of the third via hole is greater than or equal to a size of the first via hole, and the size of the third via hole is greater than a size of the second via hole; and the pixel electrode is electrically connected to a drain electrode of the thin film transistor through the first via hole, the second via hole and the third via hole.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 93.0
- Lexical Diversity: 2.44186
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16080207', '15807451', '15750984', '15529495', '15568155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9365949518452455
- 35 USC 102 Novelty (BERT): 0.519827934828379
- Combined Prediction Score: 0.8949182501435589
- Mean Citation Score: 305.86805
- Max Citation Score: 318.64468
- Similarity Product: 226.59831142104383

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test