PATENT CLAIM ANALYSIS

Application Number: 15884167
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["438", "107000"]

Abstract:
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Claim (Index 3):
The microelectronic device of  claim 1 , wherein the plurality of cavities extending through the second dielectric layer each include at least one sidewall, and wherein the at least one sidewall is substantially perpendicular to the first substrate contact surface.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 86.0
- Lexical Diversity: 2.2381
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13740698', '13069601', '14643329', '15668179', '12778335']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8602430938063843
- 35 USC 102 Novelty (BERT): 0.5228512655710189
- Combined Prediction Score: 0.8265039109828478
- Mean Citation Score: 250.522154
- Max Citation Score: 314.0601
- Similarity Product: 248.5975045381665

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test