PATENT CLAIM ANALYSIS

Application Number: 15946324
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["341", "118000"]

Abstract:
A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.

Claim (Index 15):
The circuit of  claim 13 , wherein the summation circuit is further configured to store the summed value in the second register as the accumulated value in response to both the assertion of the decrement signal and a deassertion of the reset signal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.39286
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13068435', '15256444', '14202420', '12543071', '13438268']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5916354228329861
- 35 USC 102 Novelty (BERT): 0.4864619115824878
- Combined Prediction Score: 0.5811180717079363
- Mean Citation Score: 158.81598200000005
- Max Citation Score: 165.38701
- Similarity Product: 117.36094407614948

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test