PATENT CLAIM ANALYSIS

Application Number: 16047048
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "297000"]

Abstract:
The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

Claim (Index 15):
A method comprising:\n forming an interconnection structure on a substrate, the interconnection structure comprising a plurality of metal layers; and forming a capacitor between a first metal layer and a second metal layer of the plurality of metal layers, wherein the second metal layer is disposed above the first metal layer, wherein the capacitor comprises a dielectric material layer and a plurality of nanocrystals dispersed in the dielectric material layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 1.85714
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14995036', '16001075', '11730810', '15137362', '11807466']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9058140476936958
- 35 USC 102 Novelty (BERT): 0.4769062435278129
- Combined Prediction Score: 0.8629232672771074
- Mean Citation Score: 154.43041799999995
- Max Citation Score: 211.03865
- Similarity Product: 171.98127879748642

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test