PATENT CLAIM ANALYSIS

Application Number: 16057204
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Claim (Index 16):
A kit for producing a multi-chip module hybrid integrated circuit, the kit comprising:\n an interconnecting substrate; at least one VLSI core integrated circuit (\u201cIC\u201d) that is compatible for installation on the interconnecting substrate; and a plurality of chiplets compatible for installation on the interconnecting substrate on at least one chiplet-compatible chip site provided on said interconnecting substrate, wherein the plurality of chiplets includes at least one of an active chiplet that comprises at least one active circuit, a mixed chiplet that comprises at least one active circuit and at least one passive circuit, and a passive chiplet that comprises at least 40 passive components, not including interconnections therebetween; wherein the interconnecting substrate provides interconnection between the at least one VLSI core IC and the at least one chiplet-compatible chip site; and wherein, for each of a plurality of enhanced features that are not supported by the at least one VLSI core IC, a group of one or more of the plurality of chiplets are installed on the interconnecting substrate so as to implement the enhanced feature.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 96.0
- Lexical Diversity: 1.88172
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13395813', '15725030', '14848477', '15178240', '12489486']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5630744379826368
- 35 USC 102 Novelty (BERT): 0.4870880056486223
- Combined Prediction Score: 0.5554757947492354
- Mean Citation Score: 205.019484
- Max Citation Score: 214.88882
- Similarity Product: 142.65590486672878

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test