PATENT CLAIM ANALYSIS

Application Number: 15925762
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189050"]

Abstract:
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Claim (Index 25):
The semiconductor device according to  claim 24 , further comprising:\n a memory array including a plurality of memory cells, wherein the plurality of memory cells are coupled to a plurality of bit lines and a plurality of word lines respectively, wherein the plurality of the first data buffers and the plurality of the logic circuits are arranged in an input circuit for the memory array, wherein the plurality of the logic circuits includes a plurality of the first data input nodes for receiving a plurality of the data signals respectively, and wherein the plurality of the logic circuits provide the plurality of the data signals to the plurality of bit lines respectively.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.53333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15211298', '15607599', '15841950', '14944262', '11320751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7831258879094067
- 35 USC 102 Novelty (BERT): 0.5012348009804992
- Combined Prediction Score: 0.754936779216516
- Mean Citation Score: 213.51475
- Max Citation Score: 289.29242
- Similarity Product: 215.36425158403875

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test