PATENT CLAIM ANALYSIS

Application Number: 16136046
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["327", "158000"]

Abstract:
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second arid third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

Claim (Index 16):
The apparatus of  claim 11 , further comprising a counter circuit configured to count a number of clock pulses of the clock signal during the first period,\n wherein the clock divider circuit has a frequency division ratio based, at least in part, on the number of clock pulses of the clock signal.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 97.0
- Lexical Diversity: 1.97674
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15786362', '13415777', '11643916', '11000940', '15059453']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7335112647741517
- 35 USC 102 Novelty (BERT): 0.5349708294749371
- Combined Prediction Score: 0.7136572212442303
- Mean Citation Score: 241.812814
- Max Citation Score: 366.8524
- Similarity Product: 260.8346458718538

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test