PATENT CLAIM ANALYSIS

Application Number: 16033759
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
Methods of forming semiconductor devices include forming a lower dielectric layer to a height below a height of a dummy gate hardmask disposed across multiple device regions. The dummy gate structure includes a dummy gate and a dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.

Claim (Index 7):
The method of  claim 4 , further comprising forming a sacrificial liner over the dummy gate after the dummy gate hardmask is etched back to protect the dummy gate from the conversion of the protective layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.08571
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15397122', '16033786', '14984201', '15608159', '15149764']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9183677544491768
- 35 USC 102 Novelty (BERT): 0.517341811977774
- Combined Prediction Score: 0.8782651602020365
- Mean Citation Score: 247.556636
- Max Citation Score: 328.77255
- Similarity Product: 275.25975974251634

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test