PATENT CLAIM ANALYSIS

Application Number: 16368485
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["345", "213000"]

Abstract:
A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Claim (Index 9):
The semiconductor device according to  claim 2 , wherein:\n the first current mirror includes\n a pair of second conductivity-type first stage transistors first terminals of which are connected to the first power supply terminal, and control terminals of which are connected to each other, \n fifth and sixth nodes connected to second terminals of the pair of first stage transistors, respectively, and \n a pair of second conductivity-type second stage transistors first terminals of which are connected to the fifth and sixth nodes, respectively, second terminals of which are connected to the first and second nodes, respectively, and control terminals of which are connected to each other; \n the second terminal of one of the pair of second stage transistors connected to the second node is connected to the control terminals of the pair of first stage transistors, and the first and second common wires are connected to the sixth and fifth nodes, respectively; the second current mirror includes\n a pair of first conductivity-type first stage transistors first terminals of which are connected to the second power supply terminal, and control terminals of which are connected to each other, \n seventh and eighth nodes connected to second terminals of the pair of first conductivity-type first stage transistors, respectively, and \n a pair of first conductivity-type second stage transistors first terminals of which are connected to the seventh and eighth nodes, respectively, second terminals of which are connected to the third and fourth nodes, respectively, and control terminals of which are connected to each other; and \n the second terminal of one of the pair of first conductivity-type second stage transistors connected to the fourth node is connected to the control terminals of the pair of first conductivity-type first stage transistors, and the third and fourth common wires are connected to the eighth and seventh nodes, respectively.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 99.0
- Lexical Diversity: 1.85714
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15442107', '13155023', '13029888', '15818628', '16243249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6893441286934572
- 35 USC 102 Novelty (BERT): 0.6132274339942543
- Combined Prediction Score: 0.681732459223537
- Mean Citation Score: 296.590204
- Max Citation Score: 540.95166
- Similarity Product: 519.1442082971836

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test