PATENT CLAIM ANALYSIS

Application Number: 16363622
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-09
Patent Classification: ["716", "111000"]

Abstract:
A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Claim (Index 29):
A computing device-implemented method for fabricating a semiconductor device structure in a virtual fabrication environment provided by at least one computing device equipped with one or more processors, the method comprising:\n receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated; inserting a user-specified virtual metrology measurement step into the process sequence, the virtual metrology measurement step indicating a point during the process sequence for a measurement to be performed; performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:\n executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, and \n performing the measurement indicated by the virtual metrology measurement step within a region of the 3D structural model; and \n exporting virtual metrology measurement data generated from the virtual metrology measurement step of the virtual fabrication run to an automated data analysis tool or a display.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 99.0
- Lexical Diversity: 1.67241
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13831440', '13831444', '13831450', '13831433', '15089999']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.455655140128646
- 35 USC 102 Novelty (BERT): 0.5916432515414473
- Combined Prediction Score: 0.4692539512699262
- Mean Citation Score: 508.18026
- Max Citation Score: 567.6293
- Similarity Product: 516.4403996914148

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test