PATENT CLAIM ANALYSIS

Application Number: 16232834
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["710", "005000"]

Abstract:
Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.

Claim (Index 7):
The integrated circuit device of  claim 6 , wherein the FIFO controller enables the memory block to be a FIFO for any location in system memory.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.88889
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16146849', '11360337', '12060776', '16123765', '15438228']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6849685086301519
- 35 USC 102 Novelty (BERT): 0.4803439720169105
- Combined Prediction Score: 0.6645060549688278
- Mean Citation Score: 168.573196
- Max Citation Score: 171.96599999999995
- Similarity Product: 117.73218683409686

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test