PATENT CLAIM ANALYSIS

Application Number: 16195738
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["365", "185110"]

Abstract:
A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.

Claim (Index 11):
The method according to  claim 10 , further comprising:\n in response to the second command set, calculating the read voltage applied to the second word line based on the stored correction value.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 3.37255
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15822581', '15442683', '16156912', '16118543', '15439912']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7991612690149718
- 35 USC 102 Novelty (BERT): 0.4999273760627611
- Combined Prediction Score: 0.7692378797197507
- Mean Citation Score: 231.136242
- Max Citation Score: 282.7221
- Similarity Product: 211.6410810546041

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test