PATENT CLAIM ANALYSIS

Application Number: 16022274
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["711", "125000"]

Abstract:
An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.

Claim (Index 7):
The method of  claim 1  wherein said determining is based on information stored in a translation lookaside buffer.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 94.0
- Lexical Diversity: 1.61446
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15801649', '15946848', '10039368', '10037041', '13672188']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5015406145466168
- 35 USC 102 Novelty (BERT): 0.5165330313306706
- Combined Prediction Score: 0.5030398562250222
- Mean Citation Score: 217.994932
- Max Citation Score: 259.23468
- Similarity Product: 163.2489794227195

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test