PATENT CLAIM ANALYSIS

Application Number: 16224206
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["365", "148000"]

Abstract:
Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Claim (Index 12):
The method of  claim 11 , further comprising setting the selected bit line to ground.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 3.30909
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16043688', '15039784', '14567988', '15817887', '15206616']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8348530906289652
- 35 USC 102 Novelty (BERT): 0.5421529538404563
- Combined Prediction Score: 0.8055830769501142
- Mean Citation Score: 354.860182
- Max Citation Score: 413.5406
- Similarity Product: 282.5565735280752

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test