PATENT CLAIM ANALYSIS

Application Number: 16424344
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["438", "299000"]

Abstract:
An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.

Claim (Index 11):
The system of  claim 1 , wherein the body region of the transistor of each memory cell of the memory cell array is electrically floating, and wherein each memory cell is programmable to store one of two logic states, each logic state is representative of a charge in the body region of the associated transistor.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 100.0
- Lexical Diversity: 2.13846
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12268671', '14028309', '12363841', '12332413', '11633311']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.905919693455402
- 35 USC 102 Novelty (BERT): 0.548117559692455
- Combined Prediction Score: 0.8701394800791072
- Mean Citation Score: 373.309114
- Max Citation Score: 440.98917
- Similarity Product: 390.37295488989287

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test