PATENT CLAIM ANALYSIS

Application Number: 16235956
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["326", "038000"]

Abstract:
The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.

Claim (Index 14):
The electronic device of  claim 10 , wherein the FPGA comprises:\n an array of sectors, wherein each sector comprises a clock distribution element comprises a sector delay element; and a plurality of boundary phase difference detection circuitry configurable to receive at least two clocks from clock distribution elements of adjacent sectors and to control at least one sector delay element of adjacent sectors.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 98.0
- Lexical Diversity: 1.37838
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16236062', '14882065', '16146849', '15392225', '15338074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6714941240172732
- 35 USC 102 Novelty (BERT): 0.4842682969573538
- Combined Prediction Score: 0.6527715413112812
- Mean Citation Score: 165.987802
- Max Citation Score: 189.29652
- Similarity Product: 128.53192340185402

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test