PATENT CLAIM ANALYSIS

Application Number: 15874205
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "427000"]

Abstract:
One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

Claim (Index 7):
The method of  claim 1 , wherein said patterned layer of metal-containing material is electrically conductive.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 1.89583
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15874077', '11368898', '11461457', '11339839', '12901845']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9178738611324552
- 35 USC 102 Novelty (BERT): 0.4889191350038909
- Combined Prediction Score: 0.8749783885195987
- Mean Citation Score: 173.22834600000004
- Max Citation Score: 227.56474
- Similarity Product: 177.20719814465642

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test