PATENT CLAIM ANALYSIS

Application Number: 16221552
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["327", "108000"]

Abstract:
An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

Claim (Index 6):
The apparatus according to  claim 1 , wherein the first bias voltage depends on a supply voltage of the CMOS circuitry.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 1.65217
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15429690', '15634716', '13850269', '11028934', '13850271']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7828258879159693
- 35 USC 102 Novelty (BERT): 0.5383436835579641
- Combined Prediction Score: 0.7583776674801688
- Mean Citation Score: 245.036482
- Max Citation Score: 385.01248
- Similarity Product: 382.7453027192688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test