PATENT CLAIM ANALYSIS

Application Number: 16157104
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "578000"]

Abstract:
Provided is a power transistor device including a substrate structure, a first conductive layer, a second conductive layer and a third conductive layer. The substrate structure has a base portion and fin portions. The fin portions protrude from a surface of the base portion and extend along a first direction. The first conductive layer is disposed across the fin portions and extends along a second direction different from the first direction. The second conductive layer is disposed across the fin portions, is located at one side of the first conductive layer and extends along the second direction. The first spacer is disposed between and in physical contact with the first conductive layer and the second conductive layer.

Claim (Index 9):
The power transistor device according to  claim 6 , further comprising:\n a third spacer, disposed between and in physical contact with the second conductive layer and the fourth conductive layer; and a fourth spacer, disposed between and in physical contact with the third conductive layer and the fifth conductive layer.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 2.8
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15873910', '15353163', '13632162', '15450193', '15226906']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9133404263575456
- 35 USC 102 Novelty (BERT): 0.5149247857688142
- Combined Prediction Score: 0.8734988622986726
- Mean Citation Score: 223.08041
- Max Citation Score: 312.2146600000001
- Similarity Product: 238.5582949376083

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test