PATENT CLAIM ANALYSIS

Application Number: 15945799
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "407000"]

Abstract:
Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.

Claim (Index 6):
The structure of  claim 1 , wherein an upper surface of the second metal is recessed below an upper surface of the inter-layer dielectric.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 2.72881
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14730444', '14871580', '15859947', '15297850', '15793163']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9195603120817942
- 35 USC 102 Novelty (BERT): 0.480856620962389
- Combined Prediction Score: 0.8756899429698537
- Mean Citation Score: 179.263974
- Max Citation Score: 198.73132
- Similarity Product: 152.30205307004215

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test