PATENT CLAIM ANALYSIS

Application Number: 15871818
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "324000"]

Abstract:
In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

Claim (Index 8):
The method for manufacturing a semiconductor device according to  claim 7 ,\n wherein the step (d) includes the steps of: (d3) sequentially stacking a fifth insulation film and a sixth insulation film over the top surface of the semiconductor substrate in the first region and the third region in such a manner as to cover each of the first gate electrode and the third gate electrode, and thereby forming the second insulation film including the fifth insulation film and the sixth insulation film; and (d4) subjecting the sixth insulation film to anisotropic etching, and thereby exposing the top surface of the fifth insulation film, wherein the step (f) includes the steps of: (f4) after the step (e), with the third region covered with a protective film, forming a pair of first semiconductor regions having a first conductivity type at the top surface of the semiconductor substrate in the first region, and then, removing the protective film; and (f5) forming a pair of second semiconductor regions having the first conductivity type, and having a higher density than that of the first semiconductor region at the top surface of the semiconductor substrate in the first region, and thereby forming the first source/drain regions each formed of the first semiconductor region and the second semiconductor region, the method further comprising the steps of: (g) after the step (f4), forming a seventh insulation film covering the side surface of the third gate electrode via the second insulation film; (h) removing the fifth insulation film and the fourth insulation film exposed from the seventh insulation film, and then, forming an epitaxial layer over the top surface of the semiconductor layer; and (i) before the step (f5), removing the seventh insulation film, and a part of the fifth insulation film, and thereby exposing each of the top surface of the semiconductor layer, and the top surface of the semiconductor substrate in the first region from the fifth insulation film.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.26984
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13964576', '15011510', '15661649', '14921445', '15468673']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9304812944350112
- 35 USC 102 Novelty (BERT): 0.5154987679077386
- Combined Prediction Score: 0.8889830417822839
- Mean Citation Score: 295.1903220000001
- Max Citation Score: 312.2362
- Similarity Product: 239.3011486279607

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test