PATENT CLAIM ANALYSIS

Application Number: 15763828
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-12
Patent Classification: ["257", "095000"]

Abstract:
The invention relates to an optoelectronic semiconductor chip ( 100 ), comprising an n-doped semiconductor layer ( 3 ), a p-doped semiconductor layer ( 5 ) and an active layer ( 4 ) arranged between the n-doped semiconductor layer ( 3 ) and the p-doped semiconductor layer ( 5 ), wherein the p-doped semiconductor layer ( 5 ) has an electrically conductive layer ( 7 ) arranged above it that is set up for making electrical contact with the p-doped semiconductor layer ( 5 ), wherein a lateral edge ( 2 ) is arranged laterally with respect to the n-doped semiconductor layer ( 3 ), the p-doped semiconductor layer ( 5 ) and the active layer ( 4 ), wherein the lateral edge ( 2 ) has at least two oblique edge portions, wherein a first edge portion ( 21 ) has at least areas arranged laterally with respect to the p-doped semiconductor layer ( 5 ), wherein a second lateral edge ( 22 ) has at least areas arranged laterally with respect to the n-doped semiconductor layer ( 3 ), wherein the angle of the first edge portion ( 21 ) in relation to the active layer ( 4 ) is shallower than the angle of the second edge portion ( 22 ), and wherein the electrically conductive layer ( 7 ) is at a lateral distance from the lateral edge ( 2 ).

Claim (Index 10):
A method for producing an optoelectronic semiconductor chip comprising the steps of:\n A) Providing at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and an active layer, which is arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, B) Applying an electrically conductive layer over the p-doped semiconductor layer, C) Applying a mask at least in regions to the electrically conductive layer, D) Forming the side flank, which extends laterally with respect to the n-doped semiconductor layer, to the p-doped semiconductor layer and to the active layer, with the partial steps of: D1) Removal of the electrically conductive layer and at least partially of the n-doped semiconductor layer, p-doped semiconductor layer and active layer in the regions which are not covered by the mask, D2) Withdrawal of the mask at least laterally in the direction away from the forming side flank, D3) Removal of the electrically conductive layer, such that the side flank is laterally spaced from the electrically conductive layer, wherein the side flank has at least two angular partial flanks, wherein the first partial flank is arranged at least in regions laterally with respect to the p-doped semiconductor layer, wherein the second partial flank is arranged at least in regions laterally with respect to the n-doped semiconductor layer, wherein the angle of the first partial flank with respect to the active layer is flatter than the angle of the second partial flank.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 3.72727
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15573467', '15018845', '13821554', '16085934', '15522783']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9236695538326132
- 35 USC 102 Novelty (BERT): 0.5045417532261965
- Combined Prediction Score: 0.8817567737719715
- Mean Citation Score: 274.778632
- Max Citation Score: 299.67538
- Similarity Product: 257.17625307195425

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test