PATENT CLAIM ANALYSIS

Application Number: 15991020
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["327", "156000"]

Abstract:
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Claim (Index 15):
A time-to-digital converter circuit, comprising:\n a first trigger circuit to generate a first trigger signal responsive to an asserted edge of a third clock coincident with a first clock asserted high; a second trigger circuit to generate a second trigger signal responsive to an asserted edge of the third clock coincident with a second clock asserted high; an exclusive-OR gate coupled to the first trigger circuit and the second trigger circuit and to generate an exclusive-OR output signal responsive to the first of the first or second trigger signals to be a logic high; a synchronization circuit coupled to the logic gate and configured to synchronize the logic gate output signal to the third clock to produce a synchronization output signal; a counter circuit to count pulses of the synchronization output signal; a two's complement circuit to convert a count value derived from the counter circuit to a two's complement signal; a multiplexer including a first input, a second input, and a multiplexer output, the first input coupled to receive the count value derived from the counter circuit, the second input coupled to receive the two's complement signal and the multiplexer output comprising the signal from the first or second inputs based on a control signal.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 93.0
- Lexical Diversity: 2.625
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15183752', '10839201', '15675160', '12018770', '13380392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7733703347530461
- 35 USC 102 Novelty (BERT): 0.464801765211102
- Combined Prediction Score: 0.7425134777988517
- Mean Citation Score: 171.15700599999997
- Max Citation Score: 173.64496
- Similarity Product: 136.02997354940413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test