PATENT CLAIM ANALYSIS

Application Number: 16047953
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "194000"]

Abstract:
A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.

Claim (Index 10):
The data storage device of  claim 9 , wherein the one or more timing margins are based on the read of the predefined data pattern at each of the one or more intervals of the delayed data strobe signal.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 95.0
- Lexical Diversity: 2.4
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15962206', '15467775', '15648909', '12557658', '14047118']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8121629680252425
- 35 USC 102 Novelty (BERT): 0.4882137412856867
- Combined Prediction Score: 0.779768045351287
- Mean Citation Score: 197.336142
- Max Citation Score: 215.64778
- Similarity Product: 149.86118226979494

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test