PATENT CLAIM ANALYSIS

Application Number: 15867036
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "350000"]

Abstract:
Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

Claim (Index 3):
The method of  claim 2 ,\n wherein the forming of the sidewall spacer comprises:\n conformally depositing a first spacer layer; \n selectively and anisotropically etching the first spacer layer to remove horizontal portions of the first spacer layer; \n after the selectively and anisotropically etching of the first spacer layer, conformally depositing a second spacer layer; and \n selectively and anisotropically etching the second spacer layer to remove horizontal portions of the second spacer layer so as to form a multi-layer sidewall spacer and expose top surfaces of the second portions of the semiconductor fin, \n wherein the forming of the first transistor further comprises forming a first layer of interlayer dielectric material adjacent to the multi-layer sidewall spacer such that top surfaces of the fin sections are at or below a level of a top surface of the first layer of interlayer dielectric material, wherein the first spacer layer, the second spacer layer and the first layer of interlayer dielectric material comprise different dielectric materials, and wherein the widening of the source/drain openings comprises:\n selectively and isotropically etching the second spacer layer such that the second spacer layer is completely removed from the source/drain openings without exposing the sacrificial gate; and \n selectively and isotropically etching the first spacer layer such that the first spacer layer is completely removed.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 86.0
- Lexical Diversity: 1.95181
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15387933', '15658835', '15787009', '15715220', '15862064']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.940103035551508
- 35 USC 102 Novelty (BERT): 0.5350007719675859
- Combined Prediction Score: 0.8995928091931158
- Mean Citation Score: 353.47274199999987
- Max Citation Score: 374.74036
- Similarity Product: 284.33952754984136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test