PATENT CLAIM ANALYSIS

Application Number: 15950516
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-01
Patent Classification: ["345", "210000"]

Abstract:
A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.

Claim (Index 12):
A scan driver comprising stage circuits coupled to respective scan lines, an i-th (i being a natural number) stage circuit of the stage circuits comprising:\n an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node; an input circuit coupled to the second power input terminal and configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal; a first driver coupled to both a first power input terminal and the second power input terminal, the first power input terminal being configured to receive a voltage of a first power source, the first driver being configured to control the voltages of the first node and the second node in response to both the third clock signal and the voltages of the third node and the fourth node; a second driver coupled to the first power input terminal and configured to supply the voltage of the first power source to the fourth node in response to both the fourth clock signal and the voltage of the second node; and a third driver configured to control the voltage of the second node in response to both the fourth clock signal and the voltage of the second node.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 3.675
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15692609', '14456995', '13687230', '13249091', '14158709']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6497520351276075
- 35 USC 102 Novelty (BERT): 0.5205293002232334
- Combined Prediction Score: 0.6368297616371701
- Mean Citation Score: 310.9061000000001
- Max Citation Score: 329.3755
- Similarity Product: 295.3055701573193

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test