PATENT CLAIM ANALYSIS

Application Number: 15882521
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Claim (Index 5):
The method of  claim 1 , further comprising forming contact via structures on a respective one of the electrically conductive layers in the first terrace region and in the second terrace region.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.26415
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15611220', '15877219', '15632983', '15488924', '15813579']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9381201003420472
- 35 USC 102 Novelty (BERT): 0.5610244618833288
- Combined Prediction Score: 0.9004105364961752
- Mean Citation Score: 405.285566
- Max Citation Score: 476.46417
- Similarity Product: 335.9865232396084

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test