PATENT CLAIM ANALYSIS

Application Number: 16051772
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["029", "852000"]

Abstract:
A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.

Claim (Index 4):
A structure for a multi-layered a printed circuit board (PCB) comprising:\n a multi-layered printed circuit board (PCB) formed of individual layers that pressed together that are first etching each of said individual layers of said PCB except for an outer layer; a first signal trace placed on any one of said layers of said PCB; a second signal trace placed on another layer of said PCB; adding or inserting seed resist material to said layers of said PCB;\n At least one via hole drilled through said PCB and intersecting said first signal trace and said second signal trace with a conductive material that is electro-deposited on said layers of said first and said signal traces; \n plated seed resist layer applied by electroless plating to said layers; and said outer layers being etched thereby preventing electrically conductive material from attaching to walls of said vias prior to electro-deposition of conductive material thereby electro-plating said via and adding or inserting seed-resist material on a wall of said via; \n seed-resist material added or inserted into said PCB on said via hole to prevent electrically conductive material from attaching to a wall of said vias prior to electro-deposition of conductive material.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 1.56757
- Patent Class: 29.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12483223', '14205331', '15723086', '12190551', '14205337']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.860636984812884
- 35 USC 102 Novelty (BERT): 0.4730230819806373
- Combined Prediction Score: 0.8218755945296593
- Mean Citation Score: 174.645696
- Max Citation Score: 186.86516
- Similarity Product: 142.85575692927122

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test