PATENT CLAIM ANALYSIS

Application Number: 16188332
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["257", "288000"]

Abstract:
A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.

Claim (Index 9):
The semiconductor device according to  claim 1 , wherein the semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET).

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 3.42222
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14766955', '16048488', '16113523', '16036324', '12182322']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.936540998141152
- 35 USC 102 Novelty (BERT): 0.5064808198123739
- Combined Prediction Score: 0.893534980308274
- Mean Citation Score: 266.181958
- Max Citation Score: 278.28085
- Similarity Product: 209.0061153112113

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test