PATENT CLAIM ANALYSIS

Application Number: 16145734
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-04
Patent Classification: ["365", "185210"]

Abstract:
A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.

Claim (Index 19):
A method of operating a sense-amplifier circuit, the method comprising:\n during a differential-ended reading operation, receiving a first cell current from a bit line associated with a memory cell; during the differential-ended reading operation, receiving a first reference current from a reference bit line associated with a complementary memory cell; during the differential-ended reading operation, generating a first output voltage at a first output terminal and a second output voltage at a second output terminal, the first and second output voltages being a function of a difference between the first cell current and the first reference current; during a single-ended reading operation, receiving a second cell current from a bit line associated with the memory cell; during the single-ended reading operation, receiving a second reference current from a reference current generator; during the single-ended reading operation, generating a third output voltage at the first output terminal and a fourth output voltage at the second output terminal, the third and fourth output voltages being a function of a difference between the second cell current and the second reference current; and causing an injection of current into a source line associated with the memory cell and the complementary memory cell, the injected current being substantially uniform in the differential and in the single-ended reading operations.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 2.29688
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12883072', '15212211', '15275362', '11726993', '12911575']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8000466984743101
- 35 USC 102 Novelty (BERT): 0.4755232044040466
- Combined Prediction Score: 0.7675943490672837
- Mean Citation Score: 223.855316
- Max Citation Score: 239.12238
- Similarity Product: 201.20032784535528

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test