PATENT CLAIM ANALYSIS

Application Number: 16243455
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["327", "538000"]

Abstract:
An oscillator circuit including a ring oscillator and a reference current source is provided. The ring oscillator includes an odd number of inverter stages. Each inverter stage includes a first transistor having a first reference threshold that varies over temperature. The reference current source is configured to generate a plurality of currents, where a respective current is applied directly to the drain of a respective first transistor of a respective inverter stage. The reference current source includes a reference transistor that has a second reference threshold that varies over temperature; a resistor coupled between a gate and a source of the reference transistor; a second transistor having a source coupled to the gate of the reference transistor for generating a reference current that flows through the resistor to regulate a voltage of the resistor to the second threshold voltage; and a current mirror configured to generate the plurality of currents.

Claim (Index 1):
An oscillator circuit, comprising:\n a ring oscillator including a plurality of inverter stages having an odd number, the plurality of inverter stages comprising a first inverter stage, a last inverter stage, and one or more intermediate inverter stages, wherein each inverter stage of the plurality of inverter stages includes:\n an input terminal; \n an output terminal; \n a first transistor having a drain coupled to the output terminal, a source coupled to a reference voltage, and a gate coupled to the input terminal, wherein the first transistor has a first reference threshold that varies; and \n a capacitance having a first side coupled to the drain of the first transistor and a second side coupled to the source of the first transistor, wherein the input terminal of an intermediate inverter stage of the one or more intermediate inverter stages is coupled to the output terminal of one of: the first inverter stage or another intermediate inverter stage of the one or more intermediate inverter stages that is an upstream inverter stage, wherein the output terminal of the intermediate inverter stage is coupled to the input terminal of one of: the last inverter stage or another intermediate inverter stage of the one or more intermediate inverter stages that is a downstream inverter stage, and wherein the input terminal of the first inverter stage is coupled to the output terminal of the last inverter stage; and \n a reference current source configured to generate a plurality of currents, wherein the plurality of currents are respectively provided to a plurality of drains of a respective plurality of first transistors of the plurality of inverter stages, the reference current source including:\n a resistance having first and second terminals; \n a reference transistor having a drain configured to receive a bias current, a source coupled to the first terminal of the resistance and configured to receive the reference voltage and a gate coupled to the second terminal of the resistance, wherein the reference transistor has a second reference threshold that varies over temperature; \n a bias device configured to generate the bias current; \n a second transistor having a source coupled to the gate of the reference transistor, a gate coupled to the drain of the reference transistor and a drain configured to the second terminal of the resistance, the second transistor being configured to output the reference current and being operative to regulate a voltage of the resistance to the second threshold voltage; and \n a first current mirror coupled to the drain of the second transistor and configured to generate the plurality of currents by mirroring the reference current.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 99.0
- Lexical Diversity: 2.78947
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11093619', '12653004', '13410104', '12360416', '12385353']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7479274100741261
- 35 USC 102 Novelty (BERT): 0.5025160513800848
- Combined Prediction Score: 0.723386274204722
- Mean Citation Score: 248.773162
- Max Citation Score: 265.75366
- Similarity Product: 200.7972179877877

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test