PATENT CLAIM ANALYSIS

Application Number: 15940230
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-01
Patent Classification: ["257", "369000"]

Abstract:
A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

Claim (Index 10):
The SRAM cell of  claim 1 , further comprising a first gate electrode layer covering a channel of the read pull-down transistor, and a second gate electrode layer extending continuously to cover the channel regions of the second pull-up transistor and the second pull-down transistor, wherein:\n the first and second gate electrodes are separated from each other by a dielectric layer filling a space therebetween, and are electrically connected to each other by an interconnection layer disposed on the first gate electrode layer, the dielectric layer, and the second gate electrode layer, the second gate electrode layer includes a first section covering at least the channel region of the second pull-down transistor and a second section covering at least the channel region of the second pull-up transistor, the gate electrode of the read pull-down transistor constitutes a portion or an entity of the first gate electrode layer, and the gate electrodes of the second pull-down transistor and the second pull-up transistor constitute a portion or an entity of the second gate electrode layer, and a work function level of the first electrode layer is lower than that of the first section of the second gate electrode layer.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 3.02128
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15437915', '15158103', '15141414', '10818133', '11776118']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9232636193478264
- 35 USC 102 Novelty (BERT): 0.4961565196652379
- Combined Prediction Score: 0.8805529093795678
- Mean Citation Score: 264.715836
- Max Citation Score: 278.6089
- Similarity Product: 239.81665147333143

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test