PATENT CLAIM ANALYSIS

Application Number: 15903999
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "149000"]

Abstract:
According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.

Claim (Index 10):
The device of  claim 7 , wherein\n the third distributor comprises: a seventh operational amplifier including a first input terminal to which the fourth voltage is input; an eleventh transistor including a gate electrically coupled to an output terminal of the seventh operational amplifier, one end electrically coupled to a power supply voltage, and the other end which outputs the fifth voltage; and a ninth resistor including one end electrically coupled to the other end of the eleventh transistor, and the other end electrically coupled to a second input terminal of the seventh operational amplifier; a twelfth transistor including one end electrically coupled to the other end of the eleventh transistor, and the other end electrically coupled to the second input terminal of the seventh operational amplifier; and a tenth resistor including one end electrically coupled to the other end of the twelfth transistor and the other end of the ninth resistor, and the other end electrically coupled to a ground voltage; and a third address controller which supplies a signal in accordance with a row address to a gate of the twelfth transistor, and the fourth distributor comprises: an eighth operational amplifier including a first input terminal to which the fourth voltage is input; a thirteenth transistor including a gate electrically coupled to an output terminal of the eighth operational amplifier, one end electrically coupled to the power supply voltage, and the other end which outputs the sixth voltage; and an eleventh resistor including one end electrically coupled to the other end of the thirteenth transistor, and the other end electrically coupled to a second input terminal of the eighth operational amplifier; a fourteenth transistor including one end electrically coupled to the other end of the thirteenth transistor, and the other end electrically coupled to the second input terminal of the eighth operational amplifier; a twelfth resistor including one end electrically coupled to the other end of the fourteenth transistor and the other end of the eleventh resistor, and the other end electrically coupled to the ground voltage; and a fourth address controller which supplies a signal in accordance with a row address to a gate of the fourteenth transistor.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.85
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15065449', '15455906', '15261680', '15702298', '12409666']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7950416749689941
- 35 USC 102 Novelty (BERT): 0.4521423237658326
- Combined Prediction Score: 0.760751739848678
- Mean Citation Score: 141.43437
- Max Citation Score: 149.34566
- Similarity Product: 119.44573881728888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test