PATENT CLAIM ANALYSIS

Application Number: 16431846
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["257", "040000"]

Abstract:
An apparatus includes transistor and a set of one or more serially-connected diodes coupled to the transistor. The transistor includes a gate, and first and second terminals. A first diode in the set of serially-connected diodes has a first terminal connected to the second terminal of the transistor. At least one of the diodes includes a first layer including silicon having a first type of carrier as its majority carrier, a first terminal, and a second terminal. The first terminal includes a second layer formed on the first layer, a third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier formed on the second layer, and a conductive layer formed on the third layer. The second terminal includes a fourth layer comprising crystalline hydrogenated silicon of the first carrier type formed on the first layer, and a conductive layer formed on the fourth layer.

Claim (Index 5):
The apparatus as set forth in  claim 1 , wherein the first type of carrier is an electron and the second type of carrier is a hole.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 100.0
- Lexical Diversity: 3.30612
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16431012', '15346546', '15346462', '14226285', '13949498']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.929441164287108
- 35 USC 102 Novelty (BERT): 0.5372317403551117
- Combined Prediction Score: 0.8902202218939083
- Mean Citation Score: 247.889396
- Max Citation Score: 373.83295
- Similarity Product: 368.86237493627664

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test