PATENT CLAIM ANALYSIS

Application Number: 16226628
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "149000"]

Abstract:
A 3D semiconductor device including: a first level including a single crystal layer, a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the single crystal layer and includes interconnects between the first transistors forming control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; and polysilicon pillars, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the third transistors, where at least one of the second memory cells is at least partially atop of the control circuits.

Claim (Index 1):
A 3D semiconductor device, the device comprising:\n a first level comprising a single crystal layer, a plurality of first transistors and at least one metal layer,\n wherein said at least one metal layer overlays said single crystal layer and comprises interconnects between said first transistors forming control circuits; \n a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors; a third level overlaying said second level, said third level comprising a plurality of third transistors; and polysilicon pillars,\n wherein at least one of said second transistors comprises a first channel region and at least one of said third transistors comprises a second channel region, \n wherein a portion of at least one of said polysilicon pillars is in direct contact with said first channel region and said second channel region, \n wherein said second transistors are aligned to said first transistor with less than 150 nm alignment error, \n wherein said second level and said third level thickness is greater than 20 nm and less than 300 nm, \n wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following the same lithography step, \n wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors, \n wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors, \n wherein at least one of said second memory cells is at least partially atop of said control circuits, and \n wherein said control circuits are connected so to control at least one of said second transistors and at least one of said third transistors.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 98.0
- Lexical Diversity: 3.81395
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15727592', '15351389', '15862616', '15904377', '14506160']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7906034707660828
- 35 USC 102 Novelty (BERT): 0.5354782286463585
- Combined Prediction Score: 0.7650909465541105
- Mean Citation Score: 332.590816
- Max Citation Score: 383.1293
- Similarity Product: 358.9986991622091

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test