PATENT CLAIM ANALYSIS

Application Number: 16037617
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "043000"]

Abstract:
An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.

Claim (Index 3):
The integrated semiconductor device of  claim 1 ,\n wherein the transistor comprises any one or any combination of two or more of a Radio Frequency (RF) Complementary Metal-Oxide-Semiconductor (CMOS) transistor, a Varactor, a poly resistor and an inductor formed on a substrate.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 95.0
- Lexical Diversity: 2.02326
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15685697', '15606360', '15860026', '15588011', '14802228']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.928816079022774
- 35 USC 102 Novelty (BERT): 0.562180054462934
- Combined Prediction Score: 0.8921524765667901
- Mean Citation Score: 290.389106
- Max Citation Score: 440.55823
- Similarity Product: 377.04978346181815

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test