PATENT CLAIM ANALYSIS

Application Number: 16049624
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["719", "312000"]

Abstract:
Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

Claim (Index 11):
The user device of  claim 10 , wherein the single completion status implicitly includes at least one other payload transaction status.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 1.93902
- Patent Class: 719.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15984153', '15865638', '14879030', '15011291', '15721200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5678435231190144
- 35 USC 102 Novelty (BERT): 0.5228811842163865
- Combined Prediction Score: 0.5633472892287517
- Mean Citation Score: 260.273578
- Max Citation Score: 303.18237
- Similarity Product: 186.6863378457964

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test