PATENT CLAIM ANALYSIS

Application Number: 15939292
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["257", "774000"]

Abstract:
A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

Claim (Index 3):
The package structure of  claim 1 , wherein the insulators are located within the positioning location of the at least one semiconductor die in the stacking direction.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.77083
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15652249', '15854736', '15696192', '15794006', '15202541']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9219141094745928
- 35 USC 102 Novelty (BERT): 0.4829383409342556
- Combined Prediction Score: 0.878016532620559
- Mean Citation Score: 190.057256
- Max Citation Score: 202.1296
- Similarity Product: 152.96866848535538

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test