PATENT CLAIM ANALYSIS

Application Number: 15913297
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "316000"]

Abstract:
A semiconductor device and a fabrication method are provided. The fabrication method includes providing a gate structure on a substrate and a first protective layers on the gate structure; forming an initial sidewall spacer on a sidewall of each of the gate structure and the first protective layer; forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first and initial sidewall spacers being made of different materials; forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer; and forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material. The second sidewall spacer has a top surface higher than or level with a top surface of the gate structure.

Claim (Index 17):
The semiconductor device according to  claim 15 , wherein:\n the interlayer dielectric layer and the second sidewall spacer are made of a same material.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.85714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14970881', '14070645', '15059635', '15645013', '14968108']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9268200067574828
- 35 USC 102 Novelty (BERT): 0.5051935858705976
- Combined Prediction Score: 0.8846573646687943
- Mean Citation Score: 235.77663
- Max Citation Score: 248.71288
- Similarity Product: 166.93784354327204

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test