PATENT CLAIM ANALYSIS

Application Number: 16220268
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "737000"]

Abstract:
An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.

Claim (Index 12):
The integrated circuit package assembly of  claim 11 , wherein the outermost sidewalls of the first integrated circuit die are aligned with the outermost sidewalls of the third integrated circuit die.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 3.77143
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15716959', '14818877', '13353644', '14534838', '14199545']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926475859827802
- 35 USC 102 Novelty (BERT): 0.5092307424282975
- Combined Prediction Score: 0.8847513480878516
- Mean Citation Score: 243.193156
- Max Citation Score: 281.13962000000004
- Similarity Product: 205.0083865516997

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test