PATENT CLAIM ANALYSIS

Application Number: 16023643
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["327", "175000"]

Abstract:
A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Claim (Index 7):
A clock duty cycle correction circuit comprising:\n a charge pump comprising:\n a current source; \n a first current output terminal; \n a second current output terminal; \n a first clock input terminal; \n a second clock input terminal; and \n a first transistor coupled to the current source, the first clock input terminal, and the first current output terminal to connect the current source to the first output terminal based on assertion of a clock signal at the first clock input terminal; \n a second transistor coupled to the current source, the second clock input terminal, and the second current output terminal to connect the current source to the second output terminal based on assertion of an inverted version of the clock signal at the second clock input terminal; \n a reset terminal; and \n a reset transistor coupled to the first current output terminal, the second current output terminal, and the reset terminal to short the first current output terminal to the second current output terminal based on assertion of a reset signal at the reset terminal; and \n a controller configured to:\n compare charge accumulated from the first current output to charge accumulated from the second current output over a plurality of cycles of the clock signal to determine which of a positive portion of the clock signal and a negative portion of the clock signal is longer; and \n generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on which of the positive portion of the clock signal and the negative portion of the clock signal is longer.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 3.08
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15598339', '14927949', '10277738', '11819414', '11005821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7973414019936957
- 35 USC 102 Novelty (BERT): 0.5643318586342443
- Combined Prediction Score: 0.7740404476577506
- Mean Citation Score: 332.072184
- Max Citation Score: 445.38293
- Similarity Product: 443.6540637020248

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test