PATENT CLAIM ANALYSIS

Application Number: 16033597
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "387000"]

Abstract:
A semiconductor device includes a substrate, a gate region formed on the substrate, a self-aligned gate cut formed in the gate region, and a middle of line (MOL) area formed on the gate region, wherein the self-aligned gate cut provides critical dimensions in a range from 5 nm to 30 nm. The self-aligned gate cut reduces capacitance and power, provides flexibility in placement of the MOL area, and reduces local routing congestion.

Claim (Index 8):
The semiconductor device of  claim 3 , wherein the CMOS device further comprises a PFET fin and an NFET fin formed in the gate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 1.90698
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15177362', '16020061', '15258513', '14951726', '15067953']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9131739864632258
- 35 USC 102 Novelty (BERT): 0.4815314655127381
- Combined Prediction Score: 0.870009734368177
- Mean Citation Score: 138.13996799999998
- Max Citation Score: 140.53676000000002
- Similarity Product: 92.89347672667029

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test