PATENT CLAIM ANALYSIS

Application Number: 15884328
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["438", "127000"]

Abstract:
A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

Claim (Index 14):
A method for fabricating a chip package, comprising:\n forming an insulating encapsulation to laterally encapsulate sidewalls of at least one integrated circuit component; forming a conductive layer on the at least one integrated circuit component and the insulating encapsulation; forming a photoresist layer on the conductive layer and performing a multi-step exposure and development process to pattern the photoresist layer, wherein performing the multi-step exposure and development process to pattern the photoresist layer comprises:\n providing a first mask comprising a first alignment pattern and a first layout pattern; \n performing a first step exposure process via a first mask and a first development process to form a first alignment opening and a plurality of first wiring openings in a first portion of the photoresist layer, and the first portion of the photoresist layer being covered by the first mask; \n providing a second mask comprising a second alignment pattern and a second layout pattern; \n performing a second step exposure process via a second mask and a second development process to form a plurality of second wiring openings in a second portion of the photoresist layer, a part of the first portion and the second portion of the photoresist layer being covered by the second mask, and the second alignment pattern of the second mask being substantially aligned with the first alignment opening formed in the photoresist layer when performing the second step exposure process; \n forming an alignment mark in the first alignment opening; and forming a plurality of conductive wirings in the first wiring openings and the second wiring openings, wherein the conductive wirings are electrically connected to the at least one integrated circuit component.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 1.41379
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15257920', '15215594', '15281086', '15690196', '15619648']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8507419138073767
- 35 USC 102 Novelty (BERT): 0.4799194228385932
- Combined Prediction Score: 0.8136596647104983
- Mean Citation Score: 170.054582
- Max Citation Score: 184.33864
- Similarity Product: 133.9637146329212

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test