PATENT CLAIM ANALYSIS

Application Number: 16161084
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-06
Patent Classification: ["365", "222000"]

Abstract:
A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.

Claim (Index 6):
The dynamic random access memory as claimed in  claim 4 , wherein a first number of the memory cells are coupled between the first node and the second node of each of the bit lines, a second number of the memory cells are coupled between the third node and the fourth node of each of the bit lines, and the first number and the second number are unequal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.74419
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11779716', '10921760', '11254722', '11945282', '13317595']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7990954895500614
- 35 USC 102 Novelty (BERT): 0.4799575267795635
- Combined Prediction Score: 0.7671816932730116
- Mean Citation Score: 167.99770800000005
- Max Citation Score: 175.39719
- Similarity Product: 118.19067510515568

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test