PATENT CLAIM ANALYSIS

Application Number: 16190017
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["714", "764000"]

Abstract:
A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Claim (Index 5):
The method of  claim 2 , wherein if the damaged address location is found in the shadow group, one second repair entry in the write cache is created for any data content to be written to the damaged address location.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 2.91228
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15230414', '16190043', '14457113', '12348895', '13772400']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3840144415038803
- 35 USC 102 Novelty (BERT): 0.5648332695746668
- Combined Prediction Score: 0.402096324310959
- Mean Citation Score: 334.613976
- Max Citation Score: 538.4235
- Similarity Product: 336.2506300688982

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test