PATENT CLAIM ANALYSIS

Application Number: 15911148
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "351000"]

Abstract:
A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.

Claim (Index 6):
A static random access memory (SRAM) device, comprising:\n a latch circuit comprising a first inverter and a second inverter, the first inverter comprising a first input node, a first load transistor, a first drive transistor and a first output node, the second inverter comprising a second input node, a second load transistor, a second drive transistor and a second output node, the first output node being electrically connected to the second input node and the second output node being electrically connected to the first input node; a first transfer transistor connected to the first output node; and a second transfer transistor connected to the second output node, each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors comprising a multi-bridge channel transistor, and at least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors comprises a multi-bridge channel transistor having a number of multi-bridge channels that is different from a number of multi-bridge channels of the other transistors, wherein the number of multi-bridge channels included in each of the first and second transfer transistors is less than the number of multi-bridge channels included in each of the first and second drive transistors.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 3.375
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15246526', '12533394', '12651667', '15634227', '15654190']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9149471654087172
- 35 USC 102 Novelty (BERT): 0.5955738041684856
- Combined Prediction Score: 0.8830098292846942
- Mean Citation Score: 301.775772
- Max Citation Score: 512.0465
- Similarity Product: 464.0447958954276

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test