PATENT CLAIM ANALYSIS

Application Number: 16186248
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["712", "029000"]

Abstract:
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Claim (Index 4):
The hybrid data processing device of  claim 2 , wherein at least one processor core comprises an ARM processor core.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 98.0
- Lexical Diversity: 1.91549
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13804419', '15823353', '15288569', '13826039', '11416278']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5789554369602602
- 35 USC 102 Novelty (BERT): 0.5277521878843726
- Combined Prediction Score: 0.5738351120526715
- Mean Citation Score: 260.91516
- Max Citation Score: 317.35715
- Similarity Product: 192.97423229118

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test