PATENT CLAIM ANALYSIS

Application Number: 16092454
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["257", "703000"]

Abstract:
A semiconductor package ( 1, 1′, 1 ″), the package ( 1, 1′, 1 ″) comprising a first substrate ( 2 ) comprising at a front cavity side ( 5 ′) a plurality of cavities ( 6, 6 ′), each of the cavities ( 6, 6 ′) having a bottom wall ( 7 ) and side walls ( 8 ), and having a conductive path ( 10 ) forming an electric contact surface ( 9 ) located at the inner side of the bottom wall ( 7 ) of the cavity ( 6, 6 ′), a plurality of semiconductor elements ( 16, 7 ), each of the semiconductor elements ( 16, 17 ) comprising a first electric contact surface ( 9 ) on a first side ( 26 ) and a second electric contact surface ( 9 ) on a second side ( 28 ) opposite to the first side ( 26 ), wherein at least one of the semiconductor elements ( 16, 17 ) is placed within a corresponding cavity ( 6, 6 ′) at the front cavity side ( 5 ′) of the first substrate ( 2 ), wherein the first electric contact ( 27 ) of the semiconductor element ( 16, 17 ) and the electric contact surface ( 9 ) at the inner side of the bottom wall ( 7 ) of the corresponding cavity ( 6, 6 ′) are electrically conductive bonded in a material-locking manner, and a second substrate ( 3 ), the second substrate ( 3 ) being attached with a connection side ( 12, 13 ) to the front cavity side ( 5 ′) of the first substrate ( 2 ) thereby encapsulating the semiconductor elements ( 16, 17 ) located within the corresponding cavities ( 6, 6 ′) at the front cavity side ( 5 ′) of the first substrate ( 2 ).

Claim (Index 5):
The semiconductor package of  claim 2 ,\n wherein the second substrate further comprises, on a cavity side, a plurality of cavities, each of the cavities having a bottom wall, side walls, and a conductive path forming an electric contact surface located at the inner side of the bottom wall of the cavity, wherein at least one of the plurality of semiconductor elements is placed within a corresponding cavity at the cavity side of the second substrate, wherein the first electric contact of the semiconductor element and the electric contact surface at the inner side of the bottom wall of the corresponding cavity are electrically conductive bonded in a material-locking manner, and wherein the third substrate is attached with the connection side to the cavity side of the second substrate, thereby encapsulating the semiconductor elements located within the corresponding cavities at the cavity side of the first substrate.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 97.0
- Lexical Diversity: 4.48718
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12508609', '13306679', '16111984', '14886776', '11706223']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9205829784332512
- 35 USC 102 Novelty (BERT): 0.4580831787844996
- Combined Prediction Score: 0.8743329984683762
- Mean Citation Score: 171.48029200000005
- Max Citation Score: 173.7661
- Similarity Product: 149.8494623226583

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test