PATENT CLAIM ANALYSIS

Application Number: 16241332
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "329000"]

Abstract:
The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO 2  layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO 2  layer on the SiO 2  layer such that the SiO 2  layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO 2  layer in plan view, and a step of forming a SiO 2  layer by etching the SiO 2  layer below the SiO 2  layer and the resist layer using the SiO 2  layer and the resist layer as masks.

Claim (Index 1):
A method for producing a pillar-shaped semiconductor device, the method comprising:\n a step of providing a structure including:\n a substrate, \n a first semiconductor pillar that stands on a plane of the substrate in a vertical direction, and \n a first impurity region that is in contact with a lower portion of the first semiconductor pillar or a side surface of the lower portion and contains a donor or acceptor impurity atom; \n a step of forming a first material layer that has conductivity, extends in a horizontal direction, and is connected to, in plan view, at least one of an entire periphery of the lower portion of the first semiconductor pillar and an entire periphery of a first conductor layer surrounding a first insulating layer surrounding the first semiconductor pillar; a step of forming, on the first material layer, a second material layer that surrounds the first semiconductor pillar in plan view; a step of forming, on the first material layer, a third material layer that is partly connected to the second material layer in plan view; and a step of etching the first material layer using the second material layer and the third material layer as masks, wherein a first region of the first material layer that surrounds the first semiconductor pillar in plan view is formed below the second material layer, and a second region of the first material layer that is partly connected to the first region in plan view is formed below the third material layer.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 99.0
- Lexical Diversity: 2.77586
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15976510', '15917168', '14689640', '16203982', '14976691']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9271677838414192
- 35 USC 102 Novelty (BERT): 0.6236912029010211
- Combined Prediction Score: 0.8968201257473793
- Mean Citation Score: 455.56423800000016
- Max Citation Score: 550.8797
- Similarity Product: 544.571080760628

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test