PATENT CLAIM ANALYSIS

Application Number: 15924350
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "029000"]

Abstract:
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Claim (Index 3):
The semiconductor arrangement of  claim 1 , wherein the first nanowire channel comprises germanium.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 2.38182
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15463326', '13971239', '14929504', '15816231', '15199535']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9202086215790998
- 35 USC 102 Novelty (BERT): 0.5145953214961235
- Combined Prediction Score: 0.8796472915708022
- Mean Citation Score: 249.441672
- Max Citation Score: 301.5787
- Similarity Product: 248.59243421570665

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test