PATENT CLAIM ANALYSIS

Application Number: 15973917
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "676000"]

Abstract:
A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.

Claim (Index 7):
The method of  claim 1 , wherein the solder caps comprise a Pb-free solder composition.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 93.0
- Lexical Diversity: 2.16176
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15197861', '15064750', '14797056', '15064955', '12463184']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9213108420524264
- 35 USC 102 Novelty (BERT): 0.5031051985982643
- Combined Prediction Score: 0.8794902777070102
- Mean Citation Score: 199.712946
- Max Citation Score: 206.10768
- Similarity Product: 125.57707640519142

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test