PATENT CLAIM ANALYSIS

Application Number: 15982949
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "295000"]

Abstract:
Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.

Claim (Index 29):
A method of forming a memory array, comprising:\n forming an assembly which comprises capacitors extending within a matrix; the capacitors having first electrodes, second electrodes, and insulative capacitor material between the first and second electrodes; the capacitors being arranged in array, the array comprising edges and the capacitors along the edges being edge capacitors; the capacitors that are not along the edges being internal capacitors of the array; the edge capacitors having inner edges facing toward the internal capacitors, and having outer edges in opposing relation to the inner edges; the matrix including an insulative beam over a sacrificial material; the insulative beam extending laterally between the capacitors and being along the upper regions of the capacitors; the insulative beam having peripheral extensions that extend laterally beyond the edge capacitors; removing the sacrificial material to form first void regions under the insulative beam, along the lower regions of the internal capacitors, and along the inner edges of the edge capacitors, and to form second void regions along the outer edges of the edge capacitors; forming at least one conductive plate over the insulative beam and electrically coupled with the second electrodes; and forming an insulative structure over the at least one conductive plate; the insulative structure including substantially vertical regions along the outer edges of the edge capacitors and spaced from the outer edges of the edge capacitors by the second void regions.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.60317
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15400886', '15340838', '15402679', '15340842', '15677151']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9166299805101622
- 35 USC 102 Novelty (BERT): 0.528218138124036
- Combined Prediction Score: 0.8777887962715496
- Mean Citation Score: 250.27305
- Max Citation Score: 360.1607
- Similarity Product: 339.0358949957848

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test