PATENT CLAIM ANALYSIS

Application Number: 15871074
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["438", "257000"]

Abstract:
A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

Claim (Index 1):
A method for manufacturing a semiconductor memory device, comprising:\n providing a substrate, wherein the substrate has a first region, a second region and a third region; forming a first stack structure on the first region, wherein the first stack structure sequentially comprises a first gate dielectric layer, a first floating gate, a first inter-gate dielectric layer and a first control gate; forming a second stack structure on the second region, wherein the second stack structure sequentially comprises a second gate dielectric layer, a second floating gate, a second inter-gate dielectric layer and a second control gate; forming a third stack structure on the third region, wherein the third stack structure sequentially comprises a third gate dielectric layer, a third floating gate, a third inter-gate dielectric layer and a third control gate; forming a first mask layer on the substrate to cover the third stack structure; performing a first ion implantation process, so that conductive types of the second floating gate and the second control gate are changed to a first conductive type; removing the first mask layer, and forming a second mask layer on the substrate to cover the first stack structure and the second stack structure; and performing a second ion implantation process, so that conductive types of the third floating gate and the third control gate are changed to a second conductive type.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 3.44681
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12012593', '13230228', '14072250', '15640090', '14808463']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8603673152120277
- 35 USC 102 Novelty (BERT): 0.4815738308079233
- Combined Prediction Score: 0.8224879667716173
- Mean Citation Score: 217.603496
- Max Citation Score: 229.37608
- Similarity Product: 189.4684645188332

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test