PATENT CLAIM ANALYSIS

Application Number: 15985563
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["375", "376000"]

Abstract:
Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M−x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.

Claim (Index 1):
A method comprising:\n generating, by a clock module, a reference clock signal; adjusting, by a first digital-to-time converter, the reference clock signal in accordance with a first control signal; generating, by the first digital-to-time converter, a first input signal corresponding to the adjusted reference clock signal; receiving, by a time-to-digital converter, the first input signal; generating, by the time-to-digital converter, an output signal based on the first input signal; generating an output high-frequency clock signal based on the output signal from the time-to-digital converter; generating a derived signal from the output high-frequency clock signal; adjusting, by a second digital-to-time converter, the derived signal in accordance with a second control signal, wherein the first and second control signals are centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the first and second control signals are respectively defined as (M+x) and (M\u2212x); generating, by the second digital-to-time converter, a second input signal corresponding to the adjusted derived signal; and receiving, by the time-to-digital converter, the second input signal, wherein the time-to-digital converter generates the output signal based on both the first input signal and the second input signal.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 1.88764
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12978221', '15370796', '15869854', '15625449', '15170882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4593697391202946
- 35 USC 102 Novelty (BERT): 0.5126771343274501
- Combined Prediction Score: 0.4647004786410102
- Mean Citation Score: 265.01081200000004
- Max Citation Score: 291.6605
- Similarity Product: 228.79191289007665

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test