PATENT CLAIM ANALYSIS

Application Number: 16009196
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "024000"]

Abstract:
A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.

Claim (Index 12):
The method of  claim 8 , wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use changed chemistry relative to the second etching.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.56897
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15260509', '15690601', '15465989', '15880757', '15967524']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9226010524887316
- 35 USC 102 Novelty (BERT): 0.5266942671900414
- Combined Prediction Score: 0.8830103739588624
- Mean Citation Score: 299.410214
- Max Citation Score: 307.86075
- Similarity Product: 202.1176598698497

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test