PATENT CLAIM ANALYSIS

Application Number: 15864479
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["711", "137000"]

Abstract:
A microcontroller includes multiple ways each including only one tag. When a first access and a second access are accesses performed in succession to consecutive addresses, and when the second access is the access through a first way, a cache controller performs the following operations: prefetching to the way whose tag value is smaller by 1 than the tag value corresponding to the first way when the second access is the access in the direction in which the address is incremented with respect to the first access; and prefetching to the way whose tag value is greater by 1 than the tag value corresponding to the first way when the access is in the direction in which the address is decremented.

Claim (Index 9):
The semiconductor device according to  claim 1 ,\n wherein the cache controller includes an address control unit and a data control unit, wherein the address control unit is coupled to the processor via an address bus, and, wherein the data control unit is coupled to the processor via a data bus.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 86.0
- Lexical Diversity: 2.35185
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14439355', '12952828', '11743697', '13033765', '09804677']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4953968627050641
- 35 USC 102 Novelty (BERT): 0.5613579878711057
- Combined Prediction Score: 0.5019929752216683
- Mean Citation Score: 248.164154
- Max Citation Score: 453.01434000000006
- Similarity Product: 307.00880963617806

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test