PATENT CLAIM ANALYSIS

Application Number: 16045120
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["330", "253000"]

Abstract:
An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.

Claim (Index 36):
The method of  claim 32 , further comprising:\n implanting impurity ions into a region where some of the plurality of transistors are formed in the semiconductor substrate to form a buried channel layer, wherein in the act of implanting impurity ions into the region where some of the plurality of transistors is formed in the semiconductor substrate to form the buried channel layer, the buried channel layer is formed by implanting impurity ions into a region where transistors constituting the current source of the constant current circuit are formed.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 95.0
- Lexical Diversity: 1.82759
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13331574', '10108538', '10377717', '13659386', '10738590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7493219880103825
- 35 USC 102 Novelty (BERT): 0.4931650151262583
- Combined Prediction Score: 0.7237062907219701
- Mean Citation Score: 215.354636
- Max Citation Score: 223.60107
- Similarity Product: 175.7235221274519

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test