PATENT CLAIM ANALYSIS

Application Number: 15921056
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "392000"]

Abstract:
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.

Claim (Index 11):
A semiconductor device, comprising:\n an element separation layer formed on a semiconductor substrate to separate the semiconductor substrate into a digital circuit forming area and an analog circuit forming area; a first well layer of a first conductivity type formed in the digital circuit forming area; a second well layer of the first conductivity type formed in the analog circuit forming area; a first gate insulating film formed on a surface of the first well layer; a second gate insulating film formed on a surface of the second well layer; a first gate electrode formed on a surface of the first gate insulating film; a second gate electrode formed on a surface of the second gate insulating film; sidewalls formed of insulating films on side surfaces of respective ones of the first gate electrode and the second gate electrode; a first source region and a first drain region of a second conductivity type formed in the first well layer with the first gate electrode interposed therebetween; a second source region and a second drain region of the second conductivity type formed in the second well layer with the second gate electrode interposed therebetween and have a shallower depth from a surface of the semiconductor substrate than the first source region and the first drain region; and silicide films formed on surfaces of the first source region, the first drain region, and the first gate electrode and the second source region, the second drain region, and the second gate electrode.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.45902
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12219019', '13075625', '10403122', '11882355', '12963270']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9307813175158728
- 35 USC 102 Novelty (BERT): 0.5142639529962789
- Combined Prediction Score: 0.8891295810639134
- Mean Citation Score: 321.176508
- Max Citation Score: 328.9029
- Similarity Product: 291.3036287929952

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test