PATENT CLAIM ANALYSIS

Application Number: 15910929
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Claim (Index 4):
The semiconductor device of  claim 2 ,\n wherein the ILD layer comprises SiO 2 , and wherein the filling comprises SiN and/or SiO.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 1.36364
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15271867', '15841942', '14639159', '15859775', '13041134']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.923790799771908
- 35 USC 102 Novelty (BERT): 0.52514637028794
- Combined Prediction Score: 0.8839263568235112
- Mean Citation Score: 203.485026
- Max Citation Score: 326.3773
- Similarity Product: 235.5198306599736

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test