PATENT CLAIM ANALYSIS

Application Number: 16283391
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["365", "063000"]

Abstract:
A resistive memory apparatus includes a memory cell array, a local switch, and a global switch. The memory cell array may include a plurality of resistive memory cells coupled to a plurality of connection lines. The local switch may select a target connection line coupled to a target memory cell and a preset number of connection lines adjacent to the target connection line according to a signal obtained by decoding an address. The global switch may apply a preset level of voltage to the selected adjacent connection lines according to the signal obtained by decoding the address.

Claim (Index 3):
The resistive memory apparatus of  claim 1 , wherein the plurality of connection lines includes a bit line, and the address includes a column address.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 99.0
- Lexical Diversity: 2.45238
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15818425', '12973000', '13453152', '14783248', '13753648']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8192266371311591
- 35 USC 102 Novelty (BERT): 0.472953136913625
- Combined Prediction Score: 0.7845992871094057
- Mean Citation Score: 195.490528
- Max Citation Score: 204.15483
- Similarity Product: 162.44686498407484

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test