PATENT CLAIM ANALYSIS

Application Number: 16208335
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["438", "400000"]

Abstract:
A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.

Claim (Index 8):
The method of  claim 7 , wherein forming the first circuit comprises forming a plurality of first devices that were formed during a front end of line (FEOL) portion of a process for manufacturing the semiconductor die, and;\n wherein forming the second circuit comprises forming a plurality of second devices that were formed during a back end of line (BEOL) portion of the process of manufacturing the semiconductor die.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 2.27273
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15235878', '13665603', '11874182', '12146546', '14872910']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8399236342232101
- 35 USC 102 Novelty (BERT): 0.5075202221071751
- Combined Prediction Score: 0.8066832930116067
- Mean Citation Score: 160.09399399999995
- Max Citation Score: 281.97433
- Similarity Product: 221.8922176824242

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test