PATENT CLAIM ANALYSIS

Application Number: 15934094
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "657000"]

Abstract:
A stacked III-V semiconductor diode having an n + -layer with a dopant concentration of at least 10 19  N/cm 3 , an n − -layer with a dopant concentration of 10 12 -10 16  N/cm 3 , a layer thickness of 10-300 microns, a p + -layer with a dopant concentration of 5×10 18 -5×10 20  cm 3 , with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n + -layer or the p + -layer is formed as the substrate and a lower side of the n − -layer is materially bonded with an upper side of the n + -layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.

Claim (Index 1):
A stacked III-V semiconductor diode comprising:\n an n + -layer with an upper side, a lower side, a dopant concentration of at least 10 19  N/cm 3  and a layer thickness of about 675 microns or less, wherein said n + -layer comprises a GaAs compound; an n \u2212 -layer with an upper side and a lower side, a dopant concentration of 10 12 -10 16  N/cm 3 , a layer thickness of 10-300 microns, and comprising a GaAs compound; a p + -layer with an upper side, a lower side, a dopant concentration of 5\u00d710 18 -5\u00d710 20  N/cm 3 , with a layer thickness greater than 2 microns and comprising a GaAs compound; and a doped intermediate layer with a layer thickness of 1-50 \u03bcm and a dopant concentration of 10 12 -10 17  N/cm 3  is disposed between the n \u2212 -layer and the p + -layer, and is materially bonded with an upper side and a lower side, and the lower side of the intermediate layer is materially bonded with the upper side of the n \u2212 -layer, and the upper side of the intermediate layer is materially bonded with the lower side of the p + -layer, wherein the n + -layer, the n \u2212 -layer, and the p + -layer are monolithically formed, wherein the n + -layer or the p + -layer is formed as a substrate and the lower side of the n \u2212 -layer is materially connected to the upper side of the n + -layer, wherein the intermediate layer is materially bonded with the n \u2212 -layer and with the p + -layer and is p-doped, wherein the stacked III-V semiconductor diode has a first defect layer with a layer thickness between 0.5 microns and 40 microns, wherein the defect layer is arranged within the p-type layer, and wherein the defect layer has a defect concentration ranging between 1\u00d710 13  N/cm 3  and 5\u00d710 16  N/cm 3 .

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 2.05556
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15812416', '15812432', '15812446', '13571535', '14887582']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9215831135769992
- 35 USC 102 Novelty (BERT): 0.5081749637468772
- Combined Prediction Score: 0.880242298593987
- Mean Citation Score: 247.846366
- Max Citation Score: 301.7398
- Similarity Product: 244.11595579817296

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test