PATENT CLAIM ANALYSIS

Application Number: 16031407
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "499000"]

Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Claim (Index 9):
The structure of  claim 7 , further comprising a gate structure formed directly on the shallow trench isolation region.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 1.6129
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13116396', '12369249', '12342527', '12342488', '12411494']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91475380437627
- 35 USC 102 Novelty (BERT): 0.5089573700021311
- Combined Prediction Score: 0.8741741609388561
- Mean Citation Score: 212.886
- Max Citation Score: 216.76637
- Similarity Product: 120.7210986704576

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test