PATENT CLAIM ANALYSIS

Application Number: 16025465
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-10
Patent Classification: ["257", "738000"]

Abstract:
In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.

Claim (Index 1):
A method of forming a semiconductor device, comprising:\n providing a substrate having an electrically conductive pattern disposed adjacent to a top major surface and conductive lands disposed adjacent to an opposing bottom major surface, wherein the electrically conductive pattern and the conductive lands are electrically connected to each other and separated by an insulating layer; electrically connecting a first semiconductor die to the conductive lands of the substrate and proximate to the bottom major surface of the substrate; providing a first package body that encapsulates the first semiconductor die and encapsulates at least portions of the substrate; and providing a first conductive via structure comprising a first conductive via portion disposed on one side of the first semiconductor die and a second conductive via portion disposed on a second side of the first semiconductor die; wherein:\n the first conductive via portion extends from at least a first conductive land towards a bottom exterior surface of the first package body; \n the second conductive via portion extends from at least a second conductive land towards the bottom exterior surface of the first package body; \n the first conductive via portion comprises a first outer surface exposed by the bottom exterior surface of the first package body and configured as a first external electrical interconnect structure; and \n the second conductive via portion comprises a second outer surface exposed by the bottom exterior surface of the first package body and configured as a second external electrical interconnect structure.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.68293
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12330424', '13246564', '12390999', '12351690', '12017266']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9393382446364535
- 35 USC 102 Novelty (BERT): 0.4909890496105062
- Combined Prediction Score: 0.8945033251338589
- Mean Citation Score: 250.464536
- Max Citation Score: 270.23312000000004
- Similarity Product: 229.3279517273903

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test