PATENT CLAIM ANALYSIS

Application Number: 15932293
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["341", "143000"]

Abstract:
A configurable analog to digital converter (ADC) is provided. The configurable ADC includes a comparator receiving and comparing a first analog voltage signal to a second analog voltage signal V-DAC and outputting a signal C-OUT that is responsive to a result of the comparison, an integrator operating on C-OUT and outputting an N-bit value, a digital-to analog converter (DAC) converting the N-bit value to the second analog voltage signal V-DAC, and an integrator, the integrator including the N-bit memory, which is coupled to an arithmetic logic unit (ALU), the N-bit memory and ALU cooperating to perform operations using both the N-bit value and C-OUT. The configurable ADC is configured to operate in more than one mode selected from a plurality of selectable ADC modes.

Claim (Index 21):
The readout circuit of  claim 20 , wherein respective selection of the first and second ADC modes is based upon a first sensed condition associated with the first set of one or more pixels and a second sensed condition that is different than the first sensed condition and is associated with the second set of one or more pixels.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 88.0
- Lexical Diversity: 2.07463
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15667445', '12345844', '12753681', '15052452', '15049933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.626291191642557
- 35 USC 102 Novelty (BERT): 0.5108435528140469
- Combined Prediction Score: 0.6147464277597059
- Mean Citation Score: 242.531284
- Max Citation Score: 253.11365
- Similarity Product: 172.37430166971387

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test