PATENT CLAIM ANALYSIS

Application Number: 16028845
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["327", "156000"]

Abstract:
A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.

Claim (Index 16):
The circuitry of  claim 14 , wherein when the clock generation circuit operates in a second configuration, the 2-to-1 multiplexer switches the second reference clock to the output of the 2-to-1 multiplexer, and the dual-mode PLL operates in the integer-N mode.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 95.0
- Lexical Diversity: 2.525
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12900424', '13569643', '12229813', '15138749', '15414518']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7817024789766881
- 35 USC 102 Novelty (BERT): 0.4656437138505506
- Combined Prediction Score: 0.7500966024640744
- Mean Citation Score: 173.77095400000005
- Max Citation Score: 178.64233000000004
- Similarity Product: 143.56907478483382

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test