PATENT CLAIM ANALYSIS

Application Number: 15869825
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "072000"]

Abstract:
The present application discloses an array substrate and a display panel, the display panel including: a substrate, a gate electrode, a gate insulating layer, a semiconductor layer, a source and a drain electrode, the gate electrode formed on an upper surface of the substrate; the gate insulating layer formed on upper surfaces of the gate electrode and the substrate to cover the gate electrode; the semiconductor layer formed on an upper surface of the gate insulating layer, and disposed above the gate electrode, the semiconductor layer including silicon germanium oxide, and the semiconductor layer including a channel portion; the source electrode formed on surfaces of the gate insulating layer and the semiconductor layer, and disposed on a side of the channel portion; and the drain electrode formed on the surfaces of the gate insulating layer and the semiconductor layer, and disposed on the other side of the channel portion.

Claim (Index 12):
The array substrate according to  claim 2 , wherein the semiconductor layer comprises a doped layer and an active layer;\n the doped layer is disposed at a top of the semiconductor layer and is divided into two portions by the channel portion, one of the portion is adjacent to the drain electrode and the other portion is adjacent to the source electrode; the active layer is disposed at a bottom of the semiconductor layer, the doped layer is disposed on an upper surface of the active layer; the doped layer comprises a first doped layer and a second doped layer; the second doped layer is disposed at the top of the semiconductor layer, the first doped layer is disposed at the bottom of the semiconductor layer, and is between the second doped layer and the active layer; a doping concentration of the second doped layer is greater than a doping concentration of the first doped layer; and wherein the array substrate further comprises: a protective layer is formed on upper surfaces of the source electrode and the drain electrode to cover the source electrode and the drain electrode, and the protective layer is disposed above the channel portion; a conductive layer is formed on an upper surface of the protective layer, and is divided by the channel portion; the conductive layer is a metal layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 4.04878
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11453320', '14276903', '15180970', '14819611', '11453910']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9188747636566392
- 35 USC 102 Novelty (BERT): 0.5154345543147129
- Combined Prediction Score: 0.8785307427224466
- Mean Citation Score: 270.74729799999994
- Max Citation Score: 279.30942000000005
- Similarity Product: 202.47845939324856

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test