PATENT CLAIM ANALYSIS

Application Number: 16022704
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Claim (Index 15):
A method of forming a semiconductor package, comprising:\n providing a substrate; and forming a first dielectric layer having first via openings over the substrate; forming a second dielectric layer having first trench openings on the first dielectric layer, wherein at least one first trench opening is joined with the via opening to form a first dual damascene opening in the first and second dielectric layers; forming a first seed metallic layer over the second dielectric layer and covering the first dual damascene opening; forming a first metal layer on the first seed metallic layer filling up the first dual damascene opening; forming a first redistribution layer having a first dual damascene redistribution pattern in the first dual damascene opening; forming a third dielectric layer having second via openings on the second dielectric layer, wherein locations of the second via openings are correspondingly aligned with locations of the first via openings; forming a fourth dielectric layer having second trench openings on the third dielectric layer, wherein at least one second trench opening is joined with the second via opening to form a second dual damascene opening in the third and fourth dielectric layers; forming a second seed metallic layer over the fourth dielectric layer and covering the second dual damascene opening; forming a second metal layer on the second seed metallic layer filling up the second dual damascene opening; and forming a second redistribution layer having a second dual damascene redistribution pattern in the second dual damascene opening.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 3.02778
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15688817', '15693950', '15157220', '14447426', '15859123']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9134323177667903
- 35 USC 102 Novelty (BERT): 0.4994848334609795
- Combined Prediction Score: 0.8720375693362094
- Mean Citation Score: 217.664304
- Max Citation Score: 267.35162
- Similarity Product: 213.0664585283506

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test