PATENT CLAIM ANALYSIS

Application Number: 15958122
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["711", "163000"]

Abstract:
A processor may be coupled to a flash memory by way of an interface. The processor may be caused to read and/or write data, such as computer executable instructions, from/to the flash memory via the interface. An interface filter may be interposed between the processor and the flash memory to enhance the security and validity of data transactions associated with the processor and the flash memory.

Claim (Index 9):
An apparatus, comprising:\n a master component; a slave component coupled to the master component; an interface coupling the master component and the slave component, the interface providing at least a slave select (SS) line and at least one data line, the SS line including a signal generated by the master component to select the slave component, and the at least one data line including an instruction for communication to the slave component; and a processor device coupled to the SS line and the at least one data line, the processor device to:\n analyze the instruction, and \n interrupt the signal on the SS line in response to the analysis of the instruction.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 1.73171
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11945316', '11945292', '15468781', '13453169', '15247632']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4811643409867498
- 35 USC 102 Novelty (BERT): 0.4937775445282129
- Combined Prediction Score: 0.4824256613408961
- Mean Citation Score: 141.05449600000003
- Max Citation Score: 148.87492
- Similarity Product: 85.61678699400902

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test