PATENT CLAIM ANALYSIS

Application Number: 15898420
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["257", "369000"]

Abstract:
A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Claim (Index 7):
The method of  claim 2  further comprising:\n providing a reactive metal layer on the work function layer before the step of providing the contact metal layer and before the step of performing the low temperature anneal, the step of performing the low temperature anneal being performed before the step of providing the contact metal layer; and \n removing the reactive metal layer after the step of performing the low temperature anneal and before the step of providing the contact metal layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.34146
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11955491', '15455203', '14198976', '14047849', '15284567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907246108191207
- 35 USC 102 Novelty (BERT): 0.4784505553981439
- Combined Prediction Score: 0.8643665529119008
- Mean Citation Score: 161.625392
- Max Citation Score: 192.00551
- Similarity Product: 144.6919421551299

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test