PATENT CLAIM ANALYSIS

Application Number: 15950907
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "347000"]

Abstract:
A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.

Claim (Index 13):
The device according to  claim 10 , wherein the gate electrode layer comprises titanium nitride (TiN), aluminium (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), rhenium (Re) or ruthenium (Ru).

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 2.20339
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13964405', '13556406', '15787257', '10605726', '15410848']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9325411814438886
- 35 USC 102 Novelty (BERT): 0.5092431264060225
- Combined Prediction Score: 0.890211375940102
- Mean Citation Score: 280.64702
- Max Citation Score: 291.48004
- Similarity Product: 223.3167022891569

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test