PATENT CLAIM ANALYSIS

Application Number: 15918199
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

Claim (Index 16):
A vertical fin field effect transistor device, comprising:\n one or more vertical fin(s) on a substrate; a bottom source/drain at the surface of the substrate, where at least a portion of the bottom source/drain is below at least one of the one or more vertical fin(s); a fin liner on at least a portion of the bottom source/drain and at least a portion of the one or more vertical fin(s), wherein the fin liner is made of a material selected from the group consisting of silicon oxide (SiO), silicon carbide (SiC), silicon borocarbide (SiBC), boron carbide (BC), and combinations thereof; a germanium oxynitride sacrificial layer on the fin liner; and a bottom spacer on the germanium oxynitride sacrificial layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.09375
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15416281', '15498112', '15793470', '15177358', '15492745']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9344628976977092
- 35 USC 102 Novelty (BERT): 0.5616522747484153
- Combined Prediction Score: 0.8971818354027797
- Mean Citation Score: 385.510606
- Max Citation Score: 469.3481
- Similarity Product: 352.70189771941904

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test