PATENT CLAIM ANALYSIS

Application Number: 15956306
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "330000"]

Abstract:
Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.

Claim (Index 14):
The structure of  claim 13  wherein the first liner is comprised of carbon-incorporated silicon oxide, titanium oxide, hafnium oxide, or aluminum oxide, and the dielectric cap is comprised of silicon nitride.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 2.76923
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15791658', '15841887', '15175540', '15626732', '14096563']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9137213497251304
- 35 USC 102 Novelty (BERT): 0.4870456487700764
- Combined Prediction Score: 0.8710537796296249
- Mean Citation Score: 202.459218
- Max Citation Score: 215.75308
- Similarity Product: 159.36885974126815

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test