PATENT CLAIM ANALYSIS

Application Number: 16121427
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

Claim (Index 16):
The integrated circuit of  claim 7 , further comprising:\n at least one power rail at a boundary of the integrated circuit; and a via connecting the source contact of one of the plurality of field effect transistors to the at least one power rail.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 2.68421
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15977949', '11566287', '13747972', '10721437', '15454099']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914426040112602
- 35 USC 102 Novelty (BERT): 0.4927253455654872
- Combined Prediction Score: 0.8722559706578904
- Mean Citation Score: 204.101616
- Max Citation Score: 210.0875
- Similarity Product: 142.56231234818696

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test