PATENT CLAIM ANALYSIS

Application Number: 15862041
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["714", "719000"]

Abstract:
An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Claim (Index 11):
A semiconductor device comprising:\n a first memory which holds a part of bits of logical data for a logical address; a second memory which holds other part of bits of the logical data for the logical address; a first BIST (Built In Self Test) circuit which diagnoses the first memory; a second BIST circuit which diagnoses the second memory; and a total judgment circuit, wherein each of the first BIST circuit and the second BIST circuit has\n an address generation circuit which generates a target address to be tested in a corresponding memory, \n a test data generation circuit which generates write data for the address and expected value data for read data from the address, and \n a judgment circuit which compares matching/non-matching of the read data and the expected value data corresponding to each bit, for each address, judges that error correction is possible when a number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC (Error Correcting Code) circuit, and judges that error correction is not possible when the number is not within the range, \n wherein the total judgment circuit judges that error correction is not possible as a final test result, when the judgment circuit in the first BIST circuit and the judgment circuit in the second BIST circuit both judge that the error correction is possible at a same logical address.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.10417
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15658734', '10699223', '10805227', '10739123', '10271533']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.303688313690701
- 35 USC 102 Novelty (BERT): 0.4894918452756336
- Combined Prediction Score: 0.3222686668491942
- Mean Citation Score: 223.031606
- Max Citation Score: 266.2719
- Similarity Product: 220.34816702758675

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test