PATENT CLAIM ANALYSIS

Application Number: 15978497
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "782000"]

Abstract:
A semiconductor device ( 100 ) comprising a leadframe ( 120 ) having an assembly pad ( 121 ) in a first horizontal plane ( 180 ), the pad's first surface ( 121 a ) with a semiconductor chip ( 110 ) attached; further a plurality of leads ( 122 ) in a parallel second horizontal plane ( 190 ) offset from the first plane in the direction of the attached chip, the leads having a third surface ( 122 a ) with bonding wires, and an opposite fourth surface ( 122 b ); a package ( 140 ) encapsulating leadframe, chip, and wires, the package having a fifth surface ( 140 a ) parallel to the first and second planes; a plurality of recess holes ( 150 ) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder ( 160 ) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Claim (Index 1):
A semiconductor device comprising:\n a die attach pad including a first surface and an opposite second surface; a semiconductor chip attached to the die attach pad, the semiconductor chip electrically connected to a plurality of leads, each of the plurality of leads including a first lead surface, a second lead surface opposite to the first lead surface, a third lead surface including a plane parallel to and offset from a plane along the first lead surface, and a fourth lead surface including a plane parallel to and offset from a plane along the second lead surface, the semiconductor chip electrically connected to the first lead surface of each of the plurality of leads; and a packaging compound covering portions of the semiconductor chip, the die attach pad and the plurality of leads forming a package, the opposite second surface of the die attach pad exposed from the package on a package surface, the opposite second surface being coplanar with the package surface;\n wherein the packaging compound includes a plurality of recess holes having solder, each of the plurality of recess holes extending from the second lead surface to the package surface, each of the plurality of recess holes including a depth larger than a diameter; and \n wherein a first distance between a plane along the first surface and a plane along the opposite second surface is less than a second distance between a plane along the package surface and the plane along the second lead surface; and wherein the plane along the opposite lead surface and the plane along the fourth lead surface are within planes between two opposite surfaces of the semiconductor chip.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.78788
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14453650', '14215896', '14683277', '13542827', '11051061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9015645230872268
- 35 USC 102 Novelty (BERT): 0.5419894008243397
- Combined Prediction Score: 0.865607010860938
- Mean Citation Score: 250.4113
- Max Citation Score: 375.82388
- Similarity Product: 311.23080828781605

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test