PATENT CLAIM ANALYSIS

Application Number: 15986203
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "302000"]

Abstract:
Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing an SOI substrate with a buried insulator layer therein, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a doped layer over the SOI substrate, wherein the grown second polysilicon material and epitaxially grown doped layer form a basis for a strap merging the doped layer and the second polysilicon material.

Claim (Index 20):
A structure comprising:\n at least two Embedded Dynamic Random Access Memory (eDRAM) structures each including: an SOI substrate with a buried insulator therein; a doped layer disposed over the SOI substrate; a trench formed through the SOI substrate, with a dielectric liner deposited along an exposed perimeter therein; a first polysilicon material filling the trench in the substrate; a second polysilicon material in contact with the first polysilicon material, wherein the second polysilicon material and the doped layer form a connection over the SOI substrate, wherein the second polysilicon material and the doped layer are coplanar as a result of performing a planarization process on an excess portion of the second polysilicon material grown over the doped layer; a transistor spacer layer over i) the doped layer, ii) the second polysilicon material, and iii) the shallow-trench isolation layer; a shallow-trench isolation (STI) region in contact with the connection, forming a strap in the structure and separating it from at least one neighboring device and a vertical transistor structure over the transistor spacer layer, wherein the shallow-trench isolation region of one of the at least two eDRAM structures electrically isolates the vertical transistor structure of one of the at least two eDRAM structures from another vertical transistor structure of another one of the least two eDRAM structures.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 93.0
- Lexical Diversity: 2.01754
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12651608', '12776829', '13845506', '12048263', '13865306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.924344251354376
- 35 USC 102 Novelty (BERT): 0.5082151293280653
- Combined Prediction Score: 0.8827313391517451
- Mean Citation Score: 274.42786200000006
- Max Citation Score: 284.2069
- Similarity Product: 202.7369926197589

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test