PATENT CLAIM ANALYSIS

Application Number: 16289075
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["712", "009000"]

Abstract:
An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

Claim (Index 13):
The method as in  claim 9 , wherein one or more processing elements in the set of throughput clusters are capable of simultaneously multithreading by simultaneously executing multiple micro-threads.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 99.0
- Lexical Diversity: 2.74468
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15226875', '13730055', '13729915', '13729931', '15145748']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5676119952377222
- 35 USC 102 Novelty (BERT): 0.5229052450356321
- Combined Prediction Score: 0.5631413202175132
- Mean Citation Score: 261.692968
- Max Citation Score: 304.17712
- Similarity Product: 197.5020526491737

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test