PATENT CLAIM ANALYSIS

Application Number: 16116893
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "185180"]

Abstract:
A semiconductor device includes a plurality of nonvolatile memory cells ( 1 ). Each of the nonvolatile memory cells comprises a MOS type first transistor section ( 3 ) used for information storage, and a MOS type second transistor section ( 4 ) which selects the first transistor section. The second transistor section has a bit line electrode ( 16 ) connected to a bit line, and a control gate electrode ( 18 ) connected to a control gate control line. The first transistor section has a source line electrode ( 10 ) connected to a source line, a memory gate electrode ( 14 ) connected to a memory gate control line, and a charge storage region ( 11 ) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

Claim (Index 92):
A semiconductor device comprising:\n a semiconductor substrate; a nonvolatile memory cell; a switch MOS transistor; and a bit line coupled the nonvolatile memory cell and the switch MOS transistor, where the nonvolatile memory cell includes:\n a gate structure disposed over a main surface of the semiconductor substrate, \n a first semiconductor region formed in the main surface of the semiconductor substrate, and \n a second semiconductor region formed in the main surface of the semiconductor substrate, \n wherein the gate structure has a control gate electrode, and a memory gate electrode disposed next to the control gate electrode, wherein the first semiconductor region is positioned adjacent to the control gate electrode of the gate structure, wherein the second semiconductor region is positioned adjacent to the memory gate electrode of the gate structure, wherein the switch MOS transistor is electrically connected to the first semiconductor region through the bit line, wherein the memory gate electrode is disposed over the main surface of the semiconductor substrate via a first insulating film, wherein the switch MOS transistor has a first gate electrode disposed over the main surface of the semiconductor substrate via a second insulating film, and wherein the second insulating film has a thickness less than a thickness of the first insulating film.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 96.0
- Lexical Diversity: 2.80282
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12718111', '13867055', '10484578', '15796193', '13223380']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8236145385658598
- 35 USC 102 Novelty (BERT): 0.5479035453354582
- Combined Prediction Score: 0.7960434392428196
- Mean Citation Score: 408.327878
- Max Citation Score: 413.91068
- Similarity Product: 371.79639646544456

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test