PATENT CLAIM ANALYSIS

Application Number: 16017652
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "724000"]

Abstract:
A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

Claim (Index 12):
The semiconductive apparatus of  claim 11 , further including a tertiary-level capacitor that is seated on the secondary die, wherein the tertiary-level capacitor is electrically coupled to the secondary die by a through-silicon via.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 94.0
- Lexical Diversity: 1.10345
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15853330', '15937411', '15845382', '16015739', '15637935']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9113801380370478
- 35 USC 102 Novelty (BERT): 0.4725991722868042
- Combined Prediction Score: 0.8675020414620234
- Mean Citation Score: 125.0413452
- Max Citation Score: 134.07442
- Similarity Product: 94.16305602231384

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test