PATENT CLAIM ANALYSIS

Application Number: 15869542
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["716", "113000"]

Abstract:
Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.

Claim (Index 1):
A method comprising:\n generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 1.76923
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15869484', '13032059', '13967329', '15691472', '14174375']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3067655145729158
- 35 USC 102 Novelty (BERT): 0.4791814844572319
- Combined Prediction Score: 0.3240071115613474
- Mean Citation Score: 144.803382
- Max Citation Score: 207.36023
- Similarity Product: 133.9933258078921

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test