PATENT CLAIM ANALYSIS

Application Number: 15990370
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "213000"]

Abstract:
Apparatuses and methods for including bond pads and circuits in a semiconductor device are disclosed. An example apparatus includes a bond pad including one or more metal layers and one or more circuits. The circuits include one or more layers overlapped with the bond pad and coupled to metal layers of the bond pad. The pin capacitance can be reduced by overlapping of related layers and minimizing the areas of the unrelated layers.

Claim (Index 11):
The apparatus of  claim 10 , wherein each of the first portion of the first layer or the first portion of the transistor layer is positioned at an edge of the bond pad.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 93.0
- Lexical Diversity: 1.75
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11458501', '10694675', '11684674', '10304416', '13222130']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9085171773276532
- 35 USC 102 Novelty (BERT): 0.4692697613572479
- Combined Prediction Score: 0.8645924357306126
- Mean Citation Score: 108.253677
- Max Citation Score: 114.5993
- Similarity Product: 79.48388172094822

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test