PATENT CLAIM ANALYSIS

Application Number: 16137227
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["326", "119000"]

Abstract:
A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

Claim (Index 15):
A method for performing a digital XNOR operation comprising:\n providing an input signal and the input signal complement to an XNOR cell for performing a digital XNOR operation of the input signal with a weight, the XNOR cell including at least one pair of FE-FETs and a plurality of selection transistors coupled with the at least one pair of FE-FETs, the at least one pair of FE-FETs coupled with a plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, wherein the plurality of selection transistors includes a first selection transistor and a second selection transistor, the plurality of FE-FETS consists of the first FE-FET and the second FE-FET, each of the selection transistors including a gate, a source and a drain, the source of the first selection transistor being connected a first gate of the first FE-FET, the source of the second selection transistor being connected to a second gate of the second FE-FET, the drain of the first selection transistor being coupled with a program line, the drain of the second selection transistor being coupled with a program complement line, the gate of the first selection transistor and the gate of the second selection transistor being coupled to a select line; and programming the first weight and the second weight into the first FE-FET and the second FE-FET, the step of programming the first weight and the second weight further including\n erasing the first FE-FET and the second FE-FET by setting the program line to a ground, setting the program complement line to the ground, setting the select line to a high state, setting an input line and an input complement line of the plurality of input lines to the high state; and \n writing to the first FE-FET and the second FE-FET after the erasing step by setting the input signal line to the ground, setting the input signal complement line to the ground, setting the select line to the high state, and one of pulsing the programing line, pulsing the program complement line and pulsing neither of the program line and the program complement line.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 97.0
- Lexical Diversity: 2.24444
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15961220', '15717023', '12272184', '15640127', '15859583']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6514494609573297
- 35 USC 102 Novelty (BERT): 0.4765662213503825
- Combined Prediction Score: 0.633961136996635
- Mean Citation Score: 137.655408
- Max Citation Score: 161.6707
- Similarity Product: 108.7764611213386

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test