PATENT CLAIM ANALYSIS

Application Number: 16042000
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-11
Patent Classification: ["365", "185330"]

Abstract:
A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Claim (Index 1):
A memory device, comprising:\n a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes:\n source and drain regions formed in the substrate and defining a channel region of the substrate extending there between, \n a floating gate disposed over and insulated from a first portion of the channel region, \n a control gate disposed over and insulated from a second portion of the channel region; \n a plurality of word lines each electrically connecting together all of the control gates for one of the rows of the memory cells; a plurality of bit lines each electrically connecting together the drain regions for one of the columns of the memory cells; a plurality of first sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns of the memory cells; a plurality of second sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns of the memory cells, wherein the first plurality of the columns is different from the second plurality of the columns; a first source line and a second source line; a plurality of first select transistors each connected between one of the first sub source lines and the first source line; a plurality of second select transistors each connected between one of the second sub source lines and the second source line; a plurality of select transistor lines each connected to a gate of one of the first select transistors and a gate of one of the second select transistors.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 3.975
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15593231', '13284795', '10896152', '14190010', '15987735']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8164988487929353
- 35 USC 102 Novelty (BERT): 0.4922537042281067
- Combined Prediction Score: 0.7840743343364526
- Mean Citation Score: 281.5021020000001
- Max Citation Score: 295.2722
- Similarity Product: 267.1246403795004

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test