PATENT CLAIM ANALYSIS

Application Number: 15864090
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["341", "136000"]

Abstract:
A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

Claim (Index 2):
The comparator of  claim 1 , wherein the first switching circuitry includes a first transistor and the second switching circuitry includes a second transistor, and wherein the reset signal is coupled to the gate of the first transistor and the gate of the second transistor.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 3.925
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15466691', '13600559', '13051929', '12511250', '11113954']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5854277570223084
- 35 USC 102 Novelty (BERT): 0.5421277811690065
- Combined Prediction Score: 0.5810977594369782
- Mean Citation Score: 245.369932
- Max Citation Score: 365.85
- Similarity Product: 280.25724856853486

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test