PATENT CLAIM ANALYSIS

Application Number: 15864979
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["438", "067000"]

Abstract:
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Claim (Index 10):
The method of  claim 9 , wherein the first dielectric layer extends from the conductive plug to the conductive material disposed within the second trench.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.31111
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15167390', '13898641', '13937055', '14263520', '15441791']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8502652384807229
- 35 USC 102 Novelty (BERT): 0.5136544519268662
- Combined Prediction Score: 0.8166041598253372
- Mean Citation Score: 227.775984
- Max Citation Score: 323.50806
- Similarity Product: 315.3806055268907

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test