PATENT CLAIM ANALYSIS

Application Number: 15877931
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["438", "276000"]

Abstract:
A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

Claim (Index 15):
The semiconductor device of  claim 13  wherein the plurality of CMOS devices are a plurality of p-FETs, the dopant being the p-type dopant.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.80357
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14954166', '15040278', '15215921', '15809122', '14226488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8573533087604512
- 35 USC 102 Novelty (BERT): 0.5193606559782601
- Combined Prediction Score: 0.8235540434822322
- Mean Citation Score: 251.72877000000005
- Max Citation Score: 257.39532
- Similarity Product: 158.87246574256898

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test