PATENT CLAIM ANALYSIS

Application Number: 16046634
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-10
Patent Classification: ["257", "314000"]

Abstract:
Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Claim (Index 9):
The method of  claim 8 , wherein forming the alternating dielectric stack comprises:\n forming at least 32 dielectric layer pairs stacked in a vertical direction, each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 95.0
- Lexical Diversity: 2.56522
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16046887', '16046627', '15455667', '15455600', '15597965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9106676716533348
- 35 USC 102 Novelty (BERT): 0.5143003388249492
- Combined Prediction Score: 0.8710309383704962
- Mean Citation Score: 228.86277400000003
- Max Citation Score: 320.21066
- Similarity Product: 290.3966963367725

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test