PATENT CLAIM ANALYSIS

Application Number: 15881022
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "774000"]

Abstract:
A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

Claim (Index 19):
A method comprising:\n forming a semiconductor substrate; forming a plurality of low-k dielectric layers over the semiconductor substrate; forming a plurality of seal rings, comprising:\n forming a plurality of seal ring metal lines in first alternating layers of the plurality of low-k dielectric layers, each of the plurality of seal ring metal lines forming a continuous loop around a corresponding seal ring region; and \n forming a plurality of seal ring metal vias in second alternating layers of the plurality of low-k dielectric layers, each of the second alternating layers interposed between alternate ones of the first alternating layers; \n forming a first passivation layer over the plurality of low-k dielectric layers; forming a first group of dummy bumps, the first group of dummy bumps disposed directly over a first seal ring region of the corresponding seal ring regions, the first group of dummy bumps comprising a plurality of dummy bump connectors, wherein each dummy bump of the first group of dummy bumps is electrically decoupled from the plurality of low-k dielectric layers by the first passivation layer; forming a second group of dummy bumps, the second group of dummy bumps disposed directly over a second seal ring region of the corresponding seal ring regions, the second group of dummy bumps comprising one or more dummy bump connectors, wherein each dummy bump of the second group of dummy bumps is electrically decoupled from the plurality of low-k dielectric layers by the first passivation layer; forming a group of active bumps, the group of active bumps disposed directly over an outer seal ring region of the corresponding seal ring regions, the group of active bumps comprising one or more active bump connectors, wherein each of the active bump connectors is coupled to a device in the semiconductor substrate; and bonding the semiconductor substrate to another substrate to form a package, wherein the one or more dummy bumps is electrically coupled to a device in the other substrate, wherein the first seal ring region is disposed in a first corner of the package and the second seal ring region is disposed in a second corner of the package, wherein a first number of dummy bumps in the first seal ring region is different than a second number of dummy bumps in the second seal ring region.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 3.51351
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12915170', '12953130', '14730231', '13712665', '15232959']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9110763562032518
- 35 USC 102 Novelty (BERT): 0.4781122534301926
- Combined Prediction Score: 0.8677799459259459
- Mean Citation Score: 169.65573200000003
- Max Citation Score: 172.6217
- Similarity Product: 123.17778972035649

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test