PATENT CLAIM ANALYSIS

Application Number: 16047079
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "288000"]

Abstract:
A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

Claim (Index 16):
The method of  claim 15  further comprising grinding a back surface of the semiconductor substrate to reveal the conductive material.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 3.02083
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13457823', '13774344', '14325727', '13228196', '13335569']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9187283361659948
- 35 USC 102 Novelty (BERT): 0.5170165947060011
- Combined Prediction Score: 0.8785571620199956
- Mean Citation Score: 245.86813
- Max Citation Score: 285.36533
- Similarity Product: 170.00461905326006

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test