PATENT CLAIM ANALYSIS

Application Number: 16139146
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["341", "172000"]

Abstract:
An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB. The DAC further including and a plurality of second capacitors coupled to the reference voltage, wherein the redistribution capacitor having a capacitive value that is equal to (1−N) times the total capacitance of a parallel combination of the one or more first capacitors. And the second capacitors are associated with less significant bits, and an input voltage line carrying an input voltage (V IN ) switchably coupled to the first input or switchably coupled to the second input.

Claim (Index 9):
A method for performing an analog-to-digital conversion, the method comprising:\n supplying an input voltage (V IN ) as a second input to a comparator having an output, a first input, and the second input; supplying the output of the comparator to an input of a successive approximation register (SAR) to generate based thereon a parallel digital output having a plurality of more significant bits, including a most significant bit (MSB), and a plurality of less significant bits; supplying the parallel digital output to a digital-to-analog converter (DAC) to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator, wherein the internal analog signal is generated by voltage division across a plurality of capacitors, wherein the DAC includes a first capacitor network having a first capacitor and a second capacitor network having plurality of second capacitors, and a third capacitor network having a plurality of third capacitors, the first capacitor having a value based on the total parallel capacitance of each of the second capacitors and coupled between a first line carrying a first voltage and a second line carrying a second voltage, the plurality of second capacitors associated with the plurality of more significant bits, including the MSB, further wherein the plurality of second capacitors each switchable coupled between the first line and the second line and having respectively a value based on a ratio of the first voltage to a third voltage that is less than the first voltage, further wherein the plurality of third capacitors are associated with the less significant bits and respectively switchably coupled between the first line and a third line carrying the third voltage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 97.0
- Lexical Diversity: 3.02299
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15799812', '10663729', '15586015', '14932798', '15052452']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6051576791592664
- 35 USC 102 Novelty (BERT): 0.5050164988122549
- Combined Prediction Score: 0.5951435611245653
- Mean Citation Score: 266.04663
- Max Citation Score: 282.888
- Similarity Product: 237.90019760513303

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test