PATENT CLAIM ANALYSIS

Application Number: 16270036
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["345", "215000"]

Abstract:
Disclosed is a display device for use of a surface display of an arbitrary shape, including a plural. number of display element units, each made up of a circuit that forms a single stage of a scanning circuit and a pixel circuit connected to an output of the scanning circuit, are arranged in a unicursal fashion on a display substrate.

Claim (Index 1):
A display device comprising:\n a plurality of stages of unit circuits arranged in a cascade connection to form a scanning circuit, each of the unit circuits including an input node to receive a scanning signal, a clock input node to receive a clock signal and an output node to output the scanning signal, each of the unit circuits, responsive to the clock signal received at the clock input node, outputting, from the output node thereof, the scanning signal received at a scanning signal input terminal or received at the input node thereof from a preceding unit circuit to transfer the scanning signal to a succeeding unit circuit from the output node thereof and supplying the scanning signal from the output node thereof to a pixel circuit arranged in a stage corresponding to each of the unit circuits; a plurality of the pixel circuits, each of the pixel circuits including:\n a display element having a first end connected to a common electrode; and \n a switch transistor adapted to be turned on and off by the scanning signal supplied thereto from the output node of a corresponding stage of the unit circuit, the switch transistor arranged between a terminal to which a data signal is supplied and a second end of the display element; and \n a wiring that is connected in common to terminals to which a plurality of the data signals are applied, wherein a voltage signal corresponding to a grayscale level to be displayed by the display element is sequentially applied to the wiring with a clock cycle, wherein a plurality of the display elements are arranged in a two-dimensional directions to form a display area, with the scanning circuit disposed inside the display area, as viewed in a planer view, wherein the scanning circuit and the pixel circuits are formed on a non-rectangular substrate with one or more edges being curved, as viewed in a planer view, and the display area, inside of which the scanning circuit is formed, is formed along the edge of the substrate, wherein with respect to a linear array of an array of the display elements, a part of the scanning circuit is disposed between two adjacent linear arrays of the display elements.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 1.58537
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14794845', '15982081', '11871173', '14288950', '12705235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6826669884996512
- 35 USC 102 Novelty (BERT): 0.5181568622768787
- Combined Prediction Score: 0.666215975877374
- Mean Citation Score: 310.385466
- Max Citation Score: 340.6275
- Similarity Product: 336.23269639983766

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test