PATENT CLAIM ANALYSIS

Application Number: 16194878
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-06
Patent Classification: ["341", "120000"]

Abstract:
An electronic circuit includes a reference ADC and a plurality of sub-ADCs. The reference ADC converts an input signal to reference data in response to a reference clock. The plurality of sub-ADCs may respectively convert the input signal to a plurality of output data, in response respectively to the plurality of conversion clocks providing different timings. Based on a difference between the reference data and each of the plurality of output data and output data corresponding to the difference among the plurality of output data, a timing of a conversion clock associated with the output data corresponding to the difference among the plurality of conversion clocks is adjusted.

Claim (Index 20):
The electronic circuit of  claim 16 , wherein\n the different delay times of the plurality of delay circuits are independently adjusted based on the delay calibration values.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 98.0
- Lexical Diversity: 2.53333
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16194824', '16194844', '14343975', '12929441', '14948875']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6115589524329518
- 35 USC 102 Novelty (BERT): 0.5478810447137091
- Combined Prediction Score: 0.6051911616610276
- Mean Citation Score: 261.53027799999995
- Max Citation Score: 388.13565
- Similarity Product: 328.60223315831416

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test