PATENT CLAIM ANALYSIS

Application Number: 15924917
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["710", "112000"]

Abstract:
The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

Claim (Index 32):
The method of  claim 31 , wherein the method includes providing the information associated with the expected latency of the execution of the sense or program command to the controller responsive to an additional command from the controller.

Metadata:
- Claim Count in Document: 92.0
- Percentile: 90.0
- Lexical Diversity: 2.13636
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15199802', '14293521', '15691859', '11816858', '14678889']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6331278154813818
- 35 USC 102 Novelty (BERT): 0.4981409378107524
- Combined Prediction Score: 0.6196291277143189
- Mean Citation Score: 147.83459
- Max Citation Score: 151.44533
- Similarity Product: 89.56327383639814

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test