PATENT CLAIM ANALYSIS

Application Number: 16013618
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "205000"]

Abstract:
Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

Claim (Index 13):
The apparatus of  claim 11 , wherein the decoder circuit includes a row decoder.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 2.30435
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16009806', '15591015', '13970518', '11501144', '11500786']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8091308278417928
- 35 USC 102 Novelty (BERT): 0.5321853694465398
- Combined Prediction Score: 0.7814362820022674
- Mean Citation Score: 237.32802
- Max Citation Score: 387.1804
- Similarity Product: 248.067467903018

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test