PATENT CLAIM ANALYSIS

Application Number: 16077176
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "347000"]

Abstract:
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Claim (Index 24):
The multilayer structure of  claim 15  wherein the surface roughness of the roughened front surface of the high resistivity single crystal semiconductor layer substrate is between about 0.1 micrometer and about 1 micrometer as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 1.12903
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15435428', '15984586', '15526798', '16077142', '15828534']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.935435750373804
- 35 USC 102 Novelty (BERT): 0.5622720094230544
- Combined Prediction Score: 0.8981193762787292
- Mean Citation Score: 410.202564
- Max Citation Score: 431.36313
- Similarity Product: 360.23556440932816

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test