PATENT CLAIM ANALYSIS

Application Number: 16101438
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["438", "199000"]

Abstract:
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel.

Claim (Index 4):
The 3D semiconductor device according to  claim 1 ,\n wherein at least one of said second transistors is a vertically oriented transistor.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 96.0
- Lexical Diversity: 3.6
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15950169', '16004404', '16024911', '15990684', '15904377']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.892098189304815
- 35 USC 102 Novelty (BERT): 0.5297053085277811
- Combined Prediction Score: 0.8558589012271116
- Mean Citation Score: 336.533492
- Max Citation Score: 364.4499
- Similarity Product: 357.8453760225713

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test