PATENT CLAIM ANALYSIS

Application Number: 16157837
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "072000"]

Abstract:
Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Claim (Index 1):
A display apparatus, comprising:\n a substrate; a semiconductor layer formed on the substrate, wherein the semiconductor layer includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer; a first gate insulating layer formed on the semiconductor layer; a first gate wiring formed on the first gate insulating layer, wherein the first gate wiring overlaps the first semiconductor layer; a second gate insulating layer formed on the first gate wiring; a second gate wiring formed on the second gate insulating layer, wherein the second gate wiring overlaps the second semiconductor layer; a third gate insulating layer covering the second gate wiring; a driving voltage line formed on the third gate insulating layer, wherein the driving voltage line intersects the first gate wiring and the second gate wiring; a data line formed on the third gate insulating layer, wherein the data line intersects the first gate wiring and the second gate wiring; a short circuit protection area formed between the first gate wiring and the second gate wiring, wherein the short circuit protection area is formed between the driving voltage line and the data line; and a stepped part protruding from any one of the first gate wiring and the second gate wiring formed in the short circuit protection area,

Metadata:
- Claim Count in Document: 3.0
- Percentile: 97.0
- Lexical Diversity: 4.36111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15091624', '12571552', '10890129', '14184996', '11941147']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9168479812046318
- 35 USC 102 Novelty (BERT): 0.50743703987765
- Combined Prediction Score: 0.8759068870719336
- Mean Citation Score: 218.279756
- Max Citation Score: 314.65244
- Similarity Product: 292.4239201079488

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test