PATENT CLAIM ANALYSIS

Application Number: 15949898
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["375", "376000"]

Abstract:
A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Claim (Index 21):
The method of  claim 19 , wherein:\n the method further comprises implementing at least two phase adjustment control loops,\n including \n a first phase adjustment control loop to adjust phase of a recovered clock using the decisions as to the logic states of the bits of the sequence and to adjust the expected data transition times are dependent on the recovered clock, so as to advance or retard the phase also advances or retards prospective expected data transition times when the first phase adjustment loop advances or retards phase of the recovered clock, and \n a second phase adjustment control loop to identify a desired data sampling time, and to responsively establish a phase offset of prospective data sampling times relative to the recovered clock as a function of the desired data sampling time, \n such that the first phase adjustment control loop and the second phase adjustment control loop respectively adjust the prospective expected data transition times and the phase offset; and \n an update rate of the second phase adjustment control loop is slower than an update rate of the first phase adjustment control loop.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 2.44068
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15209529', '12812720', '14563626', '15209494', '11428818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4706510794237489
- 35 USC 102 Novelty (BERT): 0.4978010562913236
- Combined Prediction Score: 0.4733660771105064
- Mean Citation Score: 202.43881
- Max Citation Score: 246.34514
- Similarity Product: 199.1318817585229

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test