PATENT CLAIM ANALYSIS

Application Number: 15992604
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["327", "206000"]

Abstract:
A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.

Claim (Index 15):
The clock detector of  claim 14 , wherein each of said first hysteresis buffer and said second hysteresis buffer comprises a Schmtt trigger.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 93.0
- Lexical Diversity: 3.55814
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['09405300', '15435519', '13648557', '13482948', '14498161']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7679004190094504
- 35 USC 102 Novelty (BERT): 0.4801501238263425
- Combined Prediction Score: 0.7391253894911396
- Mean Citation Score: 149.914742
- Max Citation Score: 162.25996
- Similarity Product: 109.20583360178232

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test