PATENT CLAIM ANALYSIS

Application Number: 16166598
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["438", "199000"]

Abstract:
A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where the contact plugs are connected to the plurality of first single crystal transistors and the first metal layer, where the first metal layer interconnect the first single crystal transistors forming memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a second metal layer; a third metal layer, where the second metal layer overlays the third level, where the third metal layer overlays the second metal layer, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, where the memory control circuits include control sub-circuits to remap a degraded memory block to an alternative memory space within the device.

Claim (Index 8):
A 3D semiconductor device, the device comprising:\n a first level comprising a plurality of first single crystal transistors; a first metal layer,\n wherein said first metal layer interconnect said first single crystal transistors forming memory control circuits; \n a second level above said first level, said second level comprising a plurality of second transistors; a third level above said second level, said third level comprising a plurality of third transistors; a second metal layer; a third metal layer,\n wherein said second metal layer is above said third level, \n wherein said third metal layer is above said second metal layer, \n wherein said second transistors are aligned to said first transistors with less than 140 nm alignment error, \n wherein said third metal comprise bit lines, \n wherein said second level comprises a plurality of first memory cells, \n wherein said third level comprises a plurality of second memory cells, \n wherein one of said second transistors is at least partially self-aligned to at least one of said third transistors being formed following the same lithography step, \n wherein one of said second memory cells comprises at least one of said third transistors, and \n wherein said memory control circuits comprise control sub-circuits to remap a degraded memory block to an alternative memory space within said device.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 3.80851
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16004404', '15950169', '15990684', '16024911', '13869963']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8813756248675202
- 35 USC 102 Novelty (BERT): 0.5269770094503532
- Combined Prediction Score: 0.8459357633258036
- Mean Citation Score: 340.6060960000001
- Max Citation Score: 363.28952
- Similarity Product: 345.1522584239387

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test