PATENT CLAIM ANALYSIS

Application Number: 15968065
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["326", "030000"]

Abstract:
A memory system includes: a buffer memory device; and a memory controller configured to communicate data with the buffer memory device, wherein the memory controller includes: an input/output power voltage sensor configured to generate a first signal by sensing a change in input/output power voltage; and an impedance calibration circuit configured to perform an impedance calibration operation in response to the first signal.

Claim (Index 12):
The memory controller of  claim 11 , wherein the reference voltage generating unit includes a second resistor ladder including a plurality of resistors coupled in series between the input/output power voltage and a ground voltage,\n wherein the second resistor ladder generates a plurality of reference division voltages having voltage levels different from one another, and wherein the plurality of reference division voltages include a plurality of first division voltages included in a first reference voltage range and a plurality of second division voltages included in a second reference voltage range that is lower than the first reference voltage range.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 1.81579
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15968026', '13239478', '14723614', '15922332', '15200064']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6644594611317118
- 35 USC 102 Novelty (BERT): 0.5272591806698622
- Combined Prediction Score: 0.650739433085527
- Mean Citation Score: 259.901554
- Max Citation Score: 337.2395
- Similarity Product: 235.81123710587624

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test