PATENT CLAIM ANALYSIS

Application Number: 15901212
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-06
Patent Classification: ["375", "355000"]

Abstract:
A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.

Claim (Index 1):
A clock and data recovery (CDR) circuit, comprising:\n a sampler for receiving a data signal and a clock signal, and generating first, second, and third sampled signals; a phase detector that is connected to the sampler for receiving the first, second, and third sampled signals, and generating first and second early-late vote (ELV) signals; and a proportional-integral (PI) controller that is connected to the phase detector, the PI controller comprising:\n a charge pump that receives the first and second ELV signals, and steers a current signal into or out of one of summing nodes based on the first and second ELV signals; \n a resistive-capacitive (RC) circuit that is connected to a current-source circuit of the charge pump, the RC circuit providing a stability of a common-mode feedback (CMFB) loop when a CMFB amplifier circuit is connected to the current-source circuit; \n an integrator circuit that receives the current signal from one of the summing nodes, and generates a first control signal; \n a proportional circuit that receives the first and second ELV signals, and generates a second control signal; and \n an oscillator that is connected to the integrator and proportional circuits for receiving the first and second control signals, respectively, and generating the clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 3.09091
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14826888', '15138758', '15286029', '10947891', '11732357']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.470777559296149
- 35 USC 102 Novelty (BERT): 0.4853235528109214
- Combined Prediction Score: 0.4722321586476262
- Mean Citation Score: 190.468862
- Max Citation Score: 217.53734
- Similarity Product: 164.20609674538375

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test