PATENT CLAIM ANALYSIS

Application Number: 16129767
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2018-12
Patent Classification: ["438", "030000"]

Abstract:
A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.

Claim (Index 11):
A manufacture method of a low temperature poly-silicon array substrate, comprising steps of:\n step 1, providing a substrate, and defining a negative-channel metal-oxide-semiconductor (NMOS) region and a positive-channel metal-oxide-semiconductor (PMOS) region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region; step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region; step 3, coating a photoresist layer on the polysilicon layer, wherein after a halftone mask is employed to implement exposure and development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in a middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal; employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region; employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer thinner; employing a remaining part of thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions, wherein the thin layer regions of the first photoresist layer are removed before the implementation of N type heavy doping to the two sides of the first polysilicon section, while a part of the thick layer region of the first photoresist layer is preserved to serve as a mask for the implementation of N type heavy doping, the thick layer region being removed after the implementation of N type heavy doping; step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively; employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section; step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section; step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer; step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via; step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain; step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode; step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer; step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via; wherein in step 2, the low temperature crystallization process is one of excimer laser annealing and metal-Induced lateral crystallization; and wherein in step 2, an operation of channel doping is: coating a photoresist layer on the polysilicon layer, and employing a mask to implement exposure and development to the photoresist layer, and after removing the photoresist layer in the NMOS region, implementing P type light doping to the polysilicon layer in the entire NMOS region.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 97.0
- Lexical Diversity: 1.58824
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15111822', '15115692', '15031279', '15105572', '16101534']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8521365796188585
- 35 USC 102 Novelty (BERT): 0.5774994964634372
- Combined Prediction Score: 0.8246728713033163
- Mean Citation Score: 335.336498
- Max Citation Score: 452.4254
- Similarity Product: 434.76029920921326

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test