PATENT CLAIM ANALYSIS

Application Number: 16017865
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["375", "371000"]

Abstract:
Methods and apparatus relating to functional safety clocking framework for real time systems are described. In an embodiment, clock monitoring logic circuitry monitors a plurality of clock signals. Safety island logic circuitry receives an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals. Safety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals. Other embodiments are also disclosed and claimed.

Claim (Index 23):
The one or more computer-readable medium of  claim 22 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the clock monitoring logic circuitry to determine existence of the aging error based on monotonic movement of one or more of the plurality of clock signals.

Metadata:
- Claim Count in Document: 49.0
- Percentile: 94.0
- Lexical Diversity: 2.03448
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13401030', '12107415', '15059341', '10042098', '14464661']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4299371128625718
- 35 USC 102 Novelty (BERT): 0.4711351581233534
- Combined Prediction Score: 0.43405691738865
- Mean Citation Score: 107.64974
- Max Citation Score: 112.8912
- Similarity Product: 75.4383897849083

Labels:
- Claim Label 101: 0
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test