PATENT CLAIM ANALYSIS

Application Number: 16023951
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Claim (Index 1):
A method of manufacturing a semiconductor structure, comprising:\n receiving a substrate comprising a die pad disposed over the substrate and a passivation disposed over the substrate and surrounding the die pad; forming an RDL over the passivation, wherein the RDL includes a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connected with the die pad; disposing a conductive bump over the interconnect structure; and disposing an isolation layer to surround the substrate and the RDL.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.44118
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14993454', '15234813', '14840808', '15676375', '15727252']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914978005527962
- 35 USC 102 Novelty (BERT): 0.4929293829232434
- Combined Prediction Score: 0.8727731432674901
- Mean Citation Score: 215.564494
- Max Citation Score: 259.2275
- Similarity Product: 212.5392922942341

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test