PATENT CLAIM ANALYSIS

Application Number: 16011483
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["375", "286000"]

Abstract:
For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

Claim (Index 2):
The modulator of  claim 1 , wherein the multiple is a small multiple.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 94.0
- Lexical Diversity: 1.95238
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14180315', '15206011', '14976100', '15494366', '09900395']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5276799372920293
- 35 USC 102 Novelty (BERT): 0.5286047172545772
- Combined Prediction Score: 0.5277724152882841
- Mean Citation Score: 263.389584
- Max Citation Score: 330.24603
- Similarity Product: 182.6789962622344

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test