PATENT CLAIM ANALYSIS

Application Number: 16188411
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "390000"]

Abstract:
An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.

Claim (Index 16):
The integrated circuit structure of  claim 15 , wherein the SRAM cell comprises a write port and a read port, and the port is the write port, and wherein the word-line is a write word-line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15089947', '15641013', '15047927', '15061573', '16022831']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9266593677786268
- 35 USC 102 Novelty (BERT): 0.5466285110964852
- Combined Prediction Score: 0.8886562821104126
- Mean Citation Score: 338.56403200000005
- Max Citation Score: 397.75092
- Similarity Product: 243.5118463438511

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test