PATENT CLAIM ANALYSIS

Application Number: 15964647
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "063000"]

Abstract:
A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

Claim (Index 2):
The data processing system of  claim 1 , wherein first cycle timing comprises a data rate of two bits per complete clock cycle.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 91.0
- Lexical Diversity: 3.62222
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15903253', '12566626', '12824536', '12215761', '10698704']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8075082358663045
- 35 USC 102 Novelty (BERT): 0.4911350462691343
- Combined Prediction Score: 0.7758709169065875
- Mean Citation Score: 194.116232
- Max Citation Score: 219.0328
- Similarity Product: 146.2654973197937

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test