PATENT CLAIM ANALYSIS

Application Number: 15951033
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["257", "288000"]

Abstract:
A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an active region on the substrate, an electrode in the active region, and an interlayer dielectric layer covering the active region and the electrode. The method also includes etching the interlayer dielectric layer to form a contact hole exposing the electrode, forming a conductive adhesion layer on a bottom and sidewalls of the contact hole, and forming a contact member on the conductive adhesion layer filling the contact hole. The conductive adhesion layer at the bottom and sidewalls of the contact hole prevents the electrode from being oxidized while forming the contact member, thereby effectively reducing the contact resistance and the barrier height of the semiconductor device.

Claim (Index 9):
The method of  claim 8 , wherein etching the interlayer dielectric layer comprises:\n performing a first etch process on the interlayer dielectric layer to form an opening exposing the electrode; performing a second etch process on a portion of a sidewall of the opening to form the contact hole.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 2.42593
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15483554', '14472571', '11797401', '11976252', '11519615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9266352104715944
- 35 USC 102 Novelty (BERT): 0.4940197952134808
- Combined Prediction Score: 0.883373668945783
- Mean Citation Score: 228.226706
- Max Citation Score: 237.44948
- Similarity Product: 178.58705381854057

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test