PATENT CLAIM ANALYSIS

Application Number: 15897550
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185220"]

Abstract:
Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Claim (Index 17):
An apparatus, comprising:\n means for erasing a set of memory cells in an erase loop of a multi-loop erase operation; and means for selectively programming one or more memory cells of the set of memory cells positioned adjacent to select gate transistors, during the erase loop; wherein:\n the set of memory cells are in a NAND chain; \n a bottom of the NAND chain is connected to a substrate; and \n the means for erasing comprises means for applying an erase pulse to the substrate, and means for applying a control gate voltage to the one or more memory cells while the erase pulse is applied to the substrate, wherein the control gate voltage applied to the one or more memory cells is incremented over the erase loops of the erase operation.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 2.14493
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14612561', '15816546', '14612601', '15163171', '15693982']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.822676767201724
- 35 USC 102 Novelty (BERT): 0.5033096642863109
- Combined Prediction Score: 0.7907400569101827
- Mean Citation Score: 312.745902
- Max Citation Score: 316.5821
- Similarity Product: 269.3470435478807

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test