PATENT CLAIM ANALYSIS

Application Number: 16055451
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A device fabricated on a wafer is disclosed. The device includes a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI. The second block includes a first vertical section coupled to a first ground, a second vertical section, a third vertical section coupled to a second ground. The second vertical section is doped lightly compared to the first vertical section and the second vertical section.

Claim (Index 12):
The device of  claim 6 , wherein the second vertical section includes:\n an n-well layer over the horizontal buried oxide layer, wherein the n-well is configured to be connected to a supply voltage.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 96.0
- Lexical Diversity: 2.91892
- Patent Class: nan
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['09991277', '12288575', '13226838', '13483569', '15252920']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5319910520799926
- 35 USC 102 Novelty (BERT): 0.4685307996099554
- Combined Prediction Score: 0.525645026832989
- Mean Citation Score: 154.64093599999995
- Max Citation Score: 166.61028000000005
- Similarity Product: 127.9248681095338

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test