PATENT CLAIM ANALYSIS

Application Number: 15944321
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "668000"]

Abstract:
The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Claim (Index 24):
A semiconductor package comprising:\n a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; two or more connection units spaced-apart from each other and disposed adjacently to the semiconductor chip; and a connection member disposed on the two or more connection units and the semiconductor chip, wherein each of the two or more connection units includes a first insulating layer and a second insulating layer disposed on the first insulating layer, one of the two or more connection units further includes a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer thereof and a third redistribution layer disposed on the second insulating layer, the first redistribution layer of the one of the two or more connection units being covered by the second insulating layer of the one of the two or more connection units, the connection member includes an insulating layer and a redistribution layer disposed on the insulating layer, and the first to third redistribution layers of the one of the two or more connection units and the redistribution layer of the connection member are electrically connected to the connection pads of the semiconductor chip.

Metadata:
- Claim Count in Document: 82.0
- Percentile: 91.0
- Lexical Diversity: 2.92593
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15297831', '15673149', '15377402', '15595226', '15413713']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9418229576416604
- 35 USC 102 Novelty (BERT): 0.558462331248148
- Combined Prediction Score: 0.9034868950023092
- Mean Citation Score: 403.37675
- Max Citation Score: 436.10257
- Similarity Product: 397.9188074957085

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test