PATENT CLAIM ANALYSIS

Application Number: 15956139
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-07
Patent Classification: ["257", "324000"]

Abstract:
A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.

Claim (Index 15):
A method of forming a three-dimensional memory device, comprising:\n forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers over a substrate; forming vertically offset surfaces in a contact region of the vertically alternating sequence, wherein the vertically offset surfaces laterally extend along a first horizontal direction along a second horizontal direction that is perpendicular to the first horizontal direction, wherein the vertically offset surfaces are formed at N different horizontal planes that are vertically spaced apart among one another by a thickness of a respective neighboring pair of a continuous insulating layer and a continuous sacrificial material layer, and a sequence of the vertically offset surfaces along the second horizontal direction is selected such that the vertically offset surfaces have a vertical cross-sectional profile along the second horizontal direction which contains both a stepwise decreasing profile and a stepwise increasing profile; patterning the vertically offset surfaces into column stairs, wherein each column stair continuously extends from a bottommost layer to a topmost layer within the vertically alternating sequence; forming groups of memory stack structures through the vertically alternating sequence in a memory array region, wherein each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film; forming trenches through the alternating stack along the first horizontal direction; forming backside recesses by removing remaining portions of the continuous sacrificial material layers through the trenches; and forming electrically conductive layer in the backside recesses.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 2.27419
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15943859', '15717102', '15834261', '15628495', '15685254']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9349202023303014
- 35 USC 102 Novelty (BERT): 0.5285659331955856
- Combined Prediction Score: 0.8942847754168298
- Mean Citation Score: 356.93722599999984
- Max Citation Score: 362.49683
- Similarity Product: 274.20208352218566

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test