PATENT CLAIM ANALYSIS

Application Number: 16052085
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["257", "368000"]

Abstract:
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

Claim (Index 7):
The method of  claim 6  wherein the first gate structure and the second gate structure are exposed when the first dielectric layer is recessed, and further comprising:\n forming a stress liner over the first gate structure, the second gate structure, and the recessed first dielectric layer in the first device area, \n wherein the stress liner fills a first portion of the space over the portion of the recessed first dielectric layer without void formation.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.89474
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11672150', '11559574', '15366223', '14740987', '15847028']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9134987632669568
- 35 USC 102 Novelty (BERT): 0.4932583822469028
- Combined Prediction Score: 0.8714747251649513
- Mean Citation Score: 201.604758
- Max Citation Score: 204.89648
- Similarity Product: 136.2746659611893

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test