PATENT CLAIM ANALYSIS

Application Number: 16101480
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-04
Patent Classification: ["365", "189050"]

Abstract:
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

Claim (Index 15):
The method of  claim 10 , further comprising loading a register on the first memory module prior to receiving the rank read command, the register loaded with a first configuration value enabling the relaying of the delayed version of the read command.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 1.64615
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15522182', '15522164', '13080720', '15745396', '15552569']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7890044060842453
- 35 USC 102 Novelty (BERT): 0.5024136848781976
- Combined Prediction Score: 0.7603453339636406
- Mean Citation Score: 214.00676
- Max Citation Score: 279.33347000000003
- Similarity Product: 191.57350805495025

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test