PATENT CLAIM ANALYSIS

Application Number: 15869592
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["365", "130000"]

Abstract:
A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Claim (Index 1):
An apparatus, comprising:\n a three-dimensional array of non-volatile memory cells formed over a substrate, comprising:\n a plurality of layers of word lines, each of the layers of word lines running horizontally over the substrate, the layers separated in a vertical direction by dielectric layers; \n a plurality of bit lines running vertically with respect to the substrate; and \n a plurality of memory cells each connected between a corresponding one of the word lines and a corresponding one of the bit lines, each of the memory cells comprising:\n a phase change memory material configured to provide a first current path between the corresponding word line and the corresponding bit line for the memory cell, the phase change memory material having a first resistivity in a first phase and a second resistivity in a second phase, the first resistivity being higher than the second resistivity; and \n an intermediate resistance material adjacent to the phase change memory material and configured to provide second current path in parallel with the first current path between the memory cell's corresponding word line and bit line, the intermediate resistance material having a resistivity between the first and second resistivities; and \n \n one or more control circuits connected to the three-dimensional array of non-volatile memory cells, the control circuits configured to program multi-state data into the memory cells and read multi-state data from the memory cells.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 86.0
- Lexical Diversity: 1.69492
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15869553', '11769324', '14715579', '13773963', '11748595']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.786327519715634
- 35 USC 102 Novelty (BERT): 0.4811697901472336
- Combined Prediction Score: 0.7558117467587939
- Mean Citation Score: 192.311936
- Max Citation Score: 228.93353
- Similarity Product: 176.97997419447896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test