PATENT CLAIM ANALYSIS

Application Number: 15964085
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "737000"]

Abstract:
A method for manufacturing a three dimensional integrated circuit (3DIC) package includes stacking a plurality of semiconductor chips vertically and sequentially on a carrier to form a stacking structure; applying a molding material on the carrier to surround the stacking structure; removing the carrier to expose a surface of the stacking structure; forming a redistribution layer on the exposed surface of the stacking structure; and disposing a plurality of electrical bumpers on the redistribution layer.

Claim (Index 2):
The method of  claim 1 , wherein forming of the redistribution layer comprises:\n forming the redistribution layer on a surface of the semiconductor chip exposing from the molding material.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.86364
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14640028', '15956055', '15462906', '13586890', '15434664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9137997852317384
- 35 USC 102 Novelty (BERT): 0.4742266211990811
- Combined Prediction Score: 0.8698424688284727
- Mean Citation Score: 136.085352
- Max Citation Score: 140.04958
- Similarity Product: 98.21951196790933

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test