PATENT CLAIM ANALYSIS

Application Number: 15884711
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "311000"]

Abstract:
The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.

Claim (Index 12):
The method of  claim 10 , further comprising\n forming a gate stack on the fin active region, wherein the gate stack includes a metal electrode; depositing a silicon layer on the metal electrode; annealing to react the silicon layer and a metal of the metal electrode, thereby forming a silicide layer on the metal electrode; and etching to remove unreacted silicon.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.07843
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15800359', '15864525', '15803083', '14504258', '14942740']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9251785763217056
- 35 USC 102 Novelty (BERT): 0.5005673695005797
- Combined Prediction Score: 0.8827174556395931
- Mean Citation Score: 227.521044
- Max Citation Score: 243.49124
- Similarity Product: 171.31326436127424

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test