PATENT CLAIM ANALYSIS

Application Number: 15941995
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.

Claim (Index 1):
A system comprising:\n an integrated memory controller unit; and a processor core coupled to the integrated memory controller unit, the processor core comprising: a plurality of vector registers, including a first vector register to store a source vector that is to have a plurality of memory indices; a plurality of mask registers, including a first mask register to store a predicate operand, the predicate operand to have a plurality of predicate elements, each predicate element corresponding to a memory index of the source vector in a same relative position; a decode unit to decode an instruction, the instruction having a first field to specify the first vector register, a second field to specify the first mask register, and a single bit to indicate whether non-temporal locality gather hints are to be provided; and an execution unit coupled with the decode unit, the plurality of vector registers, and the plurality of mask registers, the execution unit, in response to the decode of the instruction and the single bit indicating that the non-temporal locality gather hints are to be provided, to: provide the non-temporal locality gather hints for memory locations that correspond to memory indices for which the corresponding predicate elements have a first value; and not provide the non-temporal locality gather hints for memory locations that correspond to memory indices for which the corresponding predicate elements have a second value.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 90.0
- Lexical Diversity: 3.14583
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15942046', '15433500', '14335006', '14969249', '13838544']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.535086622780393
- 35 USC 102 Novelty (BERT): 0.5995259666591773
- Combined Prediction Score: 0.5415305571682714
- Mean Citation Score: 397.42178
- Max Citation Score: 505.02063
- Similarity Product: 492.69734610619423

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test