PATENT CLAIM ANALYSIS

Application Number: 15951262
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["257", "565000"]

Abstract:
A semiconductor device including a first conductivity type substrate, a first conductivity type carrier store layer formed on an upper surface side of the substrate, a second conductivity type channel dope layer formed on the carrier store layer, a first conductivity type emitter layer formed on the channel dope layer, a gate electrode in contact with the emitter layer, the channel dope layer and the carrier store layer via a gate insulating film, and a second conductivity type collector layer formed on a lower surface side of the substrate, wherein the gate insulating film has a first part in contact with the emitter layer and the channel dope layer, a second part in contact with the carrier store layer, and a third part in contact with the substrate, and at least a part of the second part is thicker than the first part and the third part.

Claim (Index 18):
A method of manufacturing a semiconductor device comprising:\n forming a first conductivity type carrier store layer on a first conductivity type substrate, forming a second conductivity type channel dope layer on the carrier store layer, and forming a first conductivity type emitter layer partially on the channel dope layer; partially etching a portion where the emitter layer is formed in plan view and a portion where the emitter layer is not formed in plan view, thereby forming a first trench to which the substrate is exposed; embedding the first trench with a gate insulating film; etching a part of the gate insulating film at the portion where the emitter layer is formed in plan view so that the emitter layer, the channel dope layer, the carrier store layer and the substrate are not exposed, thereby forming a second trench in the gate insulating film; embedding the second trench with a gate electrode; and forming a gate wire on the gate insulating film at the portion where the emitter layer is not formed in plan view and the gate electrode.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 3.43478
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13205845', '11626141', '12926678', '10843571', '11947429']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9101142853995
- 35 USC 102 Novelty (BERT): 0.5025442372761052
- Combined Prediction Score: 0.8693572805871606
- Mean Citation Score: 267.03742
- Max Citation Score: 278.34668
- Similarity Product: 241.18720470543383

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test