PATENT CLAIM ANALYSIS

Application Number: 16006498
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "149000"]

Abstract:
The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.

Claim (Index 1):
A method for synchronizing a number of clock pulses, comprising the steps:\n for each clock pulse, translating the incoming clock signal transitions to a binary value encoding the deviation from an expected arrival time; selecting first and a second binary value; calculating the average of these values and computing its difference to the expected value; and applying a corresponding phase correction or clock shift.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 1.04
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14274956', '15146890', '13306828', '14831784', '14029699']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7569492700080169
- 35 USC 102 Novelty (BERT): 0.4616530202159286
- Combined Prediction Score: 0.7274196450288081
- Mean Citation Score: 172.13580599999997
- Max Citation Score: 174.81987
- Similarity Product: 139.4342809587461

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test