PATENT CLAIM ANALYSIS

Application Number: 15976315
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "145000"]

Abstract:
Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS −V G  hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS  states at V G =0.

Claim (Index 4):
The NVM device recited in  claim 1 , wherein:\n the circuit topology is configured as a latch configured to have a differential-driving input pair D/DN; the latch comprising:\n a first transistor, M 1 , M 1  having an M 1 -source, an M 1 -gate, and an M 1 -drain; \n a second transistor, M 2 , M 2  having an M 2 -source, an M 2 -gate, and an M 2 -drain; \n a third transistor, M 3 , M 3  having an M 3 -source, an M 3 -gate, and an M 3 -drain; \n a fourth transistor, M 4 , M 4  having an M 4 -source, an M 4 -gate, and an M 4 -drain; \n a fifth transistor, M 5 , M 5  having an M 5 -source, an M 5 -gate, and an M 5 -drain; \n a sixth transistor, M 6 , M 6  having an M 6 -source, an M 6 -gate, and an M 6 -drain; \n a seventh transistor, M 7 , M 7  having an M 7 -source, an M 7 -gate, and an M 7 -drain; \n an eighth transistor, M 8 , M 8  having an M 8 -source, an M 8 -gate, and an M 8 -drain; \n each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8  is a metal oxide semiconductor field effect transistor (MOSFET); \n each of M 5  and M 6  is a FeFET; \n M 1 -drain being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, a data output Q, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, a data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 1 -gate being connected to a clock driver CLK; \n M 1 -source being connected to a data input D; \n M 2 -drain being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 2 -gate being connected to M 1 -gate; \n M 2 -source being connected to a data input DN; \n M 3 -drain being connected to a voltage supply V DD ; \n M 3 -gate being connected to M 3 -source, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 3 -source being connected to M 3 -gate, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 4 -drain being connected to V DD ; \n M 4 -gate being connected to M 3 -source, M 4 -source, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 4 -source being connected to M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 5 -drain be connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 5 -gate being connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -drain, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; \n M 5 -source being connected to M 7 -drain; \n M 6 -drain can being connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 5 -drain, M 6 -gate, and M 8 -gate; \n M 6 -gate being connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 5 -drain, M 6 -drain, and M 8 -gate; \n M 6 -source being connected to M 8 -drain; \n M 7 -drain being connected to M 5 -source; \n M 7 -gate being connected to M 6 -gate, M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 5 -drain, data output QN, M 5 -drain, M 6 -drain, and M 8 -gate; \n M 7 -source being connected to ground, GND; \n M 8 -drain being connected to M 6 -source; \n M 8 -gate being connected to M 7 -gate, M 6 -gate, M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 5 -drain, data output QN, M 5 -drain, and M 6 -drain; and \n M 8 -source being connected to GND.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 93.0
- Lexical Diversity: 1.77632
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12860253', '15594807', '13137566', '12856962', '13396272']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7784824059780886
- 35 USC 102 Novelty (BERT): 0.4659327003720508
- Combined Prediction Score: 0.7472274354174848
- Mean Citation Score: 165.774406
- Max Citation Score: 186.89499
- Similarity Product: 145.11889976617456

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test