PATENT CLAIM ANALYSIS

Application Number: 15767623
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["257", "433000"]

Abstract:
An image sensing chip packaging structure and a packaging method therefor. The image sensing chip packaging structure is provided with an image sensing chip and a control chip used for controlling the image sensing chip. The image sensing chip packaging structure also comprises a substrate, provided with a first surface and a second surface opposite to each other. The image sensing chip is electrically connected to the substrate, and is located on the first surface of the substrate. The control chip is electrically connected to the substrate, and is located on the second surface of the substrate. By applying a stacked packaging technology to the packaging of the image sensing chip, the size of the packaging structure of the image sensing chip is reduced, thereby improving the integration of the image sensing chip.

Claim (Index 9):
The image sensor chip packaging method according to  claim 8 , wherein, before the connecting electrically the image sensor chip to the substrate, the method further comprises:\n providing a wafer, wherein the wafer comprises image sensor chips arranged in an array, each of the image sensor chips comprises a first surface and a second surface opposite to each other, and the first surface of the image sensor chip is arranged with a photosensitive region and a contact pad on a region other than the photosensitive region; providing a protective cover plate with a same size as the wafer, wherein a surface of the protective cover plate is arranged with support units arranged in an array, and the support units correspond to the image sensor chips in a one-to-one manner; aligning and laminating the wafer with the protective cover plate, to form a sealed cavity between each of the image sensor chips and the protective cover plate, wherein the photosensitive region is located in the cavity; forming a plurality of through silicon vias on the second surface of the image sensor chip with a through silicon via process, wherein the through silicon vias correspond to contact pads in a one-to-one manner, and the contact pad is exposed from a bottom of the through silicon via; forming a metal wiring layer in the through silicon via, wherein the metal wiring layer is electrically connected to the contact pad; forming a solder ball on the second surface of the image sensor chip, wherein the solder ball is electrically connected to the metal wiring layer; and cutting the wafer and the protective cover plate to separate the image sensor chips connected to each another.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 91.0
- Lexical Diversity: 3.13043
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15767121', '15765968', '15765802', '15507901', '11878220']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.931414734318858
- 35 USC 102 Novelty (BERT): 0.5032266322605409
- Combined Prediction Score: 0.8885959241130262
- Mean Citation Score: 240.58439600000003
- Max Citation Score: 277.59982
- Similarity Product: 228.7487711627722

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test