PATENT CLAIM ANALYSIS

Application Number: 16226433
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["365", "185050"]

Abstract:
A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Claim (Index 16):
The apparatus of  claim 11 , wherein the first and second physical memory portions of the logic sector are addressable by the first and second drain selectors, respectively.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 98.0
- Lexical Diversity: 1.78462
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14453360', '13198978', '11279385', '11279381', '11279384']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8462369394881413
- 35 USC 102 Novelty (BERT): 0.5230967113654589
- Combined Prediction Score: 0.813922916675873
- Mean Citation Score: 332.187202
- Max Citation Score: 358.86365
- Similarity Product: 256.61102927284537

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test