PATENT CLAIM ANALYSIS

Application Number: 16034233
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-08
Patent Classification: ["326", "030000"]

Abstract:
Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistance calibration circuit configured to provide an impedance code to set impedance of a driver circuit. The resistance calibration circuit includes an adder/subtractor circuit configured to change the impedance code by a first step size responsive to the impedance code being less than a value to adjust the impedance of the driver circuit and further configured to change the impedance code by a second step size responsive to the impedance code greater or equal than the value to adjust the impedance of the driver circuit. The second step size is different from the first step size.

Claim (Index 6):
The apparatus of  claim 3  wherein each of the plurality of full adder circuits is configured to receive a respective one bit of the impedance code.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 95.0
- Lexical Diversity: 2.46939
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15882723', '15630901', '14726063', '14705762', '15834892']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6888410651486924
- 35 USC 102 Novelty (BERT): 0.5277257336463208
- Combined Prediction Score: 0.6727295319984552
- Mean Citation Score: 235.195998
- Max Citation Score: 365.20486
- Similarity Product: 293.3298467000103

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test