PATENT CLAIM ANALYSIS

Application Number: 16107942
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["438", "014000"]

Abstract:
A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

Claim (Index 6):
The system of  claim 1 , wherein the memory further stores instructions that, when executed by the processor, cause the processor to classify the reconstructed wafer map with one of a plurality of labels using a classifier, and\n wherein the classifier is trained using:\n a training set of ground truth wafer maps; and \n a plurality of labels of the training set of ground truth wafer maps, the plurality of labels being computed by applying an anomaly detection technique to the training set of ground truth wafer maps to identify one or more classes of wafers, the classes of wafers comprising anomalous wafers and non-anomalous wafers.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 96.0
- Lexical Diversity: 1.62745
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15943392', '15886873', '16104449', '15882770', '15966375']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8600072635114745
- 35 USC 102 Novelty (BERT): 0.4902302331866884
- Combined Prediction Score: 0.8230295604789959
- Mean Citation Score: 233.289106
- Max Citation Score: 253.72859
- Similarity Product: 210.44025503255423

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test