PATENT CLAIM ANALYSIS

Application Number: 15896404
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["438", "300000"]

Abstract:
A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Claim (Index 20):
The method of  claim 16 , wherein\n a dielectric constant of the second dielectric layer is less than that of the first dielectric layer, and a dielectric constant of the third dielectric layer is less than that of the first dielectric layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 88.0
- Lexical Diversity: 1.78261
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15299864', '14492595', '11583500', '15274087', '15354212']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8543496444393716
- 35 USC 102 Novelty (BERT): 0.528714878239942
- Combined Prediction Score: 0.8217861678194286
- Mean Citation Score: 252.74455200000003
- Max Citation Score: 320.2966
- Similarity Product: 228.685658950758

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test