PATENT CLAIM ANALYSIS

Application Number: 15977949
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-06
Patent Classification: ["257", "365000"]

Abstract:
A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

Claim (Index 11):
The field effect transistor of  claim 9 , wherein the length of the portion of the dielectric separation is from approximately 0 nm to approximately 6 nm.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.4
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15818657', '15458655', '15683304', '15485188', '14829797']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92121816492623
- 35 USC 102 Novelty (BERT): 0.5404264772485129
- Combined Prediction Score: 0.8831389961584584
- Mean Citation Score: 300.9669780000001
- Max Citation Score: 366.33676
- Similarity Product: 258.6516030643177

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test