PATENT CLAIM ANALYSIS

Application Number: 15879457
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "774000"]

Abstract:
A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

Claim (Index 11):
A stacked via structure, comprising:\n a first dielectric layer comprising a first via opening; a first conductive via in the first via opening, a first level height offset being between a top surface of the first conductive via and a top surface of the first dielectric layer; a first patterned seed layer covering the first conductive via and a portion of the first dielectric layer; a first redistribution wiring disposed on first patterned seed layer; a second dielectric layer disposed on the first dielectric layer and the first redistribution wiring, the second dielectric layer comprising a second via opening; a second conductive via in the second via opening, the second conductive via being electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer, and a second level height offset being between a top surface of the second conductive vias and a top surface of the second dielectric layer; a second patterned seed layer covering the second conductive via and a portion of the second dielectric layer; and a second redistribution wiring disposed on the second patterned seed layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 4.37838
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15164888', '15795281', '15281086', '15215594', '15257920']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912383591845576
- 35 USC 102 Novelty (BERT): 0.4839955740692692
- Combined Prediction Score: 0.8695447900679453
- Mean Citation Score: 190.244746
- Max Citation Score: 198.61655
- Similarity Product: 143.7736589309454

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test