PATENT CLAIM ANALYSIS

Application Number: 16123266
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["327", "333000"]

Abstract:
According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.

Claim (Index 1):
A level shift circuit comprising:\n a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output; a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain; a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain; a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain; a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain; a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and a potential adjusting circuit that is electrically connected to at least the second node.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 3.70732
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15694556', '11199017', '12877748', '14633027', '11044030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.759923164044489
- 35 USC 102 Novelty (BERT): 0.4531252250522721
- Combined Prediction Score: 0.7292433701452673
- Mean Citation Score: 169.919638
- Max Citation Score: 179.87349
- Similarity Product: 155.92923484690192

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test