PATENT CLAIM ANALYSIS

Application Number: 15947831
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Claim (Index 17):
A method comprising:\n exchanging data between two or more processors over a first interconnect; exchanging data between one or more of the processors and one or more system components over a second interconnect; executing instructions and processing data with a plurality of cores of a first processor, the plurality of cores comprising symmetric multi-threaded cores; storing the instructions and the data in a cache subsystem, the cache subsystem comprising a plurality of first level caches and at least one higher level cache, each first level cache integral to one of the plurality of cores and the higher level cache subdivided into a plurality of cache portions, each cache portion physically proximate to a predetermined subset of the plurality of cores and accessible to each of the plurality of cores; sharing the higher level cache by the plurality of cores; providing coherent, non-uniform access to the plurality of cache portions by the plurality of cores based, at least in part, on relative physical proximity between each cache portion and each of the plurality of cores; setting a first frequency for a first subset of the plurality of cores and a second frequency for a second subset of the plurality of cores in accordance with a detected workload on the first and second subsets of the plurality of cores, respectively; and selectively gating power in accordance with the detected workload.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.08
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13729579', '14498353', '15370904', '13539044', '15602603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5136565338320832
- 35 USC 102 Novelty (BERT): 0.4911321774323761
- Combined Prediction Score: 0.5114040981921125
- Mean Citation Score: 201.898608
- Max Citation Score: 253.76993
- Similarity Product: 201.5688099964261

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test