PATENT CLAIM ANALYSIS

Application Number: 16162480
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["345", "100000"]

Abstract:
A pulse is inputted to TFTs  101  and  104  so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT  105  then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT  105  further rises due to an operation of capacitance  107  as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT  105.

Claim (Index 5):
The semiconductor device according to  claim 2 , wherein the other of the source and the drain of the fifth transistor is electrically connected to the third line.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.13636
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14816124', '15343373', '14332468', '15802524', '13604709']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.772269689791926
- 35 USC 102 Novelty (BERT): 0.5961654395951174
- Combined Prediction Score: 0.7546592647722452
- Mean Citation Score: 488.126016
- Max Citation Score: 489.8225
- Similarity Product: 447.5511318351328

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test