PATENT CLAIM ANALYSIS

Application Number: 16026081
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["323", "280000"]

Abstract:
A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V fb . The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor M P  is connected to the output terminal of the error amplifier, the source terminal of the power transistor M P  is connected to an input voltage V IN , and the drain terminal of the power transistor M P  is grounded.

Claim (Index 8):
The ripple pre-amplification based fully integrated low dropout regulator according to  claim 7 , wherein\n the compensation circuit comprises a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a capacitance; wherein a drain terminal of the twelfth PMOS transistor and a drain terminal of the sixteenth NMOS transistor are connected to each other and connected to the series connection point of the first voltage dividing resistor and the second voltage dividing resistor; the eleventh PMOS transistor and the twelfth PMOS transistor constitute a third current mirror and a third mirror ratio is 1:K 4 ; a gate terminal and a drain terminal of the eleventh PMOS transistor are short-circuited and connected to a gate terminal of the twelfth PMOS transistor and a drain terminal of the fifteenth NMOS transistor; a gate terminal and a drain terminal of the fourteenth NMOS transistor are short-circuited and connected to a drain terminal of the thirteenth PMOS transistor and a gate terminal of the fifteenth NMOS transistor; the capacitance is connected between a drain terminal of the power transistor and a drain terminal of the fourteenth NMOS transistor; a gate terminal of the thirteenth PMOS transistor and a gate terminal of the sixteenth NMOS transistor are connected to the bias voltage; source terminals of the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor are connected to the input voltage; and source terminals of the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor are connected to the ground.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 95.0
- Lexical Diversity: 3.41667
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15690290', '15387678', '15509202', '15776780', '11775105']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.796972560688529
- 35 USC 102 Novelty (BERT): 0.5622484830708391
- Combined Prediction Score: 0.77350015292676
- Mean Citation Score: 378.515386
- Max Citation Score: 461.67987
- Similarity Product: 386.7714661717021

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test