PATENT CLAIM ANALYSIS

Application Number: 16041455
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "130000"]

Abstract:
Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.

Claim (Index 14):
The device of  claim 13 , wherein a first plate line of the first plurality of plate lines is coupled with the third plate line through a first on pitch via (OPV).

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.84706
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15469865', '15434395', '15434401', '15969302', '15690895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8264272888624029
- 35 USC 102 Novelty (BERT): 0.5319516390818972
- Combined Prediction Score: 0.7969797238843523
- Mean Citation Score: 257.87404000000004
- Max Citation Score: 379.70767
- Similarity Product: 230.832811261226

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test