PATENT CLAIM ANALYSIS

Application Number: 15935274
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["713", "501000"]

Abstract:
In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Claim (Index 8):
An apparatus comprising:\n a plurality of processor cores corresponding to a processor, wherein the processor is an entity to which an operating system assigns code to execute and for which the operating system selects a processor state by programming a processor state register, wherein each of a plurality of processor states supported by the processor is mapped to one of the plurality of processor cores, wherein:\n the processor implements an instruction set architecture; \n the instruction set architecture specifies a plurality of operand sizes for a first operand type; \n a first processor core of the plurality of processor cores implements only a first operand size of the plurality of operand sizes, wherein a first instruction is executable by the first processor core in the event that the first instruction uses the first operand size and the first instruction is not executable by the first processor core in the event that the first instruction uses a different operand size of the plurality of operand sizes; \n a second processor core of the plurality of processor cores implements the plurality of operand sizes, wherein the first instruction is executable by the second processor core with any of the plurality of operand sizes; and \n at most one of the plurality of processor cores is active at a given point in time, except during a context switch between two of the plurality of processor cores; and \n a processor power manager coupled to the plurality of processor cores, wherein the processor power manager is configured to:\n detect that the processor power manager has been programmed to change a current processor state mapped to the second processor core to a requested processor state mapped to the first processor core during a time that code is being executed by the second processor core; \n cause the change to the requested power state and a transfer of a processor context from the second processor core to the first processor core in response to being programmed to change from the current processor state to the requested processor state, wherein the first processor core is configured to continue execution of the code responsive to the transfer; and \n cause a transfer of the processor context back to the second processor core responsive to detecting use of an operand size different from the first operand size by an instruction within the code, and cause a change of the processor state from the requested processor state to a third processor state supported by the second processor core.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.02703
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14548912', '15866014', '14548872', '14844212', '12356761']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4533774453465228
- 35 USC 102 Novelty (BERT): 0.5591529294936171
- Combined Prediction Score: 0.4639549937612323
- Mean Citation Score: 346.589924
- Max Citation Score: 438.4663
- Similarity Product: 381.8394866758764

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test