PATENT CLAIM ANALYSIS

Application Number: 15954665
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["714", "718000"]

Abstract:
A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode. Logic BIST circuits complete a test with the LBIST mode, at a stage where the second scan test has completed.

Claim (Index 9):
The semiconductor device according to  claim 8 ,\n wherein the memory circuit, the first scan flip flop circuit for bypass, and the first selection circuit are configured with a hard macro.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.75
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11603085', '15220427', '11626574', '10086214', '14072295']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3067065705265295
- 35 USC 102 Novelty (BERT): 0.5084038228145543
- Combined Prediction Score: 0.326876295755332
- Mean Citation Score: 261.310006
- Max Citation Score: 279.22342000000003
- Similarity Product: 209.80253452819943

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test