PATENT CLAIM ANALYSIS

Application Number: 15867943
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["327", "199000"]

Abstract:
A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Claim (Index 7):
The circuit of  claim 2  wherein the charging state rate control circuit includes an inverter including a first input for receiving a clock signal, an output coupled to the capacitor, and a second input coupled to a first circuit having an input to receive a signal indicative of a desired delay between the input clock signal and the output clock signal.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.55556
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14175220', '10176852', '12062426', '09991198', '12455572']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8042632433405417
- 35 USC 102 Novelty (BERT): 0.4560027469795809
- Combined Prediction Score: 0.7694371937044456
- Mean Citation Score: 175.803684
- Max Citation Score: 179.73253
- Similarity Product: 152.8530229129839

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test