PATENT CLAIM ANALYSIS

Application Number: 15860786
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["365", "063000"]

Abstract:
A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

Claim (Index 12):
A non-volatile memory, comprising:\n a first word line; a second word line; a first auxiliary line; a second auxiliary line; a first control line; a first erase line; a first bit line; a first source line; and a first memory cell comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor, wherein the first transistor comprises a first gate, a first terminal and a second terminal, the second transistor includes a second gate, a third terminal and a fourth terminal, the third transistor comprises a third gate, a fifth terminal and a sixth terminal, the fourth transistor comprises a fourth gate, a seventh terminal and an eighth terminal, the fifth transistor comprises a fifth gate, a ninth terminal and a tenth terminal, the first capacitor is connected between the third gate and the control line, and the second capacitor is connected with the third gate and the first erase line; wherein the third gate is a floating gate, the second terminal is connected with the third terminal, the fourth terminal is connected with the fifth terminal, the sixth terminal is connected with the seventh terminal, the eighth terminal is connected with the ninth terminal, the first terminal is connected with the first bit line, the tenth terminal is connected with the first source line, the first gate is connected with the first word line, the second gate is connected with the first auxiliary line, the fourth gate is connected with the second auxiliary line, and the fifth gate is connected with the second word line.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 86.0
- Lexical Diversity: 4.65714
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15151013', '15257359', '14471613', '15481889', '15257292']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8185580163114476
- 35 USC 102 Novelty (BERT): 0.4976774315243359
- Combined Prediction Score: 0.7864699578327365
- Mean Citation Score: 290.654716
- Max Citation Score: 299.1154
- Similarity Product: 250.0157854907752

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test