PATENT CLAIM ANALYSIS

Application Number: 16120249
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2018-12
Patent Classification: ["717", "154000"]

Abstract:
Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The compiled code is then executed on the processor hardware, which detects memory aliasing at run-time and assures proper operation of the code even when memory aliasing occurs.

Claim (Index 13):
The method of  claim 10  wherein the load/store unit detects when a younger special store instruction is executed ahead of a load instruction targeting the address of the special store instruction, and in response, flushes instructions in an instruction pipeline of the processor including the load instruction and instructions after the load instruction.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 97.0
- Lexical Diversity: 1.8125
- Patent Class: 717.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15169739', '15169736', '15169743', '15826609', '15169737']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5043005950888242
- 35 USC 102 Novelty (BERT): 0.5617278710918575
- Combined Prediction Score: 0.5100433226891276
- Mean Citation Score: 402.308332
- Max Citation Score: 419.57257
- Similarity Product: 328.9063232101888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test