PATENT CLAIM ANALYSIS

Application Number: 15938258
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "401000"]

Abstract:
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

Claim (Index 10):
The semiconductor structure of  claim 1 , wherein the deep via is formed over at least one via of the plurality of vias.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 90.0
- Lexical Diversity: 1.65306
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12216678', '15479633', '15269294', '15213506', '14963235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9148426957540764
- 35 USC 102 Novelty (BERT): 0.4530772067182953
- Combined Prediction Score: 0.8686661468504983
- Mean Citation Score: 133.71507000000005
- Max Citation Score: 135.53804
- Similarity Product: 109.78753348555088

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test