PATENT CLAIM ANALYSIS

Application Number: 16018379
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["438", "157000"]

Abstract:
Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.

Claim (Index 6):
The method of  claim 5  further comprising forming a top spacer over the partially recessed conductive gate.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 94.0
- Lexical Diversity: 2.68293
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15479567', '15596634', '15905891', '15905885', '15813528']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8757264302520278
- 35 USC 102 Novelty (BERT): 0.4951343697052597
- Combined Prediction Score: 0.8376672241973511
- Mean Citation Score: 256.45428400000003
- Max Citation Score: 291.0766
- Similarity Product: 287.91079887094486

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test