PATENT CLAIM ANALYSIS

Application Number: 15896783
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["398", "115000"]

Abstract:
A PON having an OLT configured to send downlink transmissions to ONUs using amplitude modulation and two symbol rates. An example ONU includes a clock-recovery circuit capable of continuous clock extraction from the received variable-rate modulated optical signal. The continuous clock extraction can be achieved, e.g., by (i) configuring the photodetector to convert the higher-rate portions of the received optical signal into transformed electrical waveforms while converting the lower-rate portions thereof into similar electrical waveforms and (ii) configuring the clock-recovery circuit to phase-align the clock signal with signal transitions in the resulting sequence of transformed and similar electrical waveforms. An ONU configured to operate in this manner can advantageously stay locked to the received data signal during transmissions at both symbol rates, without the need to reacquire the clock signal at each rate change and/or at the beginning of each packet intended for the host ONU.

Claim (Index 10):
An apparatus comprising an optical receiver configured to receive an optical input signal modulated with data, wherein the optical receiver comprises:\n an optical-to-electrical converter configured to:\n generate a non-return-to-zero (NRZ)-modulated electrical signal in response to a first NRZ-modulated portion of the optical input signal, the first NRZ-modulated portion having a first symbol rate that is a rate of a clock; and \n generate a duobinary electrical signal in response to a second NRZ-modulated portion of the optical input signal, the second NRZ-modulated portion having a second symbol rate that is greater than the first symbol rate; and \n a clock-recovery circuit configured to generate a first clock signal in response to said NRZ-modulated electrical signal such that said first clock signal frequency locks to the rate of the clock, and to continue to generate said first clock signal in response to said duobinary electrical signal such that said first clock signal continues to frequency lock to the rate of the clock.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 88.0
- Lexical Diversity: 1.72527
- Patent Class: 398.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14329119', '09793954', '10185407', '10730413', '11176333']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7022515191425709
- 35 USC 102 Novelty (BERT): 0.4978777030433915
- Combined Prediction Score: 0.681814137532653
- Mean Citation Score: 226.597388
- Max Citation Score: 232.92899
- Similarity Product: 195.1358628562188

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test