PATENT CLAIM ANALYSIS

Application Number: 15960406
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "194000"]

Abstract:
A circuit is disclosed that includes an inverter unit and a switch unit. The inverter unit is coupled to a memory cell column. The inverter unit is configured to invert, in response to a first control signal and a second control signal, a first signal and to output a second signal for the enabling or disabling of a bit line keeper circuit that is configured to maintain a bit line to a voltage. The first signal is generated by the memory cell column. The switch unit is configured to couple a reference voltage to an input of the inverter unit, in response to a third control signal. The inverter unit is further configured to be deactivated in response to the reference voltage, the first control signal, and the second control signal.

Claim (Index 17):
The device of  claim 16 , wherein the compensation circuit further comprises:\n a first inverter having an input coupled to first terminals of the second transistor and the third transistor; a sixth transistor and a seventh transistor; an eighth transistor and a ninth transistor cascaded with the sixth transistor and the seventh transistor, a control terminal of the sixth transistor is configured to receive the third control signal, control terminals of the seventh transistor and the eighth transistor are coupled to an output of the first inverter, and a control terminal of the ninth transistor is configured to receive the first control signal; a flip-flop having an input coupled to the first terminals of the second transistor and the third transistor; and a second inverter having an input coupled to an output of the flip-flop, and an output coupled to a control terminal of the switch.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.89796
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12797852', '13006487', '14989753', '15586011', '14498412']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7967183756259983
- 35 USC 102 Novelty (BERT): 0.4740943825145575
- Combined Prediction Score: 0.7644559763148543
- Mean Citation Score: 157.458536
- Max Citation Score: 164.73686
- Similarity Product: 114.42093799613475

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test