PATENT CLAIM ANALYSIS

Application Number: 15972345
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-02
Patent Classification: ["717", "161000"]

Abstract:
Logic may transform a target code to partition data automatically and/or autonomously based on a memory constraint associated with a resource such as a target device. Logic may identify a tag in the code to identify a task, wherein the task comprises at least one loop, the loop to process data elements in one or more arrays. Logic may automatically generate instructions to determine one or more partitions for the at least one loop to partition data elements, accessed by one or more memory access instructions for the one or more arrays within the at least one loop, based on a memory constraint, the memory constraint to identify an amount of memory available for allocation to process the task. Logic may determine one or more iteration space blocks for the parallel loops, determine memory windows for each block, copy data into and out of constrained memory, and transform array accesses.

Claim (Index 5):
The apparatus of  claim 1 , wherein the logic circuitry is configured to insert instructions to call a runtime library to calculate an iteration space block for the at least one loop.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.34783
- Patent Class: 717.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14667819', '11784792', '12978465', '14497157', '14200788']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3827254159185875
- 35 USC 102 Novelty (BERT): 0.4938227827161791
- Combined Prediction Score: 0.3938351525983466
- Mean Citation Score: 154.56942399999997
- Max Citation Score: 169.34771999999995
- Similarity Product: 118.24762011614796

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test