PATENT CLAIM ANALYSIS

Application Number: 15741742
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["377", "064000"]

Abstract:
The present application discloses a shift, register circuit having a plurality of shift register units cascaded in series. The shift register circuit includes a first shift register unit and a second shift register unit. The first shift register unit includes a first pull-up node and a first output terminal and the second shift register unit includes a second pull-up node and a second output terminal. The shift register circuit includes a stabilizer circuit coupled to both the first shift register unit and the second shift register unit such that the first pull-up node is directly connected to the second pull-up node as a common pull-up node and configured to maintain a potential level of the common pull-up node stable during a stabilizing period when none of the first output terminal and the second output terminal output a turn-on signal.

Claim (Index 4):
The shift register circuit of  claim 3 , wherein the first shift register unit comprises:\n a precharge sub-circuit and a first output sub-circuit respectively coupled to the common pull-up node, wherein the precharge sub-circuit is configured to receive a first input signal and a high-voltage VDD signal, to pull up the potential level of the common pull-up node to high by setting the first input signal as a high-voltage signal, and to pull down the potential level of the shared pull-down node to that of the low-voltage signal when the potential level of the common pull-up node becomes high, wherein the first output sub-circuit includes a capacitor and a transistor configured to receive a first clock signal and controlled by the potential level of the common pull-up node and the first clock signal to output a high-voltage signal to the first output terminal; the second shift register unit comprises: a reset sub-circuit and a second output sub-circuit respectively coupled to the common pull-up node, wherein reset sub-circuit includes a transistor configured to receive a reset signal and a low-voltage VSS signal and controlled by a high-voltage signal set for the reset signal to pull down the potential level of the common pull-up node to low, wherein the second output sub-circuit includes a capacitor and a transistor configured to receive a second clock signal and controlled by the potential level of the common pull-up node and the second clock signal to output a high-voltage signal to the second output terminal.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 86.0
- Lexical Diversity: 2.88
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15752518', '15520557', '15529731', '15506398', '15327852']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7717870229915207
- 35 USC 102 Novelty (BERT): 0.4999670387656028
- Combined Prediction Score: 0.744605024568929
- Mean Citation Score: 333.4888660000001
- Max Citation Score: 342.74957
- Similarity Product: 275.7179575968051

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test