PATENT CLAIM ANALYSIS

Application Number: 16160051
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["345", "501000"]

Abstract:
A system and method to interconnect heterogeneous compute resources using graph based execution flow for image and video processing is disclosed. The system includes a mix of compute engines (SIMDs, fixed-function pipelines and hardware kernels) which work on pipelined streams of data based on programming instructions and/or configuration data. The nodes act as proxies for compute engines in graph and message based routing system to establish graph based flow control mechanism between these nodes. A message based routing mechanism to assign tasks to heterogeneous compute engines and receive their status in time-multiplexed manner thus allowing compute engines to be reused. A configuration method that allows hardware compute engines are uniquely configured based on graph node thus allows reusability and programming or selecting heterogeneous compute system for physical implementation using simple standard definition file generation method.

Claim (Index 1):
A system to interconnect heterogeneous compute resources using graph based execution flow for image and video processing, comprising:\n a. plurality of main processor units ( 11 ) to implement system bring up, configuration of the entire system, main operating system software execution, application software and overall control of the system; b. plurality of main memory units ( 12 ) to hold data for various processing and peripheral blocks; c. plurality of peripheral input/output units ( 13 ) to implement input/output functions; d. plurality of camera units ( 14 ) to acquire visual images and videos based on application requirement; e. an internal memory ( 15 ) to store data, configuration information and instructions for compute engines temporarily; f. a subsystem fabric ( 16 ) to provide communication between various units in the system; and g. a heterogeneous parallel processing system ( 20 ) to execute the data based on the data flow pipeline set by the main processor ( 11 ); wherein,\n a group of physical nodes( 50 ) to act as proxies for a group of compute engine functionalities and arranging them in a pipelines data processing flow, wherein\n i. a virtual pipeline topology is established by configuring participating nodes, using messages sent over a broadcast channel by participating nodes and appropriately filtering and processing messages by receiving nodes; \n ii. a node configuration procedure to associate a particular compute engine functionality to the node; and \n iii. a participating node to accept multiple input nodes and multiple output nodes, to create complex graphs. \n \n a group of compute engines ( 25 ) to honor the compute requests from said proxy nodes, complete execution and provide status back to said proxy node, wherein\n i. nodes ( 50 ) to associate with a compute engine ( 25 ) that implements single/multiple functions to act as a proxy; \n ii. single/multiple functions for said compute engines ( 25 ) to serve said proxy nodes in a time multiplexed manner through arbitration and message exchanges; \n iii. arbitrating a pool of homogeneous compute engines ( 25 ) with same functionality identification number to avail an instance of the functionality to said proxy node; and \n iv. said compute engine ( 25 ) gather configuration settings, parameters, instructions and data required to complete all compute operations requested based on the identity of said proxy node requesting the compute operations. \n \n a group of direct memory access engines and processor direct memory access units( 26 ) to get attached to certain participating nodes and move data between main memory ( 12 ) and internal memory ( 15 ), wherein\n i. a main processor ( 11 ) to configure processor direct memory access ( 26 ) to be part of a graph pipeline by attaching it to one of the nodes ( 50 ) in the pipeline; \n ii. processor direct memory access ( 26 ) to send and receive data flow messages so as to sequence data in a pipelined manner; \n iii. processor direct memory access ( 26 ) to communicate with data movers to initiate data transfers; and \n iv. processor direct memory access ( 26 ) to handshake with said main processor ( 11 ) during end of complete data to keep said main processor ( 11 ) informed about the status of the pipeline and take appropriate actions.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 1.70238
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14664725', '14664743', '14664736', '15450959', '15996300']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6284004010012108
- 35 USC 102 Novelty (BERT): 0.4853336775548186
- Combined Prediction Score: 0.6140937286565716
- Mean Citation Score: 184.317812
- Max Citation Score: 194.1963
- Similarity Product: 138.437272329247

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test