PATENT CLAIM ANALYSIS

Application Number: 16109656
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["327", "299000"]

Abstract:
A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.

Claim (Index 2):
The quadrature clock generation circuit of  claim 1 , wherein the I/Q correction circuit further comprises:\n a first injector buffer with an input connected to the first in-phase input and a first injector buffer output connected to the first in-phase output; and a second injector buffer with an input connected to the first quadrature input and a second injector buffer output connected to the first quadrature output.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 96.0
- Lexical Diversity: 3.0625
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12492419', '15788617', '09747163', '15932298', '11392966']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7922180887383805
- 35 USC 102 Novelty (BERT): 0.4809710504376402
- Combined Prediction Score: 0.7610933849083066
- Mean Citation Score: 214.274754
- Max Citation Score: 223.43446
- Similarity Product: 176.4778962523985

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test