PATENT CLAIM ANALYSIS

Application Number: 16266604
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-10
Patent Classification: ["326", "038000"]

Abstract:
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Claim (Index 11):
The multi-chip system of  claim 1 , further comprising:\n a substrate including a routing layer, and a high density bridge within the routing layer; wherein the first chip is mounted on the routing layer, the interfacing bar is mounted on the routing layer, and the first chip and the interfacing bar are electrically coupled with the high density bridge within the routing layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 99.0
- Lexical Diversity: 1.52941
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14040223', '13646477', '14977645', '15499557', '15816360']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6365660851138891
- 35 USC 102 Novelty (BERT): 0.4529586140595928
- Combined Prediction Score: 0.6182053380084596
- Mean Citation Score: 122.76851000000002
- Max Citation Score: 142.67065
- Similarity Product: 112.1338944434762

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test