PATENT CLAIM ANALYSIS

Application Number: 16056874
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["365", "145000"]

Abstract:
A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL 1 ), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL 2 ), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL 1 , WL 2 , the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

Claim (Index 38):
The method of  claim 36 , further comprising coupling the BL to a bit-line pre-charge circuit and pre-charging the BL to a predetermined voltage prior to discharging the SN.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 96.0
- Lexical Diversity: 2.33333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15714912', '10847412', '11756466', '10805809', '10866834']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7970297329201893
- 35 USC 102 Novelty (BERT): 0.5766343029726697
- Combined Prediction Score: 0.7749901899254373
- Mean Citation Score: 301.0830239999999
- Max Citation Score: 537.24786
- Similarity Product: 395.0100780269765

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test