PATENT CLAIM ANALYSIS

Application Number: 15969234
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "777000"]

Abstract:
The present invention ultra-low loss high energy density dielectric layers having femtosecond (10 −15  sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.

Claim (Index 1):
A high-speed semiconductor chip stack forming an electrical circuit comprising one or more physical layers of perovskite electroceramic that functions as a capacitive dielectric material and said one or more physical layers are integrated as part of at least one surface feature on a semiconductor die or an interposer embedded within the high speed semiconductor chip stack wherein the perovskite electroceramic forming said capacitive dielectric material further comprises a uniform distribution of ceramic grains with a grain size diameter less than 50 nm such that orbital deformations constitute the sole mechanism contributing to the dielectric polarization within said capacitive dielectric material.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 1.35417
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15958706', '15881164', '11479159', '14268082', '13216192']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9104879817971604
- 35 USC 102 Novelty (BERT): 0.4936451796773678
- Combined Prediction Score: 0.868803701585181
- Mean Citation Score: 181.370446
- Max Citation Score: 212.47585
- Similarity Product: 143.94232208601534

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test