PATENT CLAIM ANALYSIS

Application Number: 16141285
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["712", "215000"]

Abstract:
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Claim (Index 4):
The circuit arrangement of  claim 3 , wherein the first issue logic circuit includes an age data structure that identifies an oldest instruction queued by the first issue logic circuit, wherein the first issue logic circuit is configured to update the age data structure in connection with queuing each instruction dispatched to the first execution slice, and to access the age data structure to determine that the multi-width instruction is the oldest instruction queued by the first issue logic circuit.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 1.5
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15939367', '15093192', '14595549', '16048946', '15093172']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6565613469827042
- 35 USC 102 Novelty (BERT): 0.5636393321869962
- Combined Prediction Score: 0.6472691455031334
- Mean Citation Score: 354.655344
- Max Citation Score: 439.212
- Similarity Product: 438.3764424555303

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test