PATENT CLAIM ANALYSIS

Application Number: 16106105
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["257", "072000"]

Abstract:
The present application provides an array substrate and a method of manufacturing the same. The array substrate includes a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer.

Claim (Index 7):
The array substrate of  claim 1 , wherein the array substrate is a bottom-gate type array substrate or a top-gate type array substrate.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 96.0
- Lexical Diversity: 2.8125
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15576837', '15807451', '14134058', '14769891', '14017692']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9274470171153912
- 35 USC 102 Novelty (BERT): 0.4982097674941523
- Combined Prediction Score: 0.8845232921532674
- Mean Citation Score: 238.536898
- Max Citation Score: 248.93567
- Similarity Product: 185.3484335351992

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test