PATENT CLAIM ANALYSIS

Application Number: 15987238
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["716", "052000"]

Abstract:
A method for determining whether to order a mask structure using a processor may include acquiring a simulation result of an EUV pattern layout, determining a correlation parameter (CP), generating a predicted wafer process window, and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window. The processor may determine the CP based on a weighting value and a simulated depth of focus (DOF), a simulated energy latitude (EL), and simulated line-LER area and LER-width parameters in the simulation result. The CP may indicate a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout. The predicted wafer process window may be generated using the processor based on the CP. The predicted wafer process window may indicate whether the actual wafer result of the EUV pattern layout will include a patterning defect.

Claim (Index 14):
The method of  claim 1 , further comprising:\n forming a revised EUV pattern layout by adjusting a feature in the EUV pattern layout in response to a value of the of the CP being greater than a desired value; acquiring a revised simulation result of the revised EUV pattern layout,\n the revised simulation result including a revised simulated DOF, a revised simulated EL, a revised simulated LER area parameter that is less than or equal to the first threshold, a revised simulated LER width parameter that is less than or equal to the second threshold, and a revised weighting value; \n determining a revised CP using the processor based on the revised simulated DOF, the revised simulated EL, the revised simulated LER area parameter, the revised simulated LER width parameter, and the revised weighting value,\n the revised CP indicating a correlation between the revised simulation result of the revised EUV pattern layout and an actual wafer result of the revised EUV pattern layout; \n generating a revised predicted wafer process window based on the revised CP, the revised predicted wafer process window indicating whether the actual wafer result of the revised EUV pattern layout will include the patterning defect; and determining the mask structure is suitable for ordering based on the revised CP and the revised predicted wafer process window.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.55385
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13802257', '09906920', '14013593', '15116486', '14051640']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2917794922319022
- 35 USC 102 Novelty (BERT): 0.4764686298388577
- Combined Prediction Score: 0.3102484059925977
- Mean Citation Score: 186.873686
- Max Citation Score: 194.49612
- Similarity Product: 133.68392387267588

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test