PATENT CLAIM ANALYSIS

Application Number: 16435663
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["365", "154000"]

Abstract:
A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

Claim (Index 3):
The device of  claim 2 , wherein the plurality of bit cell transistors and the plurality of write assist circuits are each fabricated using common design rules for static random access memory (SRAM) transistors.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.22917
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16021172', '13726800', '13105382', '13149611', '14740186']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8154614629483224
- 35 USC 102 Novelty (BERT): 0.552542457555298
- Combined Prediction Score: 0.78916956240902
- Mean Citation Score: 268.93573
- Max Citation Score: 442.51065
- Similarity Product: 351.27291782476897

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test