PATENT CLAIM ANALYSIS

Application Number: 16027542
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["323", "299000"]

Abstract:
In some embodiments, a startup current limiter comprises a first comparator, a second comparator, on time circuitry coupled to an output of the second comparator, and a first logic structure coupled to the output of the second comparator and an output of the on time circuitry. In some embodiments, the startup current limiter further comprises sequencing logic coupled to an output of the first comparator, a latch coupled to an output of the first comparator at a set terminal of the latch and an output of the second comparator at a reset terminal of the latch, off time circuitry coupled to an output terminal of the latch, a second logic structure coupled to the latch and the off time circuitry, and a gate driver coupled to the second logic structure and an output of the sequencing logic.

Claim (Index 10):
An apparatus, comprising:\n a power stage operable to receive an input signal at a first voltage value and output an output signal at a second voltage value greater than the first voltage value; and a startup current limiter coupled to the power stage, comprising:\n a first comparator; \n a second comparator; \n on time circuitry coupled to an output of the second comparator; \n a first logic structure coupled to the output of the second comparator and an output of the on time circuitry; \n sequencing logic coupled to an output of the first comparator; \n a latch coupled to an output of the first comparator at a set terminal of the latch and an output of the first logic structure at a reset terminal of the latch; \n off time circuitry coupled to an output terminal of the latch; \n a second logic structure coupled to the latch and the off time circuitry; and \n a gate driver coupled the power stage and comprising:\n a reference generation circuit, comprising:\n a current mirror; \n an adjustable current source coupled to an input transistor of the current mirror; \n a first diode-connected transistor coupled to the input transistor of the current mirror; and \n a second diode-connected transistor coupled to an output transistor of the current mirror; and \n \n a control circuit, comprising:\n a de-multiplexer having a first input coupled to an output of the second logic structure and a second input coupled to an output of the sequencing logic; \n a first inverter coupled to a first output of the de-multiplexer; \n a buffer coupled to a second output of the de-multiplexer; \n a second inverter coupled to an input of the control circuit; \n a first transistor having a first gate terminal coupled to an output of the first inverter; \n a second transistor having a second gate terminal coupled to an output of the buffer; and \n a third transistor having a third gate terminal coupled to an output of the second inverter.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 95.0
- Lexical Diversity: 4.22857
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11294747', '15087342', '13270311', '13010285', '13134762']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7262134701677785
- 35 USC 102 Novelty (BERT): 0.4799346983795616
- Combined Prediction Score: 0.7015855929889568
- Mean Citation Score: 204.04508
- Max Citation Score: 214.61398
- Similarity Product: 163.491738405478

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test