PATENT CLAIM ANALYSIS

Application Number: 16193825
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-07
Patent Classification: ["365", "189150"]

Abstract:
A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

Claim (Index 4):
The memory device of  claim 2 , wherein the voltage regulation circuitry is configured to provide the second signal indicative of the MEDIUM state across the second DRW line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.97872
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15856826', '15824535', '14146613', '15891356', '13617856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7585048097078859
- 35 USC 102 Novelty (BERT): 0.5026812654165559
- Combined Prediction Score: 0.7329224552787529
- Mean Citation Score: 171.41565199999997
- Max Citation Score: 303.8009600000001
- Similarity Product: 302.3695266866304

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test