PATENT CLAIM ANALYSIS

Application Number: 16226628
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "149000"]

Abstract:
A 3D semiconductor device including: a first level including a single crystal layer, a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the single crystal layer and includes interconnects between the first transistors forming control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; and polysilicon pillars, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the third transistors, where at least one of the second memory cells is at least partially atop of the control circuits.

Claim (Index 10):
The 3D semiconductor device according to  claim 8 ,\n wherein said second transistors are aligned to said first transistors with less than 150 nm misalignment.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 98.0
- Lexical Diversity: 3.81395
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15727592', '15351389', '15862616', '15904377', '14506160']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8099627051345545
- 35 USC 102 Novelty (BERT): 0.5373669841997947
- Combined Prediction Score: 0.7827031330410785
- Mean Citation Score: 332.590816
- Max Citation Score: 383.1293
- Similarity Product: 341.45403748508693

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test