PATENT CLAIM ANALYSIS

Application Number: 15978684
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "156000"]

Abstract:
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

Claim (Index 13):
The circuit of  claim 11 , wherein the control circuit comprises:\n a first transistor coupled between a supply node and the control terminal of the pull-down transistor, said supply node configured to receive the supply voltage; and means for modulating a conductivity of said first transistor such that said first transistor is more conductive in response to decrease in the level of said supply voltage and is less conductive in response to increase in the level of said supply voltage.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 1.64
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15375390', '15132680', '13474881', '11191348', '15447853']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.816568871619765
- 35 USC 102 Novelty (BERT): 0.5243156691172222
- Combined Prediction Score: 0.7873435513695107
- Mean Citation Score: 254.928226
- Max Citation Score: 361.21967
- Similarity Product: 301.7625194662548

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test