PATENT CLAIM ANALYSIS

Application Number: 15872840
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["365", "174000"]

Abstract:
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

Claim (Index 4):
The semiconductor device according to  claim 2 , further comprising:\n circuitry to selectively couple each of the first and second I/O circuits to the corresponding first contact or second contact.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 86.0
- Lexical Diversity: 2.72
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14858888', '13502093', '15175933', '13903323', '14741796']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.786822633196956
- 35 USC 102 Novelty (BERT): 0.4755804048084843
- Combined Prediction Score: 0.7556984103581088
- Mean Citation Score: 187.75454800000003
- Max Citation Score: 208.88925
- Similarity Product: 157.58839405238632

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test