PATENT CLAIM ANALYSIS

Application Number: 15950126
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "355000"]

Abstract:
The present application belongs to field of integrated circuit and discloses an electrostatic discharge protection circuit comprising a first N-type transistor and a second N-type transistor. The first N-type transistor comprises a first gate terminal coupled to a ground terminal; a first electrode terminal coupled to the first gate terminal; and a second electrode terminal. The second N-type transistor comprises a second gate terminal coupled to a metal pad; a third electrode terminal coupled to the second gate terminal; a fourth electrode terminal, coupled to the second electrode terminal; and a first deep N well, disposed under the third electrode terminal and the fourth electrode terminal. The ESD protection circuits provided by the embodiments of the present application have advantages of small circuit area and good ESD protection.

Claim (Index 12):
The ESD protection circuit as  claim 1 , further comprising:\n a plurality of diodes, formed as a diode series; wherein an end of the diode series is coupled to the second N-type transistor, the other end of the diode series is configured to receive a supply voltage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.78
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15813179', '10743596', '10826725', '10908988', '11163571']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922871553136086
- 35 USC 102 Novelty (BERT): 0.536205663656506
- Combined Prediction Score: 0.8842049641881281
- Mean Citation Score: 285.68343
- Max Citation Score: 376.52734
- Similarity Product: 325.19289582914826

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test