PATENT CLAIM ANALYSIS

Application Number: 16136589
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["324", "691000"]

Abstract:
Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.

Claim (Index 8):
An electronic package comprising:\n a multilayer circuit board; at least one electronic component associated with the multilayer circuit board; an enclosure mounted to the multilayer circuit board and facilitating defining a secure volume associated with the multilayer circuit board, the at least one electronic component residing within the secure volume; and a tamper-respondent sensor embedded within the multilayer circuit board, the tamper-respondent sensor defining, at least in part, the secure volume associated with the multilayer circuit board, and comprising:\n multiple tamper-respondent layers within the multilayer circuit board, the multiple tamper-respondent layers being spaced apart, parallel layers within the multilayer circuit board that facilitate defining the secure volume, at least in part, within the multilayer circuit board, and the multiple tamper-respondent layers comprising:\n at least one tamper-respondent picture frame-type layer encircling the secure volume within the multilayer circuit board, a tamper-respondent picture frame-type layer of the at least one tamper-respondent picture frame-type layer comprising one or more conductive trace lines extending horizontally around the tamper-respondent picture frame-type layer within the multilayer circuit board and encircling the secure volume within the multilayer circuit board; and \n at least one tamper-respondent mat layer forming a base of the secure volume within the multilayer circuit board, the at least one tamper-respondent picture-frame-type layer being disposed over the at least one tamper-respondent mat layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.44776
- Patent Class: 324.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14865610', '14941908', '15791642', '15053336', '16048650']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6521982696921466
- 35 USC 102 Novelty (BERT): 0.6213293926666332
- Combined Prediction Score: 0.6491113819895952
- Mean Citation Score: 489.461912
- Max Citation Score: 550.6553299999998
- Similarity Product: 506.9165561462252

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test