PATENT CLAIM ANALYSIS

Application Number: 15996385
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["345", "208000"]

Abstract:
A hierarchical gate driver circuit for an array of pixel elements. The hierarchical gate driver circuit includes a shift register and two or more groups of gate lines drivers. The shift register is configured to activate a plurality of select lines based at least in part on a periodic clock signal. A first group of gate line drivers is configured to drive a plurality of first gate lines, each coupled to a respective row of first pixel elements in the array, when a first select line of the plurality of select lines is activated. A second group of gate line drivers is configured to drive a plurality of second gate lines, each coupled to a respective row of second pixel elements in the array, when a second select line of the plurality of select lines is activated.

Claim (Index 7):
The gate driver circuit of  claim 6 , wherein at least one of the driver elements comprises a boosted n-channel metal oxide semiconductor (NMOS) driver or a boosted p-channel metal oxide semiconductor (PMOS) driver.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 94.0
- Lexical Diversity: 2.80769
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13747872', '14988586', '12705235', '13863060', '13661839']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.669048249687982
- 35 USC 102 Novelty (BERT): 0.5105545246914115
- Combined Prediction Score: 0.6531988771883249
- Mean Citation Score: 207.391368
- Max Citation Score: 222.96507000000005
- Similarity Product: 126.15377199137988

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test