PATENT CLAIM ANALYSIS

Application Number: 16009406
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "192000"]

Abstract:
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.

Claim (Index 4):
The method of  claim 3 , further comprising:\n forming, for each of the one or more fin structures, a spacer layer in contact with the source/drain layer and the channel layer.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 94.0
- Lexical Diversity: 2.38
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15334479', '16007263', '15833543', '15075290', '15980250']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9198496999448752
- 35 USC 102 Novelty (BERT): 0.4791828268468939
- Combined Prediction Score: 0.875783012635077
- Mean Citation Score: 224.03810200000004
- Max Citation Score: 230.32607
- Similarity Product: 194.4133205312669

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test