PATENT CLAIM ANALYSIS

Application Number: 16430896
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["365", "203000"]

Abstract:
Integrated circuit devices include a first node, a second node, a transistor connected between the first node and the second node, a current path between a control gate of the transistor and the second node, and a controller configured to concurrently discharge a voltage level of the first node and a voltage level of the second node, monitor a representation of a voltage difference between the voltage level of the first node and a voltage level of the control gate of the transistor while discharging the voltage level of the first node and discharging the voltage level of the second node, activate the current path if the voltage difference is deemed to be greater than a first value, and deactivate the current path if the voltage difference is deemed to be less than a second value.

Claim (Index 14):
An integrated circuit device, comprising:\n a first node; a second node selectively connected to the first node through a transistor; a first comparator having a first input capacitively coupled to the first node, a second input capacitively coupled to a control gate of the transistor, and an output; a second comparator having a first input capacitively coupled to the control gate of the transistor, a second input capacitively coupled to the first node, and an output; a first voltage node connected to the first input of the first comparator, and capacitively coupled to a first reference node; a second voltage node connected to the second input of the second comparator, and capacitively coupled to a second reference node; a third voltage node connected to the second input of the first comparator, and capacitively coupled to a third reference node; a fourth voltage node connected to the first input of the second comparator, and capacitively coupled to a fourth reference node; a fifth voltage node selectively connected to the first voltage node and configured to receive a first reference voltage; a sixth voltage node selectively connected to the second voltage node and configured to receive a second reference voltage; a logic having a first input connected to the output of the first comparator and a second input connected to the output of the second comparator, and having an output configured to provide a first logic level when the output of the first comparator indicates that a voltage level of its second input is greater than a voltage level of its first input, and to provide a second logic level, different from the first logic level, when the output of the second comparator indicates that a voltage level of its first input is less than a voltage level of its second input; and a current path between the second node and the control gate of the transistor, wherein the current path is configured to be activated in response to the output of the logic having the first logic level, and to be deactivated in response to the output of the logic having the second logic level.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 100.0
- Lexical Diversity: 3.42857
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15866982', '15693133', '16222160', '11768508', '15248692']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8020683185952258
- 35 USC 102 Novelty (BERT): 0.4913987873459261
- Combined Prediction Score: 0.7710013654702957
- Mean Citation Score: 204.040506
- Max Citation Score: 283.23483
- Similarity Product: 253.8725332845229

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test