PATENT CLAIM ANALYSIS

Application Number: 15963598
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-09
Patent Classification: ["257", "345000"]

Abstract:
A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element

Claim (Index 1):
A semiconductor integrated circuit having a plurality of transistor devices fabricated on a substrate surface to support a plurality of threshold voltages, the transistor devices each having a gate with a source and a drain on either side of the gate, comprising:\n a first transistor device region having a first screening region with a first preselected doping concentration and first thickness and set to be a first predefined depth below the substrate surface; a second transistor device region having a second screening region with a second doping concentration and second thickness and second depth, wherein the second thickness and second depth are substantially similar to the first screening region but the second doping concentration is higher than the first doping concentration; and a third transistor device region having a third screening region with a third doping concentration and third thickness and third depth, wherein the third thickness and third depth are substantially similar to the second screening region but the third doping concentration is higher than the second doping concentration; wherein each of the first, second, and third transistor device regions are covered by a substantially undoped layer to form a channel; wherein each of the first, second, and third transistor device regions extend laterally across the length of the channel and abut the source and drain; wherein each of the first, second, and third transistor device regions are located to be below the surface of the substrate at a distance of at least 1/1.5 times a length of the gate and above the bottom of the source and drain to which each of the transistor device regions abuts.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 2.16981
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13926555', '15047052', '15419315', '14019187', '13559554']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9271566137724738
- 35 USC 102 Novelty (BERT): 0.5711850600584065
- Combined Prediction Score: 0.8915594584010671
- Mean Citation Score: 375.814086
- Max Citation Score: 443.3481
- Similarity Product: 429.0454521506667

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test