PATENT CLAIM ANALYSIS

Application Number: 15899138
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

Claim (Index 5):
The method of  claim 4 , wherein the second cache is a level two cache, wherein the level two data cache has a 128-byte line width and a request type width of 64 bytes wide.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.45
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13233443', '13218394', '13212980', '13223237', '13213024']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.55433902876744
- 35 USC 102 Novelty (BERT): 0.5439218713649018
- Combined Prediction Score: 0.5532973130271862
- Mean Citation Score: 329.8304300000001
- Max Citation Score: 392.72107
- Similarity Product: 251.0739959675294

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test