PATENT CLAIM ANALYSIS

Application Number: 15874444
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "063000"]

Abstract:
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.

Claim (Index 20):
The read-only memory (ROM) bitcell of  claim 15 , wherein resistance of the ROM bitcell is reduced due to using the wordline strap to couple the ROM bitcell to the wordline within the boundary of the ROM bitcell.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.21212
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15789715', '14181363', '15439899', '15462549', '14720930']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.809960677480441
- 35 USC 102 Novelty (BERT): 0.4870246313711613
- Combined Prediction Score: 0.777667072869513
- Mean Citation Score: 204.050526
- Max Citation Score: 214.72023
- Similarity Product: 148.697700134629

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test