PATENT CLAIM ANALYSIS

Application Number: 16191555
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["710", "300000"]

Abstract:
An embodiment of an extensible memory hub may include one or more upstream interface ports to couple the extensible memory hub to the controller, one or more downstream interface ports to couple the extensible memory hub to one or more of the nonvolatile memory and another extensible memory hub, and a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports and a second clock signal at a second frequency to the one or more downstream interface ports, where the first frequency may be different from the second frequency. Other embodiments are disclosed and claimed.

Claim (Index 10):
The system of  claim 9 , wherein the extensible memory hub further comprises:\n one or more bi-directional extension ports to couple the extensible memory hub to one or more of another extensible memory hub and a second nonvolatile memory device, wherein the logic is further to actively manage the buffer for data transfer between the one or more bi-directional extension ports, the one or more upstream interface ports, and the one or more downstream interface ports.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 98.0
- Lexical Diversity: 2.55814
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14314181', '15175697', '12166235', '10695383', '12350306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7395038774550706
- 35 USC 102 Novelty (BERT): 0.4803917018180576
- Combined Prediction Score: 0.7135926598913694
- Mean Citation Score: 149.359464
- Max Citation Score: 166.502
- Similarity Product: 108.98673502373695

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test