PATENT CLAIM ANALYSIS

Application Number: 15869726
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["323", "235000"]

Abstract:
A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Claim (Index 18):
A method of operating a switch-mode power converter, the method comprising:\n controlling a duty cycle of first and second switches electrically connected to a bridge node to convert a power converter input voltage to a power converter output voltage, wherein:\n the first switch has a first input and a first output, the first input having a power converter input voltage, the first output electrically connected to a bridge node, the first switch having a closed state in which the first input is electrically connected to the first output and an open state in which the first input is not electrically connected to the first output, \n the second switch has a second input and a second output, the second input electrically connected to the bridge node, the second output electrically connected to a second voltage, the second voltage lower than the power converter input voltage, the second switch having a closed state in which the second input is electrically connected to the second output and an open state in which the second input is not electrically connected to the second output, and \n first switch is in the open state when the second switch is in the closed state and the second switch is in the open state when the first switch is in the closed state; \n discharging the bridge node voltage during a high-to-low-delay time between an open time of the first switch and a close time of the second switch so that the bridge node voltage equals the second voltage at an end of the high-to-low-delay time; adjusting the high-to-low-delay time if the bridge node voltage does not equal the second voltage at the end of the high-to-low-delay time; charging the bridge node voltage during a low-to-high-delay time between an open time of the second switch and a close time of the first switch so that the bridge node voltage equals the power converter input voltage at an end of the low-to-high-delay time; adjusting the low-to-high-delay time if the bridge node voltage does not equal the power converter input voltage at the end of the low-to-high-delay time; and controlling a frequency of the first and second switches so that an inductor current of an LC circuit in electrical communication with the bridge node raises the bridge voltage to the power converter input voltage during the low-to-high-delay time.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.72727
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15243022', '11342489', '11027411', '15399335', '10668459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7265480157742559
- 35 USC 102 Novelty (BERT): 0.5367560474434129
- Combined Prediction Score: 0.7075688189411716
- Mean Citation Score: 251.844444
- Max Citation Score: 389.33008
- Similarity Product: 377.7432443221092

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test