PATENT CLAIM ANALYSIS

Application Number: 15859872
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "621000"]

Abstract:
Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.

Claim (Index 3):
The semiconductor structure of  claim 2 , wherein the first conductive layer of the TSV structure extends through at least one of the plurality of dielectric layers, and wherein the second conductive layer of the TSV structure extends from the first conductive layer through each of the plurality of dielectric layers not penetrated by the first conductive layer.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 86.0
- Lexical Diversity: 2.14286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14158577', '14081969', '14044716', '13550140', '15713011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9251638803118112
- 35 USC 102 Novelty (BERT): 0.5178607640217904
- Combined Prediction Score: 0.884433568682809
- Mean Citation Score: 229.526164
- Max Citation Score: 312.40598
- Similarity Product: 233.05863857959983

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test