PATENT CLAIM ANALYSIS

Application Number: 15770465
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["438", "637000"]

Abstract:
Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate, the dielectric lines raised above the metal lines. A hardmask layer is formed on the metal lines of the lower metallization layer, between and co-planar with the dielectric lines of the lower metallization layer. A grating structure is formed above and orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. A mask is formed above the grating structure. Select regions of the hardmask layer are removed to expose select regions of the metal lines of the lower metallization layer. Metal vias are formed on the select regions of the metal lines of the lower metallization layer.

Claim (Index 9):
The method of  claim 1 , wherein forming the grating structure comprising using a pitch halving or pitch quartering processing scheme.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 2.54839
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15772711', '14133385', '14965734', '14911991', '14137588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8604911314190077
- 35 USC 102 Novelty (BERT): 0.517847923547721
- Combined Prediction Score: 0.826226810631879
- Mean Citation Score: 238.035284
- Max Citation Score: 263.96133
- Similarity Product: 143.45113730031966

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test