PATENT CLAIM ANALYSIS

Application Number: 15987089
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "316000"]

Abstract:
In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

Claim (Index 1):
A method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, the method comprising:\n forming a mask layer over a silicon substrate in the memory cell area and the peripheral area, the mask layer including a first oxide layer formed in direct contact with the substrate and a nitride layer formed on the first oxide layer; forming a resist mask, on the nitride layer of the mask layer, over the peripheral area; patterning the mask layer in the memory cell area by using the resist mask as an etching mask; etching an upper portion of the substrate in the memory cell area by using the patterned mask layer as an etching mask such that a step is formed in the substrate; after the etching the substrate in the memory cell area, forming a second oxide layer by a thermal oxidation; and removing the second oxide layer and removing the mask layer from the peripheral area, wherein: a device forming surface of the substrate in the memory cell area is located at a lower level along the normal direction of the substrate than a device forming surface of the substrate in the peripheral area, after the removing the second oxide layer and the mask layer, the device forming surface of the substrate in the memory cell area and the device forming surface of the substrate in the peripheral area is connected by a transition area, and the method further comprises forming an isolation insulating layer in the substrate at the transition area.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.86792
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15267954', '15725000', '12020744', '11045850', '11848382']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8946520176105687
- 35 USC 102 Novelty (BERT): 0.4806736821070769
- Combined Prediction Score: 0.8532541840602195
- Mean Citation Score: 186.028024
- Max Citation Score: 248.32974
- Similarity Product: 244.57260395946625

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test