PATENT CLAIM ANALYSIS

Application Number: 16008920
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "410000"]

Abstract:
A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having width a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

Claim (Index 8):
A method, comprising:\n forming an interfacial layer over a fin, the fin being oriented in a first direction; depositing a high-k dielectric layer over the interfacial layer; depositing a polysilicon layer over the high-k dielectric layer, the polysilicon layer being oriented in a second direction generally perpendicular to the first direction; patterning the polysilicon layer, the high-k dielectric layer, and the interfacial layer, such that portions of the interfacial layer extend beyond outer edges of the high-k dielectric layer along the first direction; after the patterning, forming gate spacers on sidewalls of the polysilicon layer, wherein portions of the gate spacers are formed over the extended portions of the interfacial layer; forming source/drain features in the fin; forming a silicide layer over the source/drain features; forming an interlayer dielectric layer over the polysilicon layer, the gate spacers, and the silicide layer; removing the polysilicon layer to expose the high-k dielectric layer; forming a metal gate over the exposed high-k dielectric layer; and forming a source/drain contact plug in the interlayer dielectric layer and in contact with the silicide layer.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 94.0
- Lexical Diversity: 3.04878
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14487252', '15964557', '13440848', '12437696', '13757573']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9212807906341548
- 35 USC 102 Novelty (BERT): 0.4958103083793029
- Combined Prediction Score: 0.8787337424086695
- Mean Citation Score: 248.347608
- Max Citation Score: 258.012
- Similarity Product: 199.8113198661804

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test