PATENT CLAIM ANALYSIS

Application Number: 16354866
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["365", "185120"]

Abstract:
A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Claim (Index 1):
A memory system comprising:\n a semiconductor memory device that includes a plurality of memory cells and a word line, the plurality of memory cells including a page of memory cells, the plurality of memory cells comprising first, second, third, and fourth memory cells, the word line being electrically connected to gates of the first, second, third, and fourth memory cells; and a controller configured to read data from the page of memory cells and issue a first write command or a second write command to the semiconductor memory device, wherein the semiconductor memory device, in response to the issued first write command, executes a first program operation on the page of memory cells and a first verify operation on the memory cells of the page using a first verify voltage, and the semiconductor memory device, in response to the issued second write command, executes a second program operation on a first subset of the memory cells of the page, the first subset of the memory cells including the first and second memory cells, and a second verify operation on the first subset of the memory cells using a second verify voltage when the issued second write command corresponds to the first subset of the memory cells, and executes the second program operation on a second subset of the memory cells of the page, the second subset of the memory cells including the third and fourth memory cells, and a third verify operation on the second subset of the memory cells using a third verify voltage when the issued second write command corresponds to the second subset of the memory cells.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 3.04
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15876713', '15174527', '15588560', '15449856', '15185671']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7790909630184372
- 35 USC 102 Novelty (BERT): 0.5155370848045271
- Combined Prediction Score: 0.7527355751970461
- Mean Citation Score: 274.349464
- Max Citation Score: 328.4682
- Similarity Product: 280.9739974220753

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test