PATENT CLAIM ANALYSIS

Application Number: 15865923
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "156000"]

Abstract:
Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.

Claim (Index 20):
The memory device of  claim 19 , wherein the input/output circuitry comprises a sense amplifier, a YPASS circuitry, and a data-in circuitry.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.46479
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14087029', '13972988', '14562056', '15199167', '09829046']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8321819537962369
- 35 USC 102 Novelty (BERT): 0.5174377824322454
- Combined Prediction Score: 0.8007075366598377
- Mean Citation Score: 280.171346
- Max Citation Score: 345.6362
- Similarity Product: 286.80455459930903

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test