PATENT CLAIM ANALYSIS

Application Number: 16136671
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "077000"]

Abstract:
A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.

Claim (Index 1):
A method for fabricating an ESD protection structure, comprising:\n forming a substrate having a first region and a second region, wherein the first region and the second region are separated by a preset distance; forming a well area in the substrate, wherein the well area covers the first region, the second region, and a region between the first region and the second region; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region, wherein the first fin portion has first-type doping ions and the second fin portion has second-type doping ions; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and covering portions of top and side surfaces of the first fin portion, and a second supporting gate crossing the second fin portion and covering portions of top and side surfaces of the second fin portion; forming a dielectric layer on the well area between the first region and the second region, and between the first fin portion, the second fin portion, and the supporting gate structure, wherein the supporting gate structure is in the dielectric layer; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and being configured to connect to a first bias voltage, and a second conductive structure connecting to the second fin portion and being configured to connect to a second bias voltage, and the first bias voltage and the second bias voltage are not equal to one another.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 97.0
- Lexical Diversity: 3.34783
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15262930', '15662849', '14078655', '15275030', '15397376']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917687190631747
- 35 USC 102 Novelty (BERT): 0.5195923846639738
- Combined Prediction Score: 0.8778777100349697
- Mean Citation Score: 253.943082
- Max Citation Score: 339.1313
- Similarity Product: 305.8567765190064

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test