PATENT CLAIM ANALYSIS

Application Number: 15867688
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["345", "531000"]

Abstract:
Embodiments are generally directed to a scalable memory interface for a graphical processor unit. An embodiment of an apparatus includes a graphical processing unit (GPU) including multiple autonomous engines; a common memory interface for the autonomous engines; and a memory management unit for the common memory interface, the memory management unit including multiple engine modules, wherein each of the engine modules includes a translation-lookaside buffer (TLB) that is dedicated to providing address translation for memory requests for a respective autonomous engine of the plurality of autonomous engines, and a TLB miss tracking mechanism that provides tracking for the respective autonomous engine.

Claim (Index 12):
The medium of  claim 11 , further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:\n upon determining that the VA is a miss in the shared TLB, directing the memory request to a page walker element to walk a page table to determine the PA for the VA.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 86.0
- Lexical Diversity: 2.07407
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15482690', '15863347', '15482666', '15493267', '15482680']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6484695968098964
- 35 USC 102 Novelty (BERT): 0.5016381686449617
- Combined Prediction Score: 0.6337864539934028
- Mean Citation Score: 220.929664
- Max Citation Score: 243.44685
- Similarity Product: 161.94936111321152

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test