PATENT CLAIM ANALYSIS

Application Number: 15946940
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["716", "054000"]

Abstract:
Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Claim (Index 1):
A computer-implemented method of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation from process parameter values characterizing the semiconductor device fabrication operation, the method comprising:\n (a) receiving current values of one or more floated process model parameters to be optimized; (b) producing a configured process simulation model by providing to the process simulation model the current values of the one or more floated process model parameters and a set of fixed process model parameter value(s); (c) generating, using the configured process simulation model, a computationally predicted result of the semiconductor device fabrication operation; (d) comparing the computationally predicted result of the semiconductor device fabrication operation with a metrology result obtained from one or more substrate features produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under the set of fixed process parameter values, wherein the comparing produces one or more cost values based on a difference between the computationally predicted result of the semiconductor device fabrication operation and the metrology result; (e) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more floated process model parameters; (f) performing operation (b) with the update of the current values of the one or more floated process model parameters; and (g) repeating (c)-(f) until the current values of the one or more floated process model parameters converge to produce final values of the one or more floated process model parameters that minimize the cost values.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 91.0
- Lexical Diversity: 1.87324
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14972969', '15698458', '15018708', '15583610', '15188910']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3538101149057658
- 35 USC 102 Novelty (BERT): 0.47996659550547
- Combined Prediction Score: 0.3664257629657362
- Mean Citation Score: 249.84361600000005
- Max Citation Score: 268.2651
- Similarity Product: 211.46427414661648

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test