PATENT CLAIM ANALYSIS

Application Number: 16035430
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "185190"]

Abstract:
A semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory cells programmed to any one of first to N-th program states divided based on threshold voltages. The peripheral circuit may perform a program operation on the memory cells. The control circuit may control the peripheral circuit so that, during the program operation, a primary program operation is performed, and after the primary program operation, a secondary program operation is performed. The primary program operation may include a plurality of verify steps performed for the first to N-1-th program states and a single primary verify step performed for the N-th program state. The secondary program operation may include a secondary verify step performed for the N-th program state.

Claim (Index 1):
A semiconductor memory device, comprising:\n a memory cell array including a plurality of memory cells to be programmed to any one of first to N-th program states distinguishable based on threshold voltages of the memory cells; a peripheral circuit configured to perform a program operation including a primary program operation and a secondary program operation on the plurality of memory cells; and a control circuit configured to control the peripheral circuit to perform a plurality of verify steps for a first program states group including at least one program state among the first to N-th program states and at least one verify step for a second program states group including at least one program state among the first to N-th program states during the primary program operation and to perform the secondary program operation on the plurality of memory cells to be programmed to the the second program states group after the primary operation is performed, wherein each of the plurality of verify steps comprises a pre-verify step and a main verify step corresponding to each of the first states group, and the at least one verify step is performed using a verification voltage that is equal to or higher than a verification voltage of the main verify step for the first program states group.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 95.0
- Lexical Diversity: 2.74545
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15606674', '14980083', '15077681', '15641485', '14868586']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8006993038860953
- 35 USC 102 Novelty (BERT): 0.5342283839562991
- Combined Prediction Score: 0.7740522118931157
- Mean Citation Score: 281.254608
- Max Citation Score: 386.07587
- Similarity Product: 374.28484085204366

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test