PATENT CLAIM ANALYSIS

Application Number: 16005435
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["327", "277000"]

Abstract:
A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.

Claim (Index 9):
The delay line circuit of  claim 1 , wherein the switching circuit is further configured to\n selectively connect the speed control unit to the signal path based on whether the first output signal was transferred through an even or odd number of the first delay units.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 94.0
- Lexical Diversity: 2.18644
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15413742', '14555198', '11779341', '11033395', '12570186']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7769319489652637
- 35 USC 102 Novelty (BERT): 0.4875468222545566
- Combined Prediction Score: 0.747993436294193
- Mean Citation Score: 197.278458
- Max Citation Score: 245.42598
- Similarity Product: 219.9187417317009

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test