PATENT CLAIM ANALYSIS

Application Number: 16006823
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "369000"]

Abstract:
A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.

Claim (Index 15):
The CMOS device of  claim 11 , wherein the second insulating layer has a tensile stress.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 94.0
- Lexical Diversity: 2.44186
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13730052', '15475097', '14188181', '12437696', '14693978']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9170732080820502
- 35 USC 102 Novelty (BERT): 0.4902103347712813
- Combined Prediction Score: 0.8743869207509734
- Mean Citation Score: 162.850566
- Max Citation Score: 167.96538
- Similarity Product: 108.3728673894167

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test