PATENT CLAIM ANALYSIS

Application Number: 15892625
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["438", "586000"]

Abstract:
Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

Claim (Index 3):
The method of  claim 1 , wherein the retained portion of the conductor comprises a retained first portion of the conductor, the portion of the dielectric having the second thickness comprises a first portion of the dielectric having the second thickness, and the field-effect transistor comprises a first field-effect transistor, the method further comprising:\n forming the dielectric further having a third thickness greater than the second thickness, over the semiconductor; patterning the conductor to further retain a second portion of the conductor over a second portion of the dielectric having the second thickness and defining a control gate of a second field-effect transistor of the circuit-protection device, to further retain a third portion of the conductor over a first portion of the dielectric having the third thickness and defining a control gate of a third field-effect transistor of the circuit-protection device connected in series with the first field-effect transistor, and to further retain a fourth portion of the conductor over a second portion of the dielectric having the third thickness and defining a control gate of a fourth field-effect transistor of the circuit-protection device connected in series with the second field-effect transistor; forming a first contact to a source/drain of the third field-effect transistor adjacent a first isolation region; and forming a second contact to a source/drain of the fourth field-effect transistor adjacent a second isolation region; wherein a distance between the first contact and the first isolation region is greater than a distance between the second contact and the second isolation region.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 88.0
- Lexical Diversity: 2.82353
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13400678', '15687732', '15606080', '14982228', '12613269']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8535871425334174
- 35 USC 102 Novelty (BERT): 0.4784746250904028
- Combined Prediction Score: 0.8160758907891159
- Mean Citation Score: 192.631434
- Max Citation Score: 218.03812
- Similarity Product: 178.966457058177

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test