PATENT CLAIM ANALYSIS

Application Number: 15945913
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "777000"]

Abstract:
The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Claim (Index 17):
A chip module with a discrete electronic device embedded therein, the chip module comprising:\n a multilayer substrate with a horizontal top surface, a horizontal bottom surface and at least one vertical side surface extending peripherally between the horizontal top surface and the horizontal bottom surface, the chip module being configured to receive one or more discrete electronic devices to be mounted onto the horizontal top surface, the chip module further being configured to be mounted on a printed circuit board, a plurality of horizontal sections stacked above each other between the horizontal top surface and the horizontal bottom surface, each section comprising a lower and an upper horizontal electrically conductive layer, each section further comprising a horizontal electrically non-conductive layer arranged between the lower and the upper electrically conductive layer, each electrically conductive layer comprising one or more electrically conductive structures, a recess in the at least one vertical side surface, the recess extending vertically within a plurality of horizontal sections, a first electrically conductive connection between a first electrical contact of a first discrete electronic device of the one or more discrete electronic devices and a first electrically conductive structure.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 2.34848
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15214565', '15494672', '14918678', '15175378', '14188555']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9005909037117249
- 35 USC 102 Novelty (BERT): 0.5569062080832037
- Combined Prediction Score: 0.8662224341488728
- Mean Citation Score: 267.453234
- Max Citation Score: 405.03473
- Similarity Product: 401.6125842749745

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test