PATENT CLAIM ANALYSIS

Application Number: 16006301
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "296000"]

Abstract:
Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Claim (Index 20):
The memory cell of  claim 16  wherein a gate of the third transistor is configured to have at least one bent region, and one or more extension regions that extend along the third channel region from said at least one bent region; and wherein the gate of the third transistor and the one or more extension regions together form a substantially T-shaped configuration, substantially shelf-shaped configuration or substantially U-shaped configuration.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.86364
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15664183', '15664217', '15664161', '15664140', '15986628']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9371793469976236
- 35 USC 102 Novelty (BERT): 0.5412108587777203
- Combined Prediction Score: 0.8975824981756335
- Mean Citation Score: 329.175366
- Max Citation Score: 396.0863
- Similarity Product: 281.76905445717574

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test