PATENT CLAIM ANALYSIS

Application Number: 16111085
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "205000"]

Abstract:
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.

Claim (Index 14):
A system, comprising:\n a host configured to generate instructions; and a memory device coupled to the host and comprising:\n an array of memory cells coupled to sensing circuitry comprising a plurality of sense amplifier latches and a respective plurality of compute component latches corresponding thereto on a per column basis; and \n control circuitry configured to execute instructions from the host by causing logical operations to be performed, in parallel, on operands stored in memory cells corresponding to a same column of the array and coupled to different access lines of the array by:\n providing, to logical operation selection logic, a particular combination of logical operation selection signals corresponding to a selected logical operation to be performed on the operands corresponding to the respective same columns; \n \n wherein the selected logical operation comprises one from among a group of selectable logical operations corresponding to different respective logical selection signal combinations, the group including an exclusive OR (XOR) logical operation, an XNOR logical operation, a sense amplifier reset operation, and a sense amplifier set operation; and wherein the logical operation selection logic comprises a plurality of groups of transistors, with each group being coupled to the compute component latch and the sense amplifier latch of one of the respective columns; and wherein a result of the selected logical operation is obtained without activating a column decode signal.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 96.0
- Lexical Diversity: 1.77551
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15685643', '14921509', '16055658', '15442086', '15256066']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8082907594855814
- 35 USC 102 Novelty (BERT): 0.5208099746859755
- Combined Prediction Score: 0.7795426810056207
- Mean Citation Score: 327.9076960000001
- Max Citation Score: 346.2429
- Similarity Product: 295.8742562760651

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test