PATENT CLAIM ANALYSIS

Application Number: 16035430
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "185190"]

Abstract:
A semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory cells programmed to any one of first to N-th program states divided based on threshold voltages. The peripheral circuit may perform a program operation on the memory cells. The control circuit may control the peripheral circuit so that, during the program operation, a primary program operation is performed, and after the primary program operation, a secondary program operation is performed. The primary program operation may include a plurality of verify steps performed for the first to N-1-th program states and a single primary verify step performed for the N-th program state. The secondary program operation may include a secondary verify step performed for the N-th program state.

Claim (Index 5):
A semiconductor memory device, comprising:\n a memory cell array including a plurality of memory cells to be programmed to any one of first to N-th program states distinguishable based on threshold voltages of the memory cells; a peripheral circuit configured to perform a program operation on the plurality of memory cells; and a control circuit configured to control the peripheral circuit to perform the program operation including at least two verify steps corresponding to a first program states group including at least one program state among the first to N-th program states, respectively until the memory cells to be programmed to the first program states group have passed program verifications during the program operation, wherein, if the memory cells to be programmed to the first program states group have passed the program verifications, the control circuit performs a reprogram operation for a second program states group including at least one program state among the first to N-th program states, wherein the at least two verify steps are verify steps that use a pre-verification voltage and a main verification voltage corresponding to the first program states group, and wherein the reprogram operation with respect to the memory cells to be programmed to the second program states group is performed using the main verification voltage of the second program states group.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 95.0
- Lexical Diversity: 2.74545
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15606674', '14980083', '15077681', '15641485', '14868586']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8006856306764358
- 35 USC 102 Novelty (BERT): 0.5342458657710129
- Combined Prediction Score: 0.7740416541858935
- Mean Citation Score: 281.254608
- Max Citation Score: 386.07587
- Similarity Product: 374.9021354742712

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test