PATENT CLAIM ANALYSIS

Application Number: 16448844
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["438", "269000"]

Abstract:
A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

Claim (Index 10):
The semiconductor device of  claim 1 , wherein the interlayer spaces filled with the conductive patterns are sealed by the first isolation layers.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 100.0
- Lexical Diversity: 1.86
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15487761', '16031588', '15961143', '16410752', '16011975']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8719945938208268
- 35 USC 102 Novelty (BERT): 0.4881135027436108
- Combined Prediction Score: 0.8336064847131053
- Mean Citation Score: 207.786782
- Max Citation Score: 233.1994
- Similarity Product: 187.0317256780267

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test