PATENT CLAIM ANALYSIS

Application Number: 16237396
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["365", "227000"]

Abstract:
A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V mem  applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Claim (Index 13):
The method of  claim 12 , wherein cell size of said memory cell is the same as cell size of said second memory cell.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.4
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15880913', '14450324', '15434715', '13285945', '13758211']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7903033030584309
- 35 USC 102 Novelty (BERT): 0.4670569498383666
- Combined Prediction Score: 0.7579786677364245
- Mean Citation Score: 220.437566
- Max Citation Score: 233.46162
- Similarity Product: 230.5753579460156

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test