PATENT CLAIM ANALYSIS

Application Number: 15875300
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["345", "173000"]

Abstract:
The present disclosure provides a display substrate, display panel, and display device. The display substrate includes: a base substrate having a display area and a periphery area surrounding the display area; a plurality of force sensors disposed in the periphery area; and a substrate layer layered upon the base substrate and disposed under a film layer where the plurality of force sensors are located and including a plurality of strip-shaped convex structures; wherein a portion of each of the plurality of force sensors corresponding to each of the plurality of strip-shaped convex structures is convex, and another portion of each of the plurality of force sensors corresponding to a gap between adjacent two of the plurality of strip-shaped convex structures is concave. The present disclosure achieves that abnormal display will not appear on display panel at display area edge or position corresponding to force sensor, thereby improving display effect.

Claim (Index 11):
The display substrate according to  claim 10 , wherein\n a plurality of gate lines and a plurality of data lines are provided in the display area of the display substrate and disposed in a crisscross manner, and the plurality of gate lines and the plurality of data lines cooperatively define a plurality of pixel units, each of the pixel units is provided with a pixel electrode and a thin film transistor, a source electrode of the thin film transistor is electrically connected to the data line, a drain electrode thereof is electrically connected to the pixel electrode, and a gate electrode thereof is electrically connected to the gate line; in the display area of the display substrate, a light shielding layer, a buffer layer, a polysilicon layer, a gate insulation layer, a gate metal layer, an interlayer insulation layer, a source-drain electrode metal layer, a planarization layer, a touch lead wire layer, a first passivation layer, a first transparent conducting layer, a second passivation layer and a second transparent conducting layer are provided sequentially in a direction away from the base substrate; the polysilicon layer comprises an active layer of the thin film transistor, an orthographic projection of the light shielding layer on the base substrate covers an orthographic projection of the active layer on the base substrate, the gate metal layer comprises the gate electrode of the thin film transistor and the gate line, the source-drain electrode metal layer comprises the source electrode, the drain electrode of the thin film transistor and the data line; the source electrode and the drain electrode are connected to the active layer via a through hole penetrating both the interlayer insulation layer and the gate insulation layer; the touch lead wire layer comprises a plurality of touch lead wires, the first transparent conducting layer comprises a plurality of common electrode blocks, each of the common electrode blocks is electrically connected to the touch lead wire via a through hole penetrating the first passivation layer, the second transparent conducting layer comprises a plurality of pixel electrodes, and the pixel electrode is electrically connected to the drain electrode via a through hole penetrating the second passivation layer, the first passivation layer, and the planarization layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.42424
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15756966', '15865438', '15567060', '15391155', '14957448']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6239594402414999
- 35 USC 102 Novelty (BERT): 0.4823533163169884
- Combined Prediction Score: 0.6097988278490487
- Mean Citation Score: 184.476688
- Max Citation Score: 190.09026
- Similarity Product: 148.00470270766496

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test