PATENT CLAIM ANALYSIS

Application Number: 15981355
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "072000"]

Abstract:
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Claim (Index 1):
A semiconductor device comprising:\n a memory array including\n a plurality of word lines; \n a plurality of pair of bit lines; \n a plurality of static type memory cells coupled to the word lines and the pair of bit lines so that one static type memory cell of the static type memory cells the is coupled to one word line of the word lines and one pair of bit lines of the pair of bit lines; \n a sense amplifier circuit which amplifies data read out to one pair of bit lines from one memory cell and is controlled by a first signal; a timing adjustment circuit which receives a second signal and provides a third signal generated by delaying the second signal; and a first control circuit which provides the first signal in response to the third signal, wherein the timing adjustment circuit includes:\n a first wiring for receiving the second signal; \n a second wiring coupled to the first wiring and providing the third signal; and \n a first MOS transistor having a source-drain path between the first wiring and the second wiring.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 93.0
- Lexical Diversity: 2.06667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14981195', '15716639', '15367829', '14321169', '14026575']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.842325032452539
- 35 USC 102 Novelty (BERT): 0.5781725907672522
- Combined Prediction Score: 0.8159097882840103
- Mean Citation Score: 487.03654000000006
- Max Citation Score: 501.04446
- Similarity Product: 424.0187582554221

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test