PATENT CLAIM ANALYSIS

Application Number: 16137563
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-06
Patent Classification: ["710", "009000"]

Abstract:
A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes of the data bus system in an assignment time period. After the assigning of bus node addresses to the bus nodes in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.

Claim (Index 7):
A method for controlling a serial data bus system comprising:\n a bus line; a bus master connected to the bus line; and a plurality of bus nodes serially connected to the bus line; wherein the plurality of bus nodes includes:\n at least two addressable bus nodes operable to receive addresses in an addressing phase; and \n zero or more standard bus nodes having respectively already fixed addresses; \n wherein the method includes the addressing phase for assigning the addresses to at least one of the at least two addressable bus nodes, and an operating phase for operating the data bus system after termination of the addressing phase; wherein, in the addressing phase, at least two of the plurality of bus nodes are operative to feed into the bus line a respective current flowing to the bus master, and the plurality of bus nodes includes:\n a first bus node, connected to the bus line at a site upstream from, and closest to the bus master; \n a last bus node, connected to the bus line at a site upstream from, and farthest from the bus master; and \n zero or more middle bus nodes, connected to the bus line in between the first bus node and the last bus node; \n wherein:\n each of the at least two addressable bus nodes is operable to receive an address assigned from the bus master during the addressing phase and comprises a current measurement circuit adapted to be switched into the bus line and a controllable bypass switch connected in parallel to the current measurement circuit, and, \n each of the zero or more standard bus nodes has the respective address that is fixed prior to performing the addressing phase, \n wherein, in the method;\n in the addressing phase, an address is assigned to each addressable bus node in an open state of the bypass switch, and \n in the operating phase, the current measurement circuit of each addressed addressable bus node is bypassed by closing the bypass switch.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 97.0
- Lexical Diversity: 2.88679
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16137562', '16137561', '14043186', '15048354', '16470585']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6605230766432828
- 35 USC 102 Novelty (BERT): 0.6113022037352354
- Combined Prediction Score: 0.6556009893524781
- Mean Citation Score: 346.60678
- Max Citation Score: 574.1351
- Similarity Product: 486.8975976055026

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test