PATENT CLAIM ANALYSIS

Application Number: 15878486
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "329000"]

Abstract:
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

Claim (Index 1):
An integrated circuit structure comprising:\n a semiconductor body for a field effect transistor, the semiconductor body comprising source/drain regions and a channel region positioned laterally between the source/drain regions; a gate having a dielectric cap and a dielectric sidewall spacer, the gate being adjacent to the semiconductor body at the channel region; at least one dielectric layer above the semiconductor body at the source/drain regions and positioned laterally adjacent to the dielectric sidewall spacer; metal plugs having additional dielectric caps, the metal plugs being within metal plug openings in the at least one dielectric layer and aligned above the source/drain regions, wherein the dielectric cap, dielectric sidewall spacer and additional dielectric caps comprise different dielectric materials, and wherein the dielectric sidewall spacer is positioned laterally between the metal plugs and the gate and further between the additional dielectric caps and the dielectric cap; interlayer dielectric material above the dielectric cap, the dielectric sidewall spacer and the additional dielectric caps; a first contact comprising conductive material in a first contact opening extending vertically through the interlayer dielectric material and the dielectric cap to the gate; and second contacts comprising the conductive material in second contact openings extending through the interlayer dielectric material and the additional dielectric caps to the metal plugs.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.23288
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15354212', '15388400', '15851774', '15672336', '15443381']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.935723741218742
- 35 USC 102 Novelty (BERT): 0.6067079933337626
- Combined Prediction Score: 0.902822166430244
- Mean Citation Score: 438.69686
- Max Citation Score: 546.0278
- Similarity Product: 485.9095365239858

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test