PATENT CLAIM ANALYSIS

Application Number: 16044696
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-07
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.

Claim (Index 4):
The semiconductor package of  claim 3 , further comprising a second connection terminal extending between the second pattern and a second chip pad of the semiconductor chip,\n wherein the second pattern and the second connection terminal are electrically insulated from each other by the passivation layer.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 95.0
- Lexical Diversity: 3.32432
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15869678', '12788901', '14824394', '15666073', '15799624']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.905651219556284
- 35 USC 102 Novelty (BERT): 0.5078019935354425
- Combined Prediction Score: 0.8658662969541999
- Mean Citation Score: 248.713566
- Max Citation Score: 258.91547
- Similarity Product: 187.04151027347328

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test