PATENT CLAIM ANALYSIS

Application Number: 15906536
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["257", "529000"]

Abstract:
A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.

Claim (Index 8):
A semiconductor device according to  claim 4 , wherein the lower-layer wiring is connected to each of the both ends of the fuse element through a via.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 1.97917
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15059112', '10649771', '12963695', '15818007', '12539723']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9083005619358712
- 35 USC 102 Novelty (BERT): 0.486026827478643
- Combined Prediction Score: 0.8660731884901484
- Mean Citation Score: 184.942912
- Max Citation Score: 188.57092
- Similarity Product: 142.0856788889336

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test