PATENT CLAIM ANALYSIS

Application Number: 16113940
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["327", "175000"]

Abstract:
A duty cycle correction circuit is provided. The duty cycle correction circuit may include a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal. The duty cycle correction circuit may include a locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal, using an internal clock signal generated in a semiconductor circuit.

Claim (Index 9):
The duty cycle correction circuit according to  claim 7 , wherein the code comparator comprises:\n a plurality of logic gates configured to receive the differential duty detection codes by a pair of bits in the same order, and generate output signals by performing a first logic operation on the received signals; and an operation logic configured to generate the transmission enable signal by performing a second logic operation on the output signals of the plurality of logic gates.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.27273
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14625970', '11235646', '13234062', '12630400', '13900279']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7954398827314457
- 35 USC 102 Novelty (BERT): 0.4851684681362047
- Combined Prediction Score: 0.7644127412719216
- Mean Citation Score: 228.142034
- Max Citation Score: 251.77344
- Similarity Product: 213.3085002044677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test