PATENT CLAIM ANALYSIS

Application Number: 16386891
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "532000"]

Abstract:
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a first inter-level dielectric (ILD) layer over a substrate. A plurality of MIM (metal-insulator-metal) structures are disposed within a second inter-level dielectric (ILD) layer over the lower interconnect layer. An upper interconnect layer is coupled to the plurality of MIM structures at first locations that are directly over second locations at which the lower interconnect layer is coupled to the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.

Claim (Index 3):
The integrated chip of  claim 1 , wherein a first MIM structure of the plurality of MIM structures is confined completely above an upper surface of the lower interconnect layer.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 100.0
- Lexical Diversity: 2.26316
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15942760', '15418904', '14883808', '14249513', '14249498']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9326281671774664
- 35 USC 102 Novelty (BERT): 0.518617679330653
- Combined Prediction Score: 0.8912271183927852
- Mean Citation Score: 286.005306
- Max Citation Score: 324.46313
- Similarity Product: 259.03261808722016

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test