PATENT CLAIM ANALYSIS

Application Number: 15875577
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["385", "014000"]

Abstract:
A semiconductor structure is disclosed. The semiconductor structure includes: a substrate and a gate element over the substrate. The gate element includes: a gate dielectric layer over the substrate; a gate electrode over the gate dielectric layer; and a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode. A manufacturing method of the same is also disclosed.

Claim (Index 20):
A method for manufacturing a semiconductor structure, comprising:\n providing a semiconductor substrate; forming a gate element over the semiconductor substrate, the gate element including a gate dielectric layer, a gate electrode over the gate dielectric layer and a pair of spacers along sidewalls of the gate dielectric layer and the gate electrode; forming an inter level dielectric (ILD) material over the gate element; performing a first etch to form an opening penetrating through the ILD material and stopping at the gate electrode; and performing a second etch to expand the opening to penetrate through the gate electrode and stop at the gate dielectric layer.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.36364
- Patent Class: 385.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14483247', '14692794', '15859354', '15266819', '15258348']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7866112441358525
- 35 USC 102 Novelty (BERT): 0.4616997183569081
- Combined Prediction Score: 0.7541200915579581
- Mean Citation Score: 123.908262
- Max Citation Score: 133.21501
- Similarity Product: 98.35211327943324

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test