PATENT CLAIM ANALYSIS

Application Number: 15897706
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["438", "268000"]

Abstract:
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

Claim (Index 7):
The method according to  claim 6 , wherein the fin comprises a semiconductor fin on which a hard mask is disposed and the substrate comprises a semiconductor.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 1.90909
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15235829', '15240056', '15276349', '15188476', '15422724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8708240472176894
- 35 USC 102 Novelty (BERT): 0.5507345076276967
- Combined Prediction Score: 0.8388150932586902
- Mean Citation Score: 260.09920800000003
- Max Citation Score: 401.85196
- Similarity Product: 390.6523700646496

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test