PATENT CLAIM ANALYSIS

Application Number: 16123055
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2020-01
Patent Classification: ["345", "173000"]

Abstract:
A shift register driving a touch display device generates shifted pulse signals shifted by a specified phase. The shift register includes unit circuits connected in multiple stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor is controlled by a first control signal and outputs a high-level voltage to a first node based on the value of a trigger signal. The output transistor outputs the shifted pulse signal, which is synchronous with a clock control signal, based on the value of the high-level voltage of the first node. A blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit. After the blank period, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.

Claim (Index 7):
A touch display apparatus comprising:\n a display region; and a non-display region surrounding the display region, and the non-display region comprising: at least one gate driver with at least one shift register disposed in the non-display region; the shift register comprising a plurality of cascade-connected unit circuits, and configured to generate a plurality of shifted pulse signals shifted by a specified phase shift; each unit circuit configured to receive an clock control signal, each of the unit circuit comprising: an output terminal, electrically coupled to at least one external signal line, and configured to provide a shifted pulse signal to the connected at least one external signal line; an input transistor, controlled by a first control signal, and configured to output a high-level voltage to a first node based on a trigger signal activating the unit circuit; an output transistor, including a first control terminal connected to the first node, a first connection terminal receiving the clock control signal, and a second connection terminal connected to the output terminal, the output transistor outputting the shifted pulse signal to the output terminal in response to the high-level voltage of the first node, the shifted pulse signal being synchronous with the clock control signal; and a pull-up transistor, including a second control terminal connected to the output terminal, a third connection terminal connected to the second control terminal, and a fourth connection terminal connected to a high voltage power source; wherein the shifted pulse signal of the (N+1)th unit circuit outputted to the (N+1)th signal line is shifted a specified phase by compared to the shifted pulse signal of the Nth unit circuit outputted to the Nth signal line; a blank period is inserted between two adjacent shifted pulse signals of two adjacent unit circuits; during the (N+1)th unit circuit outputting the shifted pulse signal after the blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 2.36364
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15853911', '15660758', '15630182', '15741742', '15121897']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.650583287132203
- 35 USC 102 Novelty (BERT): 0.4719190964795335
- Combined Prediction Score: 0.6327168680669362
- Mean Citation Score: 206.760874
- Max Citation Score: 212.36757000000003
- Similarity Product: 179.38591986773378

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test