PATENT CLAIM ANALYSIS

Application Number: 16141923
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "338000"]

Abstract:
A semiconductor device and a method for manufacturing the same are disclosed. The method comprises forming active patterns on a substrate that includes first and second logic cell regions adjacent to each other in a first direction, and forming on the substrate a device isolation layer exposing upper portions of the active patterns. The forming the active patterns comprises forming first line mask patterns extending parallel to each other in the first direction and running across the first and second logic cell regions, forming on the first line mask patterns an upper separation mask pattern including a first opening overlapping at least two of the first line mask patterns, forming first hardmask patterns from the at least two first line mask patterns, and etching the substrate to form trenches defining the active patterns.

Claim (Index 7):
The method of  claim 3 , wherein the substrate further comprises third and fourth logic cell regions adjacent to each other along the first direction and separated from each other by a second cell boundary,\n wherein forming the active patterns comprises:\n forming second line mask patterns extending parallel to each other along the first direction and running across the third and fourth logic cell regions and the second cell boundary; \n forming a second lower separation mask pattern covering at least two of the second line mask patterns on the third logic cell region; \n forming a third lower separation mask pattern covering at least two of the second line mask patterns on the fourth logic cell region, wherein the second and third lower separation mask patterns are spaced apart from each other along the first direction with the second cell boundary interposed therebetween, such that a portion of at least two second line mask patterns is exposed by the second and third lower separation mask patterns; and \n performing a third etch process using the second and third lower separation mask patterns as an etch mask to remove the portion of the at least two second line mask patterns exposed by the second and third lower separation mask patterns, \n wherein the upper separation mask pattern is formed to cover the second and third lower separation mask patterns and to fill a space between the second and third lower separation mask patterns.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.29508
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15478234', '14814601', '13618428', '15392725', '14682132']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926416518502299
- 35 USC 102 Novelty (BERT): 0.534829271053724
- Combined Prediction Score: 0.8872577937574415
- Mean Citation Score: 256.3933
- Max Citation Score: 367.91516
- Similarity Product: 249.8266815016508

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test