PATENT CLAIM ANALYSIS

Application Number: 16229260
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "368000"]

Abstract:
Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.

Claim (Index 17):
A method comprising:\n forming a first gate stack, a second gate stack, and a third gate stack over a substrate, wherein the second gate stack is disposed between the first gate stack and the third gate stack, wherein a first source/drain (S/D) feature is disposed over the substrate between the first gate stack and the second gate stack and a second S/D feature is disposed over the substrate between the second gate stack and the third gate stack, and further wherein a first spacer and a second spacer are disposed along respective sidewalls of the first gate stack, a third spacer and a fourth spacer are disposed along respective sidewalls of the second gate stack, and a fifth spacer and a sixth spacer are disposed along respective sidewalls of the third gate stack; forming a first dielectric layer over the substrate, wherein the first dielectric layer is disposed over the first, second, third, fourth, fifth, and sixth spacers; recessing the first dielectric layer to expose an upper portion of the first spacer, an upper portion of the second spacer, an upper portion of the third spacer, an upper portion of the fourth spacer, an upper portion of the fifth spacer, and an upper portion of the sixth spacer, wherein the upper portions of the first, second, third, fourth, fifth, and sixth spacers have a tapered width; forming a spacer layer over the first dielectric layer, the first gate stack, the second gate stack, and the third gate stack, such that the spacer layer is disposed along the upper portions of the first, second, third, fourth, fifth, and sixth spacers; forming a second dielectric layer over the spacer layer; removing a portion of the second dielectric layer to form a contact trench, wherein the contact trench exposes a portion of the spacer layer disposed over the upper portions of the second, third, fourth, and fifth spacers; removing a portion of the exposed portion of the spacer layer to extend the contact trench and expose a portion of the first dielectric layer, thereby forming a seventh spacer disposed on the upper portion of the second spacer, an eighth spacer disposed on the upper portion of the third spacer, a ninth spacer disposed on the upper portion of the fourth spacer, and a tenth spacer disposed on the upper portion of the fifth spacer, wherein the seventh, eighth, ninth, and tenth spacers are disposed over the first dielectric layer; removing the exposed portion of the first dielectric layer to extend the contact trench, thereby exposing the first S/D feature and the second S/D feature; and forming a conductive layer in the contact trench, wherein the conductive layer provides a shared contact to the first S/D feature and the second S/D feature, wherein the shared contact spans uninterrupted between the first S/D feature and the second S/D feature over the second gate stack.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 98.0
- Lexical Diversity: 2.68333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15790975', '14477311', '14521965', '14830217', '15628267']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9004605862657733
- 35 USC 102 Novelty (BERT): 0.4880635802811174
- Combined Prediction Score: 0.8592208856673077
- Mean Citation Score: 208.86452
- Max Citation Score: 231.544
- Similarity Product: 193.546872549057

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test