PATENT CLAIM ANALYSIS

Application Number: 15978682
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["365", "189050"]

Abstract:
The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.

Claim (Index 18):
The method of  claim 17 , further comprising:\n maintaining the refresh frequency at the preset frequency when the voltage of the clock tree module remains at the high level after the refresh frequency returns to the preset frequency.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 3.71429
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10983504', '13102938', '12392495', '15133068', '11481518']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7549716649026942
- 35 USC 102 Novelty (BERT): 0.4972675861347242
- Combined Prediction Score: 0.7292012570258972
- Mean Citation Score: 196.940412
- Max Citation Score: 203.7917
- Similarity Product: 128.14966982098818

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test