PATENT CLAIM ANALYSIS

Application Number: 16057580
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["361", "679400"]

Abstract:
One feature pertains to a modular design of a motherboard for a computer system. The mother board is disaggregated into a CPU board and an IO board. The CPU board contains at least one CPU, the associated memory subsystem and the voltage regulator module. The integrated IO ports escape to a high speed connector mating with its counterpart on an IO board which contains all peripheral devices including system logic not part of the CPU. In a multi-socket configuration the CPUs are on the CPU board and the processor interconnects are routed directly in a point to point manner.

Claim (Index 10):
A method for manufacturing a computer motherboard with reduced length interconnection traces, comprising:\n dividing the motherboard into a first printed circuit board assembly and a second printed circuit board assembly; forming a first printed circuit board assembly, the first printed circuit board comprising:\n a first printed circuit board having a first surface and an opposite second surface; \n a first central processing unit mounted on the first surface of the first printed circuit board, the first central processing unit having integrated input/output ports; \n a system memory socket mounted on the first surface of the first printed circuit board; \n a power supply to provide power to the central processing unit and the memory slot; and \n a first high speed data connector mounted on the second surface of the first printed circuit board and connected to the integrated input/output ports of the first central processing unit; and \n forming a second printed circuit board assembly, the second printed circuit board comprising:\n a second printed circuit board with a first surface and an opposite second surface; \n an input/output interface coupled to the first surface of the second printed circuit board; \n a high-speed peripheral device interface; and \n a second high speed data connector mounted on the second surface of the second printed circuit board, and adapted to couple with the first high speed data connector of the first printed circuit board assembly and a high speed peripheral device interface.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 96.0
- Lexical Diversity: 1.59091
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14452221', '13535529', '13535593', '13207459', '14018957']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.831712232322206
- 35 USC 102 Novelty (BERT): 0.4616396197949156
- Combined Prediction Score: 0.794704971069477
- Mean Citation Score: 182.379358
- Max Citation Score: 198.00882
- Similarity Product: 169.39486619210956

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test