PATENT CLAIM ANALYSIS

Application Number: 15907210
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["714", "773000"]

Abstract:
A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Claim (Index 16):
The memory according to  claim 15 , further comprising:\n a buffer having a primary interface for communicating with a memory controller and a secondary interface coupled to the first IC memory chip, the buffer including repair logic to map a replacement storage element in the third IC memory chip as a substitute storage element for a storage cell location in the first IC memory chip in response to failure information associated with the storage cell location and retrieved from the second IC memory chip.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.35714
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14631570', '15829682', '15646025', '15250677', '14285467']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2558915123473017
- 35 USC 102 Novelty (BERT): 0.479624219846901
- Combined Prediction Score: 0.2782647830972616
- Mean Citation Score: 192.867174
- Max Citation Score: 241.2076
- Similarity Product: 218.90763560915

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test