PATENT CLAIM ANALYSIS

Application Number: 16127767
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["349", "043000"]

Abstract:
The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Claim (Index 1):
An array substrate, comprising a substrate, and a first metal layer, an insulating layer, a polycrystalline silicon (P\u2014Si) semiconductor layer, a dielectric spacer layer and a second metal layer that are formed on the substrate, wherein the first metal layer comprises a first zone and a second zone spaced from each other, the first zone of the first metal layer being a gate electrode of a thin film transistor (TFT) of the array substrate; the second metal layer comprises a third zone and a fourth zone arranged spaced from each other, the third zone and the fourth zone of the second metal layer being a source electrode and a drain electrode of the TFT, respectively, wherein the P\u2014Si semiconductor layer and the second zone of the first metal layer are arranged insulated and overlapped through the insulating layer sandwiched between the P\u2014Si semiconductor layer and the second zone of the first metal layer, or the P\u2014Si semiconductor layer and the fourth zone of the second metal layer are arranged insulated and overlapped through the dielectric spacer layer sandwiched between the P\u2014Si semiconductor layer and the fourth zone of the second metal layer to form a metal-insulator-semiconductor (MIS) storage capacitor of the array substrate;\n wherein the gate electrode of the TFT is located under the P\u2014Si semiconductor layer; wherein the second metal layer further comprises a seventh zone that is spaced from and adjacent to the fourth zone and is distant from the third zone; and wherein the P\u2014Si semiconductor layer is connected through the seventh zone of the second metal layer to the second zone of the first metal layer so that the MIS storage capacitor of the array substrate is formed by the P\u2014Si semiconductor layer, the fourth zone of the second metal, and the dielectric layer located therebetween.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.5082
- Patent Class: 349.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16126078', '16127704', '15208928', '15075151', '15204906']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8608022185828166
- 35 USC 102 Novelty (BERT): 0.5195209724762249
- Combined Prediction Score: 0.8266740939721574
- Mean Citation Score: 324.330956
- Max Citation Score: 350.86313
- Similarity Product: 349.4577506331772

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test