PATENT CLAIM ANALYSIS

Application Number: 15885972
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["712", "220000"]

Abstract:
A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.

Claim (Index 1):
A processing system comprising an arrangement of tiles and an interconnect for communicating between the tiles, wherein:\n each tile comprises an execution unit for executing machine code instructions, each being an instance of a predefined set of instruction types in an instruction set of the processor, each instruction type in the instruction set being defined by a corresponding opcode and zero or more operand fields for taking zero or more operands; the interconnect comprises synchronization logic in the form of hardware logic for coordinating a barrier synchronization to be performed between a group of said tiles; the instruction set comprises a synchronization instruction taking at least one operand which selects one of a plurality of available modes each specifying a different membership of said group from amongst a plurality of different available groupings, wherein the execution unit on each respective tile is configured so as in response to the opcode of the synchronization instruction to cause a synchronization request to be transmitted from the respective tile to the synchronization logic in the interconnect, and to suspend instruction issue on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic; and the synchronization logic is configured so as, in response to receiving the synchronization request from all of the tiles of said group as specified by the operand of the synchronization instruction, to return the synchronization acknowledgment back to each of the tiles in the group and thereby allow the instruction issue to resume on each of the tiles in said group.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 2.23077
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15886185', '15886138', '15886099', '15885955', '15886340']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6549915617687555
- 35 USC 102 Novelty (BERT): 0.5560640779824674
- Combined Prediction Score: 0.6450988133901268
- Mean Citation Score: 380.575198
- Max Citation Score: 433.3508
- Similarity Product: 414.937153873682

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test