PATENT CLAIM ANALYSIS

Application Number: 16038738
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "222000"]

Abstract:
In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.

Claim (Index 15):
A data processing system, comprising:\n a memory accessing agent for providing memory access requests for a memory; a memory system coupled to the memory accessing agent; and a memory controller coupled to the memory system and the memory accessing agent, the memory controller comprising:\n a command queue for storing memory access commands received from the memory accessing agent; \n an arbiter for selectively picking memory accesses from the command queue according to a first type of access and a second type of access, wherein each type of access corresponds to a different page status of a bank in the memory; and \n a final arbiter that arbitrates based on input received from a refresh logic circuit that generates a refresh command to the bank of the memory and provides a priority indicator with the refresh command, whose value is set according to a number of pending refreshes, to selectively order the refresh command with respect to a first type of access and a second type of access, \n wherein the memory controller assigns the priority indicator one of a first priority status and a second priority status, and elevates the refresh command between the first type of access and the second type of access in response to the first priority status.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 2.58621
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15408126', '15164721', '15211815', '15272626', '15252889']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7824967004428535
- 35 USC 102 Novelty (BERT): 0.5106354482526381
- Combined Prediction Score: 0.7553105752238319
- Mean Citation Score: 279.052524
- Max Citation Score: 310.9701
- Similarity Product: 252.36419539783

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test