PATENT CLAIM ANALYSIS

Application Number: 16174905
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["257", "139000"]

Abstract:
In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p + -type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p + -type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.

Claim (Index 1):
A semiconductor device comprising:\n an active region through which main current flows, the active region provided in a semiconductor substrate of a first conductivity type; a termination region surrounding a periphery of the active region; a first semiconductor region of a second conductivity type provided in the active region, in a surface layer on a first main surface side of the semiconductor substrate; a second semiconductor region of the first conductivity type selectively provided in the first semiconductor region; a third semiconductor region of the second conductivity type selectively provided in the first semiconductor region, the third semiconductor region having an impurity concentration that is higher than an impurity concentration of the first semiconductor region; a fourth semiconductor region of the second conductivity type selectively provided in the termination region, in the surface layer on the first main surface side of the semiconductor substrate; a fifth semiconductor region of the first conductivity type that is a region of the semiconductor substrate excluding the first semiconductor region and the fourth semiconductor region; a gate insulating film provided in contact with a region of the first semiconductor region, the region between the fifth semiconductor region and the second semiconductor region; a gate electrode provided opposing the first semiconductor region, across the gate insulating film; an interlayer insulating film provided on a first main surface of the semiconductor substrate and covering the second semiconductor region, the third semiconductor region, the fourth semiconductor region and the gate electrode; a first contact hole opened in the interlayer insulating film and exposing the second semiconductor region and the third semiconductor region; a plurality of second contact holes opened in the interlayer insulating film, each of the plurality of second contact holes selectively exposing the fourth semiconductor region; a first metal film provided along inner walls of the plurality of second contact holes, the first metal film having a high adhesive property with the semiconductor substrate and forming an ohmic contact with the semiconductor substrate; a second metal film embedded on the first metal film, in the plurality of second contact holes; a first electrode provided on the interlayer insulating film and electrically connected with the first semiconductor region via the second semiconductor region and the third semiconductor region, in the first contact hole, the first electrode further electrically connected with the fourth semiconductor region via the second metal film and the first metal film, in the plurality of second contact holes; and a second electrode provided at a second main surface of the semiconductor substrate.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 2.33333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14176610', '14450836', '15997621', '15878841', '15897162']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9088892631290126
- 35 USC 102 Novelty (BERT): 0.4952801229318181
- Combined Prediction Score: 0.8675283491092932
- Mean Citation Score: 259.57274200000006
- Max Citation Score: 263.29153
- Similarity Product: 232.5442711240673

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test