PATENT CLAIM ANALYSIS

Application Number: 15887166
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185230"]

Abstract:
An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Claim (Index 5):
The device of  claim 4 , wherein the resistor in the variable resistance cells comprises a buried implant resistor.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 88.0
- Lexical Diversity: 2.0625
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12314965', '11006638', '15249845', '11785311', '15293782']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8213824317210873
- 35 USC 102 Novelty (BERT): 0.4879013966190276
- Combined Prediction Score: 0.7880343282108813
- Mean Citation Score: 198.67412600000003
- Max Citation Score: 202.75536
- Similarity Product: 136.39219884856223

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test