PATENT CLAIM ANALYSIS

Application Number: 16196366
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Claim (Index 1):
A method for manufacturing a semiconductor device comprising:\n forming a plurality of lower conductive lines extending in a first direction over a semiconductor substrate; forming an insulating layer overlying the plurality of lower conductive lines; forming a plurality of first vias by forming first openings in the insulating layer and filling the first openings with a conductive material; forming a plurality of second vias by forming second openings in the insulating layer and filling the second openings with a conductive material; forming a plurality of first upper conductive lines extending in a second direction crossing the first direction and connected to the plurality of first vias; and forming a plurality of second upper conductive lines extending in the second direction and connected to the plurality of second vias, wherein: the forming the plurality of first vias and forming the plurality of second vias are performed by separate pattering operations, in at least one of the forming the first openings and forming the second openings, at least a part of two lines of the plurality of lower conductive lines are exposed in at least one opening, so that at least one via connects the at least two lines of the plurality of lower conductive lines and one line of the plurality of first or second upper conductive lines, the plurality of first upper conductive lines and the plurality of second upper conductive lines are alternately arranged with a first pitch in the first direction, and the plurality of first vias are disposed with a second pitch in the first direction, the second pitch being twice the first pitch.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 3.22449
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15061627', '16116412', '15812119', '16015714', '16116421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.908630835618373
- 35 USC 102 Novelty (BERT): 0.4572741154821091
- Combined Prediction Score: 0.8634951636047467
- Mean Citation Score: 147.224448
- Max Citation Score: 184.24911
- Similarity Product: 162.6605802674675

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test