PATENT CLAIM ANALYSIS

Application Number: 16233283
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "156000"]

Abstract:
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Claim (Index 20):
The method of  claim 16 , wherein determining the average of output values from the TDC comprises determining the average of the TDC's output values after changing to the second reference clock.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.95652
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16227777', '16226938', '16218970', '12956498', '12874462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.801921409196874
- 35 USC 102 Novelty (BERT): 0.5214560320502512
- Combined Prediction Score: 0.7738748714822118
- Mean Citation Score: 252.211654
- Max Citation Score: 322.83585
- Similarity Product: 256.02306297011376

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test