PATENT CLAIM ANALYSIS

Application Number: 16057211
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["327", "109000"]

Abstract:
In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage.

Claim (Index 4):
The apparatus of  claim 1 , wherein the n-channel FET comprises an n-channel drain extended MOS (DEMOS) transistor.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 3.29787
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12330828', '13438927', '12754176', '14700431', '10825481']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7757055045079377
- 35 USC 102 Novelty (BERT): 0.4893219829795079
- Combined Prediction Score: 0.7470671523550948
- Mean Citation Score: 176.737392
- Max Citation Score: 181.41965
- Similarity Product: 116.24679097115992

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test