PATENT CLAIM ANALYSIS

Application Number: 15909404
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["365", "185030"]

Abstract:
A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.

Claim (Index 15):
A semiconductor memory device, comprising:\n a plurality of memory cells that store first data values for multiple bits according to a first threshold voltage and second data values for the multiple bits according to a second threshold voltage higher than the first threshold voltage; a plurality of word lines and plurality of bit lines connected to the plurality of memory cells, each memory cell being respectively connected to one word line and one bit line; and a controller configured to write data to the plurality of memory cells in a write operation including a program loop with a verification operation following a program operation, wherein during the verification operation, the controller is configured to: while a first verification voltage is being applied to a word line connected to a first memory cell, apply a first voltage to a bit line connected to the first memory cell, and apply a second voltage lower than the first voltage to a bit line connected to a second memory cell that is connected to the word line, and directly after applying the first verification voltage, apply a second verification voltage to the word line, the second verification voltage being higher than the first verification voltage, and while applying the second verification voltage to the word line:\n apply the first voltage to the bit line connected to first memory cell and the bit line connected to the second memory cell if the first memory cell passes verification at the first verification voltage, and \n apply the second voltage to the bit line connected to the first memory cell and the first voltage to the bit line connected to the memory cell if the first memory cell fails verification at the first verification voltage.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.51282
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15405098', '15690256', '15908449', '15195560', '14630505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7739154330668759
- 35 USC 102 Novelty (BERT): 0.4984950755499095
- Combined Prediction Score: 0.7463733973151793
- Mean Citation Score: 251.253478
- Max Citation Score: 284.98608
- Similarity Product: 245.0711992611409

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test