PATENT CLAIM ANALYSIS

Application Number: 16189443
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-10
Patent Classification: ["365", "174000"]

Abstract:
A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.

Claim (Index 10):
A semiconductor memory device comprising:\n a plurality of sampling circuits for outputting memory output data as sampling data in response to rising timings of at least two different sampling timing signals; and a data arrangement circuit for arranging the sampling data and for outputting arrangement data.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 98.0
- Lexical Diversity: 3.56667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16013307', '12187803', '11036393', '10516093', '11505328']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7819064202714998
- 35 USC 102 Novelty (BERT): 0.4484958448204181
- Combined Prediction Score: 0.7485653627263916
- Mean Citation Score: 159.73990199999997
- Max Citation Score: 165.47968999999995
- Similarity Product: 139.32281382796046

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test