PATENT CLAIM ANALYSIS

Application Number: 15958050
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "192000"]

Abstract:
A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.

Claim (Index 2):
The semiconductor device of  claim 1 , further comprising:\n a gate structure on the nanosheet stack, the gate structure including a metal gate having a first and a second gate sidewall; a first outer spacer formed on the first gate sidewall of the metal gate; a second outer spacer formed on the second gate sidewall of the metal gate; a first epitaxy region on a first portion of the substrate; a second epitaxy region on a second portion of the substrate; an interlayer dielectric (ILD) on the first epitaxy region, the second epitaxy region and the first and second outer spacers.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 1.97826
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15332440', '15241772', '15846447', '15404469', '15846461']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9316860836784052
- 35 USC 102 Novelty (BERT): 0.5377005475190474
- Combined Prediction Score: 0.8922875300624696
- Mean Citation Score: 349.55350400000015
- Max Citation Score: 388.84467
- Similarity Product: 306.4206968974918

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test