PATENT CLAIM ANALYSIS

Application Number: 15884903
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "368000"]

Abstract:
A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Claim (Index 10):
The method of  claim 9 , further comprising forming the source region and the drain region extending into the substrate a second depth, wherein the second depth is greater than the first depth.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 2.24638
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12367988', '12979890', '13594772', '15171136', '13289051']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9081241538231108
- 35 USC 102 Novelty (BERT): 0.4885867395218738
- Combined Prediction Score: 0.866170412392987
- Mean Citation Score: 169.78888999999995
- Max Citation Score: 185.27148
- Similarity Product: 123.70624068624971

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test