PATENT CLAIM ANALYSIS

Application Number: 16240570
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "329000"]

Abstract:
Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Claim (Index 19):
The semiconductor device of  claim 11 , wherein the vertical source/drain contact and the vertical gate contact are formed of tungsten.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 99.0
- Lexical Diversity: 3.05882
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15635944', '15198644', '15431807', '15140763', '15804303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9402772209442314
- 35 USC 102 Novelty (BERT): 0.5877785767973164
- Combined Prediction Score: 0.90502735652954
- Mean Citation Score: 393.652776
- Max Citation Score: 556.5128
- Similarity Product: 397.8748929992677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test