PATENT CLAIM ANALYSIS

Application Number: 16120030
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-06
Patent Classification: ["327", "536000"]

Abstract:
An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

Claim (Index 1):
An electronic device, comprising:\n a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes:\n a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, \n a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor, \n a first controller switch operably coupled to the controller capacitor, the first controller switch including a first portion, a second portion, and a gate portion, wherein the first portion is directly connected to the source voltage and the second portion is directly connected to the controller capacitor, \n a second controller capacitor directly connected to the gate portion of the first controller switch, and \n a second controller switch including a further first portion, a further second portion, and a further gate portion, wherein the further first portion is directly connected to the source voltage, the further second portion is directly connected to the second controller capacitor and the gate portion of the first controller switch, and the further gate portion is directly connected to the controller capacitor and the second portion for receiving the gate signal; and \n a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than the boosted intermediate voltage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 2.93617
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15849052', '15849098', '16113037', '15849137', '16022444']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7987644238528684
- 35 USC 102 Novelty (BERT): 0.5737348361248784
- Combined Prediction Score: 0.7762614650800694
- Mean Citation Score: 349.802602
- Max Citation Score: 485.10675
- Similarity Product: 413.54880170193314

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test