PATENT CLAIM ANALYSIS

Application Number: 16217956
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["716", "112000"]

Abstract:
Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

Claim (Index 9):
The method of  claim 7 , further comprising:\n identifying one or more parameters of the reference curve from the source netlist; using the parameters to translate the reference curve into coordinates; and writing the coordinates into the extracted layout data.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.39024
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14693851', '14142201', '13017788', '13627933', '12708524']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3263039870163807
- 35 USC 102 Novelty (BERT): 0.4970190917508185
- Combined Prediction Score: 0.3433754974898244
- Mean Citation Score: 218.439098
- Max Citation Score: 301.26886
- Similarity Product: 210.31215505551816

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test