PATENT CLAIM ANALYSIS

Application Number: 15919746
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "676000"]

Abstract:
A power semiconductor device package includes a power semiconductor die having a first load terminal at a die frontside and a second load terminal at a die backside. The package has a package top side, a package footprint side, and a first terminal interface and a second terminal interface arranged at the package footprint side. The first terminal interface is electrically connected with the first load terminal. The die is disposed in a main cavity of an insulating core layer. A conductive material is provided at a cavity sidewall of the main cavity, and an insulation structure is provided in the main cavity. The insulation structure embeds the die, with the die backside facing the package top side. An electrical connection provided between the second load terminal and the second terminal interface is formed by at least the conductive material at the cavity sidewall.

Claim (Index 9):
The method of  claim 1 , wherein the method is part of a printed circuit board manufacturing process.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 90.0
- Lexical Diversity: 2.81818
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13432333', '14930514', '14964972', '13964153', '14642531']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919183063290806
- 35 USC 102 Novelty (BERT): 0.4987354194441786
- Combined Prediction Score: 0.8771382989061431
- Mean Citation Score: 184.22596
- Max Citation Score: 185.7608
- Similarity Product: 113.734214460659

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test