PATENT CLAIM ANALYSIS

Application Number: 15911290
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "676000"]

Abstract:
A manufacturing method of a chip package structure is provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.

Claim (Index 3):
The manufacturing method of the chip package structure according to  claim 1 , wherein the conductive frame includes a plurality of cutting marks, first cutting grooves and second cutting grooves formed on the bottom surface, the first cutting grooves intersect with the second cutting grooves to define boundaries of each of the chip package structures.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.26531
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14791310', '15135182', '15674062', '14694256', '14954981']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9306233339815618
- 35 USC 102 Novelty (BERT): 0.5133989315393276
- Combined Prediction Score: 0.8889008937373384
- Mean Citation Score: 271.74538800000005
- Max Citation Score: 310.71906
- Similarity Product: 253.1731197028184

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test