PATENT CLAIM ANALYSIS

Application Number: 16109607
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["365", "230060"]

Abstract:
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Claim (Index 2):
A method of operation in a memory controller integrated circuit (IC) chip, the method comprising:\n during an initialization mode of operation,\n receiving information from an off-chip serial presence detect (SPD) device; and \n during a memory device access mode of operation,\n transmitting a control signal to the memory device, the control signal comprising a first component of a memory access request, \n transmitting a command/address (C/A) signal to the memory device after a delay with respect to transmitting the control signal, wherein the delay is based on the information, the C/A signal comprising a second component of the memory access request.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.23529
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15626097', '14863366', '13720720', '12477703', '11252957']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7585477382066864
- 35 USC 102 Novelty (BERT): 0.4797352678370301
- Combined Prediction Score: 0.7306664911697208
- Mean Citation Score: 195.723404
- Max Citation Score: 210.8771
- Similarity Product: 164.62259487583637

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test