PATENT CLAIM ANALYSIS

Application Number: 15951441
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "618000"]

Abstract:
A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

Claim (Index 10):
The semiconductor structure of  claim 1 , wherein the organic planarizing layer is on the mandrel including the spacer material.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 3.33333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15405600', '15198843', '15677447', '15176284', '15176279']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.960323252421241
- 35 USC 102 Novelty (BERT): 0.6108320629104498
- Combined Prediction Score: 0.9253741334701618
- Mean Citation Score: 592.2194360000002
- Max Citation Score: 635.504
- Similarity Product: 477.540770026207

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test