PATENT CLAIM ANALYSIS

Application Number: 15986203
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "302000"]

Abstract:
Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing an SOI substrate with a buried insulator layer therein, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a doped layer over the SOI substrate, wherein the grown second polysilicon material and epitaxially grown doped layer form a basis for a strap merging the doped layer and the second polysilicon material.

Claim (Index 2):
The method according to  claim 1  further comprising:\n prior to filling the trench with polysilicon material, depositing a first hard mask over the substrate; \n prior to filling the trench with polysilicon material, depositing a dielectric liner along an exposed perimeter of the trench; and \n after filing the trench with the second polysilicon material, removing the first deposited hardmask.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 93.0
- Lexical Diversity: 2.01754
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12651608', '12776829', '13845506', '12048263', '13865306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9241266371180972
- 35 USC 102 Novelty (BERT): 0.5125210986855543
- Combined Prediction Score: 0.8829660832748429
- Mean Citation Score: 274.42786200000006
- Max Citation Score: 284.2069
- Similarity Product: 184.7687987679481

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test