PATENT CLAIM ANALYSIS

Application Number: 16427320
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.

Claim (Index 2):
The programmable array logic according to  claim 1 , wherein each of the first control units comprises:\n the first resistive memory, having a first terminal receiving a first control voltage, a control terminal coupled to the corresponding first signal line, and a second terminal receiving a first line bias voltage; a third resistive memory, having a first terminal receiving a second control voltage, a control terminal coupled to the corresponding first signal line, and a second terminal receiving the first line bias voltage; a first inverter, having an input terminal coupling to the corresponding first signal line and an output terminal; a first switch, having a first terminal coupled to the corresponding second signal line, a control terminal receiving the first line bias voltage, and a second terminal; and a second switch, having a first terminal coupled to the second terminal of the first switch, a control terminal coupled to the output terminal of the first inverter, and a second terminal receiving a ground voltage.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 100.0
- Lexical Diversity: 3.875
- Patent Class: nan
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15610829', '13089835', '12903152', '14677991', '13980529']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5720942813139688
- 35 USC 102 Novelty (BERT): 0.4509387611745381
- Combined Prediction Score: 0.5599787293000258
- Mean Citation Score: 162.524802
- Max Citation Score: 164.9611
- Similarity Product: 137.37251011838913

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test