PATENT CLAIM ANALYSIS

Application Number: 16276133
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "401000"]

Abstract:
A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

Claim (Index 2):
The method of  claim 1 , wherein the first source/drain region is formed under the fin structure.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.83333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16005124', '15488780', '15808124', '15413558', '15705888']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.947306454156346
- 35 USC 102 Novelty (BERT): 0.550842812353788
- Combined Prediction Score: 0.9076600899760902
- Mean Citation Score: 385.631
- Max Citation Score: 438.45352
- Similarity Product: 279.35273714876183

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test