PATENT CLAIM ANALYSIS

Application Number: 15894940
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "382000"]

Abstract:
A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.

Claim (Index 3):
The method of  claim 2 , further comprising:\n forming a contact etch stop layer (CESL) on the first spacer and the second spacer before forming the ILD layer; performing the first etching process; performing the second etching process to remove part of the CESL, part of the first spacer, and part of the second spacer; and forming the contact plug.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.02273
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15830008', '15285471', '15861700', '15172161', '14957623']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9182062133901492
- 35 USC 102 Novelty (BERT): 0.4936096373138908
- Combined Prediction Score: 0.8757465557825233
- Mean Citation Score: 233.954778
- Max Citation Score: 253.04135
- Similarity Product: 198.5056911099136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test