PATENT CLAIM ANALYSIS

Application Number: 15872230
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["326", "081000"]

Abstract:
Level-shifter circuits and methods of using the same are provided. A level-shifter circuit includes a latch unit and a level-shifting unit. The latch unit is configured to generate a latch signal for storing a logic state of a first digital signal in a first power supply domain. The level-shifting unit is configured to shift a voltage of the latch signal to output a second digital signal in a second power supply domain. The latch unit and the level-shifting unit are powered by a power supply voltage in the second power supply domain.

Claim (Index 3):
The level-shifter circuit according to  claim 2 , wherein the latch unit comprises:\n a first inverter, having an input terminal configured to receive the first digital signal and an output terminal configured to output the latch signal; and a second inverter, having an input terminal coupled to the output terminal of the first inverter and an output terminal coupled to the input terminal of the first inverter, wherein the first and second inverters are powered by the power supply voltage in the second power supply domain.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 86.0
- Lexical Diversity: 2.36585
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12037639', '15448657', '14676006', '15476003', '12629237']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7252613766620147
- 35 USC 102 Novelty (BERT): 0.4970776334995456
- Combined Prediction Score: 0.7024430023457678
- Mean Citation Score: 283.5076400000001
- Max Citation Score: 291.12076
- Similarity Product: 249.5389539300752

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test