PATENT CLAIM ANALYSIS

Application Number: 16105710
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["377", "048000"]

Abstract:
A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay includes, in part, a chain of delay elements configured to generate a multitude of delays at the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

Claim (Index 20):
The method of  claim 19 , wherein said first counter is an 8-bit down counter and wherein said second counter is a 24-bit up counter.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.68966
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15192970', '11967173', '15281617', '11891300', '12270131']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6858757404489719
- 35 USC 102 Novelty (BERT): 0.5522144654693698
- Combined Prediction Score: 0.6725096129510117
- Mean Citation Score: 258.264808
- Max Citation Score: 448.0297
- Similarity Product: 422.4141179645418

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test