PATENT CLAIM ANALYSIS

Application Number: 16107036
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Claim (Index 12):
The manufacturing method for a semiconductor device, according to  claim 11 ,\n wherein the step (c) includes the steps of (c1) depositing a metal film over each of a second part of the first projecting unit and a third part of the first projecting unit between which the first part is sandwiched in the first direction, and (c2) performing a thermal process for the metal film, thereby causing reaction between the metal film and the second part to form the first silicide layer, and causing reaction between the metal film and the third part to form the second silicide layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 96.0
- Lexical Diversity: 2.14286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16036324', '15482239', '15879257', '15626092', '15961334']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9332674300238536
- 35 USC 102 Novelty (BERT): 0.5169129072776903
- Combined Prediction Score: 0.8916319777492374
- Mean Citation Score: 291.9861420000001
- Max Citation Score: 322.3297
- Similarity Product: 265.2814397872329

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test