PATENT CLAIM ANALYSIS

Application Number: 15891352
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["327", "109000"]

Abstract:
A driving method for power semiconductor switches in an H-bridge circuit is provided. The method includes: calculating a start time and an end time of a zero level of an output voltage and determining a zero level section based on the start time and end time of the zero level; and driving an upper power semiconductor switch of a first bridge arm and an upper power semiconductor switch of a second bridge arm to be on simultaneously or driving a lower power semiconductor switch of the first bridge arm and a lower power semiconductor switch of the second bridge arm to be on simultaneously in the zero level section.

Claim (Index 1):
A driving method for power semiconductor switches in an H-bridge circuit, characterized in that the H bridge circuit comprises a first bridge arm, a second bridge arm and a bus capacitor, both the first bridge arm and the second bridge arm are connected to the bus capacitor in parallel, wherein each of the first bridge arm and the second bridge arm comprises an upper power semiconductor switch and a lower power semiconductor switch, an output voltage is generated between a connection point connecting the upper power semiconductor switch with the lower power semiconductor switch in the first bridge arm and a connection point connecting the upper power semiconductor switch with the lower power semiconductor switch in the second bridge arm; the driving method comprises:\n calculating a start time and an end time of a zero level of the output voltage and determining a zero level section based on the start time and the end time of the zero level; driving the upper power semiconductor switch of the first bridge arm and the upper power semiconductor switch of the second bridge arm to be on simultaneously or driving the lower power semiconductor switch of the first bridge arm and the lower power semiconductor switch of the second bridge arm to be on simultaneously in the zero level section; wherein each of a first preset duration and a second preset duration comprises at least one zero level section; the upper power semiconductor switch of the first bridge arm and the upper power semiconductor switch of the second bridge arm and the lower power semiconductor switch of the first bridge arm and the lower power semiconductor switch of the second bridge arm are turned on with a first turning-on logic sequence in the zero level section within the first preset duration; and the upper power semiconductor switch of the first bridge arm and the upper power semiconductor switch of the second bridge arm and the lower power semiconductor switch of the first bridge arm and the lower power semiconductor switch of the second bridge arm are turned on with a second turning-on logic sequence in the zero level section within the second preset duration.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.51111
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13705029', '14719334', '15541633', '12972794', '15145610']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7489181194113435
- 35 USC 102 Novelty (BERT): 0.4736052872521397
- Combined Prediction Score: 0.7213868361954231
- Mean Citation Score: 182.235932
- Max Citation Score: 185.80693
- Similarity Product: 149.48684417709168

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test