PATENT CLAIM ANALYSIS

Application Number: 16234319
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-08
Patent Classification: ["365", "145000"]

Abstract:
Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

Claim (Index 28):
An apparatus comprising:\n a first bitline extending horizontally; a second bitline being offset vertically from the first bitline and extending horizontally in parallel to the first bitline; a common plate extending horizontally between the first and second bitlines; a plurality of first memory cell structures disposed horizontally between the first bitline and the common plate, each of the plurality of first memory cell structures including a first access device and a first capacitor coupled in series between the first bitline and the common plate; a plurality of second memory cell structures disposed horizontally between the second bitline and the common plate, each of the plurality of second memory cell structures including a second access device and a second capacitor coupled in series between the second bitline and the common plate; a first sense amplifier coupled to the first bitline; a second sense amplifier coupled to the second bitline; a third bitline extending horizontally; a plurality of third memory cell structures each coupled to the third bitline; a fourth bitline extending horizontally; and a plurality of fourth memory cell structures each coupled to the fourth bitline; wherein the first sense amplifier is further coupled to the third bitline to compare the first and third bitlines with each other; and wherein the second sense amplifier is further coupled to the fourth bitline to compare the third and fourth bitlines with each other.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 3.08333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15900403', '16183528', '15797462', '15664143', '15986628']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8106326277079005
- 35 USC 102 Novelty (BERT): 0.5080147570839048
- Combined Prediction Score: 0.7803708406455009
- Mean Citation Score: 261.35137799999995
- Max Citation Score: 317.9322
- Similarity Product: 244.17001774860623

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test