PATENT CLAIM ANALYSIS

Application Number: 15958018
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["235", "462010"]

Abstract:
A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.

Claim (Index 16):
The semiconductor device of  claim 15 , wherein the second semiconductor region is an n-field effect transistor (nFET) region comprising:\n Si material that defines the second semiconductor channel; and a second set of spacers extending from the top surface of the Si material, wherein a region between the second set of spacers defines a second gate, and wherein the second gate includes a second high-k dielectric layer in contact with the second set of spacers, and a second metal gate material in contact with the second high-k dielectric layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.48936
- Patent Class: 235.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15603982', '15958021', '15275565', '15933949', '15412499']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6457636412891244
- 35 USC 102 Novelty (BERT): 0.5679255720203885
- Combined Prediction Score: 0.6379798343622509
- Mean Citation Score: 392.810968
- Max Citation Score: 480.60648
- Similarity Product: 452.82969094911584

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test