PATENT CLAIM ANALYSIS

Application Number: 16049545
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Claim (Index 36):
A method of manufacturing a semiconductor device, the method comprising:\n forming a first dummy gate structure and a second dummy gate structure over a substrate, the first and second and third dummy gate structures extending in a first lateral direction, each of the first and second including a dummy gate dielectric layer, a dummy gate electrode layer and sidewall spacers, a width along a second lateral direction perpendicular to the first lateral direction of the second gate electrode is greater than a width along the second lateral direction of the first gate electrode; forming an etching stop layer over the first and second dummy gate structures and the source/drain region; forming a first interlayer dielectric (ILD) layer over the etching stop layer; forming a first gate space and a second gate space by removing the dummy gate electrode layer and the dummy gate dielectric layer from the first and second dummy gate structures, respectively; forming a gate dielectric layer in the first and second gate spaces and over upper portions of the first ILD layer, the etching stop layer and the sidewall spacers;\n forming a first metal layer on the gate dielectric layer in the first gate space; \n forming a second metal layer on the gate dielectric layer in the second gate space and on the first metal layer in the second gate space; after forming the first and second metal layers, fully filling the first and second gate spaces with a third metal layer; forming a first gate recess by removing upper portions of the first, second and third metal layers formed in the first gate space, and forming a second gate recess by removing upper portions of the first and third metal layers formed in the second gate space; forming a first gate electrode and a second gate electrode by forming fourth metal layers on tops of the first, second and third metal layers, from which the upper portions have been removed, in the first gate recess and on tops of the first and third metal layers, from which the upper portions have been removed, in the second gate recess; and forming cap insulating layers over the fourth metal layers in the first and second gate recess, wherein: the cap insulating layers are in contact with the gate dielectric layer, respectively, and when the third metal layer is formed, the gate dielectric layer formed over upper portions of the first ILD layer, the etching stop layer and the sidewall spacers is removed.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.91176
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15063346', '15068409', '15649909', '14925857', '15699643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8935369520782022
- 35 USC 102 Novelty (BERT): 0.4764618139491861
- Combined Prediction Score: 0.8518294382653006
- Mean Citation Score: 175.021682
- Max Citation Score: 215.15446
- Similarity Product: 190.63861935843585

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test