PATENT CLAIM ANALYSIS

Application Number: 16504248
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.

Claim (Index 15):
An integrated circuit comprising:\n an array of logic tiles, wherein each logic tile of the array of logic tiles includes:\n at least one input clock path, wherein the input clock path includes circuitry which is configurable to receive a clock signal, \n a plurality of output clock paths, wherein each output clock path includes circuitry which is configurable to transmit a tile output clock signal to one or more logic tiles of the array of logic tiles which is/are adjacent thereto, \n tile clock generation circuitry, coupled to the input clock path, configurable to generate a tile clock, having a skew, and \n circuitry, coupled to the tile clock generation circuitry, to perform operations using or based on the tile clock; and \n wherein the array of logic tiles includes a plurality of columns of logic tiles and a plurality of rows of logic tiles, including:\n a first row of logic tiles, wherein each logic tile of the first row of logic tiles receives a first external clock signal at an input of the associated at least one input clock path and wherein each logic tile of a first plurality of logic tiles of the array of logic tiles is configurable to generate its tile clock using (i) the first external clock signal received by a logic tile of the first row of logic tiles or (ii) a delayed version of the first external clock signal received from one of the plurality of output clock paths of at least one logic tile of the first row of logic tiles, wherein the logic tiles of the first row of logic tiles are a portion of the first plurality of logic tiles, and \n a second row of logic tiles, wherein each logic tile of the second of logic tiles receives a second external clock signal at an input of the associated at least one input clock path and wherein each logic tile of a second plurality of logic tiles of the array of logic tiles is configurable to generate its tile clock using (i) the second external clock signal received by a logic tile of the second row of logic tiles or (ii) a delayed version of the second external clock signal received from one of the plurality of output clock paths of at least one logic tile of the second row of logic tiles, wherein the logic tiles of the second row of logic tiles are a portion of the second plurality of logic tiles, and wherein:\n the logic tiles of the first plurality of logic tiles are different from the logic tiles of the second plurality of logic tiles, \n at least one of the logic tiles of the first plurality of logic tiles generates its tile clock using a delayed version of the first external clock signal received from one of the plurality of output clock paths of a logic tile in the first row of logic tiles, \n at least one of the logic tiles of the second plurality of logic tiles generates its tile clock using a delayed version of the second external clock signal received from one of the plurality of output clock paths of a logic tile in the second row of logic tiles, and \n \n the first and second external clock signals have the same clock frequency and zero skew with respect to each other.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.375
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15996430', '16009656', '14712864', '15347045', '14972553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7040976996405365
- 35 USC 102 Novelty (BERT): 0.5860241933855126
- Combined Prediction Score: 0.6922903490150341
- Mean Citation Score: 431.059484
- Max Citation Score: 486.68964000000005
- Similarity Product: 472.1958917623186

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test