PATENT CLAIM ANALYSIS

Application Number: 16228392
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["341", "122000"]

Abstract:
A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).

Claim (Index 16):
A method for converting an analog input to a digital output using an area efficient successive-approximation-register analog-to-digital converter (SAR ADC) with signal-independent bit weights, and the method comprises:\n sampling the analog input onto first bit capacitors corresponding to a first bit trial, sampling the analog input onto second bit capacitors corresponding to a second bit trial; during a time that the analog input is being sampled, charging a first on-chip reference capacitor corresponding to the first bit trial to a reference voltage, and charging a second on-chip reference capacitor corresponding to the second bit trial to the reference voltage; and making a plurality of decisions by a comparator in response to the first on-chip reference capacitor being connected to the first bit capacitors, and in response to the second on-chip reference capacitor being connected to the second bit capacitors.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 1.88506
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14949423', '14747071', '16032752', '13085920', '13234595']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6691174821431279
- 35 USC 102 Novelty (BERT): 0.6017612446027802
- Combined Prediction Score: 0.6623818583890931
- Mean Citation Score: 398.0179
- Max Citation Score: 521.1347
- Similarity Product: 468.7826299793184

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test