PATENT CLAIM ANALYSIS

Application Number: 15877283
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "659000"]

Abstract:
Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

Claim (Index 1):
An integrated circuit (IC) package, comprising:\n a die that includes a plurality of bump sites; and a substrate connected to the die at the plurality of bump sites, the substrate including at least one layer that implements one or more signal traces and a plurality of shield traces, wherein each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 1.78723
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13493632', '14543838', '10825747', '13685385', '11930217']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9145849604471412
- 35 USC 102 Novelty (BERT): 0.4825808726676931
- Combined Prediction Score: 0.8713845516691963
- Mean Citation Score: 186.558532
- Max Citation Score: 205.77136
- Similarity Product: 153.99741598163604

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test