PATENT CLAIM ANALYSIS

Application Number: 15991020
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["327", "156000"]

Abstract:
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Claim (Index 6):
A time-to-digital converter circuit, comprising:\n a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal, the logic pate to generate a logic gate output signal responsive to the earliest of the first or second trigger signals to be a logic high; a synchronization circuit coupled to the logic gate and configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal; a counter circuit to count pulses of the synchronization output signal; a first trigger circuit to receive the first clock and the third clock and to generate the first trigger signal, wherein the first trigger circuit is to assert the first trigger signal responsive to an asserted edge of the third clock coincident with the first clock asserted high; a second trigger circuit to receive the second clock and the third clock and to generate the second trigger signal, wherein the second trigger circuit is to assert the second trigger signal responsive to an asserted edge of the third clock coincident with the second clock asserted high; and a first flip-flop including a first data input and a first flip-flop clock input, the first data input coupled to receive the first trigger signal and the first flip-flop clock input coupled to receive the second trigger signal; and a second flip-flop including a second data input and a second flip-flop clock input, the second data input coupled to receive the second trigger signal and the second flip-flop clock input coupled to receive the first trigger signal.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 93.0
- Lexical Diversity: 2.625
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15183752', '10839201', '15675160', '12018770', '13380392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7740381919497422
- 35 USC 102 Novelty (BERT): 0.4611646378036987
- Combined Prediction Score: 0.7427508365351378
- Mean Citation Score: 171.15700599999997
- Max Citation Score: 173.64496
- Similarity Product: 140.1528109359169

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test