PATENT CLAIM ANALYSIS

Application Number: 16019464
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["365", "154000"]

Abstract:
A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

Claim (Index 6):
The data line control circuit of  claim 1 , wherein the third voltage level is identical to the second voltage level, and the data line driving circuit comprises:\n a first driving circuit, comprising:\n a first P-channel metal-oxide-semiconductor (PMOS) transistor, wherein a source of the first PMOS transistor is coupled to the first voltage level, a drain of the first PMOS transistor is coupled to said one of the first data line and the second data line, and a gate of the first PMOS transistor is arranged to receive a first control signal; and \n a first N-channel metal-oxide-semiconductor (NMOS) transistor, wherein a drain of the first NMOS transistor is coupled to said one of the first data line and the second data line, and a gate of the first NMOS transistor is arranged to receive the first control signal; \n a second driving circuit, comprising:\n a second PMOS transistor, wherein a source of the second PMOS transistor is coupled to the first voltage level, a drain of the second PMOS transistor is coupled to said another of the first data line and the second data line, and a gate of the second PMOS transistor is arranged to receive a second control signal; and \n a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to said another of the first data line and the second data line, and a gate of the second NMOS transistor is arranged to receive the second control signal; and \n a third NMOS transistor, wherein a gate of the third NMOS transistor is arranged to receive a third control signal, a source of the third NMOS transistor is coupled to the second voltage level, and a drain of the third NMOS transistor is coupled to both of a source of the first NMOS transistor and a source of the second NMOS transistor.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.9375
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13836902', '12496976', '14692126', '15134981', '13354884']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8042228447532416
- 35 USC 102 Novelty (BERT): 0.476998977591125
- Combined Prediction Score: 0.7715004580370299
- Mean Citation Score: 236.399404
- Max Citation Score: 238.03113
- Similarity Product: 195.4427348157156

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test