PATENT CLAIM ANALYSIS

Application Number: 16218149
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "773000"]

Abstract:
Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

Claim (Index 11):
The semiconductor integrated circuit device of  claim 10 , wherein\n a third pad row comprised of a plurality of external connection pads is provided between the first and second pad rows, the plurality of external connection pads of the third pad row being connected to an outside of the semiconductor integrated circuit device.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 98.0
- Lexical Diversity: 2.45098
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15493321', '15493338', '15982766', '12268904', '12872678']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92884467380807
- 35 USC 102 Novelty (BERT): 0.5207546905832048
- Combined Prediction Score: 0.8880356754855834
- Mean Citation Score: 289.085826
- Max Citation Score: 341.69073
- Similarity Product: 325.6888444700968

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test