PATENT CLAIM ANALYSIS

Application Number: 15745396
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["711", "154000"]

Abstract:
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

Claim (Index 19):
The registering clock driver of  claim 18 , wherein the logic selectively disables the one of the first and second secondary chip-select interfaces responsive to the primary chip-select signals.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 86.0
- Lexical Diversity: 2.01852
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15262741', '15610001', '15260880', '15522182', '15552569']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5542749656197544
- 35 USC 102 Novelty (BERT): 0.5007687144217863
- Combined Prediction Score: 0.5489243404999576
- Mean Citation Score: 223.718738
- Max Citation Score: 243.826
- Similarity Product: 166.2741839107275

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test