PATENT CLAIM ANALYSIS

Application Number: 15984664
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-02
Patent Classification: ["330", "257000"]

Abstract:
An envelope tracking (ET) bias circuit includes an envelope tracking (ET) bias circuit includes an envelope detection circuit, an envelope amplifier circuit, and an envelope output circuit. The envelope detection circuit is configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal. The envelope amplifier circuit is configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled. The envelope output circuit is configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal.

Claim (Index 5):
The envelope tracking bias circuit of  claim 3 , wherein the amplifier comprises a first amplifier having a non-inverting input terminal receiving a first signal of the differential envelope signal through a first resistor, and an inverting input terminal configured to receive a second signal of the differential envelope signal through a second resistor,\n the first amplifier is configured to receive a second signal of a DC offset cancel signal from the DC offset cancelling circuit through a third resistor and the non-inverting input terminal, and receive a first signal of the DC offset cancel signal through a fourth resistor and the inverting input terminal, and the first amplifier comprises:\n a fifth resistor connected between the non-inverting input terminal and a second output terminal; \n a sixth resistor connected between the inverting input terminal and a first output terminal; \n a first capacitor connected between the non-inverting input terminal and the second output terminal; and \n a second capacitor connected between the inverting input terminal and the first output terminal.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 2.86538
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15810764', '15719843', '15875463', '14754118', '15479323']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8127744787979806
- 35 USC 102 Novelty (BERT): 0.5153207715002307
- Combined Prediction Score: 0.7830291080682056
- Mean Citation Score: 265.608286
- Max Citation Score: 309.43185
- Similarity Product: 253.01204880588952

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test