PATENT CLAIM ANALYSIS

Application Number: 16211589
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "156000"]

Abstract:
In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Claim (Index 13):
A semiconductor memory device comprising:\n an array of semiconductor memory cells arranged in rows and columns, wherein the array includes a first segment of memory cells and a second segment of memory cells, each memory cell including an access transistor coupled to a data storage element of the memory cell; a first conductive line extending over the first segment of memory cells and coupled to multiple access transistors of multiple memory cells within the first segment of memory cells; a second conductive line extending over the second segment of memory cells and generally in parallel with the first conductive line, the second conductive line coupled to multiple access transistors of multiple memory cells within the second segment of memory cells; a third conductive line extending over the second segment of memory cells and generally in parallel with the first conductive line, the third conductive line isolated from the memory cells of the second segment; and a switch arranged between the first and second segments of memory cells and configured to selectively couple the first conductive line in series with the third conductive line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.25532
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15911824', '15871484', '15627837', '16108672', '15388991']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7482486329769167
- 35 USC 102 Novelty (BERT): 0.4942292881241188
- Combined Prediction Score: 0.7228466984916369
- Mean Citation Score: 192.322156
- Max Citation Score: 286.12042
- Similarity Product: 271.13869485546826

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test