PATENT CLAIM ANALYSIS

Application Number: 15922901
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["326", "080000"]

Abstract:
An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.

Claim (Index 1):
An isolation cell connected between first and second circuit modules, wherein the first and second circuit modules comprise different power domains, the isolation cell comprising:\n an input terminal configured to receive an input signal from the first circuit module; an output terminal configured to provide an output signal to the second circuit module; a control terminal configured to receive a control signal, wherein the isolation cell generates the output signal from the input signal in response to the control signal; a first power terminal coupled with a first voltage supply of the first circuit module; a second power terminal coupled with a second voltage supply of the second circuit module; a first inverter having an input coupled to the control terminal for receiving the control signal, wherein the first inverter is coupled with the first power terminal and powered by the first voltage supply; and a second inverter having an output coupled to the output terminal for providing the output signal thereto, wherein the second inverter also is powered by the first voltage supply wherein the first inverter comprises: a first PMOS transistor having a gate terminal coupled with the control terminal for receiving the control signal, a source terminal coupled with the first power terminal, and a drain terminal; a first NMOS transistor having a gate terminal coupled with the control terminal, a drain terminal coupled with the drain terminal of the first PMOS transistor, and a source terminal; and a second NMOS transistor having a gate terminal coupled with the control terminal, a drain terminal coupled with the source terminal of the first NMOS transistor, and a source terminal connected to ground, wherein a node between the drain terminals of the first PMOS transistor and the first NMOS transistor provides an output of the first inverter; and wherein the second inverter comprises: a second PMOS transistor having a gate terminal coupled to receive an intermediate input signal, a source terminal coupled with the first power terminal, and a drain terminal; and a third NMOS transistor having a gate terminal coupled with the gate terminal of the second PMOS transistor, a drain terminal coupled with the drain terminal of the second PMOS transistor, and a source terminal connected to ground, wherein a node between the drain terminals of the second PMOS transistor and the third NMOS transistor is coupled to the output terminal.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 1.94444
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15857214', '15687781', '15826273', '15872230', '14658353']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6728113088149151
- 35 USC 102 Novelty (BERT): 0.4732055065456945
- Combined Prediction Score: 0.6528507285879931
- Mean Citation Score: 218.193646
- Max Citation Score: 224.65376
- Similarity Product: 185.84490415943145

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test