PATENT CLAIM ANALYSIS

Application Number: 15876059
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["375", "260000"]

Abstract:
Systems and methods for application specific integrated circuit design using Chronos links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Claim (Index 1):
A system for communicating between intellectual property blocks, the system comprising:\n a communication channel communicatively coupled between a first intellectual property block and a second intellectual property block for transmission of data between the first and second intellectual property blocks; a slave controller communicatively coupled between the first intellectual property block and the communication channel, the slave controller comprising:\n a slave synchronizer circuit configured to receive a first asynchronous signal from the communication channel and transform the received first asynchronous signal into a synchronous domain for controlling the transmission of data according to a first protocol of the first intellectual property block, and \n a slave digital logic circuit configured to create a first control signal and, using digital logic, regulate the transmission of data into the communication channel; and \n a master controller communicatively coupled between the communication channel and the second intellectual property block, the master controller comprising:\n a master synchronizer configured to receive a second asynchronous signal from the communication channel and transform the received second asynchronous signal into the synchronous domain for controlling the transmission of data according to a second protocol of the second intellectual property block, and \n a master digital logic circuit configured to create a second control signal and, using digital logic, regulate the transmission of data out from the communication channel.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 1.45455
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15344420', '15344441', '15344416', '15876047', '15644696']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4902609443674729
- 35 USC 102 Novelty (BERT): 0.5566057820827762
- Combined Prediction Score: 0.4968954281390033
- Mean Citation Score: 278.441596
- Max Citation Score: 464.2145
- Similarity Product: 316.3602254169583

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test