PATENT CLAIM ANALYSIS

Application Number: 15759420
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["345", "213000"]

Abstract:
A shift register includes an input circuit configured to control a voltage of a first and second node, a hold circuit configured to hold the voltage of the first and second nodes as well as an output voltage of the first and second output circuits, an output selection circuit configured to select the first and second outputs to output a scanning signal, a first output circuit configured to output a first output signal from a first output terminal based on the voltage of the first and third nodes, a second output circuit is configured to output a second output signal from a second output terminal based on the voltage of the first and fourth nodes, and a third output circuit configured to output a third output signal from a third output terminal based on a second clock signal and the voltage of the second node.

Claim (Index 1):
A shift register comprising:\n an input circuit, a hold circuit, an output selection circuit, a first output circuit, a second output circuit, and a third output circuit; wherein the input circuit is configured to control a voltage of a first node and a voltage of a second node based on a start signal from an input terminal, a first clock signal from a first clock signal terminal, and a first voltage from a first voltage terminal; wherein the hold circuit is configured to hold the voltage of the first node and the voltage of the second node as well as an output signal of the first output circuit and an output signal of the second output circuit; wherein the output selection circuit is configured to select at least one of the first output circuit and the second output circuit to output a scanning signal, and control a voltage of a third node and a voltage of a fourth node based on the voltage of the second node; wherein the first output circuit is configured to output a first output signal from a first output terminal based on the voltage of the first node and the voltage of the third node; wherein the second output circuit is configured to output a second output signal from a second output terminal based on the voltage of the first node and the voltage of the fourth node; and wherein the third output circuit is configured to output a third output signal from a third output terminal based on a second clock signal from a second clock signal terminal and the voltage of the second node.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 3.87179
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15773873', '15772422', '15680441', '15750417', '15088137']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6293079677705526
- 35 USC 102 Novelty (BERT): 0.5000133208632224
- Combined Prediction Score: 0.6163785030798197
- Mean Citation Score: 262.43501000000003
- Max Citation Score: 278.2453
- Similarity Product: 248.07888590103985

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test