PATENT CLAIM ANALYSIS

Application Number: 15948016
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "347000"]

Abstract:
The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs.

Claim (Index 14):
The semiconductor device of  claim 12 , wherein said pull-down transistor elements comprise a fully depleted portion in a channel region thereof.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 1.5303
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15647403', '15706048', '15622497', '15439444', '13404759']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9268918942091888
- 35 USC 102 Novelty (BERT): 0.5086214162484062
- Combined Prediction Score: 0.8850648464131106
- Mean Citation Score: 238.112018
- Max Citation Score: 250.25142
- Similarity Product: 159.85515403904915

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test