PATENT CLAIM ANALYSIS

Application Number: 15773422
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "329000"]

Abstract:
III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.

Claim (Index 30):
The IC of  claim 29 , wherein:\n the channel region comprises undoped GaN between the drift region and the gate electrode; and the drift region has a thickness between the drain and the channel region of at least 3 \u03bcm.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 93.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15748619', '15574817', '15771985', '15505911', '15567579']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9292093068034524
- 35 USC 102 Novelty (BERT): 0.5140638922684085
- Combined Prediction Score: 0.8876947653499478
- Mean Citation Score: 253.149252
- Max Citation Score: 273.03326
- Similarity Product: 171.71554593386887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test