PATENT CLAIM ANALYSIS

Application Number: 15938393
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["365", "189090"]

Abstract:
A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.

Claim (Index 18):
The memory circuit of  claim 17 , further comprising a write circuit configured to provide the voltage level on the bit line, the write circuit being coupled with the bit line at a first location, wherein\n the first switching circuit and the second switching circuit are coupled with the bit line at a second location, and at least a portion of the plurality of memory cells is located between the first location and the second location.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.21429
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13804405', '13780772', '14659642', '15434541', '14504596']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7874697319960354
- 35 USC 102 Novelty (BERT): 0.4651545198942722
- Combined Prediction Score: 0.7552382107858591
- Mean Citation Score: 185.340002
- Max Citation Score: 191.39548
- Similarity Product: 151.2438445632386

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test