PATENT CLAIM ANALYSIS

Application Number: 16291879
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-06
Patent Classification: ["711", "104000"]

Abstract:
A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Claim (Index 8):
The semiconductor memory apparatus according to  claim 7 , wherein the sink current control unit is configured to provide a sink voltage with a higher voltage level to the current sink unit electrically coupled with the memory element close to the read/write circuit than the current sink unit electrically coupled with the memory element far from the read/write circuit.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 99.0
- Lexical Diversity: 2.69565
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14081765', '15583476', '15583543', '09982936', '14878629']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5238849483915438
- 35 USC 102 Novelty (BERT): 0.5313634864730967
- Combined Prediction Score: 0.5246328021996991
- Mean Citation Score: 270.33735
- Max Citation Score: 341.65823
- Similarity Product: 248.5690566882515

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test