PATENT CLAIM ANALYSIS

Application Number: 16011829
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["257", "031000"]

Abstract:
Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.

Claim (Index 2):
The quantum circuit assembly according to  claim 1 , wherein at least a portion of the second capacitor plate is suspended over at least a portion of the first capacitor plate.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 94.0
- Lexical Diversity: 1.46377
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15934375', '15899918', '15241783', '15827729', '10419024']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9257139679663569
- 35 USC 102 Novelty (BERT): 0.4912146192562455
- Combined Prediction Score: 0.8822640330953457
- Mean Citation Score: 234.612906
- Max Citation Score: 236.49698
- Similarity Product: 183.254748102504

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test