PATENT CLAIM ANALYSIS

Application Number: 15921813
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["717", "151000"]

Abstract:
An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.

Claim (Index 16):
The method of  claim 14 , further comprising:\n determining a first cache hit rate for the nested loop; re-ordering one or more loops of the nested loop; determining a second cache hit rate for all iterations of the re-ordered nested loop; and determining if the nested loop is the candidate for cache blocking based on a comparison of the first cache hit rate and the second cache hit rate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 1.22222
- Patent Class: 717.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12062579', '14492899', '13534794', '12062559', '12510272']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3486873620988195
- 35 USC 102 Novelty (BERT): 0.4810251215296027
- Combined Prediction Score: 0.3619211380418979
- Mean Citation Score: 122.11925
- Max Citation Score: 129.72101999999998
- Similarity Product: 90.56445678457978

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test