PATENT CLAIM ANALYSIS

Application Number: 15918668
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.

Claim (Index 17):
The method of  claim 16 , wherein in the partially etching, portions of the dielectric layer exposed to the second opening and the third opening are removed, and portions of the dielectric layer contacting the gate spacer remain.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.06977
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15225304', '15798742', '15429894', '15859893', '15610981']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9228308416591424
- 35 USC 102 Novelty (BERT): 0.504962138737924
- Combined Prediction Score: 0.8810439713670206
- Mean Citation Score: 235.043682
- Max Citation Score: 255.34213
- Similarity Product: 198.1188796842236

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test