PATENT CLAIM ANALYSIS

Application Number: 15925762
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189050"]

Abstract:
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Claim (Index 21):
The semiconductor device according to  claim 13 , further comprising:\n a memory array including a plurality of memory cells, wherein the plurality of memory cells are coupled to a plurality of bit lines and a plurality of word lines, and wherein the logic circuit receives the data signal via the first data input node and the clock signal via the clock input node, and provides the data signal to one of the plurality of bit lines.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.53333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15211298', '15607599', '15841950', '14944262', '11320751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7831669772443189
- 35 USC 102 Novelty (BERT): 0.5008827771582016
- Combined Prediction Score: 0.7549385572357072
- Mean Citation Score: 213.51475
- Max Citation Score: 289.29242
- Similarity Product: 216.9508303196907

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test