PATENT CLAIM ANALYSIS

Application Number: 16062571
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["365", "154000"]

Abstract:
A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.

Claim (Index 10):
A semiconductor storage device comprising:\n a plurality of memory cells arranged in a matrix; a word line provided corresponding to a memory cell row; a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which said word line is formed; a word driver circuit configured to drive said word line based on first and second control signals; and a dummy word driver circuit configured to increase voltage on said word line based on interline capacitance between said word line and said dummy word line based on said first and second control signals.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 2.06977
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15586870', '12457936', '10860770', '11211543', '15052188']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8015184518068258
- 35 USC 102 Novelty (BERT): 0.4756519291655079
- Combined Prediction Score: 0.7689317995426941
- Mean Citation Score: 228.563598
- Max Citation Score: 236.59569
- Similarity Product: 196.3143151662129

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test