PATENT CLAIM ANALYSIS

Application Number: 16179432
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "675000"]

Abstract:
A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

Claim (Index 1):
A method comprising:\n attaching a first metal layer of a direct-bonded copper (\u201cDBC\u201d) substrate to at least one lead with an ultrasonic weld thereby forming an assembly, wherein the ultrasonic weld mechanically and electrically couples the first metal layer to the lead, wherein the DBC substrate comprises an insulative layer disposed between the first metal layer and a second metal layer, and wherein an entire surface of the first metal layer contacts the insulative layer after the attaching; attaching one and only one power semiconductor integrated circuit die to the first metal layer of the assembly; surrounding at least the first metal layer and the one and only one power semiconductor integrated circuit die with an amount of encapsulant; leaving at least a portion of the second metal layer of the DBC substrate exposed to form a back side of a packaged power integrated circuit device; and leaving a portion of the lead exposed, wherein the second metal layer is electrically insulated from the first metal layer, and wherein the packaged power integrated circuit device comprises only one semiconductor die.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13874479', '12771643', '14556940', '14622869', '14144587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.903945219824086
- 35 USC 102 Novelty (BERT): 0.4950878014729329
- Combined Prediction Score: 0.8630594779889706
- Mean Citation Score: 232.363312
- Max Citation Score: 236.0787
- Similarity Product: 184.7338972117424

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test