PATENT CLAIM ANALYSIS

Application Number: 15865999
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "686000"]

Abstract:
The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

Claim (Index 5):
The package stack structure of  claim 1 , further comprising a second electronic component provided on the second surface of the insulating layer.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 86.0
- Lexical Diversity: 1.34375
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12136316', '13616549', '11131408', '13112253', '15621337']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9079963723860642
- 35 USC 102 Novelty (BERT): 0.4709137848103346
- Combined Prediction Score: 0.8642881136284913
- Mean Citation Score: 160.13586600000005
- Max Citation Score: 166.2758
- Similarity Product: 124.740120589149

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test