PATENT CLAIM ANALYSIS

Application Number: 15750614
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["713", "194000"]

Abstract:
A semiconductor device  100  of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits  22, 23 , and  24  having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Claim (Index 2):
A semiconductor device comprising:\n a front end; and a back end including a plurality of layers, wherein a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ) in the plurality of layers of the back end.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.24658
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15230632', '14651130', '15080650', '14775164', '13479946']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3564334448291527
- 35 USC 102 Novelty (BERT): 0.4660138287250689
- Combined Prediction Score: 0.3673914832187442
- Mean Citation Score: 134.03261400000002
- Max Citation Score: 139.68604
- Similarity Product: 103.03857995441912

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test