PATENT CLAIM ANALYSIS

Application Number: 15866156
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["365", "189011"]

Abstract:
A memory circuit having: a control circuit of a line of a memory array including: a first transistor coupled between first and second nodes and controlled by a line selection signal including a high level and a low level; a second transistor controlled by a first signal and coupled between the first node and a voltage supply rail of a first supply voltage, the first supply voltage being higher than the high level of the line selection signal, the first node being coupled to a line of memory array, the second node receiving a timing signal; and a line deactivation circuit adapted to generate the first signal and including a reference cell and a level shifter.

Claim (Index 11):
The circuit of  claim 10 , wherein each supply circuit comprises:\n a seventh transistor coupled between a supply rail at the high voltage level and a third node and controlled by a supply control signal; and an eighth transistor coupled between a supply rail at the first supply voltage and the third node and controlled by the inverse of the supply control signal, the third node being coupled to the memory cells.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.75556
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15160968', '15447853', '12786791', '12841804', '12266593']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8089899783011835
- 35 USC 102 Novelty (BERT): 0.4865252126358083
- Combined Prediction Score: 0.776743501734646
- Mean Citation Score: 200.55072
- Max Citation Score: 208.69073
- Similarity Product: 142.77794812231303

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test