PATENT CLAIM ANALYSIS

Application Number: 15937819
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["365", "226000"]

Abstract:
The disclosure is directed to a memory device and a power reduction method of the same memory device. In an aspect, the disclosure is directed to a memory device which includes not limited to a plurality of memory banks, each having a power switch, a plurality of functional blocks for reading and writing to the plurality of memory banks and include a plurality of power switches as each functional block of the plurality of function blocks has a different power switch which turns on or turns off the functional block, a mode register circuit having a plurality of mode registers which determines whether one or more of the plurality of memory banks would maintain data storage or not, and a control logic circuit for either powering on or powering off each of the plurality of memory banks and each of the plurality of the functional blocks.

Claim (Index 6):
The memory device of  claim 3 , wherein the external command comprises one of an active command, a self refresh command, a deep self refresh (DSR) command, a deep power down command, and a standby power-down command.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.5082
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14607717', '13749687', '10672244', '11169241', '15194784']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8157645489446558
- 35 USC 102 Novelty (BERT): 0.4936145212949496
- Combined Prediction Score: 0.7835495461796852
- Mean Citation Score: 218.802664
- Max Citation Score: 228.10716
- Similarity Product: 151.05581853401185

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test