PATENT CLAIM ANALYSIS

Application Number: 15939108
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "104000"]

Abstract:
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Claim (Index 14):
The device of  claim 13 , wherein the insulating layer is on the first surface of the substrate at the first doped well and the second doped well.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 1.67327
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15177231', '15482610', '14675536', '15191359', '14739634']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9361136442049264
- 35 USC 102 Novelty (BERT): 0.5302545510370505
- Combined Prediction Score: 0.8955277348881389
- Mean Citation Score: 309.350366
- Max Citation Score: 360.22787
- Similarity Product: 288.93203354943813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test