PATENT CLAIM ANALYSIS

Application Number: 15951355
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "368000"]

Abstract:
A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

Claim (Index 10):
The method of  claim 9 , wherein the second vertical transistor has a higher threshold voltage than the first vertical transistor defined by the second gate length being greater than the first gate length.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 3.33333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15918077', '15860840', '15804303', '15863000', '15488780']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.929859652574128
- 35 USC 102 Novelty (BERT): 0.5082433016523821
- Combined Prediction Score: 0.8876980174819535
- Mean Citation Score: 258.777776
- Max Citation Score: 264.8524
- Similarity Product: 179.7661454926014

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test