PATENT CLAIM ANALYSIS

Application Number: 15886645
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

Claim (Index 14):
The semiconductor device of  claim 12 , wherein upper surfaces of the first S/D contact, the second S/D contact and the gate contact layer are located substantially at a same plane.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.74468
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15090202', '15649909', '15157283', '15485606', '14958769']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9242259075312076
- 35 USC 102 Novelty (BERT): 0.4940743614320477
- Combined Prediction Score: 0.8812107529212916
- Mean Citation Score: 180.450376
- Max Citation Score: 231.23462
- Similarity Product: 174.6517256345236

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test