PATENT CLAIM ANALYSIS

Application Number: 15891903
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["174", "257000"]

Abstract:
A material for forming of the capacitor layer which generates no crack in drilling on the dielectric layer of the capacitor in manufacturing of a highly multilayered printed wiring board embedded a capacitor circuit. Copper clad laminate for forming of an embedded capacitor layer of a multilayered printed wiring board including an embedded capacitor circuit having a layer structure of copper layer/dielectric layer of the capacitor/copper layer in an inner layer characterized in that the composite elastic modulus Er of the resin film constituting the dielectric layer of the capacitor along the thickness direction is less than 6.1 GPa is employed.

Claim (Index 1):
A copper clad laminate for forming of an embedded capacitor layer of a multilayered printed wiring board including an embedded capacitor circuit having a layer structure of copper layer/dielectric layer of the capacitor/copper layer in an inner layer characterized in that\n the dielectric layer of the capacitor contains at least a resin film as a constituent material; the Young's modulus Er of the resin film along the thickness direction is less than 6.1 GPa.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 88.0
- Lexical Diversity: 1.87273
- Patent Class: 174.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15111315', '11659948', '15773373', '13344913', '10609618']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8737681944019371
- 35 USC 102 Novelty (BERT): 0.5185495227998731
- Combined Prediction Score: 0.8382463272417306
- Mean Citation Score: 282.82341
- Max Citation Score: 317.31094
- Similarity Product: 208.74934639712453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test