PATENT CLAIM ANALYSIS

Application Number: 15991476
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "324000"]

Abstract:
A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

Claim (Index 14):
The device of  claim 13 , further comprising a gate insulating layer interposed between the first lower semiconductor pattern and the lowermost one of the electrodes.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 93.0
- Lexical Diversity: 2.42857
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15964190', '15642829', '15373922', '14519713', '15652411']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9285648052625696
- 35 USC 102 Novelty (BERT): 0.5142462361447684
- Combined Prediction Score: 0.8871329483507895
- Mean Citation Score: 302.39126
- Max Citation Score: 316.6604
- Similarity Product: 245.15543105862145

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test