PATENT CLAIM ANALYSIS

Application Number: 16260247
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "185110"]

Abstract:
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claim (Index 1):
A nonvolatile semiconductor memory device, comprising:\n a memory cell array including a plurality of memory blocks; a plurality of memory strings disposed in a matrix in each of the plurality of memory blocks, each memory string including a plurality of electrically rewritable memory transistors connected in series; a drain side select transistor having one end thereof connected to a first end of the memory string; a source side select transistor having one end thereof connected to a second end of the memory string; a plurality of word lines disposed so as to be commonly connected to the plurality of memory strings disposed in one of the plurality of memory blocks; a plurality of bit lines each extending in a first direction and each connected to the other end of the drain side select transistor in the plurality of memory blocks; a source line connected to the other end of the source side select transistor; a drain side select gate line disposed along a second direction as a longer direction thereof and so as to commonly connect a gate of the drain side select transistor aligned in the second direction, the second direction being orthogonal to the first direction; a source side select gate line disposed along the second direction as a longer direction thereof and so as to commonly connect a gate of the source side select transistor aligned in the second direction; and a control circuit configured to control a voltage applied to the plurality of memory blocks, each of the plurality of memory strings comprising: a columnar semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate, the columnar semiconductor layer being configured to function as a body of the memory transistors; a charge storage layer formed so as to surround a side surface of the columnar portion and configured to allow storage of a charge; and a word line conductive layer formed so as to surround the side surface of the columnar portion with the charge storage layer interposed therebetween, the word line conductive layer being configured to function as a gate of the memory transistors and as the word lines, wherein a plurality of the memory strings that are connected to a plurality of the drain side select transistors and a plurality of the source side select transistors which are commonly connected to one of the drain side select gate lines and one of the source side select gate lines, respectively, configure one sub-block, and wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to: apply, in a first sub-block as a selected sub-block, a first voltage to the bit line and the source line, a second voltage smaller than the first voltage to the word lines, and a third voltage lower than the first voltage by a certain value to the drain side select gate line and the source side select gate line, thereby performing the erase operation in the first sub-block; and apply, in a second sub-block as an unselected sub-block, the second sub-block existing in an identical memory block to that of the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.70588
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13149139', '16122945', '15915701', '15275614', '13970689']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8308894895013296
- 35 USC 102 Novelty (BERT): 0.5958581477356694
- Combined Prediction Score: 0.8073863553247635
- Mean Citation Score: 467.65537600000016
- Max Citation Score: 508.21423
- Similarity Product: 502.3367173761731

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test