PATENT CLAIM ANALYSIS

Application Number: 15987483
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-04
Patent Classification: ["257", "004000"]

Abstract:
Variable resistance memory devices are provided. A variable resistance memory device includes a memory cell that includes a switching device and a resistance sensing element that is connected in series with the switching device. The variable resistance memory device includes a word line that extends in a first direction and that is connected to a gate of the switching device. Moreover, the variable resistance memory device includes a plurality of bit lines extending in a second direction. A first connection node of a first bit line among the plurality of bit lines is electrically connected to the resistance sensing element. A second connection node of a second bit line, among the plurality of bit lines, adjacent the first bit line is electrically connected to the switching device.

Claim (Index 9):
A variable resistance memory device comprising:\n a plurality of memory cells comprising a plurality of resistance sensing elements, respectively, and a plurality of switching devices, respectively, wherein the plurality of resistance sensing elements is connected in series with the plurality of switching devices, respectively; a plurality of word lines extending in a first direction and spaced apart from each other in a second direction, wherein the plurality of word lines is connected to a plurality of gates, respectively, of the plurality of switching devices, respectively; and a plurality of bit lines extending in the second direction and spaced apart from each other in the first direction, wherein a first connection node of a first bit line among the plurality of bit lines is electrically connected to first ones of the plurality of resistance sensing elements, and a second connection node of a second bit line, among the bit lines, adjacent the first bit line is electrically connected to first ones of the plurality of switching devices, wherein the first ones of the plurality of resistance sensing elements are connected in series with the first ones of the plurality of switching devices, respectively, wherein a third connection node of the first bit line is electrically connected to second ones of the plurality of switching devices, and a fourth connection node of the second bit line is electrically connected to second ones of the plurality of resistance sensing elements, and wherein the second ones of the plurality of resistance sensing elements are connected in series with the second ones of the plurality of switching devices, respectively.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 3.02222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14599064', '15205498', '12851681', '15249845', '14955789']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9212328325779638
- 35 USC 102 Novelty (BERT): 0.4842060687923924
- Combined Prediction Score: 0.8775301561994067
- Mean Citation Score: 243.593992
- Max Citation Score: 244.50696
- Similarity Product: 207.2734758730316

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test