PATENT CLAIM ANALYSIS

Application Number: 16169227
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "620000"]

Abstract:
A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

Claim (Index 3):
The semiconductor according to  claim 1 , further comprising:\n a plurality of scribe lines, wherein each scribe line of the plurality of scribe lines is positioned at the substrate between each pair of adjacent die of the plurality of die, wherein each of the plurality of inter-die connections extends over one scribe line of the plurality of scribe lines positioned between each pair of adjacent die of the plurality of die.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.13889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16019882', '16056792', '16029207', '12267021', '15802121']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.908202223888986
- 35 USC 102 Novelty (BERT): 0.5277977073763281
- Combined Prediction Score: 0.8701617722377202
- Mean Citation Score: 222.953086
- Max Citation Score: 353.93246
- Similarity Product: 335.31994913532736

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test