PATENT CLAIM ANALYSIS

Application Number: 16222047
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "668000"]

Abstract:
A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.

Claim (Index 9):
The chip package as claimed in  claim 1 , wherein intervals between the cutting scratches are substantially the same.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 98.0
- Lexical Diversity: 2.25806
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15292762', '15195321', '15293577', '14881840', '15499962']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.924356882017736
- 35 USC 102 Novelty (BERT): 0.5031758838808374
- Combined Prediction Score: 0.8822387822040461
- Mean Citation Score: 219.263018
- Max Citation Score: 247.44434
- Similarity Product: 171.19895514401912

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test