PATENT CLAIM ANALYSIS

Application Number: 15866407
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "372000"]

Abstract:
Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. An MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

Claim (Index 3):
The method of  claim 2 , wherein the ATAPs are disposed in a linear fashion with respect to the global power grid.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 2.7193
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14983796', '13111435', '13859220', '13210664', '15684964']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8986007680640965
- 35 USC 102 Novelty (BERT): 0.5624881493778203
- Combined Prediction Score: 0.8649895061954689
- Mean Citation Score: 213.426664
- Max Citation Score: 493.50485
- Similarity Product: 269.2589214825034

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test