PATENT CLAIM ANALYSIS

Application Number: 15862930
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

Claim (Index 11):
The method of  claim 1 , wherein the dummy gate comprises a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:\n a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 86.0
- Lexical Diversity: 1.94
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15852109', '15426479', '15819109', '15245634', '15831354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9193965336381806
- 35 USC 102 Novelty (BERT): 0.5105225422696251
- Combined Prediction Score: 0.8785091345013251
- Mean Citation Score: 264.368154
- Max Citation Score: 295.12448
- Similarity Product: 219.28400623870849

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test