PATENT CLAIM ANALYSIS

Application Number: 15870649
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "288000"]

Abstract:
In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

Claim (Index 2):
The semiconductor device of  claim 1 , wherein\n the first cap insulating layer is made of a different material than the second cap insulating layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.28
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15141476', '15180907', '15061621', '14925857', '15479418']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9256878214047676
- 35 USC 102 Novelty (BERT): 0.4950176917882255
- Combined Prediction Score: 0.8826208084431133
- Mean Citation Score: 224.66548
- Max Citation Score: 245.86304
- Similarity Product: 189.24911806915284

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test