PATENT CLAIM ANALYSIS

Application Number: 16011129
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["257", "324000"]

Abstract:
Three-dimensional (3D) memory with control the array and control circuitry in separately processed and bonded wafers is described. In one example, a non-volatile storage component includes a first die including a three-dimensional (3D) array of non-volatile storage cells and a second die bonded with the first die. The second die includes CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells. By processing the CMOS circuitry and array on separate wafers, the periphery CMOS and interconnects do not have to withstand the thermal cycles involved in processing the memory array, which enables optimizations for the CMOS transistors and the use low resistive material for interconnects.

Claim (Index 1):
A non-volatile storage component comprising:\n a first die including a three-dimensional (3D) array of non-volatile storage cells; and a second die bonded with the first die, the second die including CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.89231
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16011139', '13247592', '14835021', '15950169', '13973774']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907519361978458
- 35 USC 102 Novelty (BERT): 0.4821845516731649
- Combined Prediction Score: 0.8649858809479287
- Mean Citation Score: 185.220382
- Max Citation Score: 264.42722000000003
- Similarity Product: 254.4495355594612

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test