PATENT CLAIM ANALYSIS

Application Number: 16022357
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["327", "291000"]

Abstract:
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.

Claim (Index 8):
An integrated circuit (IC) chip comprising:\n first circuitry to receive a data signal; second circuitry to receive a first clock signal and to generate a second clock signal based on the first clock signal, wherein the first circuitry is to receive the second clock signal via a first signal path comprising a clock signal distribution path, wherein the first circuitry is to latch data of the data signal responsive to the second clock signal; third circuitry to generate a signal S 1 , wherein a second signal path of the third circuitry comprises a model of the first signal path, wherein the signal S 1  comprises a first indication of a first delay corresponding to the model; fourth circuitry to generate, based on a cyclical signal, a signal S 2  comprising a second indication of a second delay based on a cycle of the cyclical signal; and fifth circuitry to receive the signal S 1  and the signal S 2 , the fifth circuitry further to provide to the second circuitry a control signal based on the first indication and the second indication, wherein the second circuitry is to apply a third delay to the first clock signal based on the control signal, wherein the third delay is based on a sum of a first value and a second value, wherein the first value represents the first delay, and wherein the second value represents a time for a scalar multiple of one cycle of the cyclical signal.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.57627
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16019924', '14626441', '14106269', '12757597', '13945607']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7470364981894407
- 35 USC 102 Novelty (BERT): 0.4628300851677757
- Combined Prediction Score: 0.7186158568872743
- Mean Citation Score: 144.85056400000005
- Max Citation Score: 155.35028
- Similarity Product: 116.94775370482206

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test