PATENT CLAIM ANALYSIS

Application Number: 15899390
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["365", "149000"]

Abstract:
According to an embodiment, a semiconductor device includes M write word lines, M read word lines, N write bit lines, N read bit lines, N source lines, and M×N cells. The M×N cells are arranged in a matrix including M rows×N columns. A cell in an m-th row×an n-th column includes a first FET, a second FET, and a capacitor. The first FET is connected to an m-th write word line at a gate, to an n-th write bit line at a drain, and to a source of the second FET at a source. The second FET is connected to an m-th read word line at a gate and to an n-th read bit line at a drain. The capacitor is connected to an n-th source line at one end and to the source of the first RET at the other end.

Claim (Index 12):
The semiconductor device according to  claim 11 , wherein\n the n-th write bit line and the n-th read bit line are formed at positions overlapping each other as viewed from the third direction, and in each of the first field effect transistor and the second field effect transistor of each of cells in the n-th column, a channel is formed in a region between the n-th write bit line and the n-th read bit line in the third direction.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 88.0
- Lexical Diversity: 3.09804
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13707851', '10334009', '14487578', '12272184', '13520155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8063157151844688
- 35 USC 102 Novelty (BERT): 0.4745789477366172
- Combined Prediction Score: 0.7731420384396835
- Mean Citation Score: 183.29531
- Max Citation Score: 183.84596
- Similarity Product: 132.93534393126964

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test