PATENT CLAIM ANALYSIS

Application Number: 16125117
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["714", "777000"]

Abstract:
In some examples, a memory device may be configured to provide quad bit error correction circuits. For example, the memory device may be equipped with a two layer error correction circuit. In some cases, the first layer may utilized one or more Hamming coders and the second layer may utilize one or Golay coders. In some examples, the Golay coders may be grouped into sets of Golay coders.

Claim (Index 7):
A method comprising:\n receiving, by a memory device, data bits to be stored in one or more memory arrays; processing, by one or more Hamming coders, the data bits to generate a Hamming code, the Hamming code including the data bits and Hamming code bits; processing, by one or more Golay coders, a portion of the data bits to generate a Golay code, the Golay code including the portion of the data bits and Golay code bits; and storing the Hamming code bits, the Golay code bits, and the data bits in one or more memory arrays.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 97.0
- Lexical Diversity: 1.80952
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14923565', '09821758', '11384965', '10738264', '13281007']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2896786266963865
- 35 USC 102 Novelty (BERT): 0.5365479403397966
- Combined Prediction Score: 0.3143655580607275
- Mean Citation Score: 203.84722
- Max Citation Score: 396.2293
- Similarity Product: 308.3984847440184

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test