PATENT CLAIM ANALYSIS

Application Number: 16216162
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["327", "159000"]

Abstract:
One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

Claim (Index 3):
The circuit of  claim 1 , wherein the frequency divider and phase detector is configured to generate a first set of non-overlapping switching signals corresponding to a ratio of the frequency of the input signal and a second set of non-overlapping switching signals corresponding to a phase-difference between the input signal and the PLL output signal.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 98.0
- Lexical Diversity: 2.18
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15346248', '15843589', '11626585', '14576691', '12377204']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7823522799959087
- 35 USC 102 Novelty (BERT): 0.5303529168931835
- Combined Prediction Score: 0.7571523436856362
- Mean Citation Score: 230.683
- Max Citation Score: 368.3093
- Similarity Product: 332.4904578418792

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test