PATENT CLAIM ANALYSIS

Application Number: 15899118
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["714", "727000"]

Abstract:
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Claim (Index 6):
The test interface of  claim 1  including an input/output terminal operable to receive a test data input signal and an output test data output signal, in which both control information loaded to the instruction register and address information loaded to the address register are received at the input/output terminal.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 1.84746
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15425010', '11938923', '13735545', '14567299', '15845282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2799305828467433
- 35 USC 102 Novelty (BERT): 0.4836413302185239
- Combined Prediction Score: 0.3003016575839214
- Mean Citation Score: 190.817042
- Max Citation Score: 192.16644
- Similarity Product: 142.66412270742418

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test