PATENT CLAIM ANALYSIS

Application Number: 16183612
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["712", "008000"]

Abstract:
The present disclosure provides a data read-write scheduler and a reservation station for vector operations. The data read-write scheduler suspends the instruction execution by providing a read instruction cache module and a write instruction cache module and detecting conflict instructions based on the two modules. After the time is satisfied, instructions are re-executed, thereby solving the read-after-write conflict and the write-after-read conflict between instructions and guaranteeing that correct data are provided to a vector operations component. Therefore, the subject disclosure has more values for promotion and application.

Claim (Index 1):
A reservation station for vector operations, comprising: an I/O interface, an on-chip RAM, a data read-write scheduler, a decoder and a vector operations component,\n wherein the on-chip RAM is configured to store the input data required for vector operations and store output data obtained through computation; wherein the I/O interface is configured to perform read-write access to the on-chip RAM by devices outside of the reservation station, the read-write access including: loading the input data that need to be processed to the on-chip RAM, and moving the output data obtained after operations to external devices; wherein the decoder is configured to read instructions from an external instruction cache queue, and decode the instructions into vector read instructions, vector write instructions and vector operations instructions, send the vector read instructions and vector write instructions to the data read-write scheduler, and send the vector operations instructions to the vector operations component; wherein the vector operations component is configured to receive the input data from the data read-write scheduler for operations after receiving the vector operations instruction sent by the decoder, and then transmit the output data obtained from operations to the data read-write scheduler; wherein the data read-write scheduler comprises a data read scheduler and a data write scheduler; wherein the data read scheduler comprises a read instruction preprocessing module and a read control module; the data write scheduler comprises a write instruction preprocessing unit and a write control module; wherein the read instruction preprocessing module comprises a read instruction preprocessing unit; the read instruction preprocessing unit is configured to receive a vector read instruction and detect whether there is write-after-read conflict between the vector read instruction and the vector write instruction in the data write scheduler; if there is the conflict, the vector write instruction having the write-after-read conflict with the vector read instruction serves as the vector write instruction that the vector read instruction depends on; the read control module comprises a read control unit; the read control unit is configured to parse out one or multiple read requests according to the received vector read instruction and determine whether the time for executing the read request is satisfied according to the status of the vector write instruction that the vector read instruction depends on, and when the time for executing the read request is satisfied, send the read request to the on-chip RAM and receive input data from the on-chip RAM; and wherein the write instruction preprocessing unit is configured to receive a vector write instruction and detect whether there is a read-after-write conflict between the vector write instruction and the vector read instruction in the data read scheduler, if there is the conflict, the vector read instruction having the read-after-write conflict with the vector write instruction serves as the vector read instruction that the vector write instruction depends on; the write control module is configured to parse out a write request according to the received vector write instruction and determine the time for executing the write request according to the status of the vector read instruction that the vector write instruction depends on; when the time for executing the write request is satisfied, send the write request and written data to the on-chip RAM and receive feedback of writing result from the on-chip RAM.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.64912
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16183603', '16039605', '14335029', '14315763', '14825333']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.595410779738219
- 35 USC 102 Novelty (BERT): 0.5461401682970392
- Combined Prediction Score: 0.590483718594101
- Mean Citation Score: 289.215382
- Max Citation Score: 432.84613
- Similarity Product: 307.3513155853176

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test