PATENT CLAIM ANALYSIS

Application Number: 15941169
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["377", "064000"]

Abstract:
A shift register unit includes an input circuit configured to output a pre-output signal in response to an input signal and a first clock signal, a first output circuit configured to output a first output signal in response to the pre-output signal and a second clock signal; and a second output circuit configured to output a second output signal in response to the pre-output signal and a third clock signal.

Claim (Index 5):
The shift register unit of  claim 1 , wherein the input circuit comprises:\n an input sub-circuit, connected to the input terminal, configured to output a first control signal and a second control signal in response to the input signal; a first control circuit, connected to the input sub-circuit, configured to output a third control signal in response to the first control signal; a second control circuit, connected to the input sub-circuit and the first clock terminal, configured to output a fourth control signal in response to the second control signal; a third control circuit, connected to the first control circuit and the second control circuit, configured to output a fifth control signal in response to the third control signal and the fourth control signal; and a pre-output circuit, connected to the third control circuit, configured to output the pre-output signal in response to the fifth control signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.92
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12012964', '12012845', '15773873', '15103983', '12012846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7135341501820132
- 35 USC 102 Novelty (BERT): 0.470039361051705
- Combined Prediction Score: 0.6891846712689824
- Mean Citation Score: 249.769604
- Max Citation Score: 251.78151
- Similarity Product: 214.4008787736261

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test