PATENT CLAIM ANALYSIS

Application Number: 15874099
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

Claim (Index 8):
The three-dimensional semiconductor device of  claim 1 , wherein:\n the three-dimensional semiconductor device comprises a vertical NAND device located over the substrate; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device; the substrate comprises a silicon substrate; the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate; at least one memory cell in a first device level of the three-dimensional array of NAND strings is located over another memory cell in a second device level of the three-dimensional array of NAND strings;\n the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and \n the array of monolithic three-dimensional NAND strings comprises: \n a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; \n a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and \n a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.16667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15174030', '15354116', '15337235', '15635321', '15017961']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9235830114339676
- 35 USC 102 Novelty (BERT): 0.5493400734409782
- Combined Prediction Score: 0.8861587176346686
- Mean Citation Score: 310.3296400000001
- Max Citation Score: 406.54224
- Similarity Product: 395.6608506776618

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test