PATENT CLAIM ANALYSIS

Application Number: 16233972
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "156000"]

Abstract:
A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.

Claim (Index 16):
The phase-locked loop system of  claim 12 , wherein the first DPLL includes a frequency divider, and the second DPLL is to control a divide ratio of the frequency divider.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.22581
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16227777', '16233283', '16226938', '12908484', '11463630']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7923729142346582
- 35 USC 102 Novelty (BERT): 0.5211145925592107
- Combined Prediction Score: 0.7652470820671134
- Mean Citation Score: 269.37130400000007
- Max Citation Score: 318.26407
- Similarity Product: 204.654858654458

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test