PATENT CLAIM ANALYSIS

Application Number: 15760681
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "154000"]

Abstract:
The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell ( 100 ). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Claim (Index 8):
The memory of  claim 4 , wherein the tree structure has n\u22652 number of levels, wherein the tree structure comprises >2 root branches, wherein each branch in the tree structure not being a leaf branch comprises >2 child branches; and\n wherein the select signals of each level of the n levels in the tree structure are controlled by a further decoder receiving a dedicated bits of the read address or write address, wherein the further decoder controlling the select signals of each level of the X levels in the tree structure is different from the first or second decoder.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 1.4
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15096563', '14976065', '15096434', '13539577', '11614231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8160015736102915
- 35 USC 102 Novelty (BERT): 0.5215349531926647
- Combined Prediction Score: 0.7865549115685289
- Mean Citation Score: 231.226824
- Max Citation Score: 238.97003
- Similarity Product: 99.22412985771597

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test