PATENT CLAIM ANALYSIS

Application Number: 16290346
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-08
Patent Classification: ["710", "310000"]

Abstract:
A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

Claim (Index 16):
The memory module of  claim 14 , wherein the CS decoder is to determine that the first command is a write access, and wherein the buffer component is to assert an on-die termination (ODT) signal to a non-selected rank responsive to the CS decoder determining that the first command is the write access.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 99.0
- Lexical Diversity: 2.01667
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15101870', '14538524', '15024454', '14578078', '14869294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7281527434824234
- 35 USC 102 Novelty (BERT): 0.5491441729512687
- Combined Prediction Score: 0.710251886429308
- Mean Citation Score: 377.5441
- Max Citation Score: 485.71692
- Similarity Product: 277.36548581113817

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test