PATENT CLAIM ANALYSIS

Application Number: 16197008
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "659000"]

Abstract:
Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.

Claim (Index 4):
The method of  claim 1 , wherein the substrate comprises a wafer with multiple instances of the conductive traces on the wafer.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 98.0
- Lexical Diversity: 1.89655
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15187739', '15287056', '16133070', '15499557', '11825643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.910368515743508
- 35 USC 102 Novelty (BERT): 0.5400758353640364
- Combined Prediction Score: 0.8733392477055608
- Mean Citation Score: 240.186602
- Max Citation Score: 356.1774
- Similarity Product: 210.4199013711691

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test