PATENT CLAIM ANALYSIS

Application Number: 16166010
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["712", "205000"]

Abstract:
Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Claim (Index 8):
A cache system, comprising:\n a cache controller to:\n fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in the instruction cache or a target cache line that is stored at a target address of the branch instruction, \n wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.01818
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14216493', '15862496', '15257593', '14215633', '13359767']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5574190952860021
- 35 USC 102 Novelty (BERT): 0.590104365919502
- Combined Prediction Score: 0.5606876223493521
- Mean Citation Score: 312.69396400000005
- Max Citation Score: 528.21454
- Similarity Product: 447.5712569198346

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test