PATENT CLAIM ANALYSIS

Application Number: 15861700
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "190000"]

Abstract:
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.

Claim (Index 4):
The method of  claim 3 , further comprising:\n forming a first stress layer in the first contact hole and the second contact hole; forming a second stress layer in the first contact hole and the second contact hole; planarizing part of the first stress layer and part of the second stress layer to form a first contact plug and a second contact plug.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 1.775
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15401092', '15170954', '15830008', '13925812', '13802542']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.923717150102614
- 35 USC 102 Novelty (BERT): 0.4906560949962739
- Combined Prediction Score: 0.88041104459198
- Mean Citation Score: 197.697146
- Max Citation Score: 214.05681
- Similarity Product: 150.3148248672992

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test