PATENT CLAIM ANALYSIS

Application Number: 15870855
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "530000"]

Abstract:
The present invention discloses a three-dimensional vertical read-only memory ( 3 D-OTP V ) comprising no separate diode layer. It comprises a plurality of vertical address line, a plurality of memory holes through said vertical address line, a plurality of antifuse layers and vertical address lines in said memory holes. The memory holes comprise no separate diode layer. The horizontal and vertical address lines comprise different metallic materials.

Claim (Index 10):
The 3D-OTP V  according to  claim 9 , wherein said vertical transistor is formed in a first portion of said memory hole, and said OTP string is formed in a second portion of said memory hole.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 1.85
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15488489', '15488435', '15062117', '15333116', '15062118']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9282207020321308
- 35 USC 102 Novelty (BERT): 0.5337481285756875
- Combined Prediction Score: 0.8887734446864863
- Mean Citation Score: 265.229108
- Max Citation Score: 365.9302
- Similarity Product: 274.8602295163632

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test