PATENT CLAIM ANALYSIS

Application Number: 15870735
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "316000"]

Abstract:
3 D NAND memory cells can include a source layer, a dielectric layer disposed on the source layer, and a select gate source (SGS) layer disposed on the dielectric layer. A plurality of alternating layers of conducting material and insulating material can be disposed on the SGS layer. A conductive channel can be formed within a cell pillar trench. The conductive channel can be in contact with the source layer and the plurality of alternating layers. The cell pillar trench can be positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers.

Claim (Index 25):
The method of  claim 22 , wherein the plug has a thickness of from about 5 nm to about 50 nm for every micrometer of thickness of the plurality of alternating layers.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.1875
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14109230', '14140215', '15721771', '14536021', '15477040']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919929394898814
- 35 USC 102 Novelty (BERT): 0.4981081891477251
- Combined Prediction Score: 0.8777472743237051
- Mean Citation Score: 187.295496
- Max Citation Score: 200.24869
- Similarity Product: 127.98365543750884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test