PATENT CLAIM ANALYSIS

Application Number: 16092001
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["365", "148000"]

Abstract:
The invention relates to an electronic memristive device that has a complementary analogue reconfigurable memristive bidirectional resistive switch. The device has a memristive layer sequence having a BFTO/BFO/BFTO three-ply layer and two electrodes. Titanium traps are arranged in the BFTO interfaces. As a result of mobile acid vacancies, the potential barriers at the interfaces of the electrodes with respect to the memristive layer sequence are in flexible form. By applying voltage pulses, the acid vacancies can be shifted from the interface with respect to the first electrode to the interface with respect to the second electrode, with raising of the potential barrier at one electrode bringing about complementary lowering of the potential barrier of the other electrode. The method according to the invention for operating the device proposes adapted writing processes that use the overlaying of writing pulse sequences to achieve stipulation of a state pair of complementary resistor states. In conjunction with reading pulses of adapted polarity, the device can implement fuzzy logic and be operated as an artificial synapse with the realisation of all four learning curves for complementary learning. A plurality of options for the use of the device operated according to the invention are proposed

Claim (Index 4):
Method according to  claim 3 , characterised in that binary Boolean states are assigned to the state pairs (PLRS, NHRS) or (PHRS, NLRS),\n the state pairs\n being complementary end states following a writing process, as defined in claim  1 a), in which the state pair of complementary resistance states is specified depending on the temporal offset of the writing pulse sequences of the writing pulse sequence pair, and the HRS states and LRS states becoming more distinctive as the absolute value of the temporal offset decreases, \n or\n being complementary end states following the initialisation, as defined in  claim 3  or following a writing process as defined in claim  1 a), having a temporal offset, in which the superimposition of the writing pulse, having the falling edge, of the first writing pulse sequence, and the guide pulse of the second writing pulse sequence does not reach or exceed the minimum writing voltage for the minimum writing periodwriting period that is dependent on the minimum writing voltage, and the HRS states and the LRS states becoming less distinctive as the absolute value of the temporal offset increases, \n by means of the current output signals s of the HRS states being assigned the binary value 0, and the current output signals s of the LRS states being assigned the binary value 1, \n or\n the current output signals s of the HRS states being assigned the binary value 1, and \n the current output signals s of the LRS states being assigned the binary value 0, and the binary values of the current output signals s of the complementary end states following the initialisation process correspond to the logical negation of the current output signals s of the binary values of the complementary end states following a writing process as defined in claim  1 a).

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 2.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14038197', '14126397', '14126410', '14862187', '13408134']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.760151371615276
- 35 USC 102 Novelty (BERT): 0.4864283360802607
- Combined Prediction Score: 0.7327790680617745
- Mean Citation Score: 162.47133200000005
- Max Citation Score: 177.66513
- Similarity Product: 121.27934693214657

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test