PATENT CLAIM ANALYSIS

Application Number: 15916538
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185110"]

Abstract:
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

Claim (Index 16):
The system according to  claim 15 , wherein in the data read operation, while the second voltage is applied to the first word lines, the second word lines are set in an electrically floating state.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.82692
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14843878', '15455419', '14847086', '15286751', '15916472']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7751895938094976
- 35 USC 102 Novelty (BERT): 0.5045676467711449
- Combined Prediction Score: 0.7481273991056623
- Mean Citation Score: 194.88964400000003
- Max Citation Score: 205.99907
- Similarity Product: 122.28010965839206

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test