PATENT CLAIM ANALYSIS

Application Number: 16045526
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["365", "163000"]

Abstract:
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.

Claim (Index 5):
The memory cell of  claim 2 , wherein a logic state of the memory cell is based at least in part on the first memory element storing the first logic value or the second logic value, and at least in part on the second memory element storing the first logic value or the second logic value.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 95.0
- Lexical Diversity: 1.87879
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15433881', '15046330', '15842496', '15857188', '15842504']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8079002757346544
- 35 USC 102 Novelty (BERT): 0.4863375662519601
- Combined Prediction Score: 0.7757440047863849
- Mean Citation Score: 205.48639
- Max Citation Score: 270.74777
- Similarity Product: 241.72279498666288

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test