PATENT CLAIM ANALYSIS

Application Number: 16044340
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["348", "513000"]

Abstract:
Novel tools and techniques are provided for implementing media content streaming or playback, and, more particularly, for implementing media stream synchronization. In some embodiments, a synchronization system might receive a first signal that is output from a first device, which receives an original video signal from a video source and outputs a first video signal. The synchronization system might analyze the first signal to determine a first frame buffer delay, generate a delay adjustment signal based on such determination, and send the delay adjustment signal to a frame buffer delay device. The frame buffer delay device and the first device might concurrently receive the original video signal from the video source. The first delay adjustment signal causes the frame buffer delay device to apply the first frame buffer delay to the original video signal to produce a second video signal that is synchronized with the first video signal.

Claim (Index 17):
The synchronization system of  claim 16 , further comprising a timing pattern generator, an analyzer, and a switch, wherein the first signal comprises a second timing pattern, wherein the set of instructions, when executed by the at least one processor, further causes the synchronization system to:\n switch, using the switch, input to the first device from the video source to the timing pattern generator; generate, with the timing pattern generator, a first timing pattern; send the first timing pattern to the first device via the switch, wherein synchronizing the first video signal with the second video signal comprises:\n receiving, with the analyzer, the second timing pattern that is output from the first device; \n analyzing, with the analyzer, the second timing pattern to determine the first frame buffer delay; and \n generating, with the analyzer, the first delay adjustment signal based on the determined first frame buffer delay; and \n switch, using the switch, input from the timing pattern generator to the video source, wherein synchronizing the first video signal with the second video signal comprises sending, with the analyzer, the first delay adjustment signal to the frame buffer delay device.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 2.58065
- Patent Class: 348.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15785185', '15785145', '14708947', '13107942', '09966588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5464344569687815
- 35 USC 102 Novelty (BERT): 0.5091457017758427
- Combined Prediction Score: 0.5427055814494877
- Mean Citation Score: 167.22456200000005
- Max Citation Score: 291.0754
- Similarity Product: 248.6771539449096

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test