PATENT CLAIM ANALYSIS

Application Number: 16043588
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "296000"]

Abstract:
A transistor includes a channel fin. A gate stack is formed on sidewalls of the channel fin. A top spacer is formed over the gate stack. The top spacer includes dielectric material that fully encapsulates air gaps directly above the gate stack. A top source/drain region formed on the channel fin.

Claim (Index 6):
The transistor of  claim 1 , further comprising a bottom spacer formed directly on the bottom source/drain region around the channel fin.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 1.86667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15471416', '15496797', '15992733', '15152144', '15624061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913243774438494
- 35 USC 102 Novelty (BERT): 0.5115339243678577
- Combined Prediction Score: 0.8730727894314304
- Mean Citation Score: 294.99222999999995
- Max Citation Score: 314.20438
- Similarity Product: 307.73189430597785

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test