PATENT CLAIM ANALYSIS

Application Number: 16227383
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["712", "208000"]

Abstract:
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can receive, from a software application, a request to perform an operation on a first set of variables that includes a first input value and a register value and perform the operation on a second set of variables that includes a second input value and the first register value. The processor core can vectorize the operation on the first set of variables and the second set of variables. The processor core can perform the operation on the first set of variables and the second set of variables in parallel to obtain a first operation value and a second operation value. The processor core can perform a horizontal add operation on the first operation value and the second operation value and write the result to memory.

Claim (Index 16):
A system comprising:\n a memory device; and a processor coupled to the memory device, wherein the processor is to:\n perform an operation on a first set of variables to obtain a first operation value; \n perform the operation on a second set of variables to obtain a second operation value; \n perform the operation on a third set of variables to obtain a third operation value, wherein the operation on the first set of variables, the operation on second set of variables, and the operation on third set of variables is performed in parallel; \n associate the first operation value with a first location at a register array; \n associate the second operation value with a second location at the register array; \n associating, by the processor, the third operation value with a third location at the register array; \n determine that a register value at the first location and a register value at the second location identify a same memory location; \n associate a horizontal add operation on the first operation value and the second operation value to obtain a result value; and \n write the result value to the same memory location identified by the second location and the third operation value to a third memory location identified by a register value at the third location.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 3.03846
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15301206', '15301224', '13795234', '15396568', '13487184']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4984354755935398
- 35 USC 102 Novelty (BERT): 0.4859301949796564
- Combined Prediction Score: 0.4971849475321514
- Mean Citation Score: 162.34383200000005
- Max Citation Score: 243.65208
- Similarity Product: 213.0226035034848

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test