PATENT CLAIM ANALYSIS

Application Number: 16228248
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["708", "503000"]

Abstract:
The present embodiments relate to integrated circuits with circuitry that efficiently performs mixed-precision floating-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. The specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing blocks may implement fixed-point addition, floating-point addition, fixed-point multiplication, floating-point multiplication, sum of two multiplications in a first floating-point precision, with or without casting to a second floating-point precision and the latter followed by a subsequent addition in the second floating-point precision, if desired, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers having a first floating-point precision and output the dot product in a second floating-point precision.

Claim (Index 40):
The tangible, non-transitory, and computer-readable medium of  claim 39 , wherein:\n configuring the first specialized processing block to generate the first partial product comprises the first specialized processing block to multiply each pair together of a first set of pairs of tuples from the first quaternary reduction and sum first results of the multiplication of the pairs of the first set of pairs of tuples; configuring the second specialized processing block to generate the second partial product comprises the second specialized processing block to multiply each pair together of a second set of pairs of tuples from the second quaternary reduction and sum second results of the multiplication of the pairs of the second set of pairs of tuples; and performing the binary reduction comprises configuring the second specialized processing block to add the first and second partial products together using an adder of the second specialized processing block.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 98.0
- Lexical Diversity: 1.97531
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15485248', '15270153', '15451467', '15367205', '15367208']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4494965119846033
- 35 USC 102 Novelty (BERT): 0.5611433190369375
- Combined Prediction Score: 0.4606611926898367
- Mean Citation Score: 301.26089
- Max Citation Score: 416.67908
- Similarity Product: 318.8908975605893

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test