PATENT CLAIM ANALYSIS

Application Number: 15982910
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["702", "119000"]

Abstract:
An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Claim (Index 20):
The method of  claim 16 , wherein the hardware accelerator packet builder mode comprises generating all commands and data for coordinating testing of said one or two DUTs using said hardware accelerator circuit.

Metadata:
- Claim Count in Document: 71.0
- Percentile: 93.0
- Lexical Diversity: 2.35938
- Patent Class: 702.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13773569', '13773555', '13773580', '13781337', '13950164']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2636630618148847
- 35 USC 102 Novelty (BERT): 0.5992032277947247
- Combined Prediction Score: 0.2972170784128687
- Mean Citation Score: 445.41587
- Max Citation Score: 517.82416
- Similarity Product: 472.862527256813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test