PATENT CLAIM ANALYSIS

Application Number: 15964492
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "368000"]

Abstract:
A memory cell array includes a first memory cell arranged in a first row in a first direction and a second memory cell arranged in a second row in the first direction. The first memory cell or the second memory cell includes a set of active regions, a set of gates and a first set of conductive structures. Each of the active regions of the set of active regions is separated from an adjacent active region in the first direction by a first pitch. The set of active regions extends in a second direction. The set of active regions includes a first active region adjacent to a first side of the first memory cell, and a second active region adjacent to a second side of the first memory cell. A length of the first active region is different from a length of the second active region.

Claim (Index 7):
A method of forming a memory cell array having a memory cell, the method comprising:\n generating, by a processor, a layout design of the memory cell array, the layout design having a corner notch, wherein the generating of the layout design comprises:\n generating a set of active region layout patterns corresponding to fabricating a set of active regions of the memory cell array, each active region layout pattern of the set of active region layout patterns being separated from an adjacent layout pattern of the set of active region layout patterns in a first direction by a first pitch, the set of active region layout patterns extending in a second direction different from the first direction and being located on a first layout level, the set of active region layout patterns including a first active region layout pattern adjacent to the corner notch and a first side of the memory cell, and a second active region layout pattern adjacent to a second side of the memory cell opposite from the first side of the memory cell; \n wherein at least one of the above layout patterns is stored in a non-transitory computer-readable medium, and at least one of the above generating operations is performed by a hardware processor, and manufacturing the memory cell array based on the layout design.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 3.94872
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15863090', '15682885', '15861128', '14554958', '15380936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8931953944814037
- 35 USC 102 Novelty (BERT): 0.4726977180917389
- Combined Prediction Score: 0.8511456268424373
- Mean Citation Score: 168.22874199999995
- Max Citation Score: 186.12898
- Similarity Product: 154.23338251420975

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test