PATENT CLAIM ANALYSIS

Application Number: 15897685
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["257", "190000"]

Abstract:
An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.

Claim (Index 13):
The method according to  claim 12 , wherein:\n the first sections of the first and second regions comprise doped field effect transistors (FETs), and the second sections of the first and second regions comprise doped field effect transistors (FETs).

Metadata:
- Claim Count in Document: 40.0
- Percentile: 88.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15403696', '14618442', '14618397', '15823340', '15407992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.934684255146522
- 35 USC 102 Novelty (BERT): 0.6161175465569855
- Combined Prediction Score: 0.9028275842875684
- Mean Citation Score: 378.21132400000016
- Max Citation Score: 566.6016
- Similarity Product: 512.632926744461

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test