PATENT CLAIM ANALYSIS

Application Number: 16134103
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "380000"]

Abstract:
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Claim (Index 8):
A device comprising:\n a passive device at least partially disposed over a dielectric isolation structure, the passive device including:\n a conductive layer disposed over the dielectric isolation structure; \n a polysilicon feature disposed over the conductive layer; \n a dielectric sidewall spacer physically contacting a sidewall of the polysilicon feature; and \n a first electrode extending through the polysilicon feature to the conductive layer, the first electrode having an edge facing the dielectric sidewall spacer, and wherein a portion of the polysilicon feature extends from the edge of the first electrode to the dielectric sidewall spacer.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 1.77778
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15925323', '15620241', '14543169', '12770166', '15651248']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9294784416437823
- 35 USC 102 Novelty (BERT): 0.5575479558253478
- Combined Prediction Score: 0.892285393061939
- Mean Citation Score: 339.2571480000001
- Max Citation Score: 386.80173
- Similarity Product: 342.07306749001623

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test