PATENT CLAIM ANALYSIS

Application Number: 15863704
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["257", "330000"]

Abstract:
A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.

Claim (Index 1):
A semiconductor device, comprising:\n a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type formed on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of a second conductivity type selectively formed in a surface layer of the first semiconductor layer on a side opposite to a side of the semiconductor substrate; a first semiconductor region of the first conductivity type selectively formed in a surface layer of the second semiconductor layer on a side opposite to the semiconductor substrate side; a second semiconductor region of the second conductivity type selectively formed in the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate side and having a higher impurity concentration than the second semiconductor layer; a gate electrode formed on a face of a region of the second semiconductor layer that is sandwiched between the first semiconductor layer and the first semiconductor region, with a gate insulating film interposed therebeneath; a first electrode formed on surfaces of the second semiconductor region and the first semiconductor region; a second electrode formed on a rear surface of the semiconductor substrate; and a lifetime killer region that has lifetime killers implanted therein and that is selectively formed in a region of the first semiconductor layer that crosses or is adjacent to a p-n junction formed by the first semiconductor layer of the first conductivity type and a region of the second conductivity type created therein, the lifetime killer region not substantially overlapping the second semiconductor region in a plan view except lateral edges thereof.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.32609
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15846040', '15800870', '15692690', '15397677', '15609487']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9266515868339
- 35 USC 102 Novelty (BERT): 0.4931310357629844
- Combined Prediction Score: 0.8832995317268084
- Mean Citation Score: 277.945936
- Max Citation Score: 287.13644
- Similarity Product: 273.2549915262246

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test