PATENT CLAIM ANALYSIS

Application Number: 16109857
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "296000"]

Abstract:
Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Claim (Index 4):
A semiconductor device comprising:\n a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a capacitor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are n-channel type transistors, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the first wiring, wherein a gate of the third transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring, wherein a first electrode of the capacitor is electrically connected to a gate of the fourth transistor, wherein the first electrode of the capacitor is electrically connected to a gate of the second transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the first electrode of the capacitor, and wherein a signal having a first potential and a second potential is input to a second electrode of the capacitor.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 96.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14790309', '15350712', '13468135', '14250623', '14339948']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9256127446684396
- 35 USC 102 Novelty (BERT): 0.5144520099315388
- Combined Prediction Score: 0.8844966711947494
- Mean Citation Score: 354.404852
- Max Citation Score: 382.0933
- Similarity Product: 363.97242205152514

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test