PATENT CLAIM ANALYSIS

Application Number: 15905608
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["257", "503000"]

Abstract:
A memory and a method for fabricating the memory are provided. The memory includes a bit-line layer on a semiconductor substrate and having bit lines arranged in the bit-line layer. The memory also includes a shielding layer on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. Further, the memory includes a word-line layer on the shielding layer and having word lines arranged in the word-line layer.

Claim (Index 19):
The method according to  claim 18 , further including:\n providing a connection structure, in the shielding layer and electrically isolated from the conductive shielding structure, wherein the connection structure electrically connects one of the word line and the bit line to the memory structure in the semiconductor substrate.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12715916', '14180272', '14145162', '12765478', '13729092']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9199885126181472
- 35 USC 102 Novelty (BERT): 0.4879094521750004
- Combined Prediction Score: 0.8767806065738324
- Mean Citation Score: 184.81453
- Max Citation Score: 192.6986
- Similarity Product: 135.00673496603966

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test