PATENT CLAIM ANALYSIS

Application Number: 16209520
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "185180"]

Abstract:
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Claim (Index 16):
A method of performing a reading operation in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including a memory cell array which comprises: a memory string including a plurality of memory cells connected in series therein, each of the memory cells being configured to be capable of having formed plural threshold voltage distributions therein; a first select transistor connected to one end of the memory string; a second select transistor connected to the other end of the memory string; a bit line connected to the memory string via the first select transistor; a source line connected to the memory string via the second select transistor; and a word line connected to a control gate electrode of each of the memory cells, the method comprising:\n determining the threshold voltage distributions of selected memory cells whose control gate electrodes are connected to the word line by applying a reading voltage to the control gate electrodes of the selected memory cells and detecting a current flowing in the bit line by a bit line control circuit; setting a value of the reading voltage of the control gate electrodes relative to a voltage of sources of the selected memory cells to a voltage value based on a result of determining the threshold voltage distributions of the selected memory cells; and reading data of the selected memory cells by deteii lining one threshold voltage distribution among the plural threshold voltage distributions which the selected memory cells respectively have formed therein, the threshold voltage distribution determined in reading data being obtained under a condition such that a positive voltage is applied to the source line while the value of the reading voltage relative to the voltage of the sources is set to the voltage value.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 2.96078
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15263518', '15915129', '13749029', '13246004', '14088744']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8170730549969245
- 35 USC 102 Novelty (BERT): 0.5470066209289243
- Combined Prediction Score: 0.7900664115901246
- Mean Citation Score: 395.541526
- Max Citation Score: 406.444
- Similarity Product: 393.62907797122

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test