PATENT CLAIM ANALYSIS

Application Number: 16417827
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["375", "355000"]

Abstract:
A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

Claim (Index 6):
The clock divider of  claim 5 , wherein the clock delay selector generates the delay element selection signal according to one or more bits of a binary sequence received from the bit pattern source.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 100.0
- Lexical Diversity: 1.97143
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15906000', '15273764', '16167488', '13363410', '14490952']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4794572673885683
- 35 USC 102 Novelty (BERT): 0.5186462428260454
- Combined Prediction Score: 0.483376164932316
- Mean Citation Score: 189.37786
- Max Citation Score: 327.92758
- Similarity Product: 299.47977424341684

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test