PATENT CLAIM ANALYSIS

Application Number: 15871525
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "098000"]

Abstract:
A thin film transistor, a display substrate, manufacturing methods thereof, and a display device are provided. The manufacturing method for the thin film transistor includes: forming a light-shielding metal pattern and a source-drain metal layer pattern on a base substrate; forming a buffer layer including first and second via-holes; forming a source electrode connected with the light-shielding metal pattern via the first via-hole, a drain electrode connected with the source-drain metal layer pattern via the second via-hole, and an active layer, an orthographic projection of the light-shielding metal pattern on the substrate completely covering that of the active layer on the substrate and at least partially covering those of the source and drain electrodes on the substrate; and forming a gate insulation layer and a gate electrode, orthographic projections of the gate insulation layer and the gate electrode on the substrate being identical.

Claim (Index 6):
A thin film transistor, comprising:\n a light-shielding metal pattern and a source-drain metal layer pattern on a base substrate and in an identical layer; a buffer layer covering the light-shielding metal pattern and the source-drain metal layer pattern, wherein the buffer layer comprises a first via-hole corresponding to the light-shielding metal pattern and a second via-hole corresponding to the source-drain metal layer pattern; a source electrode, a drain electrode and an active layer on the buffer layer, wherein an orthographic projection of the light-shielding metal pattern on the base substrate completely covers an orthographic projection of the active layer on the base substrate and at least covers a part of an orthographic projection of the source electrode on the base substrate and a part of an orthographic projection of the drain electrode on the base substrate, and the source electrode is electrically connected with the light-shielding metal pattern via the first via-hole, and the drain electrode is electrically connected with the source-drain metal layer pattern via the second via-hole; a gate insulation layer pattern on the active layer; and a gate electrode on the gate insulation layer pattern, wherein an orthographic projection of the gate electrode on the base substrate coincides with an orthographic projection of the gate insulation layer pattern on the base substrate.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.55738
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15156858', '15154257', '15743497', '15677542', '15707827']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9296804495602268
- 35 USC 102 Novelty (BERT): 0.5210334058217252
- Combined Prediction Score: 0.8888157451863765
- Mean Citation Score: 322.01402
- Max Citation Score: 337.4329
- Similarity Product: 260.1620222114563

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test