PATENT CLAIM ANALYSIS

Application Number: 16226938
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "159000"]

Abstract:
A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

Claim (Index 17):
The PLL of  claim 16 , wherein, upon release of the reset state of the reference clock divider and the feedback clock divider, the circuit including the finite state machine de-asserts the signal to the filter to unfreeze the output of the filter.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 98.0
- Lexical Diversity: 2.29231
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16101009', '16227777', '12111541', '14700695', '12550393']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8095753825888569
- 35 USC 102 Novelty (BERT): 0.5040454015566942
- Combined Prediction Score: 0.7790223844856407
- Mean Citation Score: 251.626852
- Max Citation Score: 258.00763
- Similarity Product: 175.04982559375404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test