PATENT CLAIM ANALYSIS

Application Number: 15910132
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["716", "112000"]

Abstract:
Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a set of chip layouts. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of properties of the respective interconnected nets. Chip layouts related to virtual ensembles that do not comply with a design rule are modified to bring non-compliant virtual ensembles into compliance.

Claim (Index 5):
The method of  claim 1 , wherein determining whether each virtual ensemble complies with a design rule includes comparing a threshold value to: R sd R sd + R g + R s \u00b7 1 R g + R s where R g  represents an electrical resistance of a path from a plasma to a gate of a transistor, R sd  represents an electrical resistance of a path from the plasma to a source/drain of the transistor, and R s  represents an electrical resistance of a shunt path between the gate and the source/drain of the transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.56
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15073898', '15081226', '15597705', '15154525', '11477700']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3549848893519975
- 35 USC 102 Novelty (BERT): 0.5374321042573823
- Combined Prediction Score: 0.373229610842536
- Mean Citation Score: 234.46639000000005
- Max Citation Score: 410.1948
- Similarity Product: 408.6126963116884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test