PATENT CLAIM ANALYSIS

Application Number: 15860566
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "427000"]

Abstract:
A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.

Claim (Index 6):
The method of  claim 1 , further comprising:\n forming an interlayer dielectric layer over the stack and the etch stop layer; and removing a portion of the interlayer dielectric layer over a logic transistor.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 86.0
- Lexical Diversity: 2.82222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15813055', '15828101', '15799416', '15706709', '15230690']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9152209793951792
- 35 USC 102 Novelty (BERT): 0.4894140391012321
- Combined Prediction Score: 0.8726402853657845
- Mean Citation Score: 211.551268
- Max Citation Score: 229.14671
- Similarity Product: 172.4118787461734

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test