PATENT CLAIM ANALYSIS

Application Number: 16170479
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["714", "727000"]

Abstract:
A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

Claim (Index 7):
A test circuit operable in an automatic test pattern generation (ATPG) mode and a logic built-in self-test (LBIST) mode, the test circuit comprising:\n a clock selection circuit comprising:\n clock logic circuitry configured to receive as input an LBIST mode signal and an ATPG mode signal, and to generate first and second outputs therefrom, the first output being in a first logic state when the test circuit is operating in either the ATPG mode or the LBIST mode, the second output being in a second logic state when the test circuit is operating in either ATPG mode or LBIST mode; \n a multiplexing circuit configured to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock; and \n a clock gate circuit enabled in response to enable signals, wherein the enable signals are an inverse of a selected one of the ATPG clock and the functional clock, the clock gate circuit configured to receive the second outputs from the clock logic circuitry and provide clock gate circuit outputs; \n wherein the clock gate circuit is configured to generate a test clock as a function of a logical operation performed on the clock gate circuit outputs

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 3.25
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15268848', '15473100', '15466001', '14152879', '15443990']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3468635844490025
- 35 USC 102 Novelty (BERT): 0.5953054924494825
- Combined Prediction Score: 0.3717077752490505
- Mean Citation Score: 346.330048
- Max Citation Score: 525.98737
- Similarity Product: 487.5370815767849

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test