PATENT CLAIM ANALYSIS

Application Number: 15873909
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "071000"]

Abstract:
A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Claim (Index 3):
The method of forming a semiconductor memory device according to  claim 1 , wherein the second layer of each of the tri-layered spacers disposed below the conductive pads is remained.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 86.0
- Lexical Diversity: 2.98039
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15592860', '15782556', '13293777', '14101631', '14445829']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9290537082163156
- 35 USC 102 Novelty (BERT): 0.5054319776629845
- Combined Prediction Score: 0.8866915351609825
- Mean Citation Score: 250.75194399999995
- Max Citation Score: 260.69778
- Similarity Product: 182.56416345767505

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test