PATENT CLAIM ANALYSIS

Application Number: 16227592
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "774000"]

Abstract:
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Claim (Index 11):
A semiconductor structure comprising:\n a conductive interconnect layer; a dielectric layer formed over the conductive interconnect layer; a first conductive layer formed in the dielectric layer and in contact with a portion of the conductive interconnect layer; a second conductive layer formed in the dielectric layer and over the first conductive layer; and a graphed barrier layer formed between the first and second conductive layers and between the second conductive layer and the dielectric layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.75
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15675498', '15675535', '13890320', '13586676', '14175685']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912940541348602
- 35 USC 102 Novelty (BERT): 0.485483085469835
- Combined Prediction Score: 0.8701947957607252
- Mean Citation Score: 202.369796
- Max Citation Score: 248.44135
- Similarity Product: 213.4441043940544

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test