PATENT CLAIM ANALYSIS

Application Number: 15743617
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["345", "212000"]

Abstract:
The present disclosure provides a GOA unit circuit, a method for driving the same, and a GOA circuit. The GOA unit circuit comprises a first input sub-circuit, a pull-up sub-circuit, a first pull-down sub-circuit, a reset sub-circuit, a second input sub-circuit, a noise control sub-circuit, a first de-noising sub-circuit, and a second de-noising sub-circuit. The first pull-down sub-circuit is connected to an output signal terminal, a first clock control signal terminal and a discharge signal terminal, a discharge signal provided by the discharge signal terminal is at a high level higher than that of an input signal provided by the input signal terminal, and the first pull-down sub-circuit is configured to discharge the output signal terminal under the control of the first clock control signal and the discharge signal, to pull down a potential at the output signal terminal to a low level. The GOA unit circuit is configured to drive gate lines of a display apparatus.

Claim (Index 12):
A method for driving a Gate Driver on Array (GOA) unit circuit, applied to the GOA unit circuit according to  claim 1 , the method comprising:\n in an input period, setting the input signal to a high level, so that the first input sub-circuit is turned on, the potential at the pull-up node is pulled up, and the pull-up sub-circuit is turned on; setting the first clock control signal to a low level, so that the output signal terminal outputs a low level; setting the reset signal to a low level, so that the reset sub-circuit is turned off; and setting the second clock control signal to a high level, so that the noise control sub-circuit is turned on, and under the control of the high potential at the pull-up node, the second input sub-circuit is turned on, the low level power supply signal is input to the pull-down node via the second input sub-circuit to pull down the potential at the pull-down node, and the first de-noising sub-circuit and the second de-noising sub-circuit are turned off; in an output period, maintaining the pull-up sub-circuit to be turned on, and setting the first clock control signal to a high level, so that the potential at the pull-up node continues to be pulled up and the output signal terminal outputs a high level; setting the input signal to a low level, so that the first input sub-circuit is turned off, and still setting the reset signal to a low level, so that the reset sub-circuit is turned off; and setting the second clock control signal to a low level, so that the noise control sub-circuit is turned off, the second input sub-circuit is maintained to be turned on, the low level power supply signal continues to be input to the pull-down node via the second input sub-circuit to continue to pull down the potential at the pull-down node, and the first de-noising sub-circuit and the second de-noising sub-circuit are turned off; in a discharge period, setting the discharge signal to a high level higher than that of the input signal, so that the first pull-down sub-circuit is turned on; setting the first clock control signal to a low level, so that the potential at the output signal terminal is pulled down to a low level; still setting the input signal to a low level, so that the first input sub-circuit is turned off, the potential at the pull-up node is decreased to some extent, and the pull-up sub-circuit is maintained to be turned on, and still setting the reset signal to a low level, so that the reset sub-circuit is turned off; and still setting the second clock control signal to a low level, so that the noise control sub-circuit is turned off, the second input sub-circuit is maintained to be turned on, the low level power supply signal continues to be input to the pull-down node via the second input sub-circuit to continue to maintain the potential at the pull-down node at a low level, and the first de-noising sub-circuit and the second de-noising sub-circuit are turned off; and in a reset period, setting the reset signal to a high level, so that the reset sub-circuit is turned on, the low level power supply signal is input to the pull-up node via the reset sub-circuit to pull down the potential at the pull-up node to a low level, the pull-up sub-circuit is turned off, and the output signal terminal still outputs a low level; still setting the input signal to a low level, so that the first input sub-circuit is turned off; and setting the second clock control signal to a high level, so that the noise control sub-circuit is turned on, and under the control of the low potential at the pull-up node, the second input sub-circuit is turned off, and the potential at the pull-down node becomes a high level, and the first de-noising sub-circuit and the second de-noising sub-circuit are turned on, so that the first de-noising sub-circuit de-noises the pull-up node, and the second de-noising sub-circuit de-noises the output signal terminal.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 3.10714
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15682740', '16066827', '15741742', '14787934', '15529613']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6977151157403341
- 35 USC 102 Novelty (BERT): 0.5377318927948765
- Combined Prediction Score: 0.6817167934457884
- Mean Citation Score: 343.007954
- Max Citation Score: 393.1922
- Similarity Product: 294.4913306327344

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test