PATENT CLAIM ANALYSIS

Application Number: 15884711
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "311000"]

Abstract:
The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.

Claim (Index 11):
The method of  claim 10 , wherein the forming of the dielectric feature in the first contact hole includes performing a bottom-up deposition, wherein dielectric feature includes a dielectric material different from that of the dielectric material layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.07843
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15800359', '15864525', '15803083', '14504258', '14942740']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9328581045519098
- 35 USC 102 Novelty (BERT): 0.5054319174108012
- Combined Prediction Score: 0.890115485837799
- Mean Citation Score: 227.521044
- Max Citation Score: 243.49124
- Similarity Product: 165.0487683730936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test