PATENT CLAIM ANALYSIS

Application Number: 16030136
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["365", "049170"]

Abstract:
A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.

Claim (Index 5):
The semiconductor storage device according to  claim 1 ,\n wherein the first word line and the second word line have a part formed using the wiring of the first wiring layer, and a part formed using the wiring of the second wiring layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 3.125
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15004990', '15251504', '15631604', '11480908', '14471278']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8250037886201127
- 35 USC 102 Novelty (BERT): 0.4900799193415537
- Combined Prediction Score: 0.7915114016922569
- Mean Citation Score: 250.09684
- Max Citation Score: 259.8976
- Similarity Product: 204.4363335170746

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test