PATENT CLAIM ANALYSIS

Application Number: 15984914
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "004000"]

Abstract:
A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

Claim (Index 22):
The semiconductor device of  claim 21 , wherein a first peripheral transistor of the first peripheral circuit section and a second peripheral transistor of the second peripheral circuit section are provided at the same height with respect to the substrate.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 3.04082
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15854551', '15828937', '14955789', '15273268', '14055061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9129641851880697
- 35 USC 102 Novelty (BERT): 0.515988375197006
- Combined Prediction Score: 0.8732666041889632
- Mean Citation Score: 236.496882
- Max Citation Score: 285.3164700000001
- Similarity Product: 214.3463531042541

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test