PATENT CLAIM ANALYSIS

Application Number: 16109092
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "225700"]

Abstract:
Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.

Claim (Index 7):
The memory device of  claim 1 , wherein each static random access memory cell has five transistors structured such that each static random access memory cell is coupled to only one access line and only one digitline.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 96.0
- Lexical Diversity: 1.45455
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10902728', '15598894', '12547337', '10620179', '11489119']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8049107843609421
- 35 USC 102 Novelty (BERT): 0.5074580307613259
- Combined Prediction Score: 0.7751655090009806
- Mean Citation Score: 184.9085
- Max Citation Score: 190.40343
- Similarity Product: 95.43652433706164

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test