PATENT CLAIM ANALYSIS

Application Number: 15973873
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "692000"]

Abstract:
A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

Claim (Index 14):
The power semiconductor package of  claim 1 , wherein the first face and second face of the first die and the first face and second face of the second die is coupled to one of the first IMS, the second IMS, and the third IMS using a sintering paste.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 93.0
- Lexical Diversity: 3.13725
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15489998', '14610115', '15081464', '14816520', '15206574']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9215339107749916
- 35 USC 102 Novelty (BERT): 0.5921937776738002
- Combined Prediction Score: 0.8885998974648726
- Mean Citation Score: 346.30378
- Max Citation Score: 495.29623
- Similarity Product: 439.8007983535063

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test