PATENT CLAIM ANALYSIS

Application Number: 16032213
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "384000"]

Abstract:
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.

Claim (Index 9):
The semiconductor device of  claim 8 , further comprising at least one metal contact formed on and in contact with the silicide area.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 3.01923
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14227345', '15417940', '15075260', '15804303', '15294345']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9314189813518357
- 35 USC 102 Novelty (BERT): 0.5479161839709512
- Combined Prediction Score: 0.8930687016137471
- Mean Citation Score: 353.317116
- Max Citation Score: 418.15707
- Similarity Product: 333.4056465405536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test