PATENT CLAIM ANALYSIS

Application Number: 15880063
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["345", "212000"]

Abstract:
A bias generation circuit coupled to a display panel is disclosed. The bias generation circuit includes a linear regulator, a charge pump and a synchronous dual mode boost DC-DC converter. The linear regulator and the charge pump are coupled to the display panel respectively. The synchronous dual mode boost DC-DC converter is selectively operated in a pulse width modulation mode or a pulse frequency modulation mode according to a control signal. In the pulse width modulation mode, the synchronous dual mode boost DC-DC converter controls the linear regulator to generate a first voltage signal to the display panel. In the pulse frequency modulation mode, the synchronous dual mode boost DC-DC converter controls the charge pump to generate a second voltage signal to the display panel.

Claim (Index 7):
The bias generation circuit of  claim 5 , wherein when the control signal is switched from the idle mode to the normal mode, the synchronous dual mode boost DC-DC converter delays a second period of time and then switched from the pulse frequency modulation (PFM) mode to the pulse width modulation (PWM) mode.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.91304
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13801817', '14483525', '15069724', '13609670', '11422465']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6973958625501797
- 35 USC 102 Novelty (BERT): 0.5135826925878071
- Combined Prediction Score: 0.6790145455539425
- Mean Citation Score: 270.726644
- Max Citation Score: 296.0839
- Similarity Product: 209.1520189496756

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test