PATENT CLAIM ANALYSIS

Application Number: 15917520
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["326", "038000"]

Abstract:
The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.

Claim (Index 5):
The configurable computing array die according to  claim 1 , wherein said first and second LUTs are respectively recorded into said first and second printed arrays using a printing method during manufacturing.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.51852
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15917530', '15450017', '15784077', '15450049', '15793912']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.728178415795417
- 35 USC 102 Novelty (BERT): 0.5630118150496666
- Combined Prediction Score: 0.711661755720842
- Mean Citation Score: 413.606816
- Max Citation Score: 457.37045
- Similarity Product: 361.3014832038164

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test