PATENT CLAIM ANALYSIS

Application Number: 15900827
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "329000"]

Abstract:
Embodiments of the present invention provide systems and methods for generating oxide spacers in a vertical field transistor. The fin of the channel facilitates the electrical current flowing between the source terminal and the drain terminal. By employing sacrificial spacers, implanted oxidation enhancement species on a silicon surface, an implanted oxidation enhancement species can be oxidized to oxide spacers.

Claim (Index 1):
A method for depositing oxide spacers in field effect transistors, comprising:\n modifying a silicon surface beneath a fin structure by implanting oxidation enhancement species onto portions of the silicon surface, wherein the fin structure contains a first wall and a second wall; oxidizing one or more portions of the modified silicon surface into a first set of oxide spacers while maintaining an original composition of the fin structure, and un-modified portions of the silicon surface beneath the fin structure; depositing a silicon gate structure around the one or more portions of the fin structure, wherein the silicon gate structure has a top layer, wherein the top layer is implanted with the oxidation enhancement species; depositing silicon-germanium onto portions of the silicon surface and onto the top layer of the deposited silicon gate structure; oxidizing the implanted the oxidation enhancement species and the deposited silicon-germanium on the top layer of the deposited silicon gate structure to form a second set of oxide spacers; generating a region below the first set of oxide spacers containing germanium in response to oxidizing the one or more portions of the modified silicon surface into the first set of oxide spacers; depositing silicon nitride spacers around the first wall and the second wall of the fin structure which protects the fin structure when forming the first set of oxide spacers and the second set of oxide spacers; and converting un-modified portions of the silicon surface beneath the fin structure, the deposited silicon gate structure, the first set of oxide spacers, the second set of oxide spacers, and the silicon nitride spacers into a vertical field effect transistor, wherein the vertical field effect transistor isolates a gate region from both a source region and a drain region through the first set of oxide spacers and the second set of oxide spacers.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.3913
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15713975', '15833543', '15812807', '15853769', '15783029']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9102088903707684
- 35 USC 102 Novelty (BERT): 0.4791812274043214
- Combined Prediction Score: 0.8671061240741238
- Mean Citation Score: 177.70279800000003
- Max Citation Score: 180.32994
- Similarity Product: 130.19271396289585

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test