PATENT CLAIM ANALYSIS

Application Number: 16393537
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["716", "103000"]

Abstract:
Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.

Claim (Index 20):
The computer system according to  claim 16 , wherein the circuit cells of the first type include at least one selected from a group consisting of: a bit row, a word line driver and a clock generator.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.31373
- Patent Class: 716.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15469747', '11128069', '10941607', '14479804', '12061155']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3823559224899696
- 35 USC 102 Novelty (BERT): 0.4646508564477439
- Combined Prediction Score: 0.390585415885747
- Mean Citation Score: 157.01896599999995
- Max Citation Score: 254.1548
- Similarity Product: 231.0872123222589

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test