PATENT CLAIM ANALYSIS

Application Number: 16224651
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-08
Patent Classification: ["716", "053000"]

Abstract:
Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Claim (Index 1):
A method of generating a proximity-corrected design layout for photoresist to be used in an etch operation, the method comprising:\n (a) receiving an initial design layout; (b) identifying a feature in the initial design layout, the feature's pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate's surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said material stack is overlaid with a layer of photoresist pattern corresponding to the initial design layout; (c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process; (d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in a look-up table (LUT) which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF; and (e) modifying the initial design layout based on the quantity characteristic of EPE; wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.09211
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15188910', '15583610', '15367060', '15018708', '15698458']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3316862812140036
- 35 USC 102 Novelty (BERT): 0.5545384020564312
- Combined Prediction Score: 0.3539714932982464
- Mean Citation Score: 338.5333500000001
- Max Citation Score: 440.0734
- Similarity Product: 432.9873310842871

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test