PATENT CLAIM ANALYSIS

Application Number: 16017515
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["710", "308000"]

Abstract:
A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

Claim (Index 1):
An apparatus, comprising:\n a memory controller comprising a memory channel interface, the memory channel interface comprising a first group of data I/Os and second group of data I/Os, the first group of data I/Os to couple to a first DIMM in a point-to-point link fashion, the second group of I/Os to couple to a second DIMM in a point-to-point link fashion, the memory controller comprising logic circuitry to send first multiplexed write data to the first DIMM that targets different groups of memory chips on the first DIMM during a same first burst write sequence, the memory controller to also concurrently send second multiplexed write data to the second DIMM that targets different groups of memory chips on the second DIMM during a same second burst write sequence that exists during a same time period as the first burst write sequence.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 1.20833
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15716485', '15196014', '14028172', '15424638', '15197424']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6668923362170581
- 35 USC 102 Novelty (BERT): 0.4751371824603839
- Combined Prediction Score: 0.6477168208413908
- Mean Citation Score: 188.670822
- Max Citation Score: 214.75385
- Similarity Product: 171.3614072788835

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test