PATENT CLAIM ANALYSIS

Application Number: 15878363
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["327", "142000"]

Abstract:
A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.

Claim (Index 2):
The control circuit of  claim 1 , wherein performing the reset operation comprises:\n transmitting at least one reset signals each having a pulse waveform to the digital frequency divider continually; keeping a reset signal being transmitted to the digital frequency divider to be at an enabling level; or transmitting at least one reset signal to the digital frequency divider after an analog frequency divider of the phase locked loop circuit has stabilized and before the first predetermined time interval has elapsed.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 86.0
- Lexical Diversity: 2.13514
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14527049', '10867013', '11744365', '14910129', '13688203']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7727512305988828
- 35 USC 102 Novelty (BERT): 0.4702884379331707
- Combined Prediction Score: 0.7425049513323116
- Mean Citation Score: 156.357524
- Max Citation Score: 167.54793999999995
- Similarity Product: 124.47012861608265

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test