PATENT CLAIM ANALYSIS

Application Number: 15871793
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["257", "369000"]

Abstract:
A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

Claim (Index 9):
The semiconductor device according to  claim 8 , further comprising:\n a plurality of third wirings disposed over the third interlayer insulating film and disposed around the second wiring in plan view, wherein sidewalls of the plurality of third wirings abut on the fourth interlayer insulating film, and wherein the fourth interlayer insulating film surrounds each of the third wirings in plan view.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.30769
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15719830', '14826730', '15677546', '12216061', '15512933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9130978496949644
- 35 USC 102 Novelty (BERT): 0.4833726770539025
- Combined Prediction Score: 0.8701253324308583
- Mean Citation Score: 205.791446
- Max Citation Score: 214.66031
- Similarity Product: 167.39473219121575

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test