PATENT CLAIM ANALYSIS

Application Number: 15865793
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "359000"]

Abstract:
A method for manufacturing a thin film transistor includes: forming a source electrode and a first insulation pattern, where an orthographic projection of the first insulation pattern at a substrate is within an orthographic projection of the source electrode at the substrate; forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode not covered by the first insulation pattern and the first insulation pattern; exposing a first portion of the action layer on the first insulation pattern by removing parts of the gate electrode and the second insulation pattern; and performing a plasma treatment to the exposed first portion, thereby forming a drain electrode.

Claim (Index 17):
The thin film transistor of  claim 16 , wherein one part of the active layer is in direct contact with the exposed portion of the source electrode which is not covered by the first insulation pattern, and another part of the active layer is in direct contact with one part of the first insulation pattern.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14764307', '15742153', '13755730', '15505108', '14436995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9330331442951344
- 35 USC 102 Novelty (BERT): 0.5160504738918609
- Combined Prediction Score: 0.8913348772548071
- Mean Citation Score: 288.300038
- Max Citation Score: 311.1226200000001
- Similarity Product: 234.87439617489343

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test