PATENT CLAIM ANALYSIS

Application Number: 15919381
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "530000"]

Abstract:
The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTP V ). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTP V  comprises no separate diode layer.

Claim (Index 1):
1 A three-dimensional vertical one-time-programmable memory (3D-OTP V ), comprising:\n a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit; a plurality of memory holes through said horizontal address lines; an antifuse layer on the sidewalls of said memory holes, said antifuse layer comprising at least first and second sub-layers, wherein said first and second sub-layers comprise different antifuse materials; a plurality of vertical address lines in said memory holes; a plurality of OTP cells at the intersections of said horizontal address lines and said vertical address lines.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 1.53846
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15488489', '15488435', '15062117', '15333116', '15062118']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9186826533745918
- 35 USC 102 Novelty (BERT): 0.5200091617756678
- Combined Prediction Score: 0.8788153042146993
- Mean Citation Score: 251.87113
- Max Citation Score: 337.57724
- Similarity Product: 289.0197022122383

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test