PATENT CLAIM ANALYSIS

Application Number: 16051721
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-12
Patent Classification: ["257", "316000"]

Abstract:
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

Claim (Index 21):
A method for forming an integrated circuit (IC), the method comprising:\n forming a plurality of memory cell structures on a memory region of a substrate, wherein a memory cell structure of the plurality of memory cell structures is formed to have a pair of control gate electrodes respectively over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes; forming a plurality of logic devices on a logic region of the substrate, wherein a logic device of the plurality of logic devices is formed to have a logic gate electrode separated from the substrate by a logic gate dielectric; forming a sidewall spacer along a sidewall surface of the logic gate electrode; and forming a contact etch stop layer (CESL) along a top surface of the substrate, extending upwardly along sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along a sidewall surface of the sidewall spacer within the logic region; wherein the contact etch stop layer (CESL) is in direct contact with the sidewall surfaces of the pair of select gate electrodes and separated from the sidewall surface of the logic gate electrode by the sidewall spacer.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 96.0
- Lexical Diversity: 2.07246
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16015480', '15694098', '15904836', '15651403', '15162761']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913374533235649
- 35 USC 102 Novelty (BERT): 0.4777135657876797
- Combined Prediction Score: 0.869808436490852
- Mean Citation Score: 194.72472
- Max Citation Score: 224.91165
- Similarity Product: 190.181459203434

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test