PATENT CLAIM ANALYSIS

Application Number: 16107963
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "189070"]

Abstract:
An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

Claim (Index 7):
The apparatus of  claim 4 , wherein the second semiconductor chip further comprises a signal data moderator circuit configured to provide the first data responsive to the first timing signal and the command stack identifier indicative of the first stack group.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 96.0
- Lexical Diversity: 4.25
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15606956', '15176442', '15217719', '16013290', '15365563']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7866269627183882
- 35 USC 102 Novelty (BERT): 0.567328686524495
- Combined Prediction Score: 0.764697135098999
- Mean Citation Score: 280.96051
- Max Citation Score: 478.74332
- Similarity Product: 354.5297898986005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test