PATENT CLAIM ANALYSIS

Application Number: 15961337
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

Claim (Index 11):
A structure of comprising:\n a first vertical-transport field effect transistor including a bottom source/drain region, a first top source/drain region, a first semiconductor fin that extends from the bottom source/drain region to the first top source/drain region, and a first gate stack section arranged to surround a portion of the first semiconductor fin; a second vertical-transport field effect transistor including a second top source/drain region, a second semiconductor fin that extends from the bottom source/drain region to the second top source/drain region, and a second gate stack section arranged to surround a portion of the second semiconductor fin; an interlayer dielectric layer over the first vertical-transport field effect transistor; and a contact located in the interlayer dielectric layer over the bottom source/drain region, the contact extending vertically through the interlayer dielectric layer to contact the first gate stack section, wherein the first gate stack section includes a first section of a work function metal layer, the second gate stack section includes a metal gate capping layer and a second section of the work function metal layer that is arranged between the metal gate capping layer and the portion of the second semiconductor fin, the first gate stack section has a first thickness, and the second gate stack section has a second thickness that is greater than the first thickness.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 2.50943
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15586621', '15654165', '15671605', '15447639', '15694109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9221559159088792
- 35 USC 102 Novelty (BERT): 0.4998964467021419
- Combined Prediction Score: 0.8799299689882055
- Mean Citation Score: 262.74217200000004
- Max Citation Score: 288.24908
- Similarity Product: 249.0227114968372

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test