PATENT CLAIM ANALYSIS

Application Number: 16116357
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["341", "126000"]

Abstract:
According to embodiments, a signal processing device includes an AD converter, a memory, a prediction logic circuit, an error amount detection circuit, and a selector. The AD converter converts an input signal to an AD conversion value at a certain sampling frequency. The memory stores an AD conversion output result. The prediction logic circuit predicts a prediction value by using the AD conversion output result at the sampling frequency. The error amount detection circuit determines that there is no error in error determination of the AD conversion value when an error amount between the prediction value and the AD conversion value is smaller than a predetermined amount, and that there is an error in the error determination when the error amount is equal to or larger than the predetermined amount. The selector outputs one of the AD conversion value and the prediction value as an AD conversion output result, on the basis of the error determination.

Claim (Index 5):
The signal processing device according to  claim 4 , wherein\n the fixed coefficient value K is not less than \u22122 and not more than 2.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 96.0
- Lexical Diversity: 2.86441
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13862803', '15489944', '10542342', '12730978', '15348391']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5273790258057889
- 35 USC 102 Novelty (BERT): 0.5079449663880313
- Combined Prediction Score: 0.5254356198640131
- Mean Citation Score: 139.481724
- Max Citation Score: 155.08757
- Similarity Product: 93.21337175732612

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test