PATENT CLAIM ANALYSIS

Application Number: 15922642
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["712", "007000"]

Abstract:
An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.

Claim (Index 32):
The processor as in  claim 30 , wherein the vector compression circuitry is to initialize control data elements of the control vector to be equal to the indices of the bit mask prior to implementing the shift operations and shifts the control data elements of the control vector within each of the levels of shift operations.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 90.0
- Lexical Diversity: 2.7
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14499038', '13994060', '14580069', '13993058', '13991858']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6259996759408455
- 35 USC 102 Novelty (BERT): 0.5297944147362248
- Combined Prediction Score: 0.6163791498203834
- Mean Citation Score: 297.37766
- Max Citation Score: 367.53796
- Similarity Product: 287.6003920286656

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test