PATENT CLAIM ANALYSIS

Application Number: 16101789
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "156000"]

Abstract:
Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

Claim (Index 10):
The method of  claim 9 , the method further comprising:\n synchronizing the master latch and the slave latch using the inverted clock signal input to avoid a dual phase dependency of a clock signal.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 96.0
- Lexical Diversity: 2.05769
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11367535', '10674847', '14613414', '14863369', '15586011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.820647677533327
- 35 USC 102 Novelty (BERT): 0.510411577890268
- Combined Prediction Score: 0.7896240675690211
- Mean Citation Score: 303.204424
- Max Citation Score: 318.51965
- Similarity Product: 223.3865337483884

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test