PATENT CLAIM ANALYSIS

Application Number: 16158261
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "344000"]

Abstract:
The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

Claim (Index 1):
A metal oxide semiconductor (MOS) device, comprising:\n a semiconductor substrate, in which are formed a plurality of isolation structures substantially parallel to each other in a longitudinal direction, to define a device region, the semiconductor substrate having an upper surface and a lower surface opposing to each other in a vertical direction, wherein a first recess and a second recess are formed on the upper surface, the first recess and the second recess being substantially parallel to each other in the longitudinal direction; a gate, which is in the device region and on the upper surface of the semiconductor substrate; a source and a drain, which are at different sides of the gate, respectively; two lightly doped diffusions (LDDs) having a same conductive type as the source and the drain, which are at different sides of the gate, respectively; two vertical connection portions which connect the two LDDs to the source and the drain, respectively; and contacts formed by a conductive material in the first recess and the second recess, respectively, wherein, viewing from a cross-section view, the first recess and the second recess are at different sides of the gate and are located between the gate and one of the isolation structures, respectively; wherein, the first recess, in a lateral direction, has a first boundary closer to the gate and a second boundary farther from the gate, and the second recess, in the lateral direction, has a third boundary closer to the gate and a fourth boundary farther from the gate, the vertical connection portion of the source being formed at the first boundary of the first recess in the vertical direction, while the vertical connection portion of the drain being formed at the third boundary of the second recess in the vertical direction; wherein, the first boundary and the third boundary, in the lateral direction, do not extend beneath the gate; wherein, from the cross-section view, the first recess and the second recess have respective depths, and the two LDDs have a depth, and the depths of the first recess and the second recess are both deeper than the depth of the two LDDs; wherein, depth is defined as a distance extending from the upper surface of the semiconductor substrate downward in the vertical direction; and wherein, the longitudinal direction, vertical direction and lateral direction are perpendicular to one another.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.10938
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15585949', '15622227', '15296703', '11490012', '11779270']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8994443108425865
- 35 USC 102 Novelty (BERT): 0.5452801257839479
- Combined Prediction Score: 0.8640278923367226
- Mean Citation Score: 249.204826
- Max Citation Score: 382.4328
- Similarity Product: 348.19628458356857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test