PATENT CLAIM ANALYSIS

Application Number: 15941340
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "024000"]

Abstract:
The present application provides a thin film transistor, a method for fabricating the same, a method for driving the same, and a display device. The thin film transistor includes a gate pattern, a gate insulation layer, an active layer pattern, a source/drain pattern, and a passivation layer. The active layer pattern is made of a carbon nanotube material, and the passivation layer is made of a charge-resistant material capable of reducing mobile charges on a surface of the carbon nanotube material.

Claim (Index 14):
The method of  claim 13 , wherein\n the gate pattern is formed to comprise a first gate electrode and a second gate electrode formed in one patterning process and electrically insulated from each other, the gate insulation layer is formed to comprise a first gate insulation layer and a second gate insulation layer formed in one patterning process, the active layer pattern is formed to comprise a first active layer and a second active layer formed in one patterning process and electrically insulated from each other, the source/drain pattern is formed to comprise a first source/drain pattern and a second source/drain pattern formed in one patterning process, the first source/drain pattern comprises a first source electrode and a first drain electrode formed in one patterning process and electrically insulated from each other, the second source/drain pattern comprises a second source electrode and a second drain electrode formed in one patterning process and electrically insulated from each other, and one of the first source electrode and the first drain electrode is electrically connected to one of the second source electrode and the second drain electrode, and the first gate electrode, the first gate insulation layer, the first active layer, the first source/drain pattern and the passivation layer form a first sub TFT, and the second gate electrode, the second gate insulation layer, the second active layer, the second source/drain pattern and the passivation layer form a second sub TFT.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 90.0
- Lexical Diversity: 2.2439
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15677542', '12188956', '15441245', '14787396', '15441246']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9268797054062564
- 35 USC 102 Novelty (BERT): 0.5068321861043534
- Combined Prediction Score: 0.884874953476066
- Mean Citation Score: 242.54152
- Max Citation Score: 284.5655
- Similarity Product: 221.657472341299

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test