PATENT CLAIM ANALYSIS

Application Number: 16032085
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "668000"]

Abstract:
The present invention provides a semiconductor substrate ( 105, 105 a ) comprising two or more layers of built-up structural layers ( 120, 220 ) formed on a sacrificial carrier ( 110 ). Each built-up structural layer, comprising a conductor trace layer ( 114 a ,) and an interconnect ( 118 a,  218 a ), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer ( 123, 124, 224 ). A multi-layer substrate ( 105, 105 a ) is then obtained after an outermost conductor trace layer ( 128 a,  228 a ) is formed on the adhesion layer and the carrier ( 110 ) or reinforcing ring ( 110 b ) is removed.

Claim (Index 6):
A multi-layer semiconductor substrate according to  claim 3 , further comprising a second insulating layer deposited on the second conductor trace layer, so that the second insulating layer is selectively removed to expose areas of the second conductor trace layer for external electrical connections.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 2.15152
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14387843', '12168280', '13047991', '12961107', '11924156']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8897536391358948
- 35 USC 102 Novelty (BERT): 0.5028699424393218
- Combined Prediction Score: 0.8510652694662375
- Mean Citation Score: 158.043542
- Max Citation Score: 261.1766
- Similarity Product: 209.3988850276947

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test