PATENT CLAIM ANALYSIS

Application Number: 15949774
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["365", "156000"]

Abstract:
A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.

Claim (Index 8):
A write assist circuit comprising:\n a first PMOS transistor and a first NMOS transistor connected in series between a power-supply voltage and a first node, gate electrodes of the first PMOS transistor and the first NMOS transistor being connected to a second node, the second node being connected to a data_bar line; a first switchable conductive path between the first node and a ground voltage; a second PMOS transistor and a second NMOS transistor connected in series between the power-supply voltage and a third node, gate electrodes of the second PMOS transistor and the second NMOS transistor being connected to a fourth node, the fourth node being connected to a data line; a second switchable conductive path between the third node and the ground voltage; a third NMOS transistor having a high resistance configuration and for which a first drain/source electrode is connected to the fourth node; a first shunt connecting the fourth node and the data line; a fourth NMOS transistor having a high resistance configuration and for which a first drain/source electrode is connected to the second node; and a second shunt connecting the second node and the data_bar line.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 91.0
- Lexical Diversity: 3.28889
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12958402', '14677991', '11750052', '13025872', '13901614']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7926900148500184
- 35 USC 102 Novelty (BERT): 0.4752272214880484
- Combined Prediction Score: 0.7609437355138214
- Mean Citation Score: 200.852354
- Max Citation Score: 212.45723
- Similarity Product: 162.36858501198472

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test