PATENT CLAIM ANALYSIS

Application Number: 15938043
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "324000"]

Abstract:
In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

Claim (Index 10):
An integrated circuit including a pair of split gate flash memory cells, comprising:\n a semiconductor substrate including a common source/drain region and first and second individual source/drain regions which are separated from the common source/drain region by first and second channel regions, respectively; first and second select gates spaced over the first and second channel regions, respectively, and separated from the first and second channel regions by first and second select gate dielectrics, respectively; first and second memory gates spaced over the first and second channel regions, respectively, and separated from the semiconductor substrate by a charge-trapping dielectric structure, wherein the charge-trapping dielectric structure extends upwardly along outer sidewalls of the first and second select gates to separate the outer sidewalls of the first and second select gates from inner sidewalls of the first and second memory gates; and an oxide spacer or nitride-free spacer, which is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the first or second individual source/drain region.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 2.81818
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14933046', '14733011', '14688011', '14332556', '14980165']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9165042935507568
- 35 USC 102 Novelty (BERT): 0.4831278721949676
- Combined Prediction Score: 0.8731666514151779
- Mean Citation Score: 219.89003
- Max Citation Score: 251.11055
- Similarity Product: 223.96572479770785

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test