PATENT CLAIM ANALYSIS

Application Number: 15935274
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["713", "501000"]

Abstract:
In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Claim (Index 11):
The apparatus as recited in  claim 10 , wherein:\n the second processor core is configured to detect that the second feature is used in the code; and the second processor core is configured to signal the different exception in response to detecting use of the second feature.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.02703
- Patent Class: 713.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14548912', '15866014', '14548872', '14844212', '12356761']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4893772845804803
- 35 USC 102 Novelty (BERT): 0.5491071220941562
- Combined Prediction Score: 0.4953502683318479
- Mean Citation Score: 346.589924
- Max Citation Score: 438.4663
- Similarity Product: 276.15233140820266

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test