PATENT CLAIM ANALYSIS

Application Number: 16110917
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["711", "108000"]

Abstract:
A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an instruction cache. In response to the CLA subsequently hitting in the instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the instruction cache.

Claim (Index 8):
A processor, comprising:\n a level one (L1) instruction cache; and an instruction fetch unit including a prefetch filter queue and a backing array, wherein the instruction fetch unit is coupled to the L1 instruction cache and is configured to:\n in response to a cache line address missing in the L1 instruction cache, allocate an entry in the prefetch filter queue for the cache line address; \n in response to the cache line address subsequently hitting in the L1 instruction cache, update an associated prefetch value for the entry in the prefetch filter queue, wherein the associated prefetch value corresponds to a number of entries in the prefetch filter queue that have cache line addresses that are sequential to the cache line address; \n in response to the entry being aged-out of the prefetch filter queue, allocate an entry in the backing array for the cache line address and the associated prefetch value; \n in response to subsequently determining that prefetching is required for the cache line address, access the backing array to determine the associated prefetch value for the cache line address; and \n in response to the backing array including the entry for the cache line address, prefetch a cache line at the cache line address and a number of sequential cache lines that follow the cache line address, as specified by the associated prefetch value in the backing array, into the L1 instruction cache.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.56897
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15151609', '15072717', '10197714', '12185219', '13023615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5403726537969199
- 35 USC 102 Novelty (BERT): 0.5782011258185128
- Combined Prediction Score: 0.5441555009990792
- Mean Citation Score: 315.798144
- Max Citation Score: 477.6528
- Similarity Product: 447.7728233050347

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test