PATENT CLAIM ANALYSIS

Application Number: 15872097
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["714", "764000"]

Abstract:
Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Claim (Index 11):
The apparatus of  claim 8 , further comprising:\n in response to selecting, based on the detected error, the order of the ECC decoder of the ECC, allocating an unused portion of the ECC memory chip for mainline data storage.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.76087
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15143865', '13015850', '11907876', '15640182', '13523091']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2914055384305097
- 35 USC 102 Novelty (BERT): 0.4708941652334935
- Combined Prediction Score: 0.3093544011108081
- Mean Citation Score: 180.850824
- Max Citation Score: 194.23546
- Similarity Product: 150.02444022843838

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test