PATENT CLAIM ANALYSIS

Application Number: 15916519
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "250000"]

Abstract:
Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.

Claim (Index 6):
The transistor device of  claim 1 , wherein the first gate structure controls a state and an operation of the transistor device and the second gate structure modulates a threshold voltage at a source of the transistor device.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 2.51351
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15898314', '15838963', '15846574', '15828386', '15609603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9201920711302944
- 35 USC 102 Novelty (BERT): 0.4696057532374851
- Combined Prediction Score: 0.8751334393410135
- Mean Citation Score: 176.881794
- Max Citation Score: 186.25536
- Similarity Product: 152.10692241394042

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test