PATENT CLAIM ANALYSIS

Application Number: 15991732
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["710", "104000"]

Abstract:
A method for detecting and identifying modules of a bus system is provided. The bus system includes a control unit, a bus starting from the control unit, and a plurality of modules connected to the bus. The method includes providing a current sink associated with each of the one or more modules. The current sink includes a transistor. The method includes providing a hall sensor associated with each of the one or more modules. The hall sensor detects a current on a low-side data line of the bus. For each one of the one or more modules: when the hall sensor detects a current on the low-side data line, the method includes maintaining a closed position of the transistor; and when the hall sensor fails to detect a current on the low-side data line, the method includes opening the transistor such that current does not flow to the module.

Claim (Index 12):
The system of  claim 8 , further comprising, when the hall sensor fails to detect a current on the low-side data line, the module associated with the hall sensor determines that the module is a last module positioned on the communication bus.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 93.0
- Lexical Diversity: 2.7931
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13098590', '13226025', '14828903', '13357255', '10607230']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.646265829718728
- 35 USC 102 Novelty (BERT): 0.4869487556588695
- Combined Prediction Score: 0.6303341223127422
- Mean Citation Score: 142.384346
- Max Citation Score: 152.64728
- Similarity Product: 92.28441498575688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test