PATENT CLAIM ANALYSIS

Application Number: 15741824
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["345", "214000"]

Abstract:
An OLED pixel driving circuit includes a first TFT, having a gate connected to a second node, and a source and a drain connected to a third node and a fourth node respectively; a second TFT, having a gate receiving a first signal, and a source and a drain connected to the second node and the fourth node respectively; a third TFT, having a gate receiving a second signal, and a source and a drain connected to a first node and the second node respectively; a fourth TFT, having a gate receiving a third signal, and a source and a drain connected to the fourth node and an anode of an OLED respectively; and a capacitor having two ends connected to the first node and the second node respectively. The third node is connected to a high voltage source and the first node is connected to a voltage input end.

Claim (Index 11):
An OLED pixel driving circuit, comprising:\n a first thin film transistor (TFT), having a gate electrode thereof connected to a second node, and having a source electrode and a drain electrode thereof connected to a third node and a fourth node respectively; a second TFT, having a gate electrode thereof receiving a first signal, and having a source electrode and a drain electrode thereof connected to the second node and the fourth node respectively; a third TFT, having a gate electrode thereof receiving a second signal, and having a source electrode and a drain electrode thereof connected to a first node and the second node respectively; a fourth TFT, having a gate electrode receiving a third signal, and having a source electrode and a drain electrode thereof connected to the fourth node and an anode of an OLED respectively, and the OLED having a cathode connected to a low voltage power source; and a capacitor, having two ends thereof connected to the first node and the second node respectively; wherein the third node is connected to a high voltage power source; wherein the first node is connected to a voltage input end for inputting a data voltage or a reference voltage; wherein the first TFT, the second TFT, the third TFT, and the fourth TFT are P-type transistors; wherein a timing arrangement of the first signal, the second signal, and the third signal includes a data voltage storing stage, a threshold compensation stage, and an illumination stage; wherein during the data voltage storing stage and the threshold voltage compensation stage, the voltage input end inputs the data voltage; wherein during the illumination stage, the voltage input end inputs the reference voltage; wherein during the data voltage storing stage, the first signal is at a high level, the second signal is at a low level, and the third signal is at a high level.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 4.20513
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15741865', '15533445', '15574930', '15744829', '15580280']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6885470490789728
- 35 USC 102 Novelty (BERT): 0.5445703063485874
- Combined Prediction Score: 0.6741493748059343
- Mean Citation Score: 331.5576779999999
- Max Citation Score: 404.1353
- Similarity Product: 354.3037730664074

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test