PATENT CLAIM ANALYSIS

Application Number: 16119462
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["375", "355000"]

Abstract:
A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Claim (Index 10):
A clock/data recovery system, comprising:\n a phase detector configured to generate a buffered data signal and a phase difference control signal based on an input data signal and a clock signal, wherein the phase difference control signal is indicative of a phase difference between the clock signal and the input data signal; a frequency detector configured to receive the input signal and generate a frequency difference control signal indicative of a frequency difference between the input data signal and the clock signal, the frequency detector comprising:\n a sampling circuit configured to generate a frequency control signal and a switch circuit control signal based on the frequency difference between the clock signal and the input data signal; and \n a voltage-to-current converter circuit coupled to the sampling circuit and configured to convert the frequency control signal to a frequency control current in response to the switch circuit control signal; and \n a filter coupled to the phase detector and the frequency detector and configured to output a control signal providing an indication of a phase difference and a frequency difference between the input data signal and the clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.54167
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15394506', '14108834', '10820691', '09712104', '16052027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4764682606423361
- 35 USC 102 Novelty (BERT): 0.5236932559765737
- Combined Prediction Score: 0.4811907601757599
- Mean Citation Score: 239.427052
- Max Citation Score: 348.4434
- Similarity Product: 310.61151563404803

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test