PATENT CLAIM ANALYSIS

Application Number: 15886813
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["438", "598000"]

Abstract:
A method for fabricating a microelectronic package is disclosed. A packaged substrate having a chip surrounded by a molding compound is prepared. An RDL structure is formed on the chip. Bump pads and SMD pads are disposed in a topmost level of metal interconnect of the RDL structure. A passivation layer covers the RDL structure. The passivation layer is subjected to a lithographic process to form bump pad openings and an SMD opening in the passivation layer. The bump pads are exposed, respectively, through the bump pad openings. The SMD pads are exposed through the SMD opening. Bumps are formed on the bump pads through the bump pad openings, respectively. A passive element is mounted on the SMD pads.

Claim (Index 21):
The method for fabricating a microelectronic package according to  claim 16 , wherein the passive element comprises a decoupling capacitor, a resistor, an inductor, or an integrated passive device (IPD).

Metadata:
- Claim Count in Document: 42.0
- Percentile: 88.0
- Lexical Diversity: 2.23729
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15069911', '15825055', '13085759', '15354447', '13234842']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8827378147741869
- 35 USC 102 Novelty (BERT): 0.4997323862306806
- Combined Prediction Score: 0.8444372719198363
- Mean Citation Score: 261.234636
- Max Citation Score: 277.68793
- Similarity Product: 233.94070220636192

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test