PATENT CLAIM ANALYSIS

Application Number: 16018606
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "328000"]

Abstract:
A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.

Claim (Index 13):
The method of  claim 12 , further comprising forming a fill layer on the work function metal layer, wherein a portion of the work function metal layer is exposed above the top surface of the fill layer, and removing the exposed portion of the work function metal layer and underlying gate dielectric layer to form indents.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 94.0
- Lexical Diversity: 2.8
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15876905', '15948563', '16008687', '15843786', '15860957']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9284245187035948
- 35 USC 102 Novelty (BERT): 0.5179155556798866
- Combined Prediction Score: 0.887373622401224
- Mean Citation Score: 309.094958
- Max Citation Score: 320.30252
- Similarity Product: 228.53724903195143

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test