PATENT CLAIM ANALYSIS

Application Number: 16049256
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "500000"]

Abstract:
An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.

Claim (Index 3):
The method of  claim 1 , wherein the crack suppressing dielectric structure is deposited after the patterning and the etching of the top metal feature so that so that the crack suppressing dielectric structure is also positioned on sidewalls of the top metal feature.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 1.71429
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15857234', '15478615', '12555162', '15071725', '13945435']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9133522601839306
- 35 USC 102 Novelty (BERT): 0.4905386303587285
- Combined Prediction Score: 0.8710708972014104
- Mean Citation Score: 147.035052
- Max Citation Score: 170.37573
- Similarity Product: 110.6156557975352

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test