PATENT CLAIM ANALYSIS

Application Number: 16050428
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A package structure includes a metal carrier, a conductive adhesive layer disposed on the metal carrier, a conductive post disposed on the conductive adhesive layer, a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, and a redistribution layer disposed on the conductive post and the semiconductor chip. The semiconductor chip includes a first terminal at an upper surface of the semiconductor chip. The first terminal of the semiconductor chip is electrically connected to the bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer.

Claim (Index 18):
A method for fabricating a package structure, comprising:\n bonding a first conductive post and a first semiconductor chip, which is laterally spaced from the first conductive post, to a metal carrier through a first conductive adhesive layer, wherein the first conductive post comprises source, drain and gate terminals at an upper surface of the first semiconductor chip; bonding a second conductive post and a second semiconductor chip, which is laterally spaced from the second conductive post, to the metal carrier through a second conductive adhesive layer, wherein the second conductive post comprises source, drain and gate terminals at an upper surface of the second semiconductor chip; forming a first insulating layer on the metal carrier to encapsulate the first and second conductive posts, and the first and second semiconductor chips; and forming a redistribution layer on the first insulating layer; wherein the source terminal of the first semiconductor chip is electrically connected to a bottom surface of the first semiconductor chip through the redistribution layer, the first conductive post and the first conductive adhesive layer, wherein the source terminal of the first semiconductor chip is electrically connected to the drain terminal of the second semiconductor chip through the redistribution layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 2.89189
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14157379', '12899258', '14814524', '14747507', '12759699']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5890920078026314
- 35 USC 102 Novelty (BERT): 0.4796157293361721
- Combined Prediction Score: 0.5781443799559856
- Mean Citation Score: 228.263842
- Max Citation Score: 236.12268
- Similarity Product: 183.1009923581028

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test