PATENT CLAIM ANALYSIS

Application Number: 16217876
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "329000"]

Abstract:
A semiconductor device includes gate stacked structures surrounding channel layers, a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, and a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

Claim (Index 12):
The method of  claim 8 , wherein the second sacrificial pillars overlap with the first slits.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 98.0
- Lexical Diversity: 1.45
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15638496', '14870164', '16033825', '14560638', '15007404']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9248125070380256
- 35 USC 102 Novelty (BERT): 0.5291057630427095
- Combined Prediction Score: 0.885241832638494
- Mean Citation Score: 242.669732
- Max Citation Score: 334.96136
- Similarity Product: 198.8338934991312

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test