PATENT CLAIM ANALYSIS

Application Number: 16207218
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "401000"]

Abstract:
A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Claim (Index 16):
The semiconductor structure of  claim 15 , wherein the second contact portion of the gate contact comprises at least one protrusion in contact with the at least one depressed contact surface of the dielectric structure.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 98.0
- Lexical Diversity: 3.43182
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15715153', '14968906', '15054141', '15099606', '15062224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9235988728045424
- 35 USC 102 Novelty (BERT): 0.5000541826053163
- Combined Prediction Score: 0.8812444037846199
- Mean Citation Score: 216.916814
- Max Citation Score: 269.0263
- Similarity Product: 216.35266450924868

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test