PATENT CLAIM ANALYSIS

Application Number: 16123915
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["716", "108000"]

Abstract:
A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

Claim (Index 13):
A system comprising:\n an emulator configured to emulate a design under test (DUT) for fabrication, and configured to trace waveforms of signals of the DUT for a time frame including a plurality of clock cycles; and a host system communicatively coupled to the emulator through an interface, the host system configured to:\n determine a first duration of a time frame at which a waveform of a reference signal of a logic gate of a plurality of logic gates is in a first state and a second duration of the time frame at which the waveform of the reference signal is in a second state different from the first state, the time frame including a plurality of clock cycles, the waveform of the reference signal obtained based on a waveform traced by the emulator, the plurality of logic gates comprising logic gates included in the DUT; \n determine a periodicity in an input waveform of an input signal of the logic gate in the first duration; \n generate an output waveform of an output signal of the logic gate for the time frame based on the determined periodicity in the first duration and irrespective of the input waveform of the input signal in the second duration, the output signal of the logic gate not traced by the emulator; and \n verify the DUT based on the output waveform prior to fabricating the DUT.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.49123
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15278659', '14745239', '15007040', '14507696', '15447010']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3027398812193858
- 35 USC 102 Novelty (BERT): 0.5134905589918946
- Combined Prediction Score: 0.3238149489966367
- Mean Citation Score: 235.627084
- Max Citation Score: 346.1858
- Similarity Product: 280.83232544484144

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test