PATENT CLAIM ANALYSIS

Application Number: 16160223
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "043000"]

Abstract:
Disclosed is an array substrate and a display device. The array substrate includes: a plurality of gate lines and a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other, wherein each pixel unit includes a thin film transistor and a pixel electrode connected with the thin film transistor, the pixel electrode, the data line, as well as an active layer, a source and a drain of the thin film transistor are disposed in a same layer and are formed through a single patterning process,

Claim (Index 6):
The array substrate of  claim 1 , wherein a material for the pixel electrode, the data line, as well as the active layer, the source and the drain of the thin film transistors comprises at least one of indium gallium zinc oxide, indium gallium tin oxide, or indium tin oxide.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 97.0
- Lexical Diversity: 2.16981
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14421947', '13985196', '14379818', '14380168', '14436995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.928801885761934
- 35 USC 102 Novelty (BERT): 0.5203193898605634
- Combined Prediction Score: 0.887953636171797
- Mean Citation Score: 277.96001800000005
- Max Citation Score: 330.26465
- Similarity Product: 272.20244286932945

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test