PATENT CLAIM ANALYSIS

Application Number: 16402603
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "621000"]

Abstract:
Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.

Claim (Index 3):
The semiconductor structure of  claim 1 , wherein the first interconnect feature comprises a second barrier layer, and wherein the first barrier layer and the second barrier layer comprise a same material.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 100.0
- Lexical Diversity: 2.14286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15859872', '14158577', '14081969', '13550140', '14044716']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9282265528031168
- 35 USC 102 Novelty (BERT): 0.5132788062223483
- Combined Prediction Score: 0.8867317781450399
- Mean Citation Score: 247.573136
- Max Citation Score: 326.97894
- Similarity Product: 298.8371680602981

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test