PATENT CLAIM ANALYSIS

Application Number: 15899497
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["714", "731000"]

Abstract:
Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.

Claim (Index 1):
A digital logic circuit which is configured to deter a race violation at an array test control boundary, comprising:\n a clock generation circuitry, wherein the clock generation circuitry includes:\n a first local clock buffer to generate:\n the primary scan clock signal feature, \n the secondary scan clock signal feature, and \n the pulsed clock signal feature; and \n \n a second local clock buffer to generate an array clock signal feature, the clock generation circuitry having both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature, and wherein the clock generation circuitry is configured to output an output clock signal feature when indicated by a first enable input, and wherein the output clock signal feature is based on what a scan enable input indicates the clock generation circuitry to generate:\n the array clock signal feature, \n a primary scan clock signal feature, \n a secondary scan clock signal feature, and \n a pulsed clock signal feature; \n \n a scanable storage element having both a scanable storage element output and a set of flip-flops, the set of flip-flops including:\n a first primary flip-flop which corresponds to a functional data path of the digital logic circuit, wherein the first primary flip-flop connects with the derivative clock signal feature, \n a second primary flip-flop which corresponds to a scan data path of the digital logic circuit, wherein the second primary flip-flop connects with the secondary scan clock signal feature and wherein the second primary flip-flop and the secondary flip-flop are part of the scan data path, and \n a secondary flip-flop connected to both the pulsed clock signal feature and the scan clock signal feature, wherein the secondary flip-flop is configured to input the output of:\n the first primary flip-flop when indicated by the pulsed clock signal feature, and \n the second primary flip-flop when indicated by the secondary scan clock signal feature, and wherein the second primary flip-flop is used in a nonperformance critical scan operation; and \n \n \n a memory array connected with:\n the scanable storage element output, and \n the array clock signal feature, wherein the memory array includes an array of static random-access memory (SRAM) cells. And wherein the digital logic circuit is configured to avoid the race violation between a set of output data of the first primary flip-flop and the pulsed clock signal feature at the secondary flip-flop independent of the what the derivative clock signal feature indicates, wherein all clock signal features are derived from a common global clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.04762
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15414600', '12685969', '12753834', '10249353', '12607657']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3051747201719026
- 35 USC 102 Novelty (BERT): 0.5464162831933185
- Combined Prediction Score: 0.3292988764740442
- Mean Citation Score: 231.954314
- Max Citation Score: 415.57434
- Similarity Product: 357.79732041531446

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test