PATENT CLAIM ANALYSIS

Application Number: 16005999
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["716", "112000"]

Abstract:
A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Claim (Index 1):
A method for generating physical design layout patterns, comprising steps of:\n selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure; converting the physical design layout patterns into two-dimensional arrays, a given two-dimensional array for a given physical design layout pattern comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations; training, utilizing the two-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network; and generating one or more synthetic two-dimensional arrays utilizing the trained generator neural network of the GAN, a given one of the synthetic two-dimensional arrays comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern; wherein the method is performed by at least one processing device comprising a processor coupled to a memory.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 94.0
- Lexical Diversity: 2.62295
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15994598', '16001531', '15994461', '15994396', '15604012']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3467682872641633
- 35 USC 102 Novelty (BERT): 0.5353986016782508
- Combined Prediction Score: 0.3656313187055721
- Mean Citation Score: 271.709514
- Max Citation Score: 420.05768
- Similarity Product: 372.7462789988804

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test