PATENT CLAIM ANALYSIS

Application Number: 15869437
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["455", "264000"]

Abstract:
A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

Claim (Index 12):
The LO generator of  claim 7 , wherein\n at least one first frequency divider of the plurality of first frequency dividers includes an injection-locked oscillator, the injection-locked oscillator including a plurality of gated inverters, the injection-locked oscillator including a sequence of stages, each stage including at least two gated inverters of the plurality of gated inverters, each gated inverter of the plurality of gated inverters includes first and second PMOS transistors and first and second NMOS transistors connected in series sequentially between a positive power voltage and a negative power voltage, the at least one first frequency divider is configured to generate, in a given stage of the sequence of stages, an input signal of a next stage in a plurality of drains of a second PMOS transistor and a first NMOS transistor of a gate inverter of the given stage, respectively, the at least one first frequency divider is configured to apply, in the given stage of the sequence of stages, an output signal of a previous stage to a plurality of gates of a first PMOS transistor and a second NMOS transistor of the gate inverter of the given stage, respectively, and the at least one first frequency divider is configured to apply the first internal oscillator signal to a plurality of gates of the second PMOS transistor and the first NMOS transistor of the gate inverter of the given stage, respectively.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 455.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11502236', '15408399', '14714954', '12118769', '11478667']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7330840414667994
- 35 USC 102 Novelty (BERT): 0.5066768723878831
- Combined Prediction Score: 0.7104433245589078
- Mean Citation Score: 248.730784
- Max Citation Score: 268.32108
- Similarity Product: 187.7461782949591

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test