PATENT CLAIM ANALYSIS

Application Number: 15957790
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "145000"]

Abstract:
Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.

Claim (Index 11):
An apparatus, comprising:\n an amplifier capacitor coupled with a digit line associated with a memory cell; and an amplifier component configured to be selectively coupled with the digit line and with the amplifier capacitor, the amplifier component comprising: a plurality of transistors, and a plurality of switching components configured to select a mode of the amplifier component by activating one or more electrical connections between respective transistors, the plurality of switching components configured to select the mode as an amplifier mode that configures the amplifier component to, while an input of the amplifier component is coupled with the digit line and an output of the amplifier component is coupled with the amplifier capacitor, adjust a voltage of the amplifier capacitor, and the plurality of switching components configured to select the mode as a latch mode that configures the amplifier component to latch a state of the memory cell in response to an activation signal, wherein the plurality of switching components are configured to select the mode as the amplifier mode which configures a first transistor of the plurality of transistors and a second transistor of the plurality of transistors to operate in a current mirror mode by activating an electrical connection between a gate of the first transistor and a gate of the second transistor.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 91.0
- Lexical Diversity: 2.37681
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15067838', '15246249', '15957742', '15090789', '15844154']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7725153955732389
- 35 USC 102 Novelty (BERT): 0.4880029005272076
- Combined Prediction Score: 0.7440641460686358
- Mean Citation Score: 237.947584
- Max Citation Score: 243.13431
- Similarity Product: 194.5598972081852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test