PATENT CLAIM ANALYSIS

Application Number: 15917507
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["710", "100000"]

Abstract:
System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Claim (Index 6):
The method of  claim 1 , wherein an input filter of a receiver is configured to suppress pulses that have a duration that is less than 50 nanoseconds.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 2.31746
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14243459', '14700860', '15179470', '14694618', '15895856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7577316764922105
- 35 USC 102 Novelty (BERT): 0.5903996464347274
- Combined Prediction Score: 0.7409984734864622
- Mean Citation Score: 405.183606
- Max Citation Score: 497.28583
- Similarity Product: 493.43519712615904

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test