PATENT CLAIM ANALYSIS

Application Number: 16194991
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["326", "040000"]

Abstract:
Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Claim (Index 26):
The programmable integrated circuit device of  claim 25 , wherein the respective activation signal is transmitted by the first address register and by the second address register in response to the first data line segment transmitting the first data frame associated to the first plurality of CRAMs and the second data line segment transmitting the second data frame to the second plurality of CRAMs.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 98.0
- Lexical Diversity: 1.55072
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15197356', '15489535', '14685098', '16146849', '11055475']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6858687906496046
- 35 USC 102 Novelty (BERT): 0.4997167188449468
- Combined Prediction Score: 0.6672535834691389
- Mean Citation Score: 210.204742
- Max Citation Score: 259.158
- Similarity Product: 181.409376595974

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test