PATENT CLAIM ANALYSIS

Application Number: 16359029
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
An output driver includes a pre-driver receiving a driver control code to generate a pull-up control signal or a pull-down control signal in response to data while a read operation is performed, an on-die termination controller receiving a first on-die termination control code to generate a first on-die termination control signal in response to an on-die termination enable signal while a write operation is performed, and a main driver including a pull-up n-channel metal-oxide-semiconductor (NMOS) driver generating high-level output data in response to the pull-up control signal while the read operation is performed, and terminating high-level input data with a first high voltage and terminating low-level input data with a first low voltage in response to the first on-die termination control signal while the write operation is performed, and a pull-down NMOS driver generating low-level output data in response to the pull-down control signal while the read operation is performed.

Claim (Index 17):
A memory system comprising:\n a first inverted chip selection signal line, a second inverted chip selection signal line, a command and address line, and a data line configured to transmit a first inverted chip selection signal, a second inverted chip selection signal, a command and address, and data, respectively; a first memory configured to receive the first inverted chip selection signal and the command and address, and receive or output the data; and a second memory configured to receive or output the second inverted chip selection signal, the command and address, and the data, wherein each of the first memory and the second memory comprises: a command and address generator configured to decode the first inverted chip selection signal or the second inverted chip selection signal and a command signal included in the command and address to generate a write command or a read command, and generate an address signal included in the command and address as a row address or a column address, a latency control signal generator configured to generate an on-die termination enable signal, which is activated using a value of a write latency and inactivated using the value of the write latency and a value of a burst length in response to the write command, and generate a read control signal, which is activated using a value of a read latency and inactivated using the value of the read latency and the value of the burst length in response to the read command, a memory cell array comprising a plurality of memory cells and configured to receive or output data from/to memory cells selected in response to the row address and the column address, an on-die termination controller configured to receive a first on-die termination control code to generate a first on-die termination control signal in response to the write command and the on-die termination enable signal, a pre-driver configured to be enabled in response to the read control signal receive a driver control code to generate a pull-up control signal or a pull-down control signal in response to data which is output from the memory cell array, and a main driver comprising a pull-up n-channel metal-oxide-semiconductor (NMOS) driver and a pull-down NMOS driver, wherein the pull-up NMOS driver is configured to generate high-level output data in response to the pull-up control signal, or terminate high-level input data with a first high voltage which is lower than or equal to an output power supply voltage and terminate low-level input data with a first low voltage between the first high voltage and a ground voltage, in response to the first on-die termination control signal, and the pull-down NMOS driver is configured to generate low-level output data in response to the pull-down control signal.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 99.0
- Lexical Diversity: 3.14
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13048219', '14093916', '14723614', '14460764', '15426603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.605380273273878
- 35 USC 102 Novelty (BERT): 0.5039457272557107
- Combined Prediction Score: 0.5952368186720614
- Mean Citation Score: 284.644152
- Max Citation Score: 300.2191
- Similarity Product: 212.85709297957425

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test