PATENT CLAIM ANALYSIS

Application Number: 16037985
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["438", "009000"]

Abstract:
Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

Claim (Index 16):
A method for semiconductor processing, the method comprising:\n forming a first ruthenium layer over a substrate; forming a first etch stop layer over the first ruthenium layer; forming a second ruthenium layer over the first etch stop layer; forming a second etch stop layer over the second ruthenium layer; forming a mask layer over the second etch stop layer; forming a hardmask layer over the mask layer; patterning the hardmask layer and the mask layer to a line pattern; transferring the line pattern to the second etch stop layer; after transferring the line pattern to the second etch stop layer, removing the hardmask layer using an oxygen-containing ash process; after removing the hardmask layer, transferring the line pattern to the second ruthenium layer comprising etching the second ruthenium layer using a gas mixture comprising oxygen and chlorine, wherein, in the gas mixture, a ratio of (i) a flow rate of the oxygen to (ii) the flow rate of the oxygen plus a flow rate of the chlorine is in a range from 82% to 95%; simultaneously patterning the second etch stop layer to a via pattern and transferring the line pattern to the first etch stop layer; simultaneously transferring the via pattern to the second ruthenium layer to form a via and transferring the line pattern to the first ruthenium layer to form a line; and forming a dielectric on the via and line.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 95.0
- Lexical Diversity: 2.09434
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14543683', '11117854', '14603018', '15818947', '14533999']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8922930970024693
- 35 USC 102 Novelty (BERT): 0.5009027803674186
- Combined Prediction Score: 0.8531540653389642
- Mean Citation Score: 213.54447
- Max Citation Score: 220.2189
- Similarity Product: 132.94224756009578

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test