PATENT CLAIM ANALYSIS

Application Number: 15961827
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-09
Patent Classification: ["257", "532000"]

Abstract:
A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

Claim (Index 13):
The method according to  claim 12 , wherein the stack structure further comprises a tungsten nitride layer between the titanium nitride layer and the tungsten layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.66667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12650261', '12972404', '12648710', '13241110', '12979865']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9251494947158428
- 35 USC 102 Novelty (BERT): 0.4883047739667603
- Combined Prediction Score: 0.8814650226409345
- Mean Citation Score: 215.757096
- Max Citation Score: 218.56407
- Similarity Product: 164.4220292676079

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test