PATENT CLAIM ANALYSIS

Application Number: 15949556
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["345", "571000"]

Abstract:
A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.

Claim (Index 2):
The display device according to  claim 1 , further comprising:\n a plurality of gate line groups provided to respective rows and each including a plurality of gate lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a gate line driving circuit configured to sequentially output a gate signal to the rows in writing the sub-pixel data into the memory blocks, the gate signal being a signal for selecting one of the rows; a plurality of source lines provided to respective columns; a source line driving circuit configured to output a plurality of pieces of the sub-pixel data to the respective source lines in writing the sub-pixel data into the memory blocks; and a gate line selection circuit configured to electrically couple one of the gate lines in each of the gate line groups to the gate line driving circuit in writing the sub-pixel data into the memory blocks, wherein in accordance with one of the gate lines that has the gate signal supplied thereto, each of the sub-pixels in one of the rows that has the gate signal supplied thereto stores, in one of the memories therein, the sub-pixel data supplied to the corresponding source line.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 2.62712
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12083992', '15699634', '14259983', '10303770', '09945826']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6492251188301482
- 35 USC 102 Novelty (BERT): 0.4749696403004688
- Combined Prediction Score: 0.6317995709771803
- Mean Citation Score: 203.915274
- Max Citation Score: 211.77795
- Similarity Product: 173.3027960474968

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test