PATENT CLAIM ANALYSIS

Application Number: 16252211
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["708", "650000"]

Abstract:
A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. Each iteration includes generating hardware design components for mapping the input range to the target output range using each of a plurality of modulo preserving range reduction methods, synthesizing the generated hardware design components, and selecting one of the generated hardware design components based on the results of the synthesis.

Claim (Index 11):
A modulo hardware generation engine configured to generate a hardware design to calculate a modulo value for any integer input value in a target input range with respect to a constant value d, the hardware design comprising one or more range reduction stages, the engine comprising:\n a plurality of range reduction modules, each range reduction module configured to generate a hardware design component to map an input range using one of a plurality of modulo preserving range reduction methods; a synthesis module configured to generate one or more synthesis metrics for a hardware design component, the one or more synthesis metrics providing an indication of a quality of a synthesized version of the hardware design component; decision logic in communication with the plurality of range reduction modules and the synthesis module, the decision logic configured to:\n (a) generate at least one hardware design component to map a desired input range to a target output range using each of the plurality of range reduction modules; \n (b) obtain one or more synthesis metrics for each of the hardware design components from the synthesis module; \n (c) select one of the hardware design components as an optimum hardware design component for the desired input range based on the synthesis metrics; and \n (d) expand the desired input range and repeat (a) to (d) until an input range of the optimum hardware design component comprises the target input range.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 99.0
- Lexical Diversity: 2.04688
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15363360', '15797020', '16130691', '15163848', '15875176']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3711668490647166
- 35 USC 102 Novelty (BERT): 0.5862266463296902
- Combined Prediction Score: 0.392672828791214
- Mean Citation Score: 241.027214
- Max Citation Score: 455.11115
- Similarity Product: 448.298947812

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test