PATENT CLAIM ANALYSIS

Application Number: 15966134
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["327", "148000"]

Abstract:
A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.

Claim (Index 2):
The phase locked loop of  claim 1 , wherein the feedback path comprises a divider coupled between an output of the VCO and the second input terminal of the PFD.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 3.01923
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11485664', '15385109', '10655853', '12882132', '12816059']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8156521516449006
- 35 USC 102 Novelty (BERT): 0.5016366437490721
- Combined Prediction Score: 0.7842506008553178
- Mean Citation Score: 277.889606
- Max Citation Score: 285.61823
- Similarity Product: 222.00461509603025

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test