PATENT CLAIM ANALYSIS

Application Number: 15862930
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

Claim (Index 15):
A semiconductor structure, comprising:\n a substrate; and a plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for one or more vertical transport field-effect transistors (VTFETs) formed with a replacement metal gate (RMG) process; wherein a given one of the VTFETs comprises a gate surrounding at least one of the plurality of fins, the gate of the given VTFET comprising a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin; a bottom source/drain region disposed over the top surface of the substrate surrounding the plurality of fins; a bottom spacer disposed over the bottom source/drain region; the gate surrounding the plurality of fins; a top spacer disposed over the gate; top source/drain regions disposed over a portion of the top spacer disposed over each of the plurality of fins; top source/drain contact metal layers disposed over the top source/drain regions; top source/drain SAC capping layers disposed over the top source/drain metal contact layers; a bottom source/drain contact metal layer disposed over a portion of the bottom source/drain region; and a bottom source/drain SAC capping layer disposed over the bottom source/drain metal contact layer; wherein the gate of the given VTFET comprises a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:\n a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and \n a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 86.0
- Lexical Diversity: 1.94
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15852109', '15426479', '15819109', '15245634', '15831354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9195723018618416
- 35 USC 102 Novelty (BERT): 0.5068085929930669
- Combined Prediction Score: 0.8782959309749641
- Mean Citation Score: 264.368154
- Max Citation Score: 295.12448
- Similarity Product: 237.66296896118163

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test