PATENT CLAIM ANALYSIS

Application Number: 16407919
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "369000"]

Abstract:
A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

Claim (Index 16):
A semiconductor device comprising:\n a substrate; a first interlayer insulating layer disposed on the substrate; a second interlayer insulating layer disposed on the first interlayer insulating layer; a third interlayer insulating layer disposed on the second interlayer insulating layer, a connection structure disposed in the first interlayer insulating layer; a plurality of vias disposed in the second interlayer insulating layer, the plurality of vias comprising a first via and a second via; and an interconnection line disposed in the third interlayer insulating layer, wherein the first via is disposed between the interconnection line and the connection structure and electrically connects the interconnection line to the connection structure, wherein a level of a bottom surface of the second via is substantially the same as a level of a top surface of the connection structure, and wherein the second via is spaced apart from the connection structure, such that a top surface of the first interlayer insulating layer covers a bottom surface of the second via.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 100.0
- Lexical Diversity: 3.51111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15870143', '15821230', '14493526', '15094586', '15935549']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9020695343769816
- 35 USC 102 Novelty (BERT): 0.5736419980730214
- Combined Prediction Score: 0.8692267807465854
- Mean Citation Score: 278.090988
- Max Citation Score: 464.27988
- Similarity Product: 380.5742591684103

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test