PATENT CLAIM ANALYSIS

Application Number: 15942797
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["327", "281000"]

Abstract:
An example delay circuit is described that includes an input node to receive a first signal, a first circuit path, a second circuit path, an output buffer, and an output node. The first circuit path includes at least one first buffer and a first array of switches. The second circuit path includes at least one second buffer and a second array of switches. The output buffer receives a mixed output of the first circuit path and the second circuit path. The output node transmits a second signal equivalent to the first signal with a programmed delay.

Claim (Index 15):
A circuit, comprising:\n an input to receive a first signal; a first circuit path comprising:\n one or more first complementary metal oxide semiconductor (CMOS) inverters electrically coupled in series with one another; and \n a first array of CMOS switches electrically coupled in series with the one or more first CMOS inverters, wherein each CMOS switch of the first array of CMOS switches is electrically coupled in parallel with other CMOS switches of the first array of CMOS switches; \n a second circuit path comprising:\n one or more second complementary metal oxide semiconductor (CMOS) inverters electrically coupled in series with one another; and \n a second array of CMOS switches electrically coupled in series with the one or more first CMOS inverters, wherein each CMOS switch of the second array of CMOS switches is electrically coupled in parallel with other CMOS switches of the second array of CMOS switches; and \n an output buffer to receive a delay signal created from combined output signals from the first circuit path and the second circuit path and to output a second signal equivalent to the first signal with a programmed delay.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 91.0
- Lexical Diversity: 2.83784
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12244286', '12716796', '11341774', '13106926', '11686560']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7573916654148947
- 35 USC 102 Novelty (BERT): 0.4650308257429968
- Combined Prediction Score: 0.7281555814477049
- Mean Citation Score: 127.4603
- Max Citation Score: 134.89702
- Similarity Product: 95.5473494671297

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test