PATENT CLAIM ANALYSIS

Application Number: 15964492
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "368000"]

Abstract:
A memory cell array includes a first memory cell arranged in a first row in a first direction and a second memory cell arranged in a second row in the first direction. The first memory cell or the second memory cell includes a set of active regions, a set of gates and a first set of conductive structures. Each of the active regions of the set of active regions is separated from an adjacent active region in the first direction by a first pitch. The set of active regions extends in a second direction. The set of active regions includes a first active region adjacent to a first side of the first memory cell, and a second active region adjacent to a second side of the first memory cell. A length of the first active region is different from a length of the second active region.

Claim (Index 13):
The method of  claim 12 , wherein generating the layout design of the memory cell array further comprises:\n generating a first well layout pattern corresponding to fabricating a first well of the memory cell array, the first well having a first dopant type, and the first well layout pattern being located on a fourth layout level different from the first layout level, the second layout level and the third layout level, the generating the first well layout pattern comprises:\n generating a first layout pattern corresponding to fabricating a first portion of the first well, the first layout pattern extending in the second direction, being adjacent to the first side of the memory cell and the corner notch, and being below the first active region layout pattern; and \n generating a second layout pattern corresponding to fabricating a second portion of the first well, the second layout pattern extending in the second direction, being adjacent to the second side of the memory cell, and being below the second active region layout pattern; and \n generating a second well layout pattern corresponding to fabricating a second well of the memory cell array, the second well having a second dopant type different from the first dopant type, and the second well layout pattern being located on the fourth layout level, being between the first layout pattern and the second layout pattern, and being below a third active region layout pattern of the set of active region layout patterns and a fourth active region of the set of active region layout patterns.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 3.94872
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15863090', '15682885', '15861128', '14554958', '15380936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.902141222790325
- 35 USC 102 Novelty (BERT): 0.4958687668627771
- Combined Prediction Score: 0.8615139771975703
- Mean Citation Score: 168.22874199999995
- Max Citation Score: 186.12898
- Similarity Product: 127.2811282527888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test