PATENT CLAIM ANALYSIS

Application Number: 16435887
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-09
Patent Classification: ["438", "268000"]

Abstract:
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

Claim (Index 9):
A method of forming a memory cell, the method comprising:\n forming sacrificial silicon oxide in a bottom portion of a vertical memory hole through a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating oxide and nitride layers defining the vertical memory hole, wherein sidewalls of the vertical memory hole include an inner layer coating, wherein the patterned substrate further comprises a first polysilicon layer formed on the inner layer coating; wherein the vertical stack comprises the bottom portion and a top portion laterally misaligned to form a ledge; forming conformal silicon nitride on exposed portions of the first polysilicon layer exposed by the sacrificial silicon oxide; removing the sacrificial silicon oxide; removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer; removing a bottom portion of the inner layer coating using a gas-phase etch; removing the conformal silicon nitride; and forming a second polysilicon layer on the first polysilicon layer producing electrical contact between the second polysilicon layer and underlying silicon.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 100.0
- Lexical Diversity: 1.75
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15882454', '15891126', '14452220', '15332910', '14222418']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.906935075338638
- 35 USC 102 Novelty (BERT): 0.5675240380438521
- Combined Prediction Score: 0.8729939716091594
- Mean Citation Score: 367.319006
- Max Citation Score: 460.03082
- Similarity Product: 388.00740597319486

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test