PATENT CLAIM ANALYSIS

Application Number: 16044775
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-09
Patent Classification: ["257", "324000"]

Abstract:
A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.

Claim (Index 1):
A memory device, comprising:\n a memory region including a plurality of electrode layers and semiconductor layers, the plurality of electrode layers being stacked in a first direction, and the semiconductor layers extending in the first direction through the plurality of electrode layers; a connection region surrounded with the memory region, the connection region including an insulating body and a plurality of contact plugs, the insulating body having a thickness in the first direction thicker than a stacked width in the first direction of the plurality of electrode layers, and the plurality of contact plugs extending in the first direction through the insulating body; an interconnection layer including interconnections, the interconnections being electrically connected respectively to the plurality of electrode layers and some of the semiconductor layers; and a circuit electrically connected to a first interconnection included in the interconnection layer, the circuit being electrically connected via one of the plurality of contact plugs to the first interconnection, the plurality of electrode layers and the insulating body being positioned between the circuit and the interconnection layer in the first direction.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 3.125
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15855186', '15919250', '14204512', '15907984', '15906423']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9177267521160208
- 35 USC 102 Novelty (BERT): 0.485451545113349
- Combined Prediction Score: 0.8744992314157537
- Mean Citation Score: 224.369582
- Max Citation Score: 241.45198
- Similarity Product: 199.75626261853927

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test