PATENT CLAIM ANALYSIS

Application Number: 16284212
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["327", "108000"]

Abstract:
A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

Claim (Index 5):
The system of  claim 1 , wherein the digital buffer circuit comprises:\n a digital output buffer coupled between an output of the digital module and the package pin; and a digital input buffer coupled between an input of the digital module and the package pin.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 99.0
- Lexical Diversity: 1.26667
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15437593', '10879338', '10677150', '14204679', '12764346']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.763729810169515
- 35 USC 102 Novelty (BERT): 0.4540678779735423
- Combined Prediction Score: 0.7327636169499178
- Mean Citation Score: 132.6608948
- Max Citation Score: 197.81079
- Similarity Product: 185.156580357864

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test