PATENT CLAIM ANALYSIS

Application Number: 15943855
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "500000"]

Abstract:
An embedded electronics package and method of manufacture includes a support substrate, a power semiconductor component coupled to a first side of the support substrate, and a logic semiconductor component coupled to a second side of the support substrate, opposite the first side. A first insulating material surrounds the logic semiconductor component. A logic interconnect layer is electrically coupled to the logic semiconductor component by at least one conductive micro-via extending through a portion of the first insulating material. A power interconnect layer is electrically coupled to the power semiconductor component by at least one conductive macro-via extending through a thickness of the support substrate. The power interconnect layer is thicker than the logic interconnect layer.

Claim (Index 33):
The electronics package of  claim 25  further comprising a passive component coupled to the first side of the insulating substrate, the passive component electrically coupled to the first interconnect layer by at least one of the at least one conductive macro-vias.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 91.0
- Lexical Diversity: 2.6383
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15816396', '15816312', '15816360', '15816254', '15670423']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9261112230591766
- 35 USC 102 Novelty (BERT): 0.50287557746714
- Combined Prediction Score: 0.883787658499973
- Mean Citation Score: 282.8864000000001
- Max Citation Score: 292.38525
- Similarity Product: 243.8305439800322

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test