PATENT CLAIM ANALYSIS

Application Number: 15869349
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "329000"]

Abstract:
Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

Claim (Index 4):
The method of  claim 3  further comprising:\n after applying the etch mask, selectively etching the trench isolation layer relative to the semiconductor fin and the sacrificial layer to form the support structure, \n wherein the support structure is arranged on a first section and a second section of the trench isolation layer that are arranged in trenches in the substrate after selectively etching the trench isolation layer, and the first sidewall and the second sidewall of the semiconductor fin are arranged between the first section of the trench isolation layer and the second section of the trench isolation layer.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15676300', '15586621', '15800563', '15427403', '15694109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921888571647101
- 35 USC 102 Novelty (BERT): 0.5159022675319163
- Combined Prediction Score: 0.8812899412355826
- Mean Citation Score: 264.099646
- Max Citation Score: 318.81198
- Similarity Product: 256.4330775406623

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test