PATENT CLAIM ANALYSIS

Application Number: 15773690
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-07
Patent Classification: ["438", "308000"]

Abstract:
A solid phase crystallization method of the present invention includes: providing amorphous silicon; heating the amorphous silicon to a first crystallization temperature; continuously heating the amorphous silicon to cause a temperature rise, in a first time period, from the first crystallization temperature to a second crystallization temperature, keeping the amorphous silicon in the second crystallization temperature for a predetermined time interval, causing a temperature drop of the amorphous silicon so as to gradually drop, in a second time period, from the second crystallization temperature to the first crystallization temperature, allowing continuous temperature drop of the amorphous silicon to reach the room temperature to thereby obtain low-temperature poly-silicon. The differences of temperature among various areas can be reduced when amorphous silicon starts to crystallize so that the difference of crystal nuclei growth rate among the various areas can be reduced to greatly improve homogeneity of grains formed through solid phase crystallization.

Claim (Index 6):
A manufacturing method of a low-temperature poly-silicon thin-film transistor (TFT) substrate, comprising the following steps:\n Step S 1 : providing a backing plate, depositing a buffer layer on the backing plate, depositing an amorphous silicon layer on the buffer layer to form a substrate-to-be-treated; Step S 2 : applying a solid phase crystallization method to convert the amorphous silicon layer into a low-temperature poly-silicon layer, wherein the solid phase crystallization method comprises: heating the substrate-to-be-treated to a first crystallization temperature, continuously heating the substrate-to-be-treated to cause a temperature rise, in a first time period, from the first crystallization temperature to a second crystallization temperature, keeping the substrate-to-be-treated in the second crystallization temperature for a predetermined time interval, causing a temperature drop of the substrate-to-be-treated so as to gradually drop, in a second time period, from the second crystallization temperature to the first crystallization temperature, allowing continuous temperature drop of the substrate-to-be-treated to reach the room temperature; Step S 3 : subjecting the low-temperature poly-silicon layer to patterning treatment to form an active layer; and depositing a gate insulation layer on the active layer and the buffer layer and forming a gate electrode on the gate insulation layer; Step S 4 : applying a self-aligning operation to implant doping ions in two ends of the active layer by using the gate electrode as a mask so as to form a source contact area and a drain contact area, and also a channel area that is between the source contact area and the drain contact area and located under and corresponding to the gate electrode; Step S 5 : depositing an interlayer dielectric layer on the gate electrode and the gate insulation layer, subjecting the interlayer dielectric layer and the gate insulation layer to patterning treatment to form, in the interlayer dielectric layer and the gate insulation layer, a source contact hole and a drain contact hole that respectively correspond to the source contact area and the drain contact area of the active layer; and Step S 6 : forming a source electrode and a drain electrode on the interlayer dielectric layer, such that the source electrode and the drain electrode are respectively set in contact with the source contact area and the drain contact area of the active layer through the source contact hole and the drain contact hole.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.31429
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15741132', '14781308', '15323648', '14771502', '10780589']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8626125788319495
- 35 USC 102 Novelty (BERT): 0.4916886353037298
- Combined Prediction Score: 0.8255201844791276
- Mean Citation Score: 243.32575400000005
- Max Citation Score: 256.09625
- Similarity Product: 215.02887451440097

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test