PATENT CLAIM ANALYSIS

Application Number: 15963042
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["327", "050000"]

Abstract:
A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator with low input referred noise that uses a small capacitor array for improved communication speed. The comparator includes a cross-coupled pair of transistors, a first input transistor, a second input transistor, a first negative capacitance device and a second negative capacitance device. The first and second transistors are in a differential configuration. A gate of the first input transistor is coupled to a first array of capacitors and a gate of the second input transistor is coupled to a second array of capacitors. The first negative capacitance device is coupled between the gate of the first input transistor and a first polarity node. The second negative capacitance device is coupled between the gate of the second input transistor and a second polarity node.

Claim (Index 8):
The comparator of  claim 1 , further comprising a first dynamic node and a second dynamic node, the first input transistor and the second input transistor are coupled between the first dynamic node and the first polarity node and the second polarity node.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.68519
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12817133', '15884813', '14995471', '15837040', '15681710']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7735369222652897
- 35 USC 102 Novelty (BERT): 0.4868631702029163
- Combined Prediction Score: 0.7448695470590523
- Mean Citation Score: 221.30404000000004
- Max Citation Score: 228.72858
- Similarity Product: 167.32516072985888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test