PATENT CLAIM ANALYSIS

Application Number: 16160622
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["361", "767000"]

Abstract:
An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Claim (Index 13):
A method comprising:\n attaching a first coupling pad to a mounting surface of a baseboard, the first coupling pad providing a first pattern of electrical contacts to correspond to at least a first type of integrated circuit; and making a dual-sided interposer substrate including:\n creating via holes through two or more printed circuit boards (PCB); \n stacking the two more PCBs in a stack having a top surface and a bottom surface; \n attaching a respective top and bottom ground plane to the top and bottom surfaces; \n forming one or more stacked vias formed through the stack of PCBs, each stacked via electrically connecting between respective electrical contacts of the first and second coupling pads to form a corresponding communication channel; and \n forming at least one grounded via between the top and bottom ground planes adjacent to a corresponding stacked via, the at least one grounded via mitigating signal integrity (SI) anomalies within a corresponding communication channel; and \n attaching a second coupling pad attached to the top surface of the dual-sided interposer substrate, the second coupling pad providing a second pattern of electrical contacts that correspond to at least a second type of integrated circuit.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 2.10959
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15474945', '15861877', '15627018', '11188080', '15187739']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7882295131170655
- 35 USC 102 Novelty (BERT): 0.6284779013804254
- Combined Prediction Score: 0.7722543519434014
- Mean Citation Score: 263.354102
- Max Citation Score: 561.7655
- Similarity Product: 557.6958749281167

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test