PATENT CLAIM ANALYSIS

Application Number: 15973392
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["713", "166000"]

Abstract:
A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a network such as the Internet. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and hardware-protects it from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.

Claim (Index 1):
A computer system comprising:\n a first partition and a second partition; the first partition comprising:\n a first CPU; and \n a first memory module comprising:\n at least one memory address range for program code, wherein the program code comprises computer-executable code, and wherein the at least one memory address range for program code is configured by hardware circuitry; and \n at least one memory address range for other data, wherein the other data comprises data read from the second partition; \n \n wherein the first CPU is hardware-configured to execute only the computer-executable code in the memory address range for program code; and the second partition comprising:\n a second CPU; \n a second memory module; and \n at least one communication module configured to couple to a network; \n wherein the first CPU is configured to access the second memory module and read data from the second partition into only the at least one memory address range for other data; and wherein the second CPU is restricted from accessing the first memory module.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.06667
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15437056', '15399654', '14841469', '13843215', '14583062']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3623705535373634
- 35 USC 102 Novelty (BERT): 0.4905252978382665
- Combined Prediction Score: 0.3751860279674537
- Mean Citation Score: 212.670656
- Max Citation Score: 266.68588
- Similarity Product: 263.0500844090843

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test