PATENT CLAIM ANALYSIS

Application Number: 15916241
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["257", "326000"]

Abstract:
A semiconductor device of the present invention includes: an element isolation part which is disposed between fins and whose height is lower than the height of each fin; a memory gate electrode placed over the fins and the element isolation part with a memory gate insulating film having a charge storage part in between; and a control gate electrode disposed in line with the memory gate electrode. The height of the element isolation part below the memory gate electrode is higher than the height of the element isolation part below the control gate electrode. A mismatch between electron injection and hole injection is improved, rewriting operation speed is accelerated, and reliability is enhanced by making the height of the element isolation part below the memory gate electrode higher than the height of the element isolation part below the control gate electrode as mentioned above.

Claim (Index 8):
A manufacturing method for a semiconductor device comprising the steps of:\n (a) forming, in a semiconductor substrate having a first fin formation region extending in a first direction and a second fin formation region disposed at a distance from the first fin formation region and extending in the first direction, an isolation trench between the first fin formation region and the second fin formation region and further forming a first fin and a second fin; (b) burying an isolation insulating film in the isolation trench to form an element isolation part; (c) depressing the surface of the element isolation part; (d) forming a first insulating film having a charge storage part over the semiconductor substrate and forming and processing a first conductive film over the first insulating film to form a first gate electrode extending in a second direction intersecting with the first direction above the first fin, the element isolation part, and the second fin; and (e) forming a second insulating film over the semiconductor substrate and forming and processing a second conductive film over the second insulating film to form a second gate electrode extending in the second direction intersecting with the first direction above the first fin, the element isolation part, and the second fin, wherein the step (e) is performed after the step (d), and wherein after the step (d), the height of the element isolation part below the first gate electrode is higher than the height of the element isolation part below the second gate electrode.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 2.45161
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15669814', '12910788', '15914837', '15879257', '15482239']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.909500029791864
- 35 USC 102 Novelty (BERT): 0.5130982121996502
- Combined Prediction Score: 0.8698598480326425
- Mean Citation Score: 271.457866
- Max Citation Score: 287.96863
- Similarity Product: 220.1096797025472

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test