PATENT CLAIM ANALYSIS

Application Number: 16164811
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "738000"]

Abstract:
A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.

Claim (Index 1):
A manufacturing method of a chip package structure, comprising:\n providing a wafer comprising a plurality of chips formed thereon, wherein each of the chips comprises an active surface and a plurality of pads disposed on the active surface; performing a dicing process on the wafer to separate the chips; providing a carrier, wherein an adhesive layer is disposed on the carrier; mounting the chips on the carrier, wherein the active surface and the pads of each of the chips are buried in the adhesive layer, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chip and cover the adhesive layer, wherein the encapsulant comprises a concave surface and a back surface opposite to the concave surface, the concave surface covers the top surface of the adhesive layer such that the concave surface is dented toward the back surface; removing the carrier by separating the adhesive layer from the chip and the encapsulant; forming a first dielectric layer to cover the concave surface and the active surface, wherein the first dielectric layer comprises a plurality of first openings exposing the pads, and the first opening comprises a first slanted side surface and an angle between the first slanted side surface and the active surface is an acute angle; forming a first patterned circuit layer on the first dielectric layer, wherein the first patterned circuit layer is electrically connected to the pads through the first openings; and forming a second dielectric layer on the first patterned circuit layer and the first dielectric layer, wherein the second dielectric layer comprises a plurality of second openings exposing a part of the first patterned circuit layer, and comprises a first scribe-line cut arranged along an edge of the second dielectric layer, wherein the first scribe-line cut exposes an edge of the first dielectric layer, and wherein a sidewall of the first scribe-line cut is recessed laterally from the edge of the first dielectric layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 2.6129
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15600804', '14095144', '15497964', '12330790', '14174988']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9175347246183236
- 35 USC 102 Novelty (BERT): 0.5260424097203412
- Combined Prediction Score: 0.8783854931285253
- Mean Citation Score: 251.68263800000005
- Max Citation Score: 350.57172
- Similarity Product: 282.721199729004

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test