PATENT CLAIM ANALYSIS

Application Number: 16042910
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["712", "222000"]

Abstract:
The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

Claim (Index 21):
A system for a double-precision floating-point sum of two double-precision floating-point numbers, comprising:\n a first processing circuit that receives a first subset of each of the two double-precision floating-point numbers and generates a control signal, data signal indicating shifted values of the one or both of the two double-precision floating-point numbers, and a first portion of the double-precision floating-point sum based at least in part on the first subset of each of the two double-precision floating-point numbers; a second processing circuit that receives a second subset of each of the two double-precision floating-point numbers and generates a carry signal and a second portion of the double-precision floating-point sum based at least in part on the second subset of each of the two double-precision floating-point numbers; and a bidirectional cascade chain that couples to the first and second processing circuits and that:\n conveys the control signal from the first processing circuit to the second processing circuit, \n conveys the data signal from the first processing circuit to the second processing circuit, and \n conveys the carry signal from the second processing circuit to the first processing circuit.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.26923
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15367205', '15367208', '16039029', '15242923', '15270153']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6819799765153923
- 35 USC 102 Novelty (BERT): 0.619560444117595
- Combined Prediction Score: 0.6757380232756126
- Mean Citation Score: 498.582776
- Max Citation Score: 607.45935
- Similarity Product: 531.4548785264432

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test