PATENT CLAIM ANALYSIS

Application Number: 16284141
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-08
Patent Classification: ["326", "062000"]

Abstract:
A level shifter includes a pair of cross-coupled PMOS transistors, intrinsic-type NMOS transistors, an input node, a control circuit and an output node. A high voltage is supplied to the PMOS transistors. The intrinsic-type NMOS transistors and the PMOS transistors are respectively coupled in serial. The input node is configured to receive input signals. The control circuit is triggered by the voltage Vdd and is configured to generate enable signals and control signals according to the input signal. The output node is configured to output the high Voltage HV or the GND voltage as the output signal. After the node aa is charged, the transistor HVNI_1 is turned off according to the control signal SW to avoid leakage current being generated. After the node MOUT is charged, the transistor HVNI_2 is turned off according to the control signal SWb to avoid leakage current being generated.

Claim (Index 1):
A level shifter, comprising:\n a first PMOS transistor, wherein an electrode of the first PMOS transistor is provided with a voltage having a first voltage level, another electrode of the first PMOS transistor is coupled to a first node and a gate of the first PMOS transistor is coupled to a second node; a second PMOS transistor, wherein an electrode of the second PMOS transistor is provided with the voltage having the first voltage level, another electrode of the second PMOS transistor is coupled to the second node, and a gate of the second PMOS transistor is coupled to the first node; a first NMOS transistor, which is an intrinsic-type transistor, wherein an electrode of the first NMOS transistor is coupled to the first node, another electrode of the first NMOS transistor is provided with a first enable signal, and a gate of the first NMOS transistor is coupled to a first control signal; a second NMOS transistor, which is air intrinsic-type transistor, wherein an electrode of the second NMOS transistor is coupled to the second node, another electrode of the second NMOS transistor is provided with a second enable signal having a logic level that is an inverse of that of the first enable signal, and a gate of the second NMOS transistor is coupled to a second control signal; an input node, configured to receive an input signal having a second voltage level or a third voltage level; a control circuit, driven by the second voltage level and configured to generate the first control signal and the second control signal according to the input signal; and an output node, configured to output an output signal having the first voltage level or the third voltage level in response to the input signal, wherein when the first NMOS transistor is turned on to charge the first node and after a first predetermined period of time, the first NMOS transistor is turned off in response to the first control signal, and when the second NMOS transistor is turned on to charge the second node and after a second predetermined period of time, the second NMOS transistor is turned off in response to the second control signal.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 99.0
- Lexical Diversity: 2.46875
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11204111', '14256689', '10854813', '11030615', '12701583']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7015640123838441
- 35 USC 102 Novelty (BERT): 0.4900337388640396
- Combined Prediction Score: 0.6804109850318637
- Mean Citation Score: 279.829364
- Max Citation Score: 287.64105
- Similarity Product: 261.89211544561385

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test