PATENT CLAIM ANALYSIS

Application Number: 16010199
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["710", "308000"]

Abstract:
An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Claim (Index 14):
The extended PCIe fabric of  claim 10 , wherein an endpoint of the extended PCIe fabric is an additional RCEP of an additional extended PCIe fabric, wherein the additional extended PCIe fabric comprises an additional set of bus numbers allowing additional endpoints to be connected to the additional RCEP beyond a capacity of the host PCIe fabric as provided by resources of a host root complex of the host PCIe fabric and a capacity of the extended PCIe fabric as provided by resources of the RCEP of the extended PCIe fabric.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 94.0
- Lexical Diversity: 2.26087
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14822685', '13931640', '16010235', '11612522', '14752099']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.743136367136018
- 35 USC 102 Novelty (BERT): 0.5652734309137665
- Combined Prediction Score: 0.7253500735137929
- Mean Citation Score: 381.683418
- Max Citation Score: 466.41196
- Similarity Product: 381.1704544830084

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test