PATENT CLAIM ANALYSIS

Application Number: 15974824
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["315", "307000"]

Abstract:
A load current adjusting circuit can include: a counter configured to generate first and second digital signals in accordance with a pulse signal, where a numerical relationship between the first and second digital signals is determined in accordance with a duty cycle of the pulse signal; and an adjusting circuit configured to adjust a load current to vary along with the duty cycle of the pulse signal in accordance with the first and second digital signals.

Claim (Index 4):
The load current adjusting circuit of  claim 3 , wherein said counter further comprises:\n a) a first pulse generator configured to generate a first enable signal for said first memory, wherein during each cycle of said pulse signal, an active pulse of said first enable signal is not more than a time length between said first and second times; and b) a second pulse generator configured to generate a reset signal for said counter, wherein during each cycle of said pulse signal, said reset signal is active for a period of time from said first time.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 2.0
- Patent Class: 315.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14256272', '14056954', '15006978', '15041205', '14937853']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7189126684818268
- 35 USC 102 Novelty (BERT): 0.470355942329126
- Combined Prediction Score: 0.6940569958665567
- Mean Citation Score: 134.85641800000002
- Max Citation Score: 136.74335
- Similarity Product: 99.27644790088536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test