PATENT CLAIM ANALYSIS

Application Number: 16018085
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["710", "113000"]

Abstract:
A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.

Claim (Index 8):
The wafer-level package of  claim 1 , wherein the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 94.0
- Lexical Diversity: 2.58621
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15015145', '15009819', '14975270', '15015110', '14335681']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6781023390639488
- 35 USC 102 Novelty (BERT): 0.4988615668332989
- Combined Prediction Score: 0.6601782618408838
- Mean Citation Score: 188.91697
- Max Citation Score: 304.11066
- Similarity Product: 301.0538044517934

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test