PATENT CLAIM ANALYSIS

Application Number: 16135660
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185110"]

Abstract:
A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory cells. The read/write circuit is configured to write data to the memory cell array or read data from the memory cell array. The control logic is configured to control the read/write circuit to perform a read/write operation for the memory cell array. The memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks. During an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block.

Claim (Index 11):
The method according to  claim 8 ,\n wherein each of the plurality of memory blocks includes an upper sub-block and a lower sub-block, the upper sub-block corresponds to the first sub-block, and the lower sub-block corresponds to the second sub-block.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 97.0
- Lexical Diversity: 2.50877
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15625162', '11138427', '13540951', '10678179', '14279037']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8269716804692427
- 35 USC 102 Novelty (BERT): 0.5326057715055689
- Combined Prediction Score: 0.7975350895728753
- Mean Citation Score: 285.283094
- Max Citation Score: 391.7481
- Similarity Product: 260.33865410878656

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test