PATENT CLAIM ANALYSIS

Application Number: 15995301
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["257", "048000"]

Abstract:
This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.

Claim (Index 7):
The method according to  claim 2 , wherein the trench comprises multiple trenches whose extension directions are substantially parallel.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 94.0
- Lexical Diversity: 2.52381
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11914594', '14622619', '15543700', '11914584', '14683444']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9286789096501352
- 35 USC 102 Novelty (BERT): 0.4986124839432135
- Combined Prediction Score: 0.8856722670794432
- Mean Citation Score: 206.386304
- Max Citation Score: 212.88326
- Similarity Product: 137.7143581518948

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test