PATENT CLAIM ANALYSIS

Application Number: 15886185
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["712", "011000"]

Abstract:
A processing system comprising an arrangement of tiles and synchronization logic in the form of hardware logic for coordinating between a group of some or all of said tiles. The instruction set comprises a synchronization instruction which causes an instance of a synchronization request to be transmitted from the respective tile to the synchronization logic, and suspends instruction issue on the respective tile pending a synchronization acknowledgement. In response to receiving an instance of the synchronization request from all of the tiles of the group, the synchronization logic returns the synchronization acknowledgment back to each of the tiles in the group to allow the instruction issue to resume. The instruction set further comprises an abstain instruction, which sends an instance of the synchronization request but does not suspend instruction issue on the respective tile pending the synchronization acknowledgement, instead allowing the instruction issue on the respective tile to continue.

Claim (Index 1):
A processing system comprising an arrangement of tiles and an interconnect for communicating between the tiles, wherein:\n each tile comprises a respective execution unit for executing machine code instructions, each being an instance of a predefined set of instruction types in an instruction set of the processor, each instruction type in the instruction set being defined by a corresponding opcode and zero or more operand fields for taking zero or more operands; the interconnect comprises synchronization logic in the form of hardware logic for coordinating between a group of some or all of said tiles; the instruction set comprises a synchronization instruction, wherein the respective execution unit on each respective tile is configured so as if an instance of the synchronization instruction is executed through the respective execution unit, then in response to the opcode of the synchronization instruction to cause an instance of a synchronization request to be transmitted from the respective tile to the synchronization logic in the interconnect, and to suspend instruction issue on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic; the synchronization logic is configured so as, in response to reaching a synchronization point whereby an instance of the synchronization request is received from all of the tiles of said group, to return the synchronization acknowledgment back to each of the tiles in the group and thereby allow the instruction issue to resume; and the instruction set further comprises an abstain instruction, wherein the execution unit on each respective tile is configured so as if an instance of the abstain instruction is executed through the respective execution unit, then in response to the opcode of the abstain instruction to cause an instance of the synchronization request to be transmitted from the respective tile to the synchronization logic in the interconnect, but not to suspend instruction issue on the respective tile pending the synchronization acknowledgement, instead allowing the instruction issue on the respective tile to continue.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.45312
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15886099', '15885955', '15886138', '15886340', '15886315']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6091224626957388
- 35 USC 102 Novelty (BERT): 0.564031561936991
- Combined Prediction Score: 0.604613372619864
- Mean Citation Score: 331.148136
- Max Citation Score: 451.43924
- Similarity Product: 419.58674634541273

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test