PATENT CLAIM ANALYSIS

Application Number: 15965733
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "205000"]

Abstract:
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Claim (Index 35):
A memory device, comprising:\n an array of memory cells; and a controller configured to control sensing circuitry coupled to the array to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input; wherein the sensing circuitry is controlled to store a result of the logical operation in at least one of the first memory cell, the second memory cell, and a third memory cell; wherein the sense line comprises a first sense line of a pair of complementary sense lines; and wherein the sensing circuitry comprises:\n a sense amplifier coupled to the pair of complementary sense lines; and \n a compute component coupled to the sense amplifier and comprising:\n a cross-coupled latch comprising a pair of first transistors and a pair of second transistors; \n a first pass transistor having a first source/drain node coupled to:\n a gate of a second one of the pair of first transistors; \n a gate of a second one of the pair of second transistors; and \n a first source/drain node of a first one of the pair of first transistors, the first pass transistor having a second source/drain node coupled to the sense line; and \n \n a second pass transistor having a first source/drain node coupled to:\n a gate of a first one of the pair of first transistors; \n a gate of a first one of the pair of second transistors; and \n a first source/drain node of the second one of the pair of first transistors, the second pass transistor having a second source/drain node coupled to the second sense line of the pair of complementary sense lines; \n \n \n wherein the compute component further comprises:\n a first inverting transistor having a first source/drain node coupled to a second source/drain node of the first pass transistor and having a second source/drain node coupled to a source/drain node of a first transistor whose gate is coupled to the gate of the second one of the pair of first transistors; and \n a second inverting transistor having a first source/drain node coupled to a second source/drain node of the second pass transistor and having a second source/drain node coupled to a source/drain node of a second transistor whose gate is coupled to the gate of the first one of the pair of first transistors.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.125
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13784219', '14878452', '15270761', '13962399', '14725956']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8021973361527277
- 35 USC 102 Novelty (BERT): 0.4661068618058322
- Combined Prediction Score: 0.7685882887180382
- Mean Citation Score: 269.222382
- Max Citation Score: 275.8427
- Similarity Product: 249.27388372607228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test