PATENT CLAIM ANALYSIS

Application Number: 15957615
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "319000"]

Abstract:
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

Claim (Index 18):
The method of  claim 16 , wherein the logic gate includes a metal material, and wherein the logic gate is insulated from the first and second side surfaces and the top surface of the second fin by a high K insulation material.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 3.07692
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15295022', '15945161', '15933124', '15050309', '15489548']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239293811310424
- 35 USC 102 Novelty (BERT): 0.5317924314194886
- Combined Prediction Score: 0.884715686159887
- Mean Citation Score: 313.718762
- Max Citation Score: 340.4594
- Similarity Product: 257.9682270049334

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test