PATENT CLAIM ANALYSIS

Application Number: 15897524
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["438", "155000"]

Abstract:
Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

Claim (Index 3):
The method of  claim 1 , further comprising, for the vertical bipolar transistor, removing the semiconductor layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.6383
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15454788', '10719195', '10581127', '11761164', '10784417']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8410595756164491
- 35 USC 102 Novelty (BERT): 0.5232684734559699
- Combined Prediction Score: 0.8092804654004012
- Mean Citation Score: 253.66796
- Max Citation Score: 320.62524
- Similarity Product: 253.3956347994376

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test