PATENT CLAIM ANALYSIS

Application Number: 16272736
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "534000"]

Abstract:
Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.

Claim (Index 1):
A fabrication method comprising:\n (a) obtaining a first integrated circuit structure comprising a first substrate comprising a bottom surface having a cavity, and comprising a first circuitry comprising one or more first capacitors each of which is at least partially located in a respective first hole formed in a top surface of the first substrate, each first capacitor comprising: a first electroconductive layer formed within or upon an interior surface of the respective first hole; a dielectric layer formed over the first electroconductive layer and at least partially located in the respective first hole; a second electroconductive layer formed over the dielectric layer and at least partially located in the respective first hole; (b) obtaining a second integrated circuit structure comprising a second substrate comprising a second circuitry comprising one or more second capacitors each of which is at least partially located in a respective second hole formed in a top surface of the second substrate, each second capacitor comprising: a first electroconductive layer formed within or upon an interior surface of the respective second hole; a dielectric layer formed over the first electroconductive layer and at least partially located in the respective second hole; a second electroconductive layer formed over the dielectric layer and at least partially located in the respective second hole; the second integrated circuit structure further comprising a semiconductor die attached to the top surface of the second substrate and electroconductively coupled to the second circuitry; (c) after obtaining the first and second integrated circuit structures, positioning the first and second integrated circuit structures to align each first hole with a corresponding second hole, and bonding the first integrated structure to the second integrated structure, the bonding comprising bonding the first substrate to the second substrate, wherein in said bonding of the first and second integrated structures, for each aligned pair of a first hole and a second hole, the first electroconductive layer of the respective first capacitor becomes electroconductively coupled to the second electroconductive layer of the respective second capacitor; wherein at a conclusion of said bonding of the first and second integrated circuit structures, the semiconductor die is disposed in the cavity but is spaced from the first substrate to define a headspace between the cavity surface and the semiconductor die surface; wherein the method further comprises injecting a filler into the headspace through one or more channels in the first substrate that communicate between the cavity and the top surface of the first substrate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 1.7619
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15804847', '14833979', '14268899', '15360121', '15651826']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9165044915769625
- 35 USC 102 Novelty (BERT): 0.5446198084508409
- Combined Prediction Score: 0.8793160232643502
- Mean Citation Score: 335.713626
- Max Citation Score: 383.6053
- Similarity Product: 377.3931325716913

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test