PATENT CLAIM ANALYSIS

Application Number: 16236431
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["327", "541000"]

Abstract:
Biasing architectures and methods for lower loss switches. In some embodiments, a switching device can include a series arm having transistors implemented in a stack configuration between first and second nodes. The switching device can further include a shunt arm having transistors implemented in a stack configuration between the first node and a ground node. The switching device can further include a bias architecture having a series arm bias circuit and a shunt arm bias circuit. The series arm bias circuit can be configured to bias the transistors of the series arm and include a gate-gate resistor that couples each pair of neighboring transistors. The shunt arm bias circuit can be configured to bias the transistors of the shunt arm and include a gate-gate resistor that couples each pair of neighboring transistors.

Claim (Index 9):
The switching device of  claim 1  wherein the series arm bias circuit further includes a body-body resistor that couples bodies of each pair of neighboring transistors, and the shunt arm bias circuit further includes a body-body resistor that couples bodies of each pair of neighboring transistors.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.78
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15497120', '15002170', '14737455', '15851810', '14737453']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8156347835291903
- 35 USC 102 Novelty (BERT): 0.511079340649788
- Combined Prediction Score: 0.7851792392412501
- Mean Citation Score: 292.40480799999995
- Max Citation Score: 302.58984
- Similarity Product: 214.4979220802879

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test