PATENT CLAIM ANALYSIS

Application Number: 16006612
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["365", "185170"]

Abstract:
A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

Claim (Index 10):
A process for forming a memory structure comprising:\n forming circuitry in a semiconductor substrate, the semiconductor substrate having a planar surface; forming a plurality of active layers, with successive active layers being isolated from each other by isolation layers, each active layer comprising first and second semiconductor sublayers of a first conductivity type, a third semiconductor layer of a second conductivity type opposite the first conductivity type; patterning and etching the active layers anisotropically to form a first system of trenches from the top of the active layers along a first direction substantially perpendicular to the planar surface, such that each trench extends lengthwise along a second direction substantially parallel to the planar surface; filling the first set of trenches with a sacrificial material; patterning and etching the sacrificial material anisotropically along the first direction to form a second set of trenches running lengthwise along a third direction substantially parallel the planar surface and substantially orthogonal to the second direction, thereby exposing a portion of each of the plurality of active layers; and isotropically etching the exposed portions of the active layers to remove exposed portions of the first, second and third semiconductor sublayers of each active layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.14062
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15248420', '15783201', '15220375', '15846766', '15837734']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.804841821209693
- 35 USC 102 Novelty (BERT): 0.4845144305403695
- Combined Prediction Score: 0.7728090821427607
- Mean Citation Score: 242.502654
- Max Citation Score: 257.059
- Similarity Product: 209.2118148707748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test