PATENT CLAIM ANALYSIS

Application Number: 15988346
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

Claim (Index 12):
The semiconductor memory device according to  claim 1 , wherein the at least one dummy contact comprises a plurality of dummy contacts arranged in a discontinuous frame shape surrounding the contact, when viewed from the top.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 2.9375
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15915136', '15696144', '14489880', '15856933', '15260011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9246046611084112
- 35 USC 102 Novelty (BERT): 0.4964516299686693
- Combined Prediction Score: 0.8817893579944371
- Mean Citation Score: 219.217202
- Max Citation Score: 249.61848
- Similarity Product: 191.95553832634445

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test