PATENT CLAIM ANALYSIS

Application Number: 15869160
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "059000"]

Abstract:
A display panel and a manufacturing method are provided. The display panel includes a substrate, multiple active switches disposed on the substrate and a low dielectric constant protective layer. The low dielectric constant protective layer is formed on the numerous active switches. A relative dielectric constant of the low dielectric constant protective layer is smaller than a relative dielectric constant of silicon nitride.

Claim (Index 1):
A display panel comprising:\n a substrate; a plurality of active switches, disposed on the substrate; a low dielectric constant protective layer formed on the plurality of active switches, wherein a relative dielectric constant of the low dielectric constant protective layer is lower than a relative dielectric constant of silicon nitride; wherein the low dielectric constant protective layer comprises a mesoporous silica; the mesoporous silica comprises a plurality of hollow columnar sub-components connected with each other, a cross section of the sub-component is hexagonal, and a middle of the sub-component has a circular through hole; the mesoporous silica comprises a plurality of sub-elements, the sub-element comprises the sub-components arranged in three lines, an intermediate line of the sub-element comprises three sub-components arranged abreast, a first line and a third line of the sub-element each comprise two sub-components arranged abreast, the two sub-components of each of the first line and the third line each are disposed between any two sub-components of the three sub-components in the intermediate line; wherein a plurality of first-layer wires are disposed on the substrate, an insulating dielectric layer is disposed on the first-layer wires, an amorphous silicon layer is disposed on the insulating dielectric layer and corresponding to a gate wire section of the first-layer wires, an ohmic contact layer is disposed on and corresponding to the amorphous silicon layer, a source wire section and a drain wire section are separated from each other and disposed on the ohmic contact layer, a groove is defined between the source wire section and the drain wire section, the groove passes through the ohmic contact layer, a bottom of the groove is the amorphous silicon layer, a width of the source wire section and the drain wire section as a whole is larger than a width of the amorphous silicon layer, the low dielectric constant protective layer is disposed on the source wire section and the drain wire section, a pixel electrode layer is disposed on the low dielectric constant protective layer, the low dielectric constant protective layer is defined with a via hole corresponding to the drain wire section, the pixel electrode layer is connected with the drain wire section by the via hole; a side of a portion of the source wire section beyond the amorphous silicon layer is immediately connected with the insulating dielectric layer, an opposite side of the portion of the source wire section is immediately connected with the low dielectric constant protective layer, and a section of the insulating dielectric layer corresponding to the via hole is connected with the drain wire section.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15869136', '16462000', '12369220', '11713046', '11452978']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9002496344977129
- 35 USC 102 Novelty (BERT): 0.5446855152395141
- Combined Prediction Score: 0.8646932225718931
- Mean Citation Score: 252.786866
- Max Citation Score: 383.91946
- Similarity Product: 298.3595205819047

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test