PATENT CLAIM ANALYSIS

Application Number: 16158560
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["257", "076000"]

Abstract:
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

Claim (Index 23):
The method of  claim 16  wherein the first gate dielectric layer is formed in situ with the first and second active layers and the second gate dielectric layer is formed ex-situ with the first and second active layers.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 97.0
- Lexical Diversity: 2.65116
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14539086', '13780192', '15700087', '16081012', '13533610']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9276527511890452
- 35 USC 102 Novelty (BERT): 0.4863644678394287
- Combined Prediction Score: 0.8835239228540835
- Mean Citation Score: 220.263382
- Max Citation Score: 243.29625
- Similarity Product: 205.66266067028045

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test