PATENT CLAIM ANALYSIS

Application Number: 16364239
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["327", "225000"]

Abstract:
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Claim (Index 1):
A comparator, comprising:\n a pair of back-to-back negative-AND (NAND) gates; and a delay circuit coupled to the pair of back-to-back NAND gates, the delay circuit configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage, wherein each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 99.0
- Lexical Diversity: 2.20513
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15945165', '15884813', '15883623', '16211259', '15864090']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7554248815499478
- 35 USC 102 Novelty (BERT): 0.5773565610329614
- Combined Prediction Score: 0.7376180494982492
- Mean Citation Score: 267.002016
- Max Citation Score: 466.54208
- Similarity Product: 459.9674168392945

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test