PATENT CLAIM ANALYSIS

Application Number: 16385271
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "421000"]

Abstract:
The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.

Claim (Index 17):
The method according to  claim 15 , wherein the depositing of the first cap layer and the depositing of the second cap layer is performed within a common process chamber, wherein the depositing of the first cap layer comprises placing the memory cell in the common process chamber, and wherein the memory cell does not leave the common process chamber until after the depositing of the second cap layer is complete.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 100.0
- Lexical Diversity: 2.2
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15687976', '16202493', '14645683', '15715487', '15362153']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9198213615131646
- 35 USC 102 Novelty (BERT): 0.5164112184989819
- Combined Prediction Score: 0.8794803472117464
- Mean Citation Score: 219.048454
- Max Citation Score: 281.3431
- Similarity Product: 196.3746536694049

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test