PATENT CLAIM ANALYSIS

Application Number: 16019677
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["257", "324000"]

Abstract:
A first memory film and a sacrificial fill structure are formed within each first-tier memory opening through a first alternating stack of first insulating layers and first spacer material layers. A second alternating stack of second insulating layers and second spacer material layers is formed over the first alternating stack, and a second-tier memory opening is formed over each sacrificial fill structure. A second memory film is formed in each upper opening, and the sacrificial fill structures are removed from underneath the second-tier memory openings to form memory openings. A semiconductor channel is formed on each vertically neighboring pair of a first memory film and a second memory film as a continuous layer. The first memory film is protected by the sacrificial fill structure during formation of the second-tier memory openings.

Claim (Index 10):
A monolithic three-dimensional memory device, comprising:\n a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate; an insulating cap layer overlying the first alternating stack; a second alternating stack of second insulating layers and second electrically conductive layers overlying the insulating cap layer; a memory opening extending through the second alternating stack, the insulating cap layer, and the first alternating stack; and a memory stack structure located within the memory opening and comprising a semiconductor channel, a first memory film laterally surrounding the semiconductor channel and embedded within the first alternating stack, and a second memory film laterally surrounding semiconductor channel and embedded within the second alternating stack, wherein the second memory film is not in direct contact with the first memory film; wherein the semiconductor channel continuously vertically extends at least from a level of a second bottommost electrically conductive layer within the first alternating stack to a level of a topmost electrically conductive layer within the second alternating stack; wherein a horizontal surface of the semiconductor channel directly contacts a bottommost second insulating layer of the second insulating layers within the second alternating stack; wherein the horizontal surface of the semiconductor channel is coplanar with a top surface of the insulating cap layer; wherein the semiconductor channel comprises:\n a first vertically-extending portion located within the first alternating stack; \n a second vertically-extending portion located within the second alternating stack; and \n a ledge portion connecting the first vertically-extending portion and the second vertically-extending portion, located within the insulating cap layer, and including the horizontal surface of the semiconductor channel that contacts the bottommost second insulating layer of the second insulating layers within the second alternating stack; and \n further comprising a dielectric core located within the semiconductor channel and including a laterally protruding portion embedded within the insulating cap layer and having a top surface that contacts a first region of the ledge portion of the semiconductor channel and having a bottom surface that contacts a second region of the ledge portion of the semiconductor channel.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 2.60377
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15914560', '15071575', '15347101', '15434544', '15335850']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9365398468091184
- 35 USC 102 Novelty (BERT): 0.5450374931109854
- Combined Prediction Score: 0.8973896114393052
- Mean Citation Score: 389.59602800000016
- Max Citation Score: 401.63498
- Similarity Product: 385.0048199122715

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test