PATENT CLAIM ANALYSIS

Application Number: 16119186
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["341", "120000"]

Abstract:
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Claim (Index 1):
A low-power track and hold circuit, the low-power track and hold circuit comprising:\n a sampling buffer; a sampling network, with dither injection, to receive a buffered input from the sampling buffer; and a hold buffer to receive a held signal from the sampling network.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.06944
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11033661', '15451194', '14955888', '13607073', '13450204']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5733044882835726
- 35 USC 102 Novelty (BERT): 0.501870874229805
- Combined Prediction Score: 0.5661611268781959
- Mean Citation Score: 203.389294
- Max Citation Score: 207.41129
- Similarity Product: 134.31877154660106

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test