PATENT CLAIM ANALYSIS

Application Number: 15933474
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["345", "076000"]

Abstract:
A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor, wherein the second transistor is in an on state during a combined programming and compensation phase and in an off state during the emission phase, and when the second transistor is in an on state the drive transistor becomes diode-connected such that a gate and a second terminal of the drive transistor are connected through the second transistor; a third transistor connected to the second terminal of the drive transistor, wherein the third transistor is in an on state during the combined programming and compensation phase to permit a reference current to be applied through the drive transistor, and is in an off state during the emission phase to remove the reference current; and a capacitor having a first plate that is connected to the gate of the drive transistor and a second plate that is connectable to a data voltage during the combined programming and compensation phase. A threshold voltage and/or a carrier mobility of the drive transistor is compensated by application of the reference current during the combined programming and compensation phase.

Claim (Index 1):
A pixel circuit for a display device that is operable in a combined programming and compensation phase, and operable in an emission phase, the pixel circuit comprising:\n a drive transistor configured to control an amount of current to the light-emitting device during the emission phase depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor, wherein the second transistor is in an on state during the combined programming and compensation phase and in an off state during the emission phase, and when the second transistor is in the on state the drive transistor becomes diode-connected such that the gate and a second terminal of the drive transistor are connected through the second transistor; a third transistor connected to the second terminal of the drive transistor, wherein the third transistor is in an on state during the combined programming and compensation phase to permit a reference current to be applied through the drive transistor, and is in an off state during the emission phase to remove the reference current; and a capacitor having a first plate that is connected to the gate of the drive transistor and a second plate that is connectable to a data voltage VDAT during the combined programming and compensation phase; wherein a threshold voltage and/or a carrier mobility of the drive transistor are at least partially compensated by application of the reference current during the combined programming and compensation phase.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 3.41176
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15756973', '14708025', '15167863', '14463511', '14342306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6219088763282535
- 35 USC 102 Novelty (BERT): 0.4924498559170686
- Combined Prediction Score: 0.6089629742871351
- Mean Citation Score: 244.400852
- Max Citation Score: 252.64645
- Similarity Product: 217.26652374154327

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test