PATENT CLAIM ANALYSIS

Application Number: 16014117
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["714", "724000"]

Abstract:
A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.

Claim (Index 16):
A computer program product, comprising a computer-readable hardware storage device having a computer-readable program code stored therein, the program code configured to be executed by a quantum-logic test-development system comprising a processor, a memory coupled to the processor, and a computer-readable hardware storage device coupled to the processor, the storage device containing program code configured to be run by the processor via the memory to implement a method for reducing complexity when testing quantum-logic circuits, the method comprising:\n receiving architectural information about a quantum-logic circuit that has at least four inputs and at least one output; optimizing a procedure for testing the quantum-logic circuit,\n where the procedure comprises a series of tests that each verify correct operation of the quantum-logic circuit in response to receiving a distinct input vector of a set of input vectors, and \n where the optimizing comprises deleting from the series of tests any test designed to place all outputs of the quantum-logic circuit in an output state that does not change from an output state generated by at least one other test of the series of tests.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.73333
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15194645', '15194718', '15434867', '13147355', '15147751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2698790046471058
- 35 USC 102 Novelty (BERT): 0.5719876962806827
- Combined Prediction Score: 0.3000898738104635
- Mean Citation Score: 294.35173
- Max Citation Score: 466.22275
- Similarity Product: 400.6549514414669

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test