PATENT CLAIM ANALYSIS

Application Number: 16004920
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-06
Patent Classification: ["257", "296000"]

Abstract:
An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

Claim (Index 17):
The RFIC of  claim 16 , in which the pair of capacitor manifolds are at a same side of the capacitor array, outside the perimeter defined by the inductor trace.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.93333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13770127', '14512191', '15687065', '15687129', '14323907']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9256627928504968
- 35 USC 102 Novelty (BERT): 0.5011200009598339
- Combined Prediction Score: 0.8832085136614304
- Mean Citation Score: 225.339226
- Max Citation Score: 237.7897
- Similarity Product: 162.99543435481792

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test