PATENT CLAIM ANALYSIS

Application Number: 15892648
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "773000"]

Abstract:
A multi-grooved interposer includes an interposer substrate containing multiple parallel grooves laterally extending along a first direction and laterally spaced among one another along a second direction, and multiple conductive strips. The multiple parallel grooves are recessed from front side surfaces of the multi-grooved interposer in a third direction toward a back side surface of the multi-grooved interposer. The multiple conductive strips continuously extend across recessed surfaces in the multiple parallel grooves and the front side surfaces along the second direction with an undulating surface profile to provide electrically conductive paths across the multiple parallel grooves. Each of the multiple parallel grooves is configured to receive an edge of a respective semiconductor chip.

Claim (Index 14):
A method of forming a chip assembly structure, comprising:\n providing a multi-grooved interposer including multiple parallel grooves laterally extending along a first direction and laterally spaced among one another along a second direction, wherein the multiple parallel grooves are recessed from front side surfaces of the multi-grooved interposer in a third direction toward a back side surface of the multi-grooved interposer, wherein multiple conductive strips continuously extend across recessed surfaces in the multiple parallel grooves and the front side surfaces along the second direction with an undulating surface profile to provide electrically conductive paths across the multiple parallel grooves; providing a plurality of semiconductor chips, wherein each of the plurality of semiconductor chips includes a major surface on which a respective set of conductive pads is located; and inserting each of the plurality of semiconductor chips partially into a respective one of the multiple parallel grooves such that each of the plurality of semiconductor chips is in electrical contact with the multiple conductive strips through physical contact between the respective set of conductive pads and respective portions of the multiple conductive strips.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 88.0
- Lexical Diversity: 2.03448
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12217643', '15584961', '12941640', '09656690', '13182220']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9257576966545354
- 35 USC 102 Novelty (BERT): 0.4812805648805
- Combined Prediction Score: 0.8813099834771319
- Mean Citation Score: 188.551942
- Max Citation Score: 195.88101
- Similarity Product: 143.20126703774568

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test