PATENT CLAIM ANALYSIS

Application Number: 15860912
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["257", "295000"]

Abstract:
A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.

Claim (Index 17):
The integrated circuit of  claim 16 , wherein the first gate structure has different gate widths across the first active region and the second active region.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 86.0
- Lexical Diversity: 3.3617
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15581565', '14856666', '14577316', '13693685', '15663089']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9035604281958096
- 35 USC 102 Novelty (BERT): 0.4724751881493057
- Combined Prediction Score: 0.8604519041911592
- Mean Citation Score: 161.367086
- Max Citation Score: 164.0523
- Similarity Product: 130.20071924865246

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test