PATENT CLAIM ANALYSIS

Application Number: 15974426
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "105000"]

Abstract:
A VTFET device and fabrication method is provided. The method includes: forming a first doped layer on a semiconductor substrate. Vertical nanowires are formed on the first doped layer. Dummy gate layers are formed on the first doped layer, and a first interlayer dielectric layer is formed on a top surface of the first doped layer exposed by dummy gate layers. Grooves are formed in the first interlayer dielectric layer, by removing a portion of the first interlayer dielectric layer and removing a partial thickness of the vertical nanowires. A second doped layer is formed in each groove. Openings are formed by etching the first interlayer dielectric layer between adjacent vertical nanowires, to expose the dummy gate layers. The dummy gate layers are removed through the openings to form cavities and each cavity includes the opening and a space provided by the removed dummy gate layers.

Claim (Index 1):
A fabrication method of a vertical tunneling field effect transistor, comprising:\n providing a semiconductor substrate; forming a first doped layer on the semiconductor substrate; forming a plurality of vertical nanowires on the first doped layer; forming dummy gate layers with top surfaces lower than top surfaces of the vertical nanowires, on the first doped layer; forming a first interlayer dielectric layer on a top of the first doped layer exposed by the dummy gate layers, and covering the top surfaces of the vertical nanowires; forming grooves in the first interlayer dielectric layer, by removing a portion of the first interlayer dielectric layer from the top surfaces of the vertical nanowires and removing a partial thickness of the vertical nanowires; forming a second doped layer in each groove; after forming the second doped layer, forming openings by etching the first interlayer dielectric layer between adjacent vertical nanowires, to expose the dummy gate layers; after forming the openings, removing the dummy gate layers through the openings to form cavities, wherein each cavity includes the opening and a space provided by the removed dummy gate layers; forming a high-k gate dielectric layer on sidewalls and a bottom of each cavity; and forming a gate electrode layer on the high-k gate dielectric layer by filling each cavity.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.59016
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14722818', '14495639', '15909419', '13904341', '14266521']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919364489718966
- 35 USC 102 Novelty (BERT): 0.482516589272157
- Combined Prediction Score: 0.8756796996742852
- Mean Citation Score: 234.23705
- Max Citation Score: 241.38937
- Similarity Product: 206.2922937869656

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test