PATENT CLAIM ANALYSIS

Application Number: 15961550
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["029", "852000"]

Abstract:
Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Claim (Index 20):
An apparatus, comprising:\n a stack comprising an upper layer and a first layer; a plurality of first holes in the upper layer of the stack, each first hole having a first width; and a first electrode and a second electrode at the first layer of the stack, the first electrode separated from the second electrode by a first distance greater than the first width, wherein a gap between the first electrode and the second electrode is aligned with the plurality of first holes.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 1.94915
- Patent Class: 29.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15810557', '15720306', '13154548', '11321156', '15244428']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8473321754700545
- 35 USC 102 Novelty (BERT): 0.4749533337918972
- Combined Prediction Score: 0.8100942913022388
- Mean Citation Score: 128.84713119999998
- Max Citation Score: 134.5744
- Similarity Product: 89.68740082817078

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test