PATENT CLAIM ANALYSIS

Application Number: 16132190
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["708", "255000"]

Abstract:
An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.

Claim (Index 3):
The random number generation circuit of  claim 1 , wherein the sampling circuit includes an input node configured to receive a control signal, the sampling circuit being configured to generate a random number in response to being triggered by the control signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 1.32353
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14750300', '15361708', '15700475', '15361594', '15358245']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4547977454266283
- 35 USC 102 Novelty (BERT): 0.5418034846452915
- Combined Prediction Score: 0.4634983193484946
- Mean Citation Score: 234.811528
- Max Citation Score: 359.76685
- Similarity Product: 265.32743429427137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test