PATENT CLAIM ANALYSIS

Application Number: 16034249
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "108000"]

Abstract:
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Claim (Index 1):
An article of manufacture comprising at least two bonded device layers of which at least one first device layer comprises silicon on insulator (SOI) circuits disposed on a buried oxide (BOX) layer having a BOX surface and a first set of middle of the line (MOL) interconnects and a first set of back end of the line (BEOL) interconnects disposed thereon, said at least one first device layer further being flipped and bonded atop a second device layer located on its parent wafer and comprising a second set of circuits, a second set of middle of line interconnects and a second set of BEOL interconnects, and said at least one first device layer and said second device layer being interconnected together by means of metal filled vias located within said first set of MOL interconnects and said BOX layer of said at least one first device layer and connecting on one end to bonding pads associated with said second device layer and on another end to metal features provided on a third set of BEOL interconnects located atop said BOX surface, where said third set of BEOL interconnects located atop said BOX surface is not directly in contact with said SOI circuits of said at least one first device layer, thus forming an enhanced 3D device stack.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 1.81481
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13016994', '12763596', '14856967', '12684779', '12615175']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8574770489863769
- 35 USC 102 Novelty (BERT): 0.5191012140757555
- Combined Prediction Score: 0.8236394654953147
- Mean Citation Score: 227.575762
- Max Citation Score: 321.5233
- Similarity Product: 236.98236930243968

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test