PATENT CLAIM ANALYSIS

Application Number: 16160521
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["375", "320000"]

Abstract:
Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.

Claim (Index 21):
A configurable receiver comprising:\n a frequency division circuit to receive a radio frequency signal and generate a frequency-divided output signal; a time-to-digital converter coupled to the frequency division circuit to identify a period of the frequency-divided output signal; a digital subtractor coupled to the time-to-digital converter to generate an offset digital time signal, the offset digital time signal operable to identify a shift in phase of the frequency-divided output signal by identifying a temporary change in the period of the frequency-divided output signal; a digital integrator coupled to the digital subtractor to provide a value representing a phase of the radio frequency signal; an amplitude detection circuit coupled to the frequency division circuit, the amplitude detection circuit coupled to receive the radio frequency signal and generate an amplitude signal representing an amplitude of the radio frequency signal; and a mode control circuit coupled to the amplitude detection circuit and to an input of a coordinate rotation digital computer (CORDIC) logic circuit, the mode control circuit configured, in a low power mode of operation, to receive an indication to disable the amplitude detection circuit and to provide a predetermined constant value to the CORDIC logic circuit in lieu of the amplitude signal from the amplitude detection circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.84906
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15655676', '15654507', '14634525', '15164363', '15097805']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4406011191887938
- 35 USC 102 Novelty (BERT): 0.5810383770667709
- Combined Prediction Score: 0.4546448449765916
- Mean Citation Score: 250.80843
- Max Citation Score: 402.70087
- Similarity Product: 368.6905706554985

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test