PATENT CLAIM ANALYSIS

Application Number: 15909936
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["712", "208000"]

Abstract:
Binary translation may be performed by a field programmable gate array (FPGA) integrated with a processor as a single integrated circuit. The FPGA contains multiple blocks of logic for performing different binary translations. The processor may offload the binary translation to the FPGA. The FPGA may use historical logging to skip the binary translation of source instructions that have been previously translated into target instructions.

Claim (Index 13):
The system of  claim 8 , wherein the operations further include predicting future instructions based on the source instructions.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 1.47917
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10039254', '14954953', '13303841', '13969718', '14698809']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5280818603688915
- 35 USC 102 Novelty (BERT): 0.4673526632436795
- Combined Prediction Score: 0.5220089406563703
- Mean Citation Score: 131.47919600000003
- Max Citation Score: 140.52437
- Similarity Product: 106.37087964620352

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test