PATENT CLAIM ANALYSIS

Application Number: 16030163
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "108000"]

Abstract:
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Claim (Index 28):
A product according to  claim 24  wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 1.81481
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13016994', '12763596', '12239688', '14537627', '13534067']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8487240717893177
- 35 USC 102 Novelty (BERT): 0.544008570075649
- Combined Prediction Score: 0.8182525216179509
- Mean Citation Score: 241.343372
- Max Citation Score: 375.27203
- Similarity Product: 216.56715433626232

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test