PATENT CLAIM ANALYSIS

Application Number: 16381625
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "314000"]

Abstract:
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.

Claim (Index 4):
The device according to  claim 2 , wherein\n the plurality of conductive layers further include a third conductive layer and a fourth conductive layer, the third conductive layer being adjacent to the first conductive layer with a second space, the first conductive layer being positioned between the second conductive layer and the third conductive layer, the fourth conductive layer being adjacent to the second conductive layer with a third space, the second conductive layer being positioned between the first conductive layer and the fourth conductive layer; third and fourth semiconductor members positioned in the first space between the first conductive layer and the second conductive layer, the third and fourth semiconductor members being arranged in the second direction, the third semiconductor member being positioned between the first conductive layer and the fourth semiconductor member, the fourth semiconductor member being positioned between the third semiconductor member and the second conductive layer, the first semiconductor member and the third semiconductor member being arranged in the first direction with the second insulating region of the insulating part interposed, the second semiconductor member and the fourth semiconductor member being arranged in the first direction with the second insulating region of the insulating part interposed; a fifth semiconductor members positioned in the second space between the first conductive layer and the third conductive layer, the fifth semiconductor member and the second insulating region of the insulating part being arranged in the second direction, the first conductive layer being positioned between the fifth semiconductor member and the second insulating region of the insulating part; and a sixth semiconductor members positioned in the third space between the second conductive layer and the fourth conductive layer, the sixth semiconductor member and the second insulating region of the insulating part being arranged in the second direction, the second conductive layer being positioned between the sixth semiconductor member and the second insulating region of the insulating part.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 100.0
- Lexical Diversity: 5.17241
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15917954', '16057648', '15461590', '15691931', '15696756']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9117089910100326
- 35 USC 102 Novelty (BERT): 0.5156820510680558
- Combined Prediction Score: 0.8721062970158349
- Mean Citation Score: 236.29268
- Max Citation Score: 294.77216
- Similarity Product: 238.25450324310304

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test