PATENT CLAIM ANALYSIS

Application Number: 16284212
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["327", "108000"]

Abstract:
A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

Claim (Index 11):
An analog/digital input/output buffer, comprising:\n an isolation analog switch coupled between an analog module and a package pin, the isolation analog switch configured to couple the analog module to the package pin, while the analog/digital input/output buffer is in an analog mode; a digital output buffer coupled between a digital module and the package pin, the digital output buffer configured to couple the digital module to the package pin, while the analog/digital input/output buffer is in a digital output mode; and a digital input buffer coupled between the digital module and the package pin, the digital input buffer configured to couple the digital module to the package pin, while the analog/digital input/output buffer is in a digital input mode.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 99.0
- Lexical Diversity: 1.26667
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15437593', '10879338', '10677150', '14204679', '12764346']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7409018042649609
- 35 USC 102 Novelty (BERT): 0.4554247528961177
- Combined Prediction Score: 0.7123540991280766
- Mean Citation Score: 132.6608948
- Max Citation Score: 197.81079
- Similarity Product: 179.79527779219146

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test