PATENT CLAIM ANALYSIS

Application Number: 15861231
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["257", "531000"]

Abstract:
An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film. A second semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a second insulating film formed over the insulating film. The first insulating film forms an uppermost layer of the first semiconductor chip. The second insulating film forms an uppermost layer of the second semiconductor chip. Each of the first and second insulating films is made of a photosensitive resin film having an adhesive property. The first and second semiconductor chips are stacked such that the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip are in contact with each other.

Claim (Index 14):
The method of manufacturing the semiconductor device according to  claim 9 ,\n wherein the step (c) includes the steps of: (c1) mounting the first semiconductor chip over a chip mounting portion; and (c2) mounting and stacking the second semiconductor chip over the first semiconductor chip such that the first photosensitive resin film of the first semiconductor chip and the second photosensitive resin film of the second semiconductor chip come in contact with each other, wherein the first semiconductor chip has a plurality of first pads, wherein the second semiconductor chip has a plurality of second pads, the method manufacturing the semiconductor device further comprising, after the step (c), the steps of: (d) electrically coupling a plurality of first external terminals to the first pads of the first semiconductor chip via a plurality of first conductive coupling members and electrically coupling a plurality of second external terminals to the second pads of the second semiconductor chip via a plurality of second conductive coupling members; and (e) after the step (d), forming a sealing portion sealing therein the first semiconductor chip, the second semiconductor chip, the chip mounting portion, the first conductive coupling members, the second conductive coupling members, the first external terminals, and the second external terminals.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 3.58333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14928780', '14594063', '14863264', '15424059', '15789740']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9259194486746202
- 35 USC 102 Novelty (BERT): 0.5224786725993641
- Combined Prediction Score: 0.8855753710670946
- Mean Citation Score: 301.188264
- Max Citation Score: 344.6762
- Similarity Product: 287.3768255938529

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test