PATENT CLAIM ANALYSIS

Application Number: 15864371
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["708", "603000"]

Abstract:
An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

Claim (Index 11):
The arithmetic logic unit of  claim 10 , wherein the second circuit further comprises a second part comprising a fourth and a fifth AND gate whose outputs are the two inputs to the OR gate, and the output of the OR gate forms the second partial result that is input to the adder, wherein an output of a multiplexor forms a first input to the fifth AND gate and the output of the first part of the second circuit forms the first input to the fourth AND gate, wherein the fourth AND gate includes a sixth control input and the fifth AND gate includes an seventh control input, wherein the seventh and eighth control signals control the output of the two-input OR gate, the function of the second circuit and the second partial result.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.73913
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10893163', '10406046', '10035033', '11506283', '11760553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4579577619079675
- 35 USC 102 Novelty (BERT): 0.5034391891960606
- Combined Prediction Score: 0.4625059046367769
- Mean Citation Score: 248.514394
- Max Citation Score: 261.6972
- Similarity Product: 197.52491865763665

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test