PATENT CLAIM ANALYSIS

Application Number: 16011884
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-04
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pillar extending in a first direction and a first conductive pattern surrounding the channel pillar. The semiconductor device also has second conductive patterns surrounding the channel pillar above the first conductive pattern, wherein the second conductive patterns are stacked in the first direction and spaced apart from each other. The semiconductor device further has an etch stop pattern disposed above the first conductive pattern and below the second conductive patterns.

Claim (Index 10):
The semiconductor device of  claim 9  further comprising:\n interlayer insulating layers respectively disposed between the first conductive pattern and the etch stop pattern, disposed between the second conductive patterns, and disposed under the second conductive patterns and above the etch stop pattern, wherein the interlayer insulating layers surround the channel pillar; \n a source contact line in contact with the source dopant region, wherein the source contact line extends from the source dopant region in the first direction; \n a sidewall insulating layer disposed between the source contact line and a sidewall of a stack structure facing the source contact line, wherein the stack structure includes the channel contact layer, the horizontal channel layer, the gate insulating layer, the first conductive pattern, the etch stop pattern, the interlayer insulating layers, and the second conductive patterns; and \n a blocking insulating layer extending along interfaces between the sidewall insulating layer and the interlayer insulating layers, interfaces between the interlayer insulating layers and the second conductive patterns, interfaces between the first multi-layered memory pattern and the second conductive patterns, an interface between the sidewall insulating layer and the etch stop pattern, an interface between the first conductive pattern and the interlayer insulating layer, an interface between the first conductive pattern and the first multi-layered memory pattern, an interface between the first conductive pattern and the gate insulating layer, and an interface between the gate insulating layer and the sidewall insulating layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.16279
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16011975', '15934477', '15259380', '15280132', '15965139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9311023112954876
- 35 USC 102 Novelty (BERT): 0.5300092848454689
- Combined Prediction Score: 0.8909930086504857
- Mean Citation Score: 312.514078
- Max Citation Score: 365.6654
- Similarity Product: 301.9855588495731

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test