PATENT CLAIM ANALYSIS

Application Number: 16215719
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["710", "109000"]

Abstract:
The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

Claim (Index 4):
The apparatus of  claim 3 , each of the number of controllers is configured to operate independently of others of the number of controllers

Metadata:
- Claim Count in Document: 6.0
- Percentile: 98.0
- Lexical Diversity: 1.85714
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15170183', '14718649', '12329982', '12359039', '14821005']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6498793860569625
- 35 USC 102 Novelty (BERT): 0.5206426504096002
- Combined Prediction Score: 0.6369557124922264
- Mean Citation Score: 144.6154
- Max Citation Score: 260.16675
- Similarity Product: 141.7138435871154

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test