PATENT CLAIM ANALYSIS

Application Number: 16131430
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "158000"]

Abstract:
The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a selection transistor coupled in series between first and second conductive lines. The method includes the steps of precharging the first conductive line; allowing the voltage of the first conductive line to decay toward zero by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level. The discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero.

Claim (Index 9):
The method of  claim 8  further comprising the step of precharging the first conductive line to a second voltage that is lower than the first voltage before the step of allowing a voltage of the sense amplifier to decay.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 97.0
- Lexical Diversity: 2.46875
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15594387', '16002828', '15438631', '15264847', '15687687']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7971771953996514
- 35 USC 102 Novelty (BERT): 0.5329798998555426
- Combined Prediction Score: 0.7707574658452405
- Mean Citation Score: 260.96557
- Max Citation Score: 395.6389
- Similarity Product: 287.12426057498453

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test