PATENT CLAIM ANALYSIS

Application Number: 15905350
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["711", "103000"]

Abstract:
A semiconductor memory device includes a memory cell array, a first data latch that retains a write unit of data to be written to the memory cell array, a first address latch that retains a write address indicating a write target destination for the write unit of data in the first data latch, a second data latch that retains fail data that is a write unit of data that has failed to be written to the memory cell array, and a second address latch that retains a fail address indicating a write target destination for the fail data. A controller is configured to output the fail address from the second address latch in response to a first output command requesting output of the fail address and to output the fail data from the second data latch in response to a second output command requesting an output of the fail data.

Claim (Index 13):
The memory device according to  claim 12 , wherein the memory cell array is a resistance-change type memory.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 3.71429
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14006296', '13325479', '10510150', '13151548', '14988558']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5315674915778351
- 35 USC 102 Novelty (BERT): 0.4889101011134294
- Combined Prediction Score: 0.5273017525313946
- Mean Citation Score: 171.27741999999995
- Max Citation Score: 178.11105
- Similarity Product: 116.28208715868294

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test