PATENT CLAIM ANALYSIS

Application Number: 16173583
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["716", "102000"]

Abstract:
A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

Claim (Index 8):
A method of an integrated circuit, the method comprising:\n generating current and voltage information for a schematic having device array layout constraint included without RC information; creating interconnection topology patterns indicating limitations of distance and location of route based on silicon proven route patterns; realizing route for the schematic according to the interconnection topology patterns and the current and voltage information generated without RC information, including:\n performing a real-time electromigration (EM) check and a real-time voltage-dependent design rule check (VDRC); and \n adjusting the interconnection topology patterns according to results of the real-time EM check and the real-time VDRC; \n generating the RC information according to the route; generating the current and voltage information for the schematic having device array layout constraint included with the RC information; determining if the schematic having the device array layout constraint and the RC information included violates one or more of system design rule constraints; revising the device array layout constraint when the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints; generating a layout of the integrated circuit based on the schematic when the schematic having the device array layout constraint and the RC information included does not violate one or more of the system design rule constraints; and fabricating an integrated circuit according to the layout.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.0
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14969647', '14799762', '14193527', '12341152', '14307788']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.292417619082268
- 35 USC 102 Novelty (BERT): 0.5243241696347137
- Combined Prediction Score: 0.3156082741375126
- Mean Citation Score: 226.679828
- Max Citation Score: 374.67477
- Similarity Product: 363.3709574003704

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test