PATENT CLAIM ANALYSIS

Application Number: 15860562
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["327", "203000"]

Abstract:
An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

Claim (Index 22):
The system of  claim 16 , wherein the master latch and the slave latch have an associated clock path which has at most seven transistors in the master and slaves latches, and wherein the master latch is a high-clock-phase latch, while the slave latch is a low-clock-phase latch.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15247713', '15260180', '14069198', '15246445', '14711686']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.801216909875825
- 35 USC 102 Novelty (BERT): 0.5415795397264797
- Combined Prediction Score: 0.7752531728608905
- Mean Citation Score: 294.14836
- Max Citation Score: 403.50293
- Similarity Product: 289.20388103246984

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test