PATENT CLAIM ANALYSIS

Application Number: 15885359
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "302000"]

Abstract:
In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

Claim (Index 1):
A method of manufacturing a semiconductor device, comprising:\n forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer; forming a sacrificial gate structure over the fin structure; etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed; forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers; etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; and forming a source/drain epitaxial layer in the second source/drain space, wherein: at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, at least one of the second semiconductor layers is separated from a bottom of the source/drain epitaxial layer by the dielectric layer, and an upper surface of the isolation insulating layer is located at a level below a bottom of the source/drain epitaxial layer.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 86.0
- Lexical Diversity: 3.26531
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15800940', '15801200', '15653068', '15725655', '15707634']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9314199112603332
- 35 USC 102 Novelty (BERT): 0.5239745433778203
- Combined Prediction Score: 0.8906753744720821
- Mean Citation Score: 335.61363399999993
- Max Citation Score: 354.50287000000014
- Similarity Product: 335.5775795321817

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test