PATENT CLAIM ANALYSIS

Application Number: 15903396
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["713", "323000"]

Abstract:
Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Claim (Index 11):
The non-transitory computer readable medium of  claim 9 , the instructions further comprising processing power profiles indicative of distinct operating modes indicating a state of power domains, voltage domains, and clock domains in the NoC.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 1.96154
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15701305', '15903462', '15903427', '14495689', '14738487']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.492612142159199
- 35 USC 102 Novelty (BERT): 0.5617171570851651
- Combined Prediction Score: 0.4995226436517956
- Mean Citation Score: 406.961678
- Max Citation Score: 466.18918
- Similarity Product: 362.1262132655168

Labels:
- Claim Label 101: 0
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test