PATENT CLAIM ANALYSIS

Application Number: 16141285
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["712", "215000"]

Abstract:
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Claim (Index 2):
The circuit arrangement of  claim 1 , further comprising a dispatch logic circuit coupled to the plurality of parallel execution slices and configured to dispatch instructions from the one or more instruction streams to the plurality of parallel execution slices for execution thereby, the dispatch logic circuit further configured to dispatch the first and second portions of the multi-width instruction respectively to the first and second execution slices for execution thereby.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 1.5
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15939367', '15093192', '14595549', '16048946', '15093172']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6293856551082394
- 35 USC 102 Novelty (BERT): 0.561157600980164
- Combined Prediction Score: 0.622562849695432
- Mean Citation Score: 354.655344
- Max Citation Score: 439.212
- Similarity Product: 436.5021515636444

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test