PATENT CLAIM ANALYSIS

Application Number: 15863989
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "072000"]

Abstract:
An LTPS array substrate includes a substrate; a gate disposed on the substrate; a first insulating layer, a polycrystalline silicon layer, and a second insulating layer sequentially disposed on the gate; a source and a drain disposed on the second insulating layer and are electrically connected to the polycrystalline silicon layer via first contact holes formed in the second insulating layer; a passivation layer disposed on the source, the drain, and the second insulating layer and including a second contact hole formed therein to expose a surface of the drain; a third insulating layer disposed on the passivation layer in such a way that the second contact hole is exposed outside the third insulating layer; and a pixel electrode disposed on the third insulation layer and electrically connected to the drain via the second contact hole.

Claim (Index 20):
The LTPS array substrate as claimed in  claim 2 , wherein the polycrystalline silicon layer is formed of a material that is doped with P impurity ions in a portion thereof.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15863993', '14762458', '15863991', '14760750', '14779089']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9413239089724424
- 35 USC 102 Novelty (BERT): 0.5559010002671052
- Combined Prediction Score: 0.9027816181019086
- Mean Citation Score: 378.1448380000001
- Max Citation Score: 425.94504000000006
- Similarity Product: 375.029204941349

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test