PATENT CLAIM ANALYSIS

Application Number: 15962561
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["716", "108000"]

Abstract:
Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Claim (Index 1):
A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for optimizing an IC design, the method comprising:\n determining a logic function that is implemented by a combinational logic circuit in the IC design; determining a permutation class representative and a permutation based on the logic function; determining a first index based on the permutation class representative; obtaining an arrival time pattern by compressing a set of input arrival times corresponding to the combinational logic circuit; applying the permutation to the arrival time pattern to obtain a permutated arrival time pattern; determining a second index based on the permutated arrival time pattern; performing an exact delay database lookup using the first index and the second index to obtain an optimized combinational logic circuit; permuting inputs of the optimized combinational logic circuit according to the permutation to obtain an optimized-and-permutated combinational logic circuit; and obtaining an optimized IC design by replacing the combinational logic circuit in the IC design with the optimized-and-permutated combinational logic circuit in the IC design.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 1.86441
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15382406', '14583007', '15195517', '15628307', '14582971']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2981689021919861
- 35 USC 102 Novelty (BERT): 0.5024461475960295
- Combined Prediction Score: 0.3185966267323905
- Mean Citation Score: 218.78278
- Max Citation Score: 318.13596
- Similarity Product: 267.27354499689096

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test