PATENT CLAIM ANALYSIS

Application Number: 15898420
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["257", "369000"]

Abstract:
A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Claim (Index 11):
The method of  claim 2  wherein the low temperature anneal has an anneal temperature of not more than six hundred degrees Celsius.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.34146
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11955491', '15455203', '14198976', '14047849', '15284567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9131494323252732
- 35 USC 102 Novelty (BERT): 0.5265663231334995
- Combined Prediction Score: 0.8744911214060958
- Mean Citation Score: 161.625392
- Max Citation Score: 192.00551
- Similarity Product: 81.69767605930387

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test