PATENT CLAIM ANALYSIS

Application Number: 15995626
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "185180"]

Abstract:
Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

Claim (Index 12):
The device of  claim 8  further comprising an interconnect region disposed laterally outward of the peripheral circuitry, the interconnect region providing connection between the first and second units of peripheral circuitry.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 94.0
- Lexical Diversity: 2.84211
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15615652', '14657252', '15843509', '15926427', '15848612']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8025519006245853
- 35 USC 102 Novelty (BERT): 0.5333399537370106
- Combined Prediction Score: 0.7756307059358278
- Mean Citation Score: 270.11935800000003
- Max Citation Score: 393.1146
- Similarity Product: 284.24451008155347

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test