PATENT CLAIM ANALYSIS

Application Number: 16006107
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["327", "175000"]

Abstract:
A duty cycle corrector includes a delay chain, an edge detector, a falling edge shift (FES) controller, a plurality of falling edge modulator (FEM) cores, and a phase interpolator. The delay chain delays a first clock to generate a delay clock, and generates first and second sampling control signals. The edge detector samples the first clock and a second clock using the first and second sampling control signals to obtain first and second sampling signals. The FES controller determines a modulation direction and a modulation width based on the first and second sampling signals. The plurality of FEM cores first modulate the first edge of the first clock and second modulate the first edge of the delay clock using the modulation direction and the modulation width. The phase interpolator performs phase interpolation on the results of the first and second modulations.

Claim (Index 1):
A duty cycle corrector comprising:\n a delay chain configured to,\n delay a first clock to generate a delay clock, and \n generate a first sampling control signal based on a first edge of the first clock and a second sampling control signal based on a second edge of the first clock; \n an edge detector configured to,\n sample the first clock using the first sampling control signal to obtain a first sampling signal, and \n sample a second clock having an opposite phase to the first clock using the second sampling control signal to obtain a second sampling signal; \n a falling edge shift (FES) controller configured to determine a modulation direction and a modulation width of the first edge of the first clock based on the first sampling signal and the second sampling signal; a plurality of falling edge modulator (FEM) cores configured to,\n first modulate the first edge of the first clock to obtain a first modulation result, and \n second modulate a first edge of the delay clock to obtain a second modulation result, the first modulation and the second modulation being performed using the modulation direction and the modulation width; and \n a phase interpolator configured to perform phase interpolation on the first modulation result and the second modulation result.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 2.9434
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13078151', '11196581', '11148642', '12455572', '14803618']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7747393423529907
- 35 USC 102 Novelty (BERT): 0.4682426018684955
- Combined Prediction Score: 0.7440896683045413
- Mean Citation Score: 214.590178
- Max Citation Score: 225.43791
- Similarity Product: 200.0866099747288

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test