PATENT CLAIM ANALYSIS

Application Number: 16244002
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["327", "175000"]

Abstract:
Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

Claim (Index 14):
The clock distribution circuitry as claimed in  claim 12 , wherein:\n the control circuitry comprises an analogue-to-digital converter and a digital-to-analogue converter; and the control circuitry is configured to employ the analogue-to-digital converter to convert the measurement into an input digital signal, to generate an output digital signal from the input digital signal for controlling the at least one said variable control signal, and to employ the digital-to-analogue converter to generate the at least one said variable control signal from the output digital signal.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 99.0
- Lexical Diversity: 2.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16244025', '13295875', '13930662', '11101958', '11671383']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7786444093072628
- 35 USC 102 Novelty (BERT): 0.4992229416932346
- Combined Prediction Score: 0.7507022625458599
- Mean Citation Score: 192.673962
- Max Citation Score: 248.65811
- Similarity Product: 172.68451280784606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test