PATENT CLAIM ANALYSIS

Application Number: 16504248
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.

Claim (Index 5):
The integrated circuit of  claim 1  wherein:\n the tile clock generation circuitry of each logic tile includes one or more buffers.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.375
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15996430', '16009656', '14712864', '15347045', '14972553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7294803389641454
- 35 USC 102 Novelty (BERT): 0.5847843823595469
- Combined Prediction Score: 0.7150107433036855
- Mean Citation Score: 431.059484
- Max Citation Score: 486.68964000000005
- Similarity Product: 452.6838829965736

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test