PATENT CLAIM ANALYSIS

Application Number: 15912486
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["712", "002000"]

Abstract:
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

Claim (Index 6):
The system of  claim 1  further comprising:\n a network interface to communicatively couple the processor to a network.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.42857
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15912498', '15912468', '15790987', '13731008', '15188817']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6347434284463149
- 35 USC 102 Novelty (BERT): 0.5599856852910253
- Combined Prediction Score: 0.627267654130786
- Mean Citation Score: 441.901764
- Max Citation Score: 508.9396
- Similarity Product: 305.2507433127403

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test