PATENT CLAIM ANALYSIS

Application Number: 15976315
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "145000"]

Abstract:
Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS −V G  hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS  states at V G =0.

Claim (Index 21):
The NVM device recited in  claim 20 , wherein the memory cell array comprises:\n a first 2T-memory cell, a second 2T-memory cell, a third 2T-memory cell, a third 2T-memory cell, a fourth 2T-memory cell, a fifth 2T-memory cell, a sixth 2T-memory cell, a seventh 2T-memory cell, and an eighth 2T-memory cell, each memory cell having a T 1  and a T 2 , wherein T 1  is a MOSFET and T 2  is a FeEFT, wherein:\n the first 2T-memory cell has a first T 1  and a first T 2 ; \n the second 2T-memory cell has a second T 1  and a second T 2 ; \n the third 2T-memory cell has a third T 1  and a third T 2 ; \n the fourth 2T-memory cell has a fourth T 1  and a fourth T 2 ; \n the fifth 2T-memory cell has a fifth T 1  and a fifth T 2 ; \n the sixth 2T-memory cell  124  has a sixth T 1  and a sixth T 2 ; \n the seventh 2T-memory cell has a seventh T 1  and a seventh T 2 ; \n the eighth 2T-memory cell  124  has an eighth T 1  and a eighth T 2 ; and \n a first BL, BL 1 , a second BL, BL 2 , a third BL, BL 3 , and a fourth BL, BL 4 ; a first WLW, WLW 1 , a second WLW, WLW 2 , a first WLR, WLR 1 , and a second WLR, WLR 2 , wherein each of WLW 1  and WLW 2  is configured to receive and/or transmit a write signal for write operations, and each of WLR 1  and WLR 2  is configured to receive and/or transmit a read signal for read operations; the first cell T 2 -drain being connected to BL 1  and WLW 1 ; the first cell T 2 -gate being connected to WLW 1 ; the first cell T 2 -source being connected to first cell T 1 -drain; the first cell T 1 -gate being connected to WLR 1  and BL 1 ; the first cell T 1 -source being connected to ground, GND; the second cell T 2 -drain being connected to BL 2  and WLW 1 ; the second cell T 2 -gate being connected to WLW 1 ; the second cell T 2 -source being connected to second cell T 1 -drain; the second cell T 1 -gate being connected to WLR 1  and BL 2 ; the second cell T 1 -source being connected to GND; the third cell T 2 -drain being connected to BL 3  and WLW 1 ; the third cell T 2 -gate being connected to WLW 1 ; the third cell T 2 -source being connected to third cell T 1 -drain; the third cell T 1 -gate being connected to WLR 1  and BL 3 ; the third cell T 1 -source being connected to GND; the fourth cell T 2 -drain being connected to BL 4  and WLW 1 ; the fourth cell T 2 -gate being connected to WLW 1 ; the fourth cell T 2 -source being connected to fourth cell T 1 -drain; the fourth cell T 1 -gate being connected to WLR 1  and BL 4 ; the fourth cell T 1 -source being connected to GND; the fifth cell T 2 -drain being connected to BL 1  and WLW 2 ; the fifth cell T 2 -gate being connected to WLW 2 ; the fifth cell T 2 -source being connected to fifth cell T 1 -drain; the fifth cell T 1 -gate being connected to WLR 2  and BL 1 ; the fifth cell T 1 -source being connected to GND; the sixth cell T 2 -drain being connected to BL 2  and WLW 2 ; the sixth cell T 2 -gate being connected to WLW 2 ; the sixth cell T 2 -source being connected to sixth cell T 1 -drain; the sixth cell T 1 -gate being connected to WLR 2  and BL 2 ; the sixth cell T 1 -source being connected to GND; the seventh cell T 2 -drain being connected to BL 3  and WLW 2 ; the seventh cell T 2 -gate being connected to WLW 2 ; the seventh cell T 2 -source being connected to seventh cell T 1 -drain; the seventh cell T 1 -gate being connected to WLR 2  and BL 3 ; the seventh cell T 1 -source being connected to GND; the eighth cell T 2 -drain being connected to BL 4  and WLW 2 ; the eighth cell T 2 -gate being connected to WLW 2 ; the eighth cell T 2 -source being connected to eighth cell T 1 -drain; the eighth cell T 1 -gate being connected to WLR 2  and BL 4 ; and the eighth cell T 1 -source being connected to GND.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 93.0
- Lexical Diversity: 1.77632
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12860253', '15594807', '13137566', '12856962', '13396272']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7960337844391792
- 35 USC 102 Novelty (BERT): 0.4818861458487213
- Combined Prediction Score: 0.7646190205801334
- Mean Citation Score: 165.774406
- Max Citation Score: 186.89499
- Similarity Product: 127.30506331477228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test