PATENT CLAIM ANALYSIS

Application Number: 15957955
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-01
Patent Classification: ["257", "737000"]

Abstract:
A method for packaging a chip, including: forming a release layer on a first panel-level substrate, and forming redistribution layers respectively on predetermined regions on the release layer, the redistribution layers located in different regions being insulated from each other, and forming a first dielectric layer during the process of forming the redistribution layers; connecting a chip and a pillar connected to the chip to the redistribution layer formed in the predetermined region through a solder cap on the pillar; packaging the chip to form an encapsulation layer; and removing the first panel-level substrate and the release layer, and forming a solder ball on one side of the redistribution layer.

Claim (Index 6):
The method for packaging a chip according to  claim 2 , wherein the step of forming the pillar comprises:\n forming the pillar by processes of exposure, development, and electroforming in sequence.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 91.0
- Lexical Diversity: 2.26415
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15951267', '15751790', '15571581', '14198493', '14496049']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9262661425037968
- 35 USC 102 Novelty (BERT): 0.5037560460736487
- Combined Prediction Score: 0.8840151328607821
- Mean Citation Score: 228.6601
- Max Citation Score: 246.37389
- Similarity Product: 171.30358531436562

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test