PATENT CLAIM ANALYSIS

Application Number: 15978750
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["711", "105000"]

Abstract:
The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Claim (Index 29):
An apparatus, comprising:\n a memory device comprising:\n a plurality of subarrays of memory cells; \n sensing circuitry including a sense amplifier and a compute component coupled to the plurality of subarrays via a respective plurality of sense lines, the sense amplifier and the compute component configured to operate as an in-memory processor for a column of memory cells coupled to a respective sense line; \n a first subarray controller of a plurality of subarray controllers that is coupled to a first subarray and is configured to execute a first set of instructions to direct performance of a first operation by a first number of in-memory processors on data stored in the first subarray; and \n a second subarray controller of the plurality that is coupled to a second subarray and is configured to independently execute a second set of instructions to direct performance of a second operation by a second number of in-memory processors on data stored in the second subarray, wherein the second operation is different than the first operation in a sequence of operations intended to yield an output; and \n wherein a controller of the memory device is configured to provide a different set of instructions for the first operation and the second operation to the respective first subarray controller and second subarray controller.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.75926
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15045750', '15081492', '15439522', '15470516', '15082652']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.548163104055846
- 35 USC 102 Novelty (BERT): 0.532581772238261
- Combined Prediction Score: 0.5466049708740875
- Mean Citation Score: 338.080242
- Max Citation Score: 363.13113
- Similarity Product: 304.8979579241288

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test