PATENT CLAIM ANALYSIS

Application Number: 16029701
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["326", "041000"]

Abstract:
A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Claim (Index 2):
The field-programmable-gate-array (FPGA) IC chip of  claim 1 , wherein the programmable logic block comprises a multiplexer having a first set of inputs associated with the resulting values and a second set of inputs associated with the inputs of the programmable logic block, wherein the multiplexer is configured to select, in accordance with its second set of inputs, one from its first set of inputs into its output.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 2.22
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15841326', '11171489', '14481943', '10827786', '12283443']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6370307252145453
- 35 USC 102 Novelty (BERT): 0.5517535909227361
- Combined Prediction Score: 0.6285030117853645
- Mean Citation Score: 226.70871
- Max Citation Score: 420.45532
- Similarity Product: 308.1478544841861

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test