PATENT CLAIM ANALYSIS

Application Number: 16237886
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.

Claim (Index 1):
A method for forming a semiconductor structure comprising steps of:\n forming an upper layer in a first interlayer dielectric (ILD) layer, wherein forming the upper layer in the first ILD layer comprises:\n forming a plurality of metal interconnects; and \n forming one or more upper layer air gaps positioned between adjacent metal interconnects; and \n forming a lower layer in the first ILD layer, wherein forming the lower layer in the first ILD layer comprises forming one or more lower layer air gaps positioned between adjacent vias formed within the lower layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.20513
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15690861', '15208021', '15690822', '15468972', '15811129']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.909068129487641
- 35 USC 102 Novelty (BERT): 0.5257255418353299
- Combined Prediction Score: 0.8707338707224099
- Mean Citation Score: 287.1675479999999
- Max Citation Score: 343.2324
- Similarity Product: 340.6898492769241

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test