PATENT CLAIM ANALYSIS

Application Number: 16100261
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["349", "038000"]

Abstract:
An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

Claim (Index 6):
A semiconductor device comprising:\n a first circuit configured to output a first selection signal to a first scan line; a second circuit configured to output a second selection signal to a second scan line; and a third circuit configured to output a third selection signal to a third scan line, wherein the second circuit comprises a first transistor, a second transistor, and a third transistor, wherein one of a source and a drain of the first transistor is electrically connected to the second scan line, wherein one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to a gate of the first transistor, wherein a gate of the second transistor is electrically connected to the first scan line through a first wiring, wherein a gate of the third transistor is electrically connected to the third scan line through a second wiring, wherein a value of a channel width W to a channel length L of the second transistor is larger than that of the first transistor, wherein a value of a channel width W to a channel length L of the third transistor is larger than that of the first transistor, wherein the first circuit is electrically connected to a third wiring which a first clock signal is input, wherein the second circuit is electrically connected to a fourth wiring which a second clock signal is input, wherein the third circuit is electrically connected to a fifth wiring which a third clock signal is input, and wherein the other of the source and the drain of the first transistor is electrically connected to the fourth wiring.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 96.0
- Lexical Diversity: 2.21667
- Patent Class: 349.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15450099', '14554216', '13974328', '11853215', '13174895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8890616693627593
- 35 USC 102 Novelty (BERT): 0.5521011852190489
- Combined Prediction Score: 0.8553656209483883
- Mean Citation Score: 415.907132
- Max Citation Score: 431.7693
- Similarity Product: 376.1585316140772

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test