PATENT CLAIM ANALYSIS

Application Number: 15911415
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Claim (Index 4):
The transistor structure of  claim 1 , further comprising a doped semiconductor region formed on the terminal area of the semiconductor fin, such that an interface between the doped semiconductor region and the terminal area of the semiconductor fin substantially encloses the second cross-sectional area.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 90.0
- Lexical Diversity: 2.71429
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15073740', '15626321', '15868224', '15793419', '14754958']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914460235223604
- 35 USC 102 Novelty (BERT): 0.5263968670932918
- Combined Prediction Score: 0.8756538984105728
- Mean Citation Score: 241.043104
- Max Citation Score: 347.99800000000016
- Similarity Product: 262.7810722767116

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test