PATENT CLAIM ANALYSIS

Application Number: 15961337
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

Claim (Index 28):
The structure of  claim 27  wherein the contact only contacts the first gate section over the vertical sidewall of the first gate section.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 2.50943
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15586621', '15654165', '15671605', '15447639', '15694109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9291885168200898
- 35 USC 102 Novelty (BERT): 0.5261032411050098
- Combined Prediction Score: 0.8888799892485819
- Mean Citation Score: 262.74217200000004
- Max Citation Score: 288.24908
- Similarity Product: 142.8870968069267

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test