PATENT CLAIM ANALYSIS

Application Number: 16102388
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "051000"]

Abstract:
Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device having improved reliability includes a memory cell array including memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation on a word line selected from among the plurality of word lines, and control logic configured to control the peripheral circuit so that, when the selected word line is a reference word line during the program operation, a partial erase operation is performed on memory cells included in a memory cell group corresponding to the reference word line.

Claim (Index 3):
The semiconductor memory device according to  claim 2 , wherein the selected memory block comprises a plurality of memory cell groups corresponding to the plurality of reference word lines, respectively.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.05556
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15613736', '15628755', '15631054', '15641485', '14219811']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8223628782286654
- 35 USC 102 Novelty (BERT): 0.4864717701147903
- Combined Prediction Score: 0.7887737674172779
- Mean Citation Score: 242.793072
- Max Citation Score: 259.40054
- Similarity Product: 214.81774202702044

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test