PATENT CLAIM ANALYSIS

Application Number: 15768549
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["327", "537000"]

Abstract:
According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output, This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs. The logic type offers higher operation speed compared to the existing solutions.

Claim (Index 1):
A logic gate consisting of only PMOS (NMOS) enhancement mode transistors implementing Boolean function with at least two inputs, characterized in\n the pull-down (pull-up) branch is realized by a single transistor with its gate and source terminals connected to the output of the logic gate; at least one pull-up (pull-down) branch, the branches realizing the pull-up (pull-down) part of the Boolean function, where the pull-up (pull-down) part consists of at least two transistors having different inputs associated with their gate terminals; the pull-down (pull-up) branch pulls the output close to the lower (higher) supply voltage when no pull-up (pull-down) branch is in conductive mode, and the pull-up (pull-down) part pulls the output close to the higher (lower) supply voltage, when at least one pull-up (pull-down) branch is in conductive mode; all the transistors forming the logic gate have the same substrate voltage.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.76842
- Patent Class: 327.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10630322', '11765751', '11055228', '10272028', '10644156']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8021399486271323
- 35 USC 102 Novelty (BERT): 0.4538400245476039
- Combined Prediction Score: 0.7673099562191795
- Mean Citation Score: 167.875932
- Max Citation Score: 169.76023999999995
- Similarity Product: 141.46522409702774

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test