PATENT CLAIM ANALYSIS

Application Number: 15987211
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

Claim (Index 15):
A semiconductor device comprising:\n a substrate including a lower wiring; an interlayer insulating film disposed on the substrate and including a first region, a second region on the first region, and a third region on the second region; an opening in the interlayer insulating film, wherein the opening includes a first portion exposing the lower wiring and defined by the first region of the interlayer insulating film, a second portion defined by the second region of the interlayer insulating film, and a third portion defined by the third region of the interlayer insulating film, wherein the third portion of the opening is elongated to form horizontal wiring; a via which fills the first portion of the opening and connected to the lower wiring on the lower wiring; and a first upper wiring on the via, wherein the first upper wiring fills the second portion of the opening and the third portion of the opening, connects to the via, and includes a short side extending in a first direction parallel to an upper surface of the substrate, at a boundary between the second region of the interlayer insulating film and the third region of the interlayer insulating film, a first width of the first upper wiring filling the second portion of the opening in the first direction is smaller than a second width of the first upper wiring filling the third portion of the opening in the first direction.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 93.0
- Lexical Diversity: 4.39024
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15840128', '15636889', '15236427', '15296202', '15870175']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9226842649640336
- 35 USC 102 Novelty (BERT): 0.4957733690087852
- Combined Prediction Score: 0.8799931753685089
- Mean Citation Score: 250.35919000000004
- Max Citation Score: 261.1193
- Similarity Product: 204.8595155166388

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test