PATENT CLAIM ANALYSIS

Application Number: 15909568
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "048000"]

Abstract:
According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

Claim (Index 9):
The manufacturing method according to  claim 7 ,\n wherein the wiring is formed in a wiring layer that is a different layer than the inspection pad in a stacking direction of a plurality of word lines of the three-dimensional arranged memory cells.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.21739
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15457316', '14809106', '12343086', '10647242', '11153531']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9007272530006816
- 35 USC 102 Novelty (BERT): 0.5048600864321691
- Combined Prediction Score: 0.8611405363438303
- Mean Citation Score: 162.613512
- Max Citation Score: 168.01617
- Similarity Product: 100.39936006011663

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test