PATENT CLAIM ANALYSIS

Application Number: 15921201
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["326", "040000"]

Abstract:
A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.

Claim (Index 2):
The reference voltage block of  claim 1 , wherein the reference voltage output signal is fed to an analog fabric of the programmable fabric of the PLD.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 90.0
- Lexical Diversity: 2.39344
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15656982', '15656978', '15656972', '15673142', '15656965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7400059183743969
- 35 USC 102 Novelty (BERT): 0.5264988793717607
- Combined Prediction Score: 0.7186552144741333
- Mean Citation Score: 306.131164
- Max Citation Score: 366.8199
- Similarity Product: 364.9436918580294

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test