PATENT CLAIM ANALYSIS

Application Number: 15885536
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["375", "232000"]

Abstract:
A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

Claim (Index 23):
The method of  claim 17 , wherein the first de-emphasis or pre-emphasis adjustment is based at least in part on a first control signal output by a first pre-driver and the second de-emphasis or pre-emphasis adjustment is based at least in part on a second control signal output by a second pre-driver circuit.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 86.0
- Lexical Diversity: 2.08621
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15885532', '10997159', '11336045', '12517274', '11386984']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4797822794164966
- 35 USC 102 Novelty (BERT): 0.5020823796859826
- Combined Prediction Score: 0.4820122894434452
- Mean Citation Score: 174.63583200000005
- Max Citation Score: 274.06625
- Similarity Product: 220.30188085086647

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test