PATENT CLAIM ANALYSIS

Application Number: 16102502
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["438", "157000"]

Abstract:
In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Claim (Index 4):
The method of  claim 3 , further comprising:\n forming a gate spacer over a side wall of the gate electrode; and forming a fin spacer over a side wall of an exposed portion of the fin structure on a side of the gate electrode and the gate spacer, wherein the gate spacer and the fin spacer form an L-shaped cross-section, the L-shaped cross-section is substantially parallel to the surface of the substrate and the L-shaped cross-section has an indented corner conformal to the footing region.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.73684
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15430901', '14180895', '14184229', '14215564', '15182995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8314139871861518
- 35 USC 102 Novelty (BERT): 0.5151255499811394
- Combined Prediction Score: 0.7997851434656505
- Mean Citation Score: 226.790824
- Max Citation Score: 305.81708
- Similarity Product: 264.10383558036085

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test