PATENT CLAIM ANALYSIS

Application Number: 15888745
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "329000"]

Abstract:
A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Claim (Index 11):
A method of forming a semiconductor structure, the method comprising:\n forming at least one semiconductor fin extending upwards from a semiconductor substrate, wherein a dielectric spacer is present on each sidewall surface of the at least one semiconductor fin and a hard mask is located on a topmost surface of the at least one semiconductor fin; recessing the semiconductor substrate to provide a semiconductor pedestal beneath the dielectric spacer and the at least one semiconductor fin: performing a self-limiting etch to convert at least the semiconductor pedestal into a semiconductor base comprises an upper portion, a lower portion and a midsection, wherein the midsection has a narrower width than the lower and upper portions; forming a bottom source/drain structure on physically exposed surfaces of the semiconductor base and the semiconductor substrate; removing each dielectric spacer from length-wise sidewalls of the at least one semiconductor fin; forming a gate structure above the bottom source/drain structure and on each side of the at least one semiconductor fin; removing the hard mask from the at least one semiconductor fin; and forming a top source/drain structure on a topmost surface of the at least one semiconductor fin.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 88.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15808178', '15492797', '15848960', '15185953', '14694562']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914655360542674
- 35 USC 102 Novelty (BERT): 0.5265252093424259
- Combined Prediction Score: 0.8758423454226492
- Mean Citation Score: 314.82422
- Max Citation Score: 342.5896
- Similarity Product: 315.1605679710388

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test