PATENT CLAIM ANALYSIS

Application Number: 15977357
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "314000"]

Abstract:
The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.

Claim (Index 1):
A non-volatile memory, comprising:\n a first selection transistor comprising:\n a first layer of a semiconductor material in which a first channel region and first and second conduction electrodes are formed; \n a first gate stack formed on the said first channel region and including a first gate electrode and a first gate insulator disposed between the first gate electrode and the first channel region; \n a second selection transistor comprising:\n a second layer of semiconductor material in which a second channel region and third and fourth conduction electrodes are formed; \n a second gate stack formed on the said second channel region and including a second gate electrode and a second gate insulator disposed between the second gate electrode and the second channel region; \n an isolation trench disposed between the first and second selection transistors; a storage structure of the RRAM type comprising:\n a control electrode; \n a dielectric layer formed under the control electrode, comprising a central part directly above the isolation trench and first and second ends respectively extending directly above the first and third conduction electrodes, the dielectric layer being configured so as to selectively form a first conducting filament between the control electrode and the first conduction electrode, and so as to selectively form a second conducting filament between the control electrode and the third conduction electrode, the dielectric layer, the first gate insulator and the second gate insulator being formed in the same material, the said memory structure and the said first and second selection transistors being formed in the same pre-metallization layer.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 93.0
- Lexical Diversity: 1.96774
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15387850', '12169264', '14657914', '14434148', '12718434']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9103572564082966
- 35 USC 102 Novelty (BERT): 0.4553941338797119
- Combined Prediction Score: 0.8648609441554381
- Mean Citation Score: 166.71666999999997
- Max Citation Score: 172.7413
- Similarity Product: 149.08375842635633

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test