PATENT CLAIM ANALYSIS

Application Number: 16029058
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "211000"]

Abstract:
A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

Claim (Index 9):
The zero counter according to  claim 6 , wherein at least one of the high or low subsection hardware logic blocks comprises:\n a further low subsection hardware logic block comprising inputs arranged to receive bits from a first further subsection of a subsection of a string, the first further subsection including a least significant bit in the subsection and one or more logic gates arranged to combine the received bits and generate at least one output; a further high subsection hardware logic block comprising inputs arranged to receive bits from a second further subsection of the subsection of a string, the second further subsection including a most significant bit in the subsection and one or more logic gates arranged to combine the received bits and generate at least one output, wherein the first and second further subsections of the subsection are non-overlapping and comprise all the bits in the subsection; and combining logic arranged to combine the output of the two further subsection hardware logic blocks and generate an output of the subsection hardware logic block.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 95.0
- Lexical Diversity: 2.10667
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15810081', '15218306', '15426907', '14598459', '15636100']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5278977570975386
- 35 USC 102 Novelty (BERT): 0.5864903766919428
- Combined Prediction Score: 0.533757019056979
- Mean Citation Score: 424.202142
- Max Citation Score: 479.53256
- Similarity Product: 465.20313284323686

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test