PATENT CLAIM ANALYSIS

Application Number: 15994435
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["438", "626000"]

Abstract:
Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

Claim (Index 6):
The method of  claim 1 , wherein a thickness of the conductive layer in the cavity is more than 2 times the thickness of the conductive layer outside the cavity.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 1.87013
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11602128', '13170095', '15919894', '10858766', '11893793']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8777892555477931
- 35 USC 102 Novelty (BERT): 0.501021890638569
- Combined Prediction Score: 0.8401125190568707
- Mean Citation Score: 224.554644
- Max Citation Score: 241.85347
- Similarity Product: 168.26064245647788

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test