PATENT CLAIM ANALYSIS

Application Number: 15902098
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "382000"]

Abstract:
In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

Claim (Index 4):
The FinFET device of  claim 3 , wherein a sidewall of the capping layer overlaps at least a portion of a sidewall of the spacer layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.71186
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15728615', '15598393', '15705888', '15598447', '15343590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9375799016305796
- 35 USC 102 Novelty (BERT): 0.5252339582450963
- Combined Prediction Score: 0.8963453072920313
- Mean Citation Score: 325.950346
- Max Citation Score: 340.2065
- Similarity Product: 247.7016563073993

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test