PATENT CLAIM ANALYSIS

Application Number: 15866587
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["386", "263000"]

Abstract:
A signal processing apparatus includes an oscillation circuit, an interpolation circuit, a matching filter, a high-pass filter and a timing recovery circuit. The oscillation circuit generates a clock signal. The interpolation circuit performs interpolation on an input signal according to the clock signal to generate an interpolation sample result. The matching filter demodulates the interpolation sample result to generate an output signal. The high-pass filter performs high-pass filtering on the interpolation sample result to generate a filtered result. The timing recovery circuit receives the filtered result, and performs timing recovery according to the filtered result.

Claim (Index 1):
A signal receiving apparatus, comprising:\n an oscillation circuit, generating a clock signal; an interpolation circuit, performing interpolation on an input signal according to the clock signal to generate an interpolation sample result; a matching filter, demodulating the interpolation sample result to generate an output signal; a high-pass filter, performing high-pass filtering on the interpolation sample result to generate a filtered signal; and a timing recovering circuit, receiving the filtered signal, and performing timing recovery according to the filtered signal, wherein the high-pass filter is implemented to share a part of a circuit with the matching filter, and wherein the matching filter and the high-pass filter comprise:\n a delay circuit, generating N number of delayed signals for the interpolation sample result, wherein a delay amount corresponding to an (i+1) th  delayed signal is greater than a delay amount corresponding to an i th  delayed signal, i is an integer index between 1 and (N\u22121), and N is an integer greater than 1; \n a multiplication circuit, multiplying the i th  delayed signal by an i th  weight to generate an i th  weighted result; \n a first addition circuit, summing up the interpolation sample result and the delayed signals having the integer index i in even numbers to generate a first summation value; \n a second addition circuit, summing up the delayed signals having the integer index i in odd numbers to generate a second summation value; \n a third addition circuit, adding the first summation value and the second summation value to generate the output signal; and \n a subtraction circuit, subtracting the second summation value from the first summation value to generate the filtered signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 3.0
- Patent Class: 386.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14257849', '14737330', '10325202', '14033128', '11936245']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5460520558132917
- 35 USC 102 Novelty (BERT): 0.4636818110411236
- Combined Prediction Score: 0.537815031336075
- Mean Citation Score: 178.52363799999995
- Max Citation Score: 188.83900000000003
- Similarity Product: 162.64008435970547

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test