PATENT CLAIM ANALYSIS

Application Number: 16164329
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["327", "225000"]

Abstract:
A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Claim (Index 8):
A semiconductor circuit comprising:\n a first logic gate that receives inputs of a second input signal, a clock signal and a feedback signal and performs a second sub-logical operation to output a first output signal, the second input signal being generated by performing a first sub-logical operation on an inverted signal of the first output signal and a first input signal; a second logic gate that receives inputs of the first input signal and the feedback signal to perform a first logical operation; and a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a second logical operation to output the feedback signal.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 2.89286
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15245239', '15499257', '13049427', '15417339', '14276088']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7709340408989837
- 35 USC 102 Novelty (BERT): 0.5407135939831446
- Combined Prediction Score: 0.7479119962073997
- Mean Citation Score: 264.513298
- Max Citation Score: 386.14514
- Similarity Product: 368.894661127956

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test