PATENT CLAIM ANALYSIS

Application Number: 15911376
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["323", "205000"]

Abstract:
A power factor correction circuit can include: a power meter configured to measure a power factor at an input port; a switching-type regulator that is controllable by a switching control signal in order to adjust the power factor of an input AC power; an EMI filter disposed between the switching-type regulator and the input port; and a controller configured to generate the switching control signal to maximize the power factor by adjusting a current reference signal according to a measured power factor, where the current reference signal represents an expected inductor current of the switching-type regulator.

Claim (Index 4):
The power factor correction circuit of  claim 3 , wherein said offset time is obtained according to the formula Td = arccos \ue8a0 ( P \ue89e \ue89e F ) 360 * T , wherein Td is said offset time, PF is said measured power factor, and T is the period of said input AC power.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 90.0
- Lexical Diversity: 1.96154
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15911317', '10893267', '14180055', '14489078', '10854240']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7433223382057255
- 35 USC 102 Novelty (BERT): 0.502035576912418
- Combined Prediction Score: 0.7191936620763948
- Mean Citation Score: 204.006002
- Max Citation Score: 245.69751
- Similarity Product: 158.94950976101342

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test