PATENT CLAIM ANALYSIS

Application Number: 15746615
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["365", "189011"]

Abstract:
An SRAM cell comprises a first inverter having an output lead coupled to the input lead of a second inverter via a first resistor. The output lead of the second inverter is coupled to the first inverter input lead via a second resistor. A first write bit line is coupled to the first inverter input lead via a first switch, and a second write bit line is coupled to the second inverter input lead via a second switch. Because of the resistors, the circuitry driving write bit lines does not have to overpower the inverters when writing data to the cell. The cell is part of an array comprising several columns of SRAM cells, each column coupled to a pair of write bit lines. A resonating oscillator drives the write bit lines with a sine wave. This reduces the power consumed by the SRAM array.

Claim (Index 16):
Structure of  claim 11  wherein a plurality of write bit lines are coupled to said resonator circuit, the capacitance of said write bit lines coupled to said resonator circuit enabling said resonator circuit to resonate.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 86.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15711110', '12027548', '13276351', '14499149', '14285410']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7737357585848286
- 35 USC 102 Novelty (BERT): 0.4927125703382566
- Combined Prediction Score: 0.7456334397601714
- Mean Citation Score: 203.202374
- Max Citation Score: 205.19534
- Similarity Product: 140.1327311390066

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test