PATENT CLAIM ANALYSIS

Application Number: 15917037
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "185020"]

Abstract:
A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.

Claim (Index 1):
A memory device comprising:\n a memory controller; and a memory cell array that includes one or more memory blocks, wherein each memory block of the one or more memory blocks includes one or more strings, each string of the one or more strings comprising:\n a plurality of dummy word lines, \n a plurality of word lines, and \n a plurality of memory cells respectively coupled to the plurality of word lines, \n wherein the memory controller is configured to program one or more data to one or more memory cells of the plurality of memory cells using operations during a programming cycle, the operations comprising: \n during a setup stage of the programming cycle,\n providing a first voltage level to the plurality of word lines, \n providing a second voltage level to a first dummy word line of the plurality of dummy word lines, and \n providing a fourth voltage level to second dummy word lines of the plurality of dummy word lines, the second dummy word lines being different from the first dummy word line, \n wherein (i) the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and (ii) the second voltage level and the fourth voltage are higher than the threshold voltage of the first transistor, \n during a program stage of the programming cycle,\n providing a third voltage level to one or more first word lines of the plurality of word lines to program one or more data to one or more memory cells coupled to the one or more first word lines, \n providing the second voltage level to the first dummy word line of the plurality of dummy word lines, and \n providing the fourth voltage level to the second dummy word lines of the plurality of dummy word lines.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 3.26531
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12583811', '12797994', '12590701', '14924523', '13962261']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8078019500070459
- 35 USC 102 Novelty (BERT): 0.4854782240703035
- Combined Prediction Score: 0.7755695774133717
- Mean Citation Score: 249.957514
- Max Citation Score: 256.99567
- Similarity Product: 205.91161779517773

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test