PATENT CLAIM ANALYSIS

Application Number: 15997338
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "048000"]

Abstract:
A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.

Claim (Index 8):
The semiconductor device of  claim 1 , further comprising:\n a semiconductor integrated circuit on the chip region of the semiconductor substrate; a test structure on the edge region of the semiconductor substrate; and a metal line connecting the semiconductor integrated circuit and the chip pad to each other, wherein the lower dielectric layer is on the semiconductor integrated circuit, the test structure, and the metal line.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 94.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15295104', '15222114', '15205414', '15791709', '15201694']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9215271272288362
- 35 USC 102 Novelty (BERT): 0.4904838114580094
- Combined Prediction Score: 0.8784227956517535
- Mean Citation Score: 245.81111
- Max Citation Score: 252.92455
- Similarity Product: 205.87959137173888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test