PATENT CLAIM ANALYSIS

Application Number: 15914387
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "355000"]

Abstract:
An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

Claim (Index 4):
The integrated circuit of  claim 3 , wherein the first and second polysilicon lines extend parallel to each other.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 90.0
- Lexical Diversity: 2.03279
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15497993', '14964704', '13480956', '14475683', '11405531']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9088173838164404
- 35 USC 102 Novelty (BERT): 0.541561301462896
- Combined Prediction Score: 0.8720917755810861
- Mean Citation Score: 237.778816
- Max Citation Score: 365.7135
- Similarity Product: 253.8006806586385

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test