PATENT CLAIM ANALYSIS

Application Number: 16157741
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["323", "313000"]

Abstract:
A transistor (M 1 ) whose gate is capacitance-coupled to a wiring (L 1 ) is connected between the wirings (L 1,  L 2 ) connected to output nodes (OT 1,  OT 2 ) outputting a reference voltage (VREF_OUT). A replica circuit ( 20 ) having a resistor ( 22 ) and a transistor (M 2 ) connected in series is provided between the wirings (L 1,  L 2 ). Gates of the transistors (M 1,  M 2 ) are connected to each other. A differential amplifier ( 23 ) receives a voltage (V_RP) of a node (N 1 ) between the resistor ( 22 ) and the transistor (M 1 ) and a standard voltage (V_ID), and provides an output to the gate of the transistor (M 2 ).

Claim (Index 10):
The reference voltage stabilizing circuit of  claim 9 , further comprising\n subsequent-stage circuits each including the first transistor, the capacitor, the replica circuit, and the differential amplifier, wherein the subsequent-stage circuits are connected in common e previous-stage circuit.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 2.81818
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12379289', '16465992', '13288881', '14845266', '15172932']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7286545700866667
- 35 USC 102 Novelty (BERT): 0.4856493283235462
- Combined Prediction Score: 0.7043540459103547
- Mean Citation Score: 178.383944
- Max Citation Score: 183.9667
- Similarity Product: 121.63960203164817

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test