PATENT CLAIM ANALYSIS

Application Number: 15900800
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "742000"]

Abstract:
A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

Claim (Index 7):
The method of forming a bit line gate structure of a dynamic random access memory (DRAM) according to  claim 1 , wherein the step of forming the metal stack on the polysilicon layer comprises depositing a titanium silicon nitride layer directly on the polysilicon layer.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 88.0
- Lexical Diversity: 2.95652
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15894840', '10708530', '12007819', '11408752', '15013389']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9272342958569396
- 35 USC 102 Novelty (BERT): 0.5006437260065827
- Combined Prediction Score: 0.8845752388719039
- Mean Citation Score: 235.053074
- Max Citation Score: 254.62166
- Similarity Product: 187.59235793844687

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test