PATENT CLAIM ANALYSIS

Application Number: 16192322
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["711", "144000"]

Abstract:
In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.

Claim (Index 1):
A processor comprising:\n a plurality of cores; and synchronization logic comprising circuitry, the circuitry to:\n receive a first memory request and a second memory request; \n determine whether the second memory request is in contention with the first memory request; and \n in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.93333
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15180351', '15333873', '15333833', '14581097', '14977841']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4868779702740843
- 35 USC 102 Novelty (BERT): 0.4242545051673762
- Combined Prediction Score: 0.4806156237634135
- Mean Citation Score: 101.037032
- Max Citation Score: 122.79137
- Similarity Product: 113.9708884208256

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test