PATENT CLAIM ANALYSIS

Application Number: 16129767
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2018-12
Patent Classification: ["438", "030000"]

Abstract:
A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.

Claim (Index 6):
The manufacture method of the low temperature poly-silicon array substrate according to  claim 2 , wherein the substrate is a glass substrate; a material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the buffer layer, the gate isolation layer, the interlayer insulation layer and the passivation protective layer are silicon oxide layers, silicon nitride layers or composite layers superimposed with silicon oxide layers and silicon nitride layers; the flat layer is an organic photoresist material.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 97.0
- Lexical Diversity: 1.58824
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15111822', '15115692', '15031279', '15105572', '16101534']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8664896040298973
- 35 USC 102 Novelty (BERT): 0.579775730850562
- Combined Prediction Score: 0.8378182167119638
- Mean Citation Score: 335.336498
- Max Citation Score: 452.4254
- Similarity Product: 435.02155216531753

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test