PATENT CLAIM ANALYSIS

Application Number: 15860059
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["349", "139000"]

Abstract:
To achieve a display device that is suitable for increasing in size and to provide a high-resolution display device. In the display device, three or more adjacent gate lines are supplied with the same selection signal. Three or more pixels that adjoin in the column direction are connected to different source lines. In each of the pixels, a transistor including a semiconductor layer is disposed. An inner source line among three or more source lines is disposed to overlap with a conductive layer that functions as a pixel electrode. Part of the semiconductor layer of the transistor is provided between the outer source line and a source line adjacent to the outer source line.

Claim (Index 15):
A display device comprising:\n a first source line; a second source line adjacent to the first source line; a third source line adjacent to the second source line; a fourth source line adjacent to the third source line; a first gate line; a second gate line adjacent to the first gate line; a third gate line adjacent to the second gate line; a fourth gate line adjacent to the third gate line; a first transistor; a second transistor; a third transistor; a fourth transistor; a first conductive layer; a second conductive layer; a third conductive layer; and a fourth conductive layer, wherein a gate of the first transistor is electrically connected to the first gate line, one of a source and a drain of the first transistor is electrically connected to the first source line, and the other of the source and the drain of the first transistor is electrically connected to the first conductive layer, wherein a gate of the second transistor is electrically connected to the second gate line, one of a source and a drain of the second transistor is electrically connected to the second source line, and the other of the source and the drain of the second transistor is electrically connected to the second conductive layer, wherein a gate of the third transistor is electrically connected to the third gate line, one of a source and a drain of the third transistor is electrically connected to the third source line, and the other of the source and the drain of the third transistor is electrically connected to the third conductive layer, wherein a gate of the fourth transistor is electrically connected to the fourth gate line, one of a source and a drain of the fourth transistor is electrically connected to the fourth source line, and the other of the source and the drain of the fourth transistor is electrically connected to the fourth conductive layer, and wherein the first gate line, the second gate line, the third gate line, and the fourth gate line are supplied with the same selection signal.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 349.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15816277', '12887179', '13855753', '13070807', '15728591']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8447798337363985
- 35 USC 102 Novelty (BERT): 0.4675796922299746
- Combined Prediction Score: 0.8070598195857561
- Mean Citation Score: 215.923426
- Max Citation Score: 217.17545
- Similarity Product: 191.0464613596141

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test