PATENT CLAIM ANALYSIS

Application Number: 15950183
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "072000"]

Abstract:
A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Claim (Index 6):
The memory device of  claim 4 , wherein each of the second switches is a double-gate transistor, and controlled to be conducted or cutoff by both the column word line and a row word line among the plurality of row word lines.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 3.17778
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15497229', '13620184', '11509991', '10389753', '12382243']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8381811994243958
- 35 USC 102 Novelty (BERT): 0.5023082254695791
- Combined Prediction Score: 0.8045939020289141
- Mean Citation Score: 260.984684
- Max Citation Score: 291.00253
- Similarity Product: 221.7018036830008

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test