PATENT CLAIM ANALYSIS

Application Number: 15896319
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["375", "358000"]

Abstract:
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.

Claim (Index 15):
A method for synthesizing a clock from an incoming data stream, the method comprising:\n receiving the incoming data stream comprising binary bits, and a feedback signal; based on the incoming data stream and the feedback signal, generating digital inputs that jointly determine a first polarity signal and a second polarity signal, the first and second polarity signals respectively indicating whether the incoming data stream is leading the feedback signal, or whether the feedback signal is leading the incoming data stream; digitally filtering the first polarity signal and the second polarity signal by:\n digitally filtering the first polarity signal such that the filtered first polarity signal is generated on a first path and a second path, the first and second paths being different; and \n digitally filtering the second polarity signal such that the filtered second polarity signal is generated on a third path and a fourth path, the third and fourth paths being different; \n generating an integral signal by integrating the filtered first polarity signal and the filtered second polarity signal,\n wherein integrating the filtered first polarity signal and the filtered second polarity signal to generate the integral signal comprises: integrating the first polarity signal from the second path and integrating the second polarity signal from the third path; and \n wherein generating the synthesized clock signal is based on the integral signal, the filtered first polarity signal from the first path, and the second polarity signal from the fourth path; and \n generating the synthesized clock signal based on the integral signal, the filtered first polarity signal, and the filtered second polarity signal, wherein the synthesized clock signal has a frequency that is controlled by the integral signal as well as the filtered first and second polarity signals, and wherein the synthesized clock signal serves as the feedback signal.

Metadata:
- Claim Count in Document: 46.0
- Percentile: 88.0
- Lexical Diversity: 2.50794
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15094374', '11190323', '11068127', '13275367', '13544001']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.495603424267683
- 35 USC 102 Novelty (BERT): 0.5473357608465322
- Combined Prediction Score: 0.5007766579255679
- Mean Citation Score: 240.25332000000003
- Max Citation Score: 406.5221
- Similarity Product: 333.0133490486205

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test