PATENT CLAIM ANALYSIS

Application Number: 15918432
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["714", "776000"]

Abstract:
This application discloses a data processing method and apparatus. The method includes: distributing, by a first distribution circuit, a first bit stream to FEC encoders  1  to N in a round robin fashion, where digital signals  1  to N that are output after being encoded by the FEC encoders  1  to N are in a one-to-one correspondence with a least significant bit to a most significant bit of an input signal of a PAM circuit, a coding gain G X  of an FEC encoder X is greater than a coding gain G Y  of an FEC encoder Y, 1≤X<Y≤N, N≥2, and X, Y, and N are all integers. In the method, different FEC coding gains can be provided for links with different bit error rates, so that a requirement of a high-rate Ethernet for a high gain during long-distance data transmission is met, and physical-layer resources occupied by FEC are reduced.

Claim (Index 21):
A data processing apparatus, comprising:\n a processing circuit comprising N subcircuits; a first data merging circuit; and a forward error correction (FEC) decoding circuit, wherein: the processing circuit is configured to respectively receive, by using the N subcircuits, N bit streams output by a pulse amplitude demodulation circuit, wherein:\n the N subcircuits are represented by subcircuits  1  to N, respectively, \n the N bit streams are represented by bit streams  1  to N, respectively, \n the bit streams  1  to N are in a one-to-one correspondence with a least significant bit to a most significant bit of an output signal of the pulse amplitude demodulation circuit, \n the subcircuits  1  to N are in a one-to-one correspondence with the bit streams  1  to N, \n L subcircuits of the N subcircuits are L FEC decoders, \n W subcircuits of the N subcircuits are W delayers, \n the L FEC decoders do not intersect with the W delayers, \n L+W=N, L\u22651, W\u22650, N\u22652, and \n L, W, and N are integers; \n the processing circuit is further configured to respectively process the bit streams  1  to N by using the subcircuits  1  to N, to obtain digital signals  1  to N, wherein the bit streams  1  to N are in a one-to-one correspondence with the digital signals  1  to N, the L FEC decoders perform FEC decoding on L input bit streams, respectively, to obtain L digital signals, and the W delayers perform delay processing on W input bit streams, respectively, to obtain W digital signals, wherein coding gains of the subcircuits  1  to N are represented by G 1  to G N , respectively, a coding gain of a subcircuit X is G X , a coding gain of a subcircuit Y is G Y , G X >G Y , 1\u2264X\u2264Y\u2264N, and X and Y are integers; the subcircuits  1  to N send the digital signals  1  to N to the first data merging circuit; the first data merging circuit is configured to merge the digital signals  1  to N into a serial first bit stream; and the FEC decoding circuit is configured to perform FEC decoding on the first bit stream, to obtain a second bit stream.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 90.0
- Lexical Diversity: 1.89888
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15789284', '15644350', '15476323', '15200930', '14536303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2513274492344923
- 35 USC 102 Novelty (BERT): 0.4995343461123714
- Combined Prediction Score: 0.2761481389222802
- Mean Citation Score: 200.285826
- Max Citation Score: 255.5279
- Similarity Product: 193.2169665175557

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test