PATENT CLAIM ANALYSIS

Application Number: 16287211
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "076000"]

Abstract:
A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

Claim (Index 1):
A transistor, comprising:\n a III-N layer structure comprising a III-N channel layer and a III-N barrier layer; a 2DEG channel in the III-N channel layer; a source and a drain; a gate between the source and the drain, the gate being over the III-N layer structure; and a graded III-N layer contacting the III-N barrier layer which is at least partially in an access region between the gate and the drain; wherein a grading profile of the graded III-N layer causes holes to be induced in at least a portion of the graded III-N layer without p-type dopants being included in the portion of the graded III-N layer; and the grading profile of the graded III-N layer is selected such that mobile charge in the 2DEG channel in an access region between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than a transistor threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the transistor threshold voltage and the drain is biased below the minimum voltage relative to the source.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 99.0
- Lexical Diversity: 3.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15564498', '15227240', '15836157', '14327371', '14262649']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90549275189712
- 35 USC 102 Novelty (BERT): 0.5646746544235328
- Combined Prediction Score: 0.8714109421497611
- Mean Citation Score: 323.874518
- Max Citation Score: 447.37366
- Similarity Product: 351.2614784312415

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test