PATENT CLAIM ANALYSIS

Application Number: 15937257
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["365", "148000"]

Abstract:
In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.

Claim (Index 8):
The memory circuit of  claim 7 , wherein the bias element is configured to apply the first non-zero bias voltage to the second bit-line concurrent to the word-line decoder applying the first read voltage to the word-line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.39024
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15425213', '15332371', '15836028', '15904963', '14240682']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8306411841358587
- 35 USC 102 Novelty (BERT): 0.5015067456181058
- Combined Prediction Score: 0.7977277402840834
- Mean Citation Score: 245.33510800000005
- Max Citation Score: 285.5029
- Similarity Product: 220.1788498306215

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test