PATENT CLAIM ANALYSIS

Application Number: 15939288
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["257", "737000"]

Abstract:
A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer.

Claim (Index 16):
The method according to  claim 9 , wherein the molding compound is formed to cover backside surfaces of the first semiconductor die and the second semiconductor die.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 3.15556
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15716506', '15841331', '13112172', '15806347', '12949396']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9225537680494968
- 35 USC 102 Novelty (BERT): 0.4823203981199943
- Combined Prediction Score: 0.8785304310565465
- Mean Citation Score: 196.025222
- Max Citation Score: 203.83536
- Similarity Product: 155.99615590307238

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test