PATENT CLAIM ANALYSIS

Application Number: 15919761
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "369000"]

Abstract:
A method for manufacturing a semiconductor device includes forming a circuit including a plurality of flip-flops, a plurality of first switches, a second switch and a signal line on a wafer, the flip-flops being connected in series through the first switches, respectively, and the signal line being connected to the second switch, and being configured to supply a signal in parallel to the flip-flops; testing the flip-flops by turning off the first switches, turning on the second switch, and supplying a test signal in parallel through the signal line to the flip-flops; and cutting at least one interconnect of a switch portion in the circuit, the switch portion including the first switches and the second switch, so that the first switch is turned on and the second switch is turned off.

Claim (Index 10):
The device according to  claim 8 , further comprising:\n a logical sum gate provided between adjacent ones of the flip-flops, an output of the first switch and the signal being inputted to the logical sum gate, and an output of the logical sum gate being inputted to one of the adjacent ones of the flip-flops.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 90.0
- Lexical Diversity: 2.71698
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12400948', '10921854', '10702077', '11457198', '11320751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9079137201544032
- 35 USC 102 Novelty (BERT): 0.4784857192306322
- Combined Prediction Score: 0.8649709200620262
- Mean Citation Score: 165.087228
- Max Citation Score: 173.88846999999996
- Similarity Product: 124.4790243907934

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test