PATENT CLAIM ANALYSIS

Application Number: 15989593
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["714", "726000"]

Abstract:
According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.

Claim (Index 6):
The device of  claim 1 , further comprising:\n a pattern generator configured to generate the test patterns, and serially output the test patterns to the scan chains.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.84783
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15056488', '10194377', '11683759', '10410283', '13284130']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.303588556076683
- 35 USC 102 Novelty (BERT): 0.5033625863518219
- Combined Prediction Score: 0.3235659591041969
- Mean Citation Score: 198.59618
- Max Citation Score: 276.38962000000004
- Similarity Product: 202.11308583246708

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test