PATENT CLAIM ANALYSIS

Application Number: 15942760
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "532000"]

Abstract:
The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has a lower interconnect layer vertically separated from a substrate by a first inter-level dielectric (ILD) layer. A conductive contact extends from a transistor device within the substrate to an uppermost surface of the first ILD layer. A plurality of MIM (metal-insulator-metal) structures are arranged over the lower interconnect layer. An upper interconnect layer is over the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.

Claim (Index 6):
The integrated chip of  claim 5 ,\n wherein the lower interconnect layer comprises a second interconnect structure separated from the first interconnect structure by the first ILD layer; and wherein the second interconnect structure is directly below a third MIM structure of the plurality of MIM structures.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 1.83824
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15418904', '14883808', '14249513', '14249482', '14289739']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927542691259457
- 35 USC 102 Novelty (BERT): 0.5250412402064095
- Combined Prediction Score: 0.8872925461541523
- Mean Citation Score: 262.950558
- Max Citation Score: 330.69165
- Similarity Product: 236.59810730616152

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test