PATENT CLAIM ANALYSIS

Application Number: 16141285
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["712", "215000"]

Abstract:
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Claim (Index 7):
The circuit arrangement of  claim 6 , wherein the first issue logic circuit is configured to issue an instruction queued in a particular queue position only when the bits in the ready and allow issue registers corresponding to the particular queue position are asserted, and wherein the first issue logic circuit is configured to defer asserting the bit in the allow issue register corresponding to a position of the multi-width instruction until the second issue cycle to cause the first portion of the multi-width instruction to be issued for execution by the first execution slice in the second issue cycle.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 1.5
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15939367', '15093192', '14595549', '16048946', '15093172']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6567657958100591
- 35 USC 102 Novelty (BERT): 0.5632040687739995
- Combined Prediction Score: 0.6474096231064531
- Mean Citation Score: 354.655344
- Max Citation Score: 439.212
- Similarity Product: 434.66042744135865

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test