PATENT CLAIM ANALYSIS

Application Number: 16148214
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "077000"]

Abstract:
A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.

Claim (Index 16):
The transistor device according to  claim 14 , wherein a body of the transistor device comprises silicon carbide.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 2.43103
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13730068', '13730133', '11952447', '13167806', '13482311']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9308727304102484
- 35 USC 102 Novelty (BERT): 0.5470447038846085
- Combined Prediction Score: 0.8924899277576843
- Mean Citation Score: 308.49285
- Max Citation Score: 406.2358
- Similarity Product: 326.44303115608693

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test