PATENT CLAIM ANALYSIS

Application Number: 15912450
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["714", "747000"]

Abstract:
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

Claim (Index 33):
The apparatus of  claim 31 , wherein the logic of the memory controller is further to:\n perform error correction for the data read from the cache line including the substitute data in response to determining that the cache line includes the error; and determine whether the error correction corrected the read data from the cache line including the substitute data, wherein the data read from the cache line including the substitute data that is returned includes error corrected data in response to the error correction correcting the error.

Metadata:
- Claim Count in Document: 77.0
- Percentile: 90.0
- Lexical Diversity: 1.84211
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14757905', '14497834', '14396327', '11508758', '15875136']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2647364436426465
- 35 USC 102 Novelty (BERT): 0.5170982034776802
- Combined Prediction Score: 0.2899726196261499
- Mean Citation Score: 185.915798
- Max Citation Score: 301.5376
- Similarity Product: 225.62878259410857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test