PATENT CLAIM ANALYSIS

Application Number: 15927044
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "230010"]

Abstract:
A circuit includes a data line, a first cell in a first row of a memory array, and a second cell in a second row of the memory array. The first cell is electrically coupled with the data line and the second cell is electrically coupled with the data line. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a first read operation on the first row.

Claim (Index 7):
The circuit of  claim 6 , wherein\n the first voltage level is a ground reference level of the memory array, and each of the first node and the second node is a ground node configured to carry the ground reference level.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.70968
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13273705', '14995387', '13489055', '14958149', '11476023']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7999118166608147
- 35 USC 102 Novelty (BERT): 0.4658164345503653
- Combined Prediction Score: 0.7665022784497698
- Mean Citation Score: 162.932648
- Max Citation Score: 165.30700000000004
- Similarity Product: 123.41109755253795

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test