PATENT CLAIM ANALYSIS

Application Number: 15742041
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["345", "208000"]

Abstract:
The invention provides a GOA circuit, comprising a plurality of cascaded GOA units. Each GOA unit comprises: a pull up control module, an output module, a pull down module and a pull down maintenance module; for N-th GOA unit: the 41 st  TFT of pull down module having a gate receiving a scan signal from (N+4)-th GOA unit, a source connected to a circuit start signal, and a drain connected to the first node, and the circuit start signal having a low voltage level lower than or equal to 0V and higher than the low voltage signal; so that when the scan signal from (N+4)-th GOA unit changing from high voltage to low voltage, the gate-source voltage difference of the 41 st  TFT being negative to effectively reduce the current leakage and prevent the current leakage from affecting the first node voltage, improve circuit stability, facilitate cost reduction and narrow border.

Claim (Index 2):
The GOA circuit as claimed in  claim 1 , wherein the clock signal comprises:\n a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eight clock signal, outputted serially; for a non-negative integer X, the (1+8X)-th GOA unit, the (2+8X)-th GOA unit, the (3+8X)-th GOA unit, the (4+8X)-th GOA unit, the (5+8X)-th GOA unit, the (6+8X)-th GOA unit, the (7+8X)-th GOA unit, and the (8+8X)-th GOA unit respectively receive the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal, the seventh clock signal, and the eight clock signal; two adjacent clock signals have rising edges with a gap of \u215b of cycle of the clock signal, the clock signal has a duty cycle ratio of 0.4; the circuit start signal has a high voltage duration equal to \u00be of the cycle of the clocks signal; the circuit start signal has a rising edge earlier than the rising edge of the first clock signal, with a gap of \u00bc of the cycle of the clocks signal.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 2.12346
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15742886', '15742037', '15742036', '15128420', '15579947']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7216347040358938
- 35 USC 102 Novelty (BERT): 0.6266805884680595
- Combined Prediction Score: 0.7121392924791103
- Mean Citation Score: 477.924164
- Max Citation Score: 553.6039
- Similarity Product: 550.4329193329928

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test