PATENT CLAIM ANALYSIS

Application Number: 16123915
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["716", "108000"]

Abstract:
A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

Claim (Index 1):
A system comprising:\n an emulator configured to emulate a design under test (DUT) for fabrication, and configured to trace waveforms of signals of the DUT for a time frame including a plurality of clock cycles; and a host system communicatively coupled to the emulator through an interface, the host system comprising:\n a section module configured to determine a logic gate from a plurality of logic gates to be evaluated based on the waveforms of the signals of the DUT traced by the emulator, the plurality of logic gates comprising logic gates included in the DUT; \n a simulation module configured to:\n simulate one or more logic gates coupled to an input signal of the logic gate for a first duration of the time frame, \n omit simulation of the one or more logic gates for a second duration of the time frame, and \n generate an output waveform of an output signal of the logic gate for the time frame based on the simulation of the one or more logic gates for the first duration, the output signal of the logic gate not traced by the emulator; and \n \n a results module configured to display the output waveform for verifying the DUT prior to fabricating the DUT.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.49123
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15278659', '14745239', '15007040', '14507696', '15447010']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3025570714155573
- 35 USC 102 Novelty (BERT): 0.5121950957001359
- Combined Prediction Score: 0.3235208738440152
- Mean Citation Score: 235.627084
- Max Citation Score: 346.1858
- Similarity Product: 303.2855602748394

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test