PATENT CLAIM ANALYSIS

Application Number: 15892734
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "348000"]

Abstract:
A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.

Claim (Index 10):
The circuit structure according to  claim 9 , comprising at least a first clock line and a separate second clock line for independently providing a higher-frequency clock signal and a lower-frequency clock signal to said higher-frequency operating circuit block and said slower-frequency operating circuit block, respectively.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.15385
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13450004', '11865780', '12172919', '15676907', '13501902']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9076424913244416
- 35 USC 102 Novelty (BERT): 0.4809759527091952
- Combined Prediction Score: 0.864975837462917
- Mean Citation Score: 163.235536
- Max Citation Score: 170.60858000000005
- Similarity Product: 118.38338002316716

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test