PATENT CLAIM ANALYSIS

Application Number: 15945665
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "048000"]

Abstract:
Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.

Claim (Index 7):
A method, comprising:\n fabricating a plurality of integrated circuit chips on a silicon wafer using mask data and a semiconductor manufacturing process; and fabricating a plurality of scribe regions situated between ones of the plurality of integrated circuit chips on the silicon wafer using the semiconductor manufacturing process, wherein fabricating the plurality of scribe regions includes, depositing a material on a particular layer of a plurality of layers in a particular scribe region of the plurality of scribe regions, wherein a coefficient of thermal expansion of the material is greater than a coefficient of thermal expansion of the silicon wafer, and wherein a collective area of the material at the particular layer is at least 40 percent of an area of the particular scribe region.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 1.77083
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14134328', '13847964', '13160713', '15168479', '13917568']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8943457421972101
- 35 USC 102 Novelty (BERT): 0.4695836411176494
- Combined Prediction Score: 0.851869532089254
- Mean Citation Score: 162.92896199999996
- Max Citation Score: 165.29288
- Similarity Product: 132.04736003149986

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test