PATENT CLAIM ANALYSIS

Application Number: 15978235
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["326", "039000"]

Abstract:
An integrated circuit comprising a first memory array and programmable/configurable logic circuitry including a plurality of logic tiles wherein each logic tile includes a perimeter, a plurality of external I/O disposed in an I/O layout on the perimeter, wherein the I/O layout of each tile is identical. Each external I/O is configurable as an external I/O to connect to and communicate with external circuitry, or a memory I/O to point-to-point connect to memory located adjacent thereto, or an unused I/O. The first memory array is physically adjacent to a first logic tile on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and point-to-point connected to the memory I/O. In operation, circuitry of the first logic tile is configured to read data from and write data to the first memory array via the memory I/O.

Claim (Index 9):
The integrated circuit of  claim 8  further including:\n a second plurality of memory arrays, wherein at least one memory array of the second plurality of memory arrays is (i) physically located between each logic tile of successive columns of logic tiles and (i) associated with at least one logic tile of a column of the successive columns; and \n wherein:\n each memory array of the second plurality of memory array is (i) physically located adjacent a second portion of the perimeter of the associated logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and (ii) point-to-point connected to the memory I/O located on a second portion of the perimeter of the associated logic tile, and \n the circuitry of each logic tile which is electrically coupled to the memory I/O located on the second portion of the perimeter of the logic tile is configured to read data from and write data to the associated memory array of the second plurality of memory arrays during operation of the programmable/configurable logic circuitry.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 93.0
- Lexical Diversity: 2.59016
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15239958', '15975037', '14972553', '14712864', '15347045']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7442674645885466
- 35 USC 102 Novelty (BERT): 0.5790780584069192
- Combined Prediction Score: 0.7277485239703839
- Mean Citation Score: 390.231684
- Max Citation Score: 530.7966
- Similarity Product: 409.0183616443634

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test