PATENT CLAIM ANALYSIS

Application Number: 16226911
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer.

Claim (Index 5):
The semiconductor device of  claim 1 , wherein the source/drain material comprises SiGe with a Ge content higher than a Ge content of the semiconductor substrate.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.45652
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15466382', '15474147', '15331331', '15272977', '15466358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9406033221282634
- 35 USC 102 Novelty (BERT): 0.6151608725413242
- Combined Prediction Score: 0.9080590771695696
- Mean Citation Score: 406.454078
- Max Citation Score: 553.8413
- Similarity Product: 523.1391725328507

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test