PATENT CLAIM ANALYSIS

Application Number: 15990538
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["327", "203000"]

Abstract:
A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Claim (Index 16):
The flip-flop of  claim 13 , wherein the sixth plurality of switch elements are arranged to provide a NAND operation, and wherein the first clock signal is generated in response to the second clock signal and a retention signal.

Metadata:
- Claim Count in Document: 54.0
- Percentile: 93.0
- Lexical Diversity: 3.70732
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15336721', '14154757', '14622531', '15417339', '14613414']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8237340721649664
- 35 USC 102 Novelty (BERT): 0.5673030888253954
- Combined Prediction Score: 0.7980909738310092
- Mean Citation Score: 367.026586
- Max Citation Score: 467.13037
- Similarity Product: 403.57595328404665

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test