PATENT CLAIM ANALYSIS

Application Number: 15869726
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["323", "235000"]

Abstract:
A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Claim (Index 1):
A switch-mode power converter comprising:\n a bridge node having a bridge voltage; a first switch having a first input and a first output, the first input having a power converter input voltage, the first output electrically connected to the bridge node, the first switch having a closed state in which the first input is electrically connected to the first output and an open state in which the first input is not electrically connected to the first output; a second switch having a second input and a second output, the second input electrically connected to the bridge node, the second output electrically connected to a second voltage, the second voltage lower than the power converter input voltage, the second switch having a closed state in which the second input is electrically connected to the second output and an open state in which the second input is not electrically connected to the second output; a logic circuit in electrical communication with the first and second switches, the logic circuit controlling a respective state of the first and second switches such that the first switch is in the open state when the second switch is in the closed state and the second switch is in the open state when the first switch is in the closed state; an LC circuit in electrical communication with the bridge node and a power converter load, the power converter load receiving an output current at a power converter output voltage, the power converter output voltage lower than the a PWM and frequency control circuit configured to control (a) a ratio of times that the first and second switches are in respective closed states to control the power converter output voltage (b) a switching frequency of the first and second switches; a first delay feedback circuit configured to control a low-to-high delay time between an open time of said second switch and a close time of said first switch; and a second delay feedback circuit configured to control a high-to-low delay time between an open time of said first switch and a close time of said second switch.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.72727
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15243022', '11342489', '11027411', '15399335', '10668459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7267367879096696
- 35 USC 102 Novelty (BERT): 0.5365311187293152
- Combined Prediction Score: 0.7077162209916341
- Mean Citation Score: 251.844444
- Max Citation Score: 389.33008
- Similarity Product: 371.2368489916707

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test