PATENT CLAIM ANALYSIS

Application Number: 16122800
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["365", "185180"]

Abstract:
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.

Claim (Index 13):
A method of operating a memory cell, the memory cell comprising a semiconductor substrate; a control gate; a floating gate having a first floating gate portion disposed in a trench in the substrate and a second floating gate portion extending away from the substrate, the second floating gate portion being electrically connected to the first floating gate portion on a first end and having a tip on a second end; an insulation region disposed between the control gate and the second floating gate portion; a source line adjacent to and insulated from the floating gate; and an erase gate insulated from and disposed over the tip of the second floating gate portion; the method comprising erasing the memory cell by:\n applying a first bias potential to the control gate and the source line; and applying a second bias potential to the erase gate, inducing tunneling of electrons from the tip of the second floating gate portion to the erase gate, wherein a capacitive coupling between the floating gate and the source line substantially limits changes in potential of the floating gate caused by capacitive coupling between the floating gate and the erase gate; wherein a difference between the second bias potential and the first bias potential is no greater than 10 volts.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 2.95745
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10934246', '10872052', '10757830', '11166882', '10358601']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7838543673837846
- 35 USC 102 Novelty (BERT): 0.4850334384961643
- Combined Prediction Score: 0.7539722744950226
- Mean Citation Score: 252.180154
- Max Citation Score: 254.52812000000003
- Similarity Product: 221.3669176134777

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test