PATENT CLAIM ANALYSIS

Application Number: 16122466
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2018-12
Patent Classification: ["714", "776000"]

Abstract:
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Claim (Index 1):
A transmitting method for transmitting a codeword generated based on a low-density parity check coding scheme, the parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure, the parity bits of the codeword being interleaved, the transmitting method comprising:\n a bit group permutation step of applying a bit group permutation process to a codeword made up of N bit groups each consisting of Q bits, to reorder the bit groups in accordance with a bit group permutation rule defining a reordering of the bit groups; a bit permutation step of applying a bit permutation process to the codeword after the bit group permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits; a modulating step of mapping each of the constellation words to a modulated signal; and a transmitting step of transmitting a transmitting signal generated from the modulated signal, wherein N is a multiple of M, the bit permutation rule defines the reordering of the bits of the codeword after the bit group permutation process, the reordering of the bit permutation rule being equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N bit groups being written into a matrix row-by-row during the writing process, the written bits being read out from the matrix column-by-column during the reading process, the matrix having M rows, the Q bits included in one bit group being written into a same row sequentially.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.0
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15388192', '15711202', '16117625', '15581148', '15335501']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5063977173892228
- 35 USC 102 Novelty (BERT): 0.680806186026436
- Combined Prediction Score: 0.5238385642529442
- Mean Citation Score: 725.76369
- Max Citation Score: 731.9698
- Similarity Product: 684.2653721117974

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test