PATENT CLAIM ANALYSIS

Application Number: 15939307
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["438", "107000"]

Abstract:
A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.

Claim (Index 11):
The method of  claim 10 , wherein the plurality of remnants cover edges of the plurality of dies and a portion of the top surface of the body part.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.39535
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15874893', '15662279', '15706783', '15717974', '15905756']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8619229200264698
- 35 USC 102 Novelty (BERT): 0.5048044794674648
- Combined Prediction Score: 0.8262110759705692
- Mean Citation Score: 180.161332
- Max Citation Score: 215.95485
- Similarity Product: 133.42219610922038

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test