PATENT CLAIM ANALYSIS

Application Number: 15912177
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "774000"]

Abstract:
An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Claim (Index 16):
The integrated circuit of  claim 8 , wherein a top surface of the second metal feature and a top surface of the second dielectric layer are coplanar.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.12121
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14970242', '11842821', '14314945', '11933931', '14523256']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9103672338001246
- 35 USC 102 Novelty (BERT): 0.4836887245719376
- Combined Prediction Score: 0.867699382877306
- Mean Citation Score: 140.719216
- Max Citation Score: 174.05199
- Similarity Product: 123.45568538752912

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test