PATENT CLAIM ANALYSIS

Application Number: 15984803
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-04
Patent Classification: ["365", "230030"]

Abstract:
Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.

Claim (Index 7):
A package device, comprising:\n a plurality of memory chips, each including memory blocks to which different chip addresses are stored, and enable input pads and enable output pads to which signals for indicating input states of the chip addresses are applied, wherein each of the memory chips includes any one of the enable input pads, and any one of the enable output pads, wherein the enable input pad included in each of the memory chips is coupled to the enable output pad of a corresponding one of the other memory chips, and wherein, in response to signals applied to the enable input pads and the enable output pads, the chip addresses are successively inputted to the memory chips.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 93.0
- Lexical Diversity: 1.90476
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10727150', '12270292', '13718222', '11508176', '14174435']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7883449214466709
- 35 USC 102 Novelty (BERT): 0.4597926074955856
- Combined Prediction Score: 0.7554896900515624
- Mean Citation Score: 183.020116
- Max Citation Score: 184.95575
- Similarity Product: 150.21187879005075

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test