PATENT CLAIM ANALYSIS

Application Number: 16009196
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "024000"]

Abstract:
A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.

Claim (Index 15):
A semiconductor fabrication system comprising a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processors via the memories, the stored program instructions causing the fabrication system to perform operations comprising:\n forming a nanosheet stack comprising a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet; forming a gate formed in a direction orthogonal to the plane of the nanosheet stack, a gate spacer positioned along a sidewall of the gate; and forming an inner spacer liner deposited around the nanosheet stack and the gate spacer,\n wherein a first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet, \n wherein a second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet, and \n wherein following the second etching, a third etching is configured to remove the material of the inner spacer liner from a top surface and a bottom surface adjacent to the edge of the channel nanosheet.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.56897
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15260509', '15690601', '15465989', '15880757', '15967524']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91354910254111
- 35 USC 102 Novelty (BERT): 0.5275024825123203
- Combined Prediction Score: 0.8749444405382312
- Mean Citation Score: 299.410214
- Max Citation Score: 307.86075
- Similarity Product: 182.88619855767487

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test