PATENT CLAIM ANALYSIS

Application Number: 16021869
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-07
Patent Classification: ["323", "268000"]

Abstract:
A digital regulator includes a voltage comparison circuit, a counter, a decoder and a switch circuit. At an initialization phase, the voltage comparison circuit is configured to compare the reference voltage signal and a first signal to output a first level signal, and the counter is configured to initialize and output an initialization signal as a control signal according to the first level signal. At an operation phase, the voltage comparison circuit is configured to compare the reference voltage signal and an output terminal of the switch circuit to output a second level signal, and the counter is configured to count according to the second level signal and output the control signal. The decoder is configured to turn on the plurality of switch units according to the control signal from the counter.

Claim (Index 4):
The digital regulator according to  claim 1 , wherein the voltage comparison circuit comprises a first voltage comparator, a second voltage comparator, a third voltage comparator and a fourth voltage comparator, the input terminal of the counter comprises a first input terminal, a second input terminal, and a third input terminal, and the third voltage comparator and the fourth voltage comparator have enabling terminals;\n wherein an output terminal of the first voltage comparator is electrically coupled to the first input terminal of the counter, and the output terminal of the switch circuit is electrically coupled to a first input terminal of the first voltage comparator; and wherein an output terminal of the second voltage comparator is electrically coupled to the enabling terminals of the third voltage comparator and the fourth voltage comparator, and a first input terminal of the second voltage comparator receives a first signal; and wherein an output terminal of the third voltage comparator is electrically coupled to the second input terminal of the counter, and a first input terminal of the third voltage comparator receives a second signal; and wherein an output terminal of the fourth voltage comparator is electrically coupled to the third input terminal of the counter, and a first input terminal of the fourth voltage comparator receives a third signal; and wherein second input terminals of the first voltage comparator, the second voltage comparator, the third voltage comparator, and the fourth voltage comparator are electrically coupled and receive the reference voltage signal; and wherein the second voltage comparator is configured to compare the reference voltage signal with the first signal and output an enabling signal; and wherein the enabling terminal of the third voltage comparator receives the enabling signal, and in response to the enabling signal being active, compares the reference voltage signal with the second signal and outputs the first level signal; and wherein the enabling terminal of the fourth voltage comparator receives the enabling signal, and in response to the enabling signal being active, compares the reference voltage signal with the third signal and outputs the first level signal; and wherein the first voltage comparator is configured to compare the reference voltage signal with the output voltage of the switch circuit and output the second level signal, wherein the enabling signal is not active for the third voltage comparator and the fourth voltage comparator at the same time.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 3.30233
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15984313', '15995629', '15435519', '15423456', '11293319']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.749766293922856
- 35 USC 102 Novelty (BERT): 0.4691490275629933
- Combined Prediction Score: 0.7217045672868698
- Mean Citation Score: 197.363422
- Max Citation Score: 205.7864
- Similarity Product: 170.88652094964982

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test