PATENT CLAIM ANALYSIS

Application Number: 15878450
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["711", "140000"]

Abstract:
Improving operation of a processing unit to access data within a cache system. A first fetch request and one or more subsequent fetch requests are accessed in an instruction stream. An address of data sought by the first fetch requested is obtained. At least a portion of the address of data sought by the first fetch request in inserted in each of the one or more subsequent fetch requests. The portion of the address inserted in each of the one or more subsequent fetch requests is utilized to retrieve the data sought by the first fetch request first in order from the cache system.

Claim (Index 1):
A method of improving operation of a processing unit to access data within a cache system, the method comprising:\n receiving by a processing unit a stream of pipelined instructions including one or more fetch requests seeking data from a multilevel cache or system memory; breaking up by the processing unit the stream of pipelined instructions during execution into multiple independent fetch requests including a first fetch request and one or more subsequent fetch requests each seeking data existing in different levels of the multilevel level cache system or system memory; accessing by the processing unit the first fetch request and one or more subsequent fetch requests; obtaining by the processing unit a memory address of data sought by the first fetch request, the obtained memory address a logical address where the data is located in the multilevel level cache system or system memory; inserting low order bits of the memory address of data sought from the cache system or main system memory by the first fetch request in each of the one or more subsequent fetch requests seeking data located in the cache system or main system memory; determining, by accessing a first level cache directory indicating data present in the first level cache, that data sought by the first fetch request is not found in the first level cache of the multilevel level cache system; attempting to access a translation look aside buffer providing access to information residing in a higher cache level of the multilevel cache system higher than the first level cache to determine an absolute address or a physical address of the data sought in a higher level cache or system memory, the attempt to access the translation look aside buffer failing to arbitrate access; and utilizing the low order bits portion of the memory address inserted in each of the one or more subsequent fetch requests in place of the memory address contained within each of the one or more subsequent fetch requests to retrieve the data sought by the first fetch request.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.31915
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15649990', '14325343', '10449825', '11780283', '11711925']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4520519971182672
- 35 USC 102 Novelty (BERT): 0.5342941427512883
- Combined Prediction Score: 0.4602762116815693
- Mean Citation Score: 204.284712
- Max Citation Score: 358.94897000000014
- Similarity Product: 298.72284943016115

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test