PATENT CLAIM ANALYSIS

Application Number: 15917183
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["257", "194000"]

Abstract:
Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.

Claim (Index 1):
A semiconductor device comprising:\n a doped semiconductor layer doped with first conductivity type impurities; a channel pattern including a first semiconductor region and a second semiconductor region, wherein the first semiconductor region encloses a sidewall of the doped semiconductor layer, wherein the second semiconductor region is disposed between the first semiconductor region and the doped semiconductor layer, and wherein the second semiconductor region is formed of semiconductor material that is different from semiconductor material from which the first semiconductor region is formed; and a first select gate enclosing a portion of the first semiconductor region overlapping the second semiconductor region.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.71875
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15865669', '13892756', '14757572', '15284067', '15235864']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.911955492879482
- 35 USC 102 Novelty (BERT): 0.4855702516791642
- Combined Prediction Score: 0.8693169687594501
- Mean Citation Score: 189.479004
- Max Citation Score: 205.26147
- Similarity Product: 149.05121105857373

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test