PATENT CLAIM ANALYSIS

Application Number: 16179432
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "675000"]

Abstract:
A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

Claim (Index 3):
The method of  claim 1 , wherein the ultrasonic weld is formed by clamping the DBC substrate and the at least one lead together with not more than about 0.05 Mpa.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13874479', '12771643', '14556940', '14622869', '14144587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9127046262419892
- 35 USC 102 Novelty (BERT): 0.5120938708544274
- Combined Prediction Score: 0.872643550703233
- Mean Citation Score: 232.363312
- Max Citation Score: 236.0787
- Similarity Product: 151.824497028172

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test