PATENT CLAIM ANALYSIS

Application Number: 15868232
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["327", "175000"]

Abstract:
Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

Claim (Index 18):
The method of  claim 17 , wherein the bitwise comparisons use XOR logic.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 2.88235
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13870893', '15812797', '14955051', '11360093', '13451131']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7825885408541761
- 35 USC 102 Novelty (BERT): 0.4643277087522123
- Combined Prediction Score: 0.7507624576439798
- Mean Citation Score: 151.31371600000003
- Max Citation Score: 156.36375
- Similarity Product: 118.020472683236

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test