PATENT CLAIM ANALYSIS

Application Number: 15901881
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["365", "185110"]

Abstract:
A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.

Claim (Index 1):
A semiconductor storage device comprising:\n a memory cell array that includes first to sixth memory cells; first to third bit lines that are respectively connected to the first to third memory cells and are disposed in sequence in a first direction; fourth to sixth bit lines that are respectively connected to the fourth to sixth memory cells and are disposed in sequence in the first direction; a sense amplifier that includes first to sixth sense circuits respectively connected to the first to sixth bit lines and in which the first and fourth sense circuits are arranged along a second direction crossing the first direction, the second and fifth sense circuits are arranged along the second direction, and the third and sixth sense circuits are arranged along the second direction; a data register that includes first to sixth latch circuits respectively connected to the first to sixth sense circuits and in which the first and fourth latch circuits are connected to the first and fourth sense circuits via a first bus, the second and fifth latch circuits are connected to the second and fifth sense circuits via a second bus, and the third and sixth latch circuits are connected to the third and sixth sense circuits via a third bus; and an input and output circuit that is connected to the first and fourth latch circuits via a first data line, is connected to the second and fifth latch circuits via a second data line, and is connected to the third and sixth latch circuits via a third data line.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 88.0
- Lexical Diversity: 3.15217
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14013833', '15411225', '15405098', '14014252', '15439912']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7689839280401016
- 35 USC 102 Novelty (BERT): 0.478054321093754
- Combined Prediction Score: 0.7398909673454669
- Mean Citation Score: 222.74659000000003
- Max Citation Score: 225.74733
- Similarity Product: 188.75555997374832

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test