PATENT CLAIM ANALYSIS

Application Number: 15942639
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "405000"]

Abstract:
Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

Claim (Index 9):
The semiconductor device of  claim 8 , wherein the first active area comprises a first source/drain region, wherein the second active area comprises a second source/drain region, and wherein the first dielectric layer extends immediately below the second source/drain region.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.42105
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13616194', '12618505', '11789616', '15089914', '10999564']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8757712297845127
- 35 USC 102 Novelty (BERT): 0.5141994641374953
- Combined Prediction Score: 0.8396140532198111
- Mean Citation Score: 217.0803
- Max Citation Score: 299.61874
- Similarity Product: 220.3979362636924

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test