PATENT CLAIM ANALYSIS

Application Number: 15886630
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "189160"]

Abstract:
Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Claim (Index 19):
The integrated circuit of  claim 18 , wherein the one or more circuit components comprise one or more transistors and one or more logic gates that are arranged to receive the control signal, sense the write operations based on the control signal, and drive the write operations for the array of bitcells.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.43182
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15256200', '15477516', '15188873', '15490352', '15789715']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8239183835389956
- 35 USC 102 Novelty (BERT): 0.4979891482322395
- Combined Prediction Score: 0.79132546000832
- Mean Citation Score: 253.10452200000003
- Max Citation Score: 290.51584
- Similarity Product: 239.9705441886139

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test