PATENT CLAIM ANALYSIS

Application Number: 16007598
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["365", "163000"]

Abstract:
A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.

Claim (Index 18):
The operating method of  claim 17 , wherein the giving of the weighting to each of the line counting signal and the block counting signal is carried out to set the weighting given to the block counting signal to be greater than the weighting given to the line counting signal.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 94.0
- Lexical Diversity: 2.2037
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16007659', '13966274', '15628840', '15298065', '10081652']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8069932755224766
- 35 USC 102 Novelty (BERT): 0.500378124808843
- Combined Prediction Score: 0.7763317604511133
- Mean Citation Score: 207.708122
- Max Citation Score: 270.92398
- Similarity Product: 193.51745615178825

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test