PATENT CLAIM ANALYSIS

Application Number: 15765214
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["345", "100000"]

Abstract:
There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

Claim (Index 16):
The driving method according to  claim 15 , wherein the pull-up node control circuit comprises:\n a first transistor, whose gate and first electrode are connected to the first power supply voltage terminal; a first capacitor, whose first terminal is connected to a second electrode of the first transistor, and second terminal is connected to the third power supply voltage terminal; and a second transistor, whose gate is connected to the first terminal of the first capacitor, first electrode is connected to the pull-up node, and second electrode is connected to the third power supply voltage terminal, wherein when the first power supply voltage terminal jumps from the first level to the second level, the first transistor is turned on to charge the first capacitor, and the second transistor is turned on to discharge the pull-up node through the third power supply voltage terminal; and when the first power supply voltage terminal further jumps from the second level to a zero voltage, the first capacitor makes the second transistor maintain turned on and continuously discharges the pull-up node through the third power supply voltage terminal.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 90.0
- Lexical Diversity: 3.57778
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15928353', '16066827', '15327852', '15532343', '15522368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7293991438054475
- 35 USC 102 Novelty (BERT): 0.5275863124731884
- Combined Prediction Score: 0.7092178606722216
- Mean Citation Score: 347.327194
- Max Citation Score: 355.60516
- Similarity Product: 283.44162078822137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test