PATENT CLAIM ANALYSIS

Application Number: 15956414
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-01
Patent Classification: ["438", "126000"]

Abstract:
A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.

Claim (Index 1):
A method of manufacturing a semiconductor package comprising:\n attaching a plurality of first conductive bumps to respective first conductive pads provided on an upper surface of a first substrate; providing an interposer with a plurality of second conductive bumps attached to respective second conductive pads on a bottom surface of the interposer; flip chip mounting a first semiconductor chip to the first substrate including electrically connecting the first semiconductor chip to third conductive pads provided on the upper surface of the first substrate; forming an insulative mold layer on the upper surface of the first substrate to cover and surround the first conductive bumps, the insulative mold layer extending along sidewalls of the first semiconductor chip and having an upper surface at least as high as an upper surface of the first semiconductor chip; etching the mold layer to provide a recess in the mold layer, to define upwardly extending protrusions formed of the etched mold layer and to expose the first conductive bumps; placing the interposer on the first substrate so that each of the plurality of second conductive bumps on the bottom surface of the interposer are in contact with a corresponding one of the plurality of first conductive bumps to provide a plurality of contacting pairs of first conductive bumps and second conductive bumps, and so that the bottom surface of the interposer is in contact with upper surfaces of the protrusions; performing a reflow process to merge each of the contacting pairs of the first conductive bumps and the second conductive bumps to form a plurality of conductive connection members, each conductive connection member extending between a corresponding first conductive pad on the upper surface of the first substrate and a corresponding second conductive pad on the bottom surface of the interposer; flowing an under-fill resin in a space between the interposer and the first substrate to surround and encapsulate the conductive connection members; and cutting the first substrate to form the semiconductor package, the semiconductor package including the first semiconductor chip and at least portions of the protrusions in contact with the interposer.

Metadata:
- Claim Count in Document: 46.0
- Percentile: 91.0
- Lexical Diversity: 2.32468
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14457094', '10184340', '15818346', '14514360', '10706576']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8662447036721872
- 35 USC 102 Novelty (BERT): 0.493460846165597
- Combined Prediction Score: 0.8289663179215283
- Mean Citation Score: 249.71133
- Max Citation Score: 264.07104
- Similarity Product: 219.8003684867477

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test