PATENT CLAIM ANALYSIS

Application Number: 15911180
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "777000"]

Abstract:
The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

Claim (Index 6):
The method of forming package structure according to  claim 1 , wherein the package step comprises forming an underfill layer between the wafer and the array chip.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.02703
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14287065', '15677339', '14323960', '14103411', '13280368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921418212835498
- 35 USC 102 Novelty (BERT): 0.4952380572992966
- Combined Prediction Score: 0.8788001972818777
- Mean Citation Score: 184.131426
- Max Citation Score: 220.267
- Similarity Product: 154.214770105958

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test