PATENT CLAIM ANALYSIS

Application Number: 15909404
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["365", "185030"]

Abstract:
A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.

Claim (Index 9):
A semiconductor memory device, comprising:\n a plurality of memory cells that store first data values for multiple bits according to a first threshold voltage and second data values for the multiple bits according to a second threshold voltage higher than the first threshold voltage; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells, each memory cell being respectively connected to one word line and one bit line; a plurality of sense amplifier units respectively connected to the plurality of bit lines, each sense amplifier unit including include a first latch circuit and configured to apply a voltage to the respective bit line according to data stored in the first latch circuit; and a controller configured to write data to the plurality of memory cells in a write operation including a program loop with a verification operation followed by a program operation, wherein the controller is configured to, during the verification operation: store data corresponding to a first logic level in a first latch circuit of a sense amplifier unit corresponding to a first memory cell connected to a word line, and store data corresponding to a second logic level in a first latch circuit of a sense amplifier unit corresponding to a second memory cell connected to the word line while applying the first verification voltage to the word line, and while applying a second verification voltage to the word line, store the data corresponding to the first logic level in the first latch circuit in the sense amplifier unit corresponding to the first memory cell, if the first memory cell passes verification at the first verification voltage, and store the data corresponding to the first logic level in the first latch circuit of the sense amplifier unit corresponding to the second memory cell.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.51282
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15405098', '15690256', '15908449', '15195560', '14630505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7738416302589654
- 35 USC 102 Novelty (BERT): 0.4990842979603627
- Combined Prediction Score: 0.746365897029105
- Mean Citation Score: 251.253478
- Max Citation Score: 284.98608
- Similarity Product: 242.58446146259308

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test