PATENT CLAIM ANALYSIS

Application Number: 15912477
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["330", "252000"]

Abstract:
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Claim (Index 13):
The amplifier of  claim 12 , wherein a voltage potential at the eighth node is greater than a voltage potential at the seventh node.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 90.0
- Lexical Diversity: 4.17949
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15690290', '15387678', '15776780', '12648946', '13177119']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7940551207740799
- 35 USC 102 Novelty (BERT): 0.5328382013007512
- Combined Prediction Score: 0.7679334288267471
- Mean Citation Score: 297.43500400000005
- Max Citation Score: 311.1313
- Similarity Product: 185.8466419837117

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test