PATENT CLAIM ANALYSIS

Application Number: 15896491
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "379000"]

Abstract:
Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.

Claim (Index 7):
The apparatus of  claim 6 , wherein the resistor comprises a first portion and a second portion, the first portion being disposed relative to the transistor area in the second direction, and the second portion being disposed relative to the additional transistor area in the second direction.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 3.08889
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15063117', '10708023', '14485698', '11811860', '13245162']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8892510107980414
- 35 USC 102 Novelty (BERT): 0.51122314483338
- Combined Prediction Score: 0.8514482242015753
- Mean Citation Score: 152.017672
- Max Citation Score: 226.62433
- Similarity Product: 133.09314665831863

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test