PATENT CLAIM ANALYSIS

Application Number: 15878781
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["712", "022000"]

Abstract:
An apparatus includes a processor configured to execute a process of generating a second program according to a first program, the second program including: a first process in which an operation according to a first operation instruction is performed on operation elements iteratively; a second process in which a mask bit string including as mask bits as the number of operand elements is set; and a third process in which the operation is performed on as respective elements as the number of operand elements according to second operation instruction, the elements including one or more remainder operation elements not subjected to the operation in the first process and one or more non-operation elements excluded from being operated on as the number of operand elements, the operation according to the second operation instruction being performed.

Claim (Index 1):
A code generation apparatus comprising:\n a memory configured to store a first program including a loop process that performs a same operation on each of a plurality of operation elements set in an array; and a processor configured to execute a process of generating a second program according to the first program, the second program including: a first process in which an operation according to a first operation instruction is performed on operation elements iteratively such that each iteration is performed on as operation elements as a number of operand elements, the operation element being extracted from the array in an order for starting from a top element of the array, the iteration being performed as times as a number specified by a quotient obtained as a result of an integer division of a total number of operation elements by the number of operand elements for indicating a unit number of operation elements operated on by one operation instruction; a second process in which a mask bit string including as mask bits as the number of operand elements is set such that a first mask bits included in the mask bit string and including as mask bits as a remainder of the division are each set to a value for indicating truth, while one or more second mask bits included in the mask bit string other than the first mask bits are each set to a value for indicating false; and a third process in which the operation is performed on as respective elements as the number of operand elements according to second operation instruction, the elements including one or more remainder operation elements not subjected to the operation in the first process and one or more non-operation elements excluded from being operated on as the number of operand elements, the operation according to the second operation instruction being performed such that each remainder operation element is assigned one of the first mask bits, each non-operation element is assigned one of second mask bits, a result of the operation for an element assigned a truth mask bit is output, and a result of the operation for an element assigned a false mask bit is not output.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.66038
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13993321', '12585573', '15470975', '13996072', '13995974']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5727070699645559
- 35 USC 102 Novelty (BERT): 0.4857029699946958
- Combined Prediction Score: 0.5640066599675699
- Mean Citation Score: 204.938616
- Max Citation Score: 221.9485
- Similarity Product: 162.44580854716895

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test