PATENT CLAIM ANALYSIS

Application Number: 16166603
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

Claim (Index 6):
The method of  claim 1 , wherein a horizontal plane that is parallel to the upper surface of the substrate extends through the first dielectric material and through the sidewalls of the memory gate and the select gate.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 97.0
- Lexical Diversity: 2.03704
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14296496', '15167070', '14182952', '14933046', '14493568']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920246275987525
- 35 USC 102 Novelty (BERT): 0.4778675777160986
- Combined Prediction Score: 0.8760084061603823
- Mean Citation Score: 181.86874000000003
- Max Citation Score: 187.40468
- Similarity Product: 142.66079973722697

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test