PATENT CLAIM ANALYSIS

Application Number: 15907570
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185110"]

Abstract:
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.

Claim (Index 19):
An apparatus, comprising:\n a plurality of non-volatile memory cells including a group of memory cells arranged in sub-groups of connected memory cells, each sub-group of connected memory cells is connected to a common control line and has its own select gate that connects to the common control line, each sub-group of connected memory cells has a separate selection line connected to its select gate; and means for erasing the memory cells by separately controlling an erase speed for the sub-groups of connected memory cells by adjusting one or more voltages on one or more of the separate selection lines in response to observing speed information for the sub-groups of connected memory cells during the erasing.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 1.51515
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15337522', '15630389', '15191150', '15151951', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8017639772473188
- 35 USC 102 Novelty (BERT): 0.4778067985881348
- Combined Prediction Score: 0.7693682593814005
- Mean Citation Score: 226.306854
- Max Citation Score: 232.60359
- Similarity Product: 185.14938066284537

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test