PATENT CLAIM ANALYSIS

Application Number: 15867470
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["716", "055000"]

Abstract:
A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.

Claim (Index 12):
The computer-implemented method of  claim 7 , wherein the parasitic component data further comprises at least one of a random wire delay sensitivity obtained from the wire delay sensitivity coefficients and a random capacitance sensitivity obtained from the capacitance sensitivity coefficients.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.4898
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11599145', '15081291', '15390322', '11164518', '14982921']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3732331627912534
- 35 USC 102 Novelty (BERT): 0.4788967258384622
- Combined Prediction Score: 0.3837995190959744
- Mean Citation Score: 197.051298
- Max Citation Score: 213.47868
- Similarity Product: 142.33818527413132

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test