PATENT CLAIM ANALYSIS

Application Number: 16408624
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.

Claim (Index 7):
A semiconductor memory device comprising:\n a plurality of electrode layers stacked in a first direction; a plurality of interlayer insulating layers provided between the plurality of electrode layers respectively; a semiconductor channel body extending in the first direction through the plurality of electrode layers and the plurality of interlayer insulating layers; and a charge storage layer extending along the semiconductor channel body in the plurality of electrode layers and the plurality of interlayer insulating layers, one of the plurality of electrode layers being positioned between the first interlayer insulating layer and the second interlayer insulating layer of the plurality of interlayer insulating layers, the one of the plurality of electrode layer having a first surface facing the first interlayer insulating layer, a second surface facing the second interlayer insulating layer, and a third surface facing the charge storage layer, wherein an interior angle between the first surface and the third surface is less than 90 degrees at a portion where the first surface is connected to the third surface, and an interior angle between the second surface and the third surface is less than 90 degrees at a portion where the second surface is connected to the third surface.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 100.0
- Lexical Diversity: 4.14286
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15463582', '15457396', '12728727', '15404420', '13421471']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.925391474069625
- 35 USC 102 Novelty (BERT): 0.4762138386902921
- Combined Prediction Score: 0.8804737105316918
- Mean Citation Score: 226.920498
- Max Citation Score: 233.70386
- Similarity Product: 207.5178725562465

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test