PATENT CLAIM ANALYSIS

Application Number: 16228067
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["710", "305000"]

Abstract:
A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Claim (Index 3):
The routing circuit of  claim 2  including a controller having inputs coupled to the TDI, TCK and TMS signal leads of the first bus, a select output coupled to the select input of the decode circuitry, and an enable output coupled to the enable input of the decode circuitry.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 3.80488
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15499362', '15179117', '14054039', '12968966', '12957904']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.800323924271238
- 35 USC 102 Novelty (BERT): 0.732971360171125
- Combined Prediction Score: 0.7935886678612267
- Mean Citation Score: 691.6110060000003
- Max Citation Score: 812.27277
- Similarity Product: 808.7128465594644

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test