PATENT CLAIM ANALYSIS

Application Number: 16014008
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["438", "666000"]

Abstract:
A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Claim (Index 16):
The semiconductor arrangement of  claim 12 , comprising:\n a second electrode overlying the first electrode and the protective ring.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.55319
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14087005', '15362759', '15412115', '14087009', '14144676']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8464974751698501
- 35 USC 102 Novelty (BERT): 0.4842702020273288
- Combined Prediction Score: 0.810274747855598
- Mean Citation Score: 169.96331
- Max Citation Score: 177.30943
- Similarity Product: 121.6698511435932

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test