PATENT CLAIM ANALYSIS

Application Number: 15933087
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "185180"]

Abstract:
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

Claim (Index 15):
An apparatus comprising:\n a group of semiconductor structures located in different levels of the apparatus and over a substrate; a pillar extending through the group of semiconductor structures, the pillar being part of a memory cell string; a group of conductive structures located over the group of semiconductor structures, the group of conductive structures being electrically separated from the group of semiconductor structures; a capacitor including a first conductive plate formed from part of a first conductive structure of the group of conductive structures, and second conductive plate formed from part of a second conductive structure of the group of conductive structures; a first conductive path coupled between the first conductive plate of the capacitor and a first node; a second conductive path coupled between the second conductive plate of the capacitor and a second node; a first transistor and a second transistor coupled in series between a third node and a fourth node, the first transistor including a gate coupled to the fourth node; and a third transistor coupled between the fourth node and the second node.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 90.0
- Lexical Diversity: 3.7
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15450638', '15231011', '15205640', '15692712', '15844007']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7838397904546555
- 35 USC 102 Novelty (BERT): 0.4520801009996869
- Combined Prediction Score: 0.7506638215091586
- Mean Citation Score: 165.63978799999995
- Max Citation Score: 179.86702
- Similarity Product: 153.53106210936545

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test