PATENT CLAIM ANALYSIS

Application Number: 15959027
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-09
Patent Classification: ["257", "421000"]

Abstract:
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

Claim (Index 17):
The magnetic random access memory structure of  claim 13 , wherein the hardmask is a conductive hardmask.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 91.0
- Lexical Diversity: 2.13514
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15596650', '13994715', '13994716', '15824448', '14968287']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9233815097264132
- 35 USC 102 Novelty (BERT): 0.5061944109205943
- Combined Prediction Score: 0.8816627998458313
- Mean Citation Score: 218.58971
- Max Citation Score: 256.72787
- Similarity Product: 176.25199514047742

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test