PATENT CLAIM ANALYSIS

Application Number: 15938393
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["365", "189090"]

Abstract:
A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.

Claim (Index 17):
A memory circuit comprising:\n a reference node configured to carry a reference voltage; a power supply node configured to carry a power supply voltage; a bit line coupled with a plurality of memory cells; a first switching circuit coupled between the reference node and the bit line, the first switching circuit configured to couple the reference node with the bit line responsive to a voltage level on the bit line; and a second switching circuit coupled between the power supply node and the bit line, the second switching circuit configured to couple the power supply node with the bit line responsive to the voltage level on the bit line.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.21429
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13804405', '13780772', '14659642', '15434541', '14504596']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7882423980743085
- 35 USC 102 Novelty (BERT): 0.4606378924905286
- Combined Prediction Score: 0.7554819475159306
- Mean Citation Score: 185.340002
- Max Citation Score: 191.39548
- Similarity Product: 157.4420600954294

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test