PATENT CLAIM ANALYSIS

Application Number: 15958768
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["327", "427000"]

Abstract:
A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.

Claim (Index 16):
The circuit of  claim 15 , wherein the control circuitry includes a self-timed circuit to control a duration of a time period that the switch transistor is temporarily on.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 2.34328
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13976156', '11889145', '12716983', '15099459', '12555447']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7789828061191955
- 35 USC 102 Novelty (BERT): 0.5081040001970055
- Combined Prediction Score: 0.7518949255269765
- Mean Citation Score: 199.029868
- Max Citation Score: 253.46991
- Similarity Product: 154.93290415387452

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test