PATENT CLAIM ANALYSIS

Application Number: 15994720
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["257", "192000"]

Abstract:
Techniques for reducing gate length variation in VFET devices are provided. In one aspect, a method for forming a VFET device includes: forming a first and a second semiconductor layer as a stack on a substrate; patterning fins in the stack each of which extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins include active fin channels; selectively thinning the active fin channels; forming sidewall spacers alongside the active fin channels; forming bottom source and drains at a base of the fins below the sidewall spacers; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers; forming top spacers on the gate stacks; and forming top source and drains on the top spacers. A VFET device is also provided.

Claim (Index 1):
A method for forming a vertical field-effect transistor (VFET) device, comprising the steps of:\n forming a first semiconductor layer and a second semiconductor layer as a stack on a substrate; patterning fins in the stack, wherein each of the fins extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins comprise active fin channels; selectively thinning the active fin channels to form a staircase structure at an interface between the active fin channels and the first semiconductor layer; forming sidewall spacers alongside the active fin channels; forming bottom source and drains at a base of the fins below the sidewall spacers such that tops of the bottom source and drains are flush with bottoms of the active fin channels, wherein the bottom source and drains have a contoured surface topography; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers surrounding the active fin channels; forming top spacers on the gate stacks; and forming top source and drains on the top spacers.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.41791
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15843318', '15713975', '15853822', '15863000', '15886539']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9390821862118176
- 35 USC 102 Novelty (BERT): 0.5527435897494102
- Combined Prediction Score: 0.9004483265655768
- Mean Citation Score: 409.694192
- Max Citation Score: 429.9327
- Similarity Product: 360.0984290211618

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test