PATENT CLAIM ANALYSIS

Application Number: 16220724
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["323", "235000"]

Abstract:
A device [ 200 , para. 24] is configured to detect a zero voltage switching (ZVS) circuit [ 110 , para. 14] output that includes a hard switching signal. The hard switching signal [ 114 , para. 16] includes a false signal [ 116 , para. 16] and a spike signal [ 118 , para. 16]. Thereafter, the device generates digital pulse signals [ 312/314 , para. 39] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [ 312 , para. 41], and uses the digital pulse signal [ 314 , para. 42] that corresponds to the spike signal for adjusting a timing [ 132 , para. 20] of a pulse width modulation (PWM) switching cycle [Vgs  106 , para. 32].

Claim (Index 4):
The device of  claim 1 , wherein the hard switching signal further includes a false signal [para. 20] that is filtered out by the blanking component.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 98.0
- Lexical Diversity: 2.52239
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13666853', '13478252', '14471961', '12871104', '16160837']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7224103399138674
- 35 USC 102 Novelty (BERT): 0.4877837483132162
- Combined Prediction Score: 0.6989476807538023
- Mean Citation Score: 144.025684
- Max Citation Score: 148.72528
- Similarity Product: 89.94357771414757

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test