PATENT CLAIM ANALYSIS

Application Number: 15868224
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "347000"]

Abstract:
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Claim (Index 12):
The IC structure of  claim 10 , wherein a height of the channel region is less than a height of the two end regions.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 2.11628
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15868274', '14616018', '15662526', '15626321', '15387933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9297280507802814
- 35 USC 102 Novelty (BERT): 0.5449860689862224
- Combined Prediction Score: 0.8912538526008755
- Mean Citation Score: 304.209024
- Max Citation Score: 406.55795
- Similarity Product: 262.3965912617922

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test