PATENT CLAIM ANALYSIS

Application Number: 15990037
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "314000"]

Abstract:
An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Claim (Index 1):
A method of forming a three-dimensional memory device, comprising:\n forming a first alternating stack comprising a first alternating stack of first insulating layers and first spacer material layers over a substrate; forming a joint-level dielectric material layer over the first alternating stack; forming a first-tier memory opening through the joint-level dielectric material layer and the first alternating stack; forming an annular dielectric spacer within the first-tier memory opening at a level of the joint-level dielectric material layer; forming a second alternating stack of second insulating layers and second electrically conductive layers over the joint-level dielectric material layer; forming a second-tier memory opening through the second alternating stack and over the first-tier memory opening; forming a memory opening including an entire volume of the second-tier memory opening and a predominant portion of a volume of the first-tier memory opening that excludes a volume of the annular dielectric spacer; forming a memory film and an cover material layer in the memory opening; anisotropically etching horizontal portions of the cover material layer and the memory film, such that a semiconductor surface is physically exposed at a bottom of a cavity within the memory opening; and forming a vertical semiconductor channel inside the memory film by depositing a semiconductor material in the memory opening, wherein the first and second spacer material layers are formed as, or are subsequently replaced with, first and second electrically conductive layers, respectively.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 1.69355
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15434544', '15445579', '15914560', '15347101', '15186768']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9380888366531906
- 35 USC 102 Novelty (BERT): 0.5740745496589172
- Combined Prediction Score: 0.9016874079537632
- Mean Citation Score: 418.19315000000006
- Max Citation Score: 479.896
- Similarity Product: 418.84867718935016

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test