PATENT CLAIM ANALYSIS

Application Number: 15933229
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["708", "252000"]

Abstract:
Techniques and circuits are provided for stochastic rounding. In an embodiment, a circuit includes carry-save adder (CSA) logic having three or more CSA inputs, a CSA sum output, and a CSA carry output. One of the three or more CSA inputs is presented with a random number value, while other CSA inputs are presented with input values to be summed. The circuit further includes adder logic having adder inputs and a sum output. The CSA carry output of the CSA logic is coupled with one of the adder inputs of the adder logic, and the CSA sum output of the CSA logic is coupled with another input of the adder inputs of the adder logic. A particular number of most significant bits of the sum output of the adder logic represent a stochastically rounded sum of the input values.

Claim (Index 21):
The method of  claim 19  wherein converting the randomly generated value into the negative randomly generated value is performed at least by negating bits of the randomly generated value.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 2.57627
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12486231', '13043101', '13469212', '12057894', '10730800']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4613332222939725
- 35 USC 102 Novelty (BERT): 0.5182024807736751
- Combined Prediction Score: 0.4670201481419427
- Mean Citation Score: 205.586462
- Max Citation Score: 211.89929
- Similarity Product: 113.0957261427987

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test