PATENT CLAIM ANALYSIS

Application Number: 15950209
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "532000"]

Abstract:
Integrated circuits including metal-insulator-metal capacitors (MIMCAPs) generally include a diffusion barrier layer on the top and bottom surfaces of the electrode and a self-formed oxide layer on sidewalls of the electrode. The diffusion barrier layers and the self-formed oxide layers on the sidewalls of the electrode prevent diffusion of the metal defining the electrode into the interlayer dielectric. Also described are processes for fabricating the MIMCAPs.

Claim (Index 15):
A method for fabricating a metal-insulator-metal capacitor in an integrated circuit, the method comprising:\n depositing a plurality of layers onto a substrate, the plurality of layers comprising, in sequence, a first barrier layer, a bottom metal electrode layer comprising a copper alloy including an alloying element, a second barrier layer, a dielectric layer, third barrier layer, a top metal electrode layer comprising the copper alloy, a fourth barrier layer wherein the first, second, third and fourth barrier layers on the respective bottom electrode layer and the top metal electrode layer comprise titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, cobalt, cobalt nitride, or combination thereof, and wherein the dielectric layer is formed of a material including oxygen and at least one element selected from the group consisting of Si, C, and F, wherein the dielectric layer completely covers and is in contact with the sidewalls of the copper alloy electrode, patterning the third barrier layer, the top metal electrode layer, and the fourth barrier layer to define a top electrode; patterning the dielectric layer such that the dielectric layer has a width equal to a width of the top electrode and underlies the top electrode; patterning the second barrier layer, the bottom metal electrode layer, and the first barrier layer to define a bottom electrode; depositing in interlayer dielectric on the top and bottom electrodes, wherein the interlayer dielectric contains oxygen; reacting the alloying element in the copper alloy of the top and bottom electrodes with at least the oxygen in the interlayer dielectric to form a reaction product therebetween containing a metal oxide on sidewalls of the top and bottom electrodes; and patterning the interlayer dielectric to form metal interconnects to the top and bottom electrodes, wherein the top and bottom electrodes and the dielectric layer therebetween define the metal-insulator-metal capacitor.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.775
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15724367', '15268787', '15215544', '15278145', '15474233']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9203629925025232
- 35 USC 102 Novelty (BERT): 0.5016299462220167
- Combined Prediction Score: 0.8784896878744725
- Mean Citation Score: 250.60648800000004
- Max Citation Score: 272.1544
- Similarity Product: 207.0425454836845

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test