PATENT CLAIM ANALYSIS

Application Number: 16145205
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["327", "261000"]

Abstract:
A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.

Claim (Index 2):
The system on chip as recited in  claim 1 , wherein the system balance circuit comprises:\n a first delayer having an input terminal that receives the reference clock signal and having an output terminal that provides the system clock signal; a second delayer having an input terminal that is coupled to the output terminal of the first delayer and having an output terminal; a first inverter having an input terminal that is coupled to the output terminal of the second delayer and having an output terminal; and a first AND gate having a plurality of input terminals that are coupled to the output terminal of the first inverter and the clock generator and having an output terminal that provides the current setting signal.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 3.36364
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11257706', '14451446', '12554076', '12979705', '10617180']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7759247618286657
- 35 USC 102 Novelty (BERT): 0.4646698558457532
- Combined Prediction Score: 0.7447992712303744
- Mean Citation Score: 163.306062
- Max Citation Score: 177.36598
- Similarity Product: 141.81876211706282

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test