PATENT CLAIM ANALYSIS

Application Number: 15953422
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["365", "096000"]

Abstract:
A programmable resistive memory has a plurality of programmable resistive devices (PRD) and at least one sensing circuit. The at least one of the programmable resistive device can include at least one programmable resistive element (PRE). The sensing circuit can include one PRD unit and a reference unit. Each unit has at least one capacitor to charge to a second supply voltage line and to discharge to the first supply voltage line through the PRE and the reference element, respectively. The capacitors are also coupled to comparators to monitor discharging voltages with respect to a reference voltage. By comparing the time difference when the comparators change their outputs, the magnitude of the PRE resistance with respect to the reference element resistance can be determined and converted into logic states.

Claim (Index 9):
An electronic system, comprises:\n a processor; and a programmable resistive memory operatively connected to the processor, the programmable resistive memory includes at least a plurality of programmable resistive device (PRD) cells for providing data storage, each of the programmable resistive device cells comprising:\n a programmable resistive element (PRE) coupled to a first supply voltage line through a selector with an enable signal; and \n a time-base sensing circuit coupled to at least one PRD cell unit and a reference unit having PRE and reference resistor, respectively; each unit has at least one capacitor that can be charged to a second supply voltage line and discharged through PRE and reference resistor, respectively, to the first supply voltage line; each unit has at least one comparators coupled to the capacitors to change output when the voltage discharged to a reference voltage. \n wherein the capacitors in both units are charged to the second supply voltage approximately and discharged to the first supply voltage line by turning on the enable signal at the same time, and wherein the PRE resistance can be converted into logic state by the time difference of the comparators changing outputs.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.10448
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14493083', '14940012', '14485698', '14101125', '15805109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7663176402990685
- 35 USC 102 Novelty (BERT): 0.5129844253389867
- Combined Prediction Score: 0.7409843188030604
- Mean Citation Score: 266.29096200000004
- Max Citation Score: 290.7004
- Similarity Product: 236.2825471423626

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test