PATENT CLAIM ANALYSIS

Application Number: 15954665
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["714", "718000"]

Abstract:
A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode. Logic BIST circuits complete a test with the LBIST mode, at a stage where the second scan test has completed.

Claim (Index 4):
The semiconductor device according to  claim 3 ,\n wherein the memory circuit unit includes\n a scan flip flop circuit for bypass which has a function for bypassing an input and/or an output of the memory circuit, and selectively latches an input signal for the memory circuit or a scan-in signal, and \n a path switch circuit which transmits an output signal of the scan flip flop circuit for bypass to the memory BIST circuit and the memory post-stage logic circuit, when it is set to the first test mode, transmits an output signal of the scan flip flop circuit for bypass to the memory post-stage logic circuit, when it is set to the second test mode, and transmits an output signal of the memory circuit to the memory BIST circuit, \n wherein the scan-in signal of the scan flip flop circuit for bypass is an output signal of any scan flip flop circuit in the logic circuit incorporated in the first scan chain, and wherein the scan flip flop circuit for bypass fixedly latches the scan-in signal, when it is set to the second test mode.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 91.0
- Lexical Diversity: 2.75
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11603085', '15220427', '11626574', '10086214', '14072295']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3069629425829632
- 35 USC 102 Novelty (BERT): 0.5068019774522369
- Combined Prediction Score: 0.3269468460698906
- Mean Citation Score: 261.310006
- Max Citation Score: 279.22342000000003
- Similarity Product: 216.01532126324184

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test