PATENT CLAIM ANALYSIS

Application Number: 15960492
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "369000"]

Abstract:
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Claim (Index 16):
The semiconductor integrated circuit device according to  claim 15 , wherein each memory cell region further includes:\n (d6) a data storage unit; (d7) a first storage node which is provided in the data storage unit; (d8) a second storage node, provided in the data storage unit, which is complementary to the first storage node; (d9) a first driver MISFET, provided in the data storage unit and the second well region, of which one of the source drain terminals thereof is connected to the first storage node; (d10) a second driver MISFET, provided in the data storage unit and the third well region, of which one of the source drain terminals thereof is connected to the second storage node; (d11) a first access MISFET, provided in the second well region, of which one of the source drain terminals thereof is connected to the first storage node and the other thereof is connected to the first bit line; (d12) a second access MISFET, provided in the third well region, of which one of the source drain terminals thereof is connected to the second storage node and the other thereof is connected to the second bit line; (d13) a third access MISFET, provided in the second well region, of which one of the source drain terminals thereof is connected to the first storage node and the other thereof is connected to the third bit line; (d14) a fourth access MISFET, provided in the third well region, of which one of the source drain terminals thereof is connected to the second storage node and the other thereof is connected to the fourth bit line; (d15) a fifth access MISFET, provided in the second well region, of which one of the source drain terminals thereof is connected to the first storage node and the other thereof is connected to the fifth bit line; and (d16) a sixth access MISFET, provided in the third well region, of which one of the source drain terminals thereof is connected to the second storage node and the other thereof is connected to the sixth bit line.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.94737
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14909135', '15338390', '15635970', '15795502', '14490235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9267942018343914
- 35 USC 102 Novelty (BERT): 0.5995757469292194
- Combined Prediction Score: 0.8940723563438743
- Mean Citation Score: 377.603038
- Max Citation Score: 496.8272
- Similarity Product: 480.83026307487495

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test