PATENT CLAIM ANALYSIS

Application Number: 15913451
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "185180"]

Abstract:
A method for detecting a flash memory array includes a plurality of word lines, a plurality of bit lines, and a source line, includes executing a first detection process. The first detection process includes: applying a first positive voltage to a P-type well of the flash memory array; applying a ground to all the word lines; floating the bit lines and the source line; determining whether a leakage current flowing through the P-type well exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited with at least one of the bit lines or the source line.

Claim (Index 19):
The device of  claim 16 , wherein when the selected bit line is short-circuited with the selected word line, data stored on the selected bit line of the flash memory array is lost, and data stored on the selected word line is able to be recovered by ECC.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.28302
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13317678', '13116002', '11279384', '13535681', '14546294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8165133152236512
- 35 USC 102 Novelty (BERT): 0.4751234755927348
- Combined Prediction Score: 0.7823743312605596
- Mean Citation Score: 207.72528
- Max Citation Score: 211.48857
- Similarity Product: 164.65875602004826

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test