PATENT CLAIM ANALYSIS

Application Number: 16029366
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-05
Patent Classification: ["327", "116000"]

Abstract:
A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.

Claim (Index 4):
The apparatus of  claim 1 , wherein the input clock signal is configured to selectively switch ON the first PMOS transistor and the first NMOS transistor and to selectively switch OFF the first PMOS transistor and the first NMOS transistor.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 95.0
- Lexical Diversity: 3.52
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14207751', '15389830', '10384262', '12786496', '12901313']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7767149764519107
- 35 USC 102 Novelty (BERT): 0.5084892851033386
- Combined Prediction Score: 0.7498924073170534
- Mean Citation Score: 267.762854
- Max Citation Score: 276.68668
- Similarity Product: 206.96045635405065

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test