PATENT CLAIM ANALYSIS

Application Number: 16013646
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "049170"]

Abstract:
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Claim (Index 32):
A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:\n a first bi-stable floating body transistor; and a second bi-stable floating body transistor; wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor are electrically connected in series through a common node; and wherein said first floating body transistor and said second floating body transistor store complementary data.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 94.0
- Lexical Diversity: 2.0
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14154138', '15375236', '14597444', '15846566', '14380779']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.837042821798442
- 35 USC 102 Novelty (BERT): 0.6366685185809572
- Combined Prediction Score: 0.8170053914766936
- Mean Citation Score: 389.131656
- Max Citation Score: 526.85046
- Similarity Product: 489.257398634609

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test