PATENT CLAIM ANALYSIS

Application Number: 15986426
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "077000"]

Abstract:
A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Claim (Index 20):
A semiconductor device, comprising:\n gate structures including channel layers disposed and vertically arranged over a fin structure; and a source/drain region disposed over the fin structure and between the gate structures, wherein: the channel layers pass through the source/drain region each of the channel layers includes a first semiconductor wire made of a first semiconductor material, and the source/drain region includes second semiconductor wires made of a second semiconductor material different from the first semiconductor material.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.38462
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15407839', '15719121', '15098073', '15464484', '15173222']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9244936954191786
- 35 USC 102 Novelty (BERT): 0.512165727445248
- Combined Prediction Score: 0.8832608986217856
- Mean Citation Score: 286.0912600000001
- Max Citation Score: 324.87036
- Similarity Product: 298.48232679885865

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test