PATENT CLAIM ANALYSIS

Application Number: 16156613
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-08
Patent Classification: ["327", "299000"]

Abstract:
A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Claim (Index 4):
The clock generation circuit of  claim 1 , wherein the frequency detector generates an update signal that is activated when the activation period of the input dock ends, and\n the control signal generator compares the target signal with the counting signal based on the update signal.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 97.0
- Lexical Diversity: 2.36842
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11964824', '12983124', '12428507', '10372265', '13237083']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7844088656456334
- 35 USC 102 Novelty (BERT): 0.4980186534777645
- Combined Prediction Score: 0.7557698444288465
- Mean Citation Score: 203.134922
- Max Citation Score: 233.72401
- Similarity Product: 155.71577750206947

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test