PATENT CLAIM ANALYSIS

Application Number: 16171422
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-09
Patent Classification: ["323", "271000"]

Abstract:
When a ramp signal intersects a feedback related signal, a constant time switching regulator enters a first state and maintains in the first state for a constant time, and after the constant time ends, when the ramp signal exceeds the feedback related signal, the switching regulator enters a second state, while when the ramp signal does not exceed the feedback related signal, the switching regulator enters a third state. In the first state, the first end of an inductor is connected to input voltage and the second end of the inductor is connected to output voltage; in the second state, the first end is connected to ground and the second end is connected to output voltage; and in the third state, the first end is connected to input voltage and the second end is connected to ground.

Claim (Index 12):
A control circuit for controlling a constant time buck-boost switching regulator, the constant time buck-boost switching regulator including a power switch circuit which includes an input switch unit and an output switch unit; the input switch unit being configured to operably switch a first end of an inductor between an input voltage and a ground, and the output switch unit being configured to operably switch a second end of the inductor between an output voltage and the ground, wherein an inductor current flows through the inductor; when a ramp signal intersects a feedback related signal, the control circuit being configured to operably control the power switch circuit to enter a first state and maintain in the first state for a constant time, and after the constant time ends, when the ramp signal exceeds the feedback related signal, the control circuit being configured to operably control the power switch circuit to enter a second state, while when the ramp signal does not exceed the feedback related signal, the control circuit being configured to control the power switch circuit to enter a third state, wherein, in the first state, the power switch circuit electrically connects the first end of the inductor to the input voltage and electrically connects the second end of the inductor to the output voltage; in the second state, the power switch circuit electrically connects the first end of the inductor to the ground and electrically connects the second end of the inductor to the output voltage; and in the third state, the power switch circuit electrically connects the first end of the inductor to the input voltage and electrically connects the second end of the inductor to the ground, and wherein the feedback related signal is related to the output voltage; the control circuit comprising:\n a comparison circuit, configured to operably compare the ramp signal with the feedback related signal to generate a comparison output signal; a constant time generation circuit, configured to operably trigger the constant time according to the comparison output signal when the ramp signal intersects the feedback related signal; and a logic driver circuit, coupled to the comparison circuit and the constant time generation circuit, and configured to operably control the power switch circuit to enter the first state and maintain in the first state for the constant time, and control the power switch circuit to enter the second or third state when the constant time ends according to a level of the comparison output signal.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 97.0
- Lexical Diversity: 3.40909
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15217102', '12799107', '15925970', '14264477', '14177558']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7688804624574832
- 35 USC 102 Novelty (BERT): 0.5515205036828659
- Combined Prediction Score: 0.7471444665800215
- Mean Citation Score: 352.470656
- Max Citation Score: 433.23782
- Similarity Product: 379.6133417020058

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test