PATENT CLAIM ANALYSIS

Application Number: 15870390
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["711", "103000"]

Abstract:
A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.

Claim (Index 23):
A system, comprising:\n means for storing a plurality of sequencer timing vectors in a volatile random access memory (RAM) at respective addresses, each sequencer timing vector having a respective timing and control signal data; means for executing a memory command on a non-volatile memory, wherein the means for executing are embodied within a memory structure comprising non-volatile memory cells of the non-volatile memory, wherein executing the memory command comprises:\n associating the memory command with an address of the volatile RAM; \n fetching a sequencer timing vector from the address associated with the memory command; and \n implementing the sequencer timing vector, the implementing comprising:\n determining a timing parameter for the sequencer timing vector by use of a mantissa and exponent included in the timing data of the sequencer timing vector, and \n providing control timing signals corresponding to the control signal data of the sequencer timing vector to command execution circuitry in accordance with the determined timing parameter, the control timing signals configured to cause the command execution circuitry to execute at least a portion of the memory command on one or more non-volatile memory cells of the non-volatile memory; \n \n means for fetching a next sequencer timing vector from a next address of the volatile RAM; means for determining whether execution of the memory command on the non-volatile memory is complete based on one or more of timing data of the next sequencer timing vector and control signal data of the next sequencer timing vector; and means for implementing the next sequencer timing vector in response to determining that execution of the memory command on the non-volatile memory is not complete.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.15789
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10486638', '15693390', '11818449', '14729659', '13915606']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5311604777900112
- 35 USC 102 Novelty (BERT): 0.4548674455843158
- Combined Prediction Score: 0.5235311745694416
- Mean Citation Score: 143.17608
- Max Citation Score: 145.96693
- Similarity Product: 114.8461058256316

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test