PATENT CLAIM ANALYSIS

Application Number: 16275038
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-09
Patent Classification: ["365", "185170"]

Abstract:
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

Claim (Index 19):
A method, comprising:\n operating a memory array having multiple strings of memory cells,\n wherein each memory cell string extends vertically and includes multiple vertically arranged memory cells and extends between a source and a respective bit line of multiple bit lines, \n wherein the multiple bit lines extend in a first direction, and include a first group of bit lines and a second group of bit lines, wherein the bit lines of the second group are vertically stacked relative to respective bit lines of the first group, \n wherein strings of memory cells that are adjacent one another along the first direction are coupled to different bit lines, \n wherein the vertically arranged memory cells of the memory cell strings are associated with a respective access line, \n wherein the access lines are coupled to respective memory cells in each of multiple strings, and \n wherein the multiple memory cell strings are selectively coupled to a respective bit line through a respective select gate drain transistor; \n the operating of the memory array comprising,\n applying a read voltage to a selected access line of multiple access lines, each access line coupled to a respective memory cell in each string of a first group of strings of memory cells; \n applying a read pass voltage to unselected access lines of the multiple access lines; \n applying a pre-charge voltage to a first group of bit lines during a read operation; \n applying a shield voltage to a second group of bit lines during at least a portion of the read operation; and \n applying an enable voltage to select gate drain transistors of a second group of memory cell strings comprising the enabled memory cells to couple the second group of memory cell strings to respective bit lines of the second group of bit lines during the read operation.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.52
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15676659', '14867948', '13919599', '12502771', '11432135']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7935133370328259
- 35 USC 102 Novelty (BERT): 0.4768450750706979
- Combined Prediction Score: 0.761846510836613
- Mean Citation Score: 212.896042
- Max Citation Score: 257.62024
- Similarity Product: 234.1703282699776

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test