PATENT CLAIM ANALYSIS

Application Number: 15918927
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["712", "227000"]

Abstract:
A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

Claim (Index 19):
The system of  claim 14 , further comprising:\n an instruction decode queue; and a latency counter including a seventh logic to assign an event tag to a subsequent instruction based upon a number of cycles for which the instruction decode queue includes bubbles, the subsequent instruction a first instruction after an allocation window including bubbles.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 90.0
- Lexical Diversity: 2.60976
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14750535', '14581081', '14580676', '14498092', '14742908']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5602861656095812
- 35 USC 102 Novelty (BERT): 0.5074403971508564
- Combined Prediction Score: 0.5550015887637088
- Mean Citation Score: 197.04397
- Max Citation Score: 288.7899
- Similarity Product: 204.37937042119503

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test