PATENT CLAIM ANALYSIS

Application Number: 15987706
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "506000"]

Abstract:
Disclosed is a method for fabricating a semiconductor device with intra-die variation control. In one embodiment, a method for fabricating a semiconductor device includes: depositing a first dielectric layer on a semiconductor substrate die; patterning a conductive layer on the first dielectric layer to create at least one device region and at least one dummy pattern region, wherein the at least one device region comprises a plurality of first conductive patterns and the at least one dummy pattern region comprises a plurality of second conductive patterns to control intra-die variation.

Claim (Index 12):
The device of  claim 9 , wherein the dummy pattern region has a first width, wherein the first width of the dummy pattern region is at least half of a second width of the device region.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 93.0
- Lexical Diversity: 2.18182
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15225024', '14995017', '11281030', '13344137', '12417394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9128478492559232
- 35 USC 102 Novelty (BERT): 0.474956504458052
- Combined Prediction Score: 0.8690587147761362
- Mean Citation Score: 133.94834799999998
- Max Citation Score: 146.54822
- Similarity Product: 103.63521367749571

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test