PATENT CLAIM ANALYSIS

Application Number: 15941195
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-01
Patent Classification: ["257", "072000"]

Abstract:
A thin film transistor, a method for manufacturing the same, an array substrate and a display device are disclosed. The thin film transistor includes a gate having a gate metal layer on a surface of a substrate; a gate insulating layer on the substrate and covering the gate; an active layer on a surface of the gate insulating layer away from the substrate; a source comprising a source metal layer on a surface of the active layer away from the substrate; and a drain having a drain metal layer on a surface of the active layer away from the substrate, wherein the gate, the source or the drain further includes a metal complex layer on a surface of the gate metal layer, the source metal layer or the drain metal layer away from the substrate.

Claim (Index 7):
The method according to  claim 6 , wherein forming the metal complex layer comprises:\n contacting the surface of the metal layer with a complex solution for about 30-90 seconds at about 30-40\u00b0 C.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 3.47619
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11297396', '15708829', '15768634', '14347124', '15128112']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9017080470424954
- 35 USC 102 Novelty (BERT): 0.5180039445258634
- Combined Prediction Score: 0.8633376367908322
- Mean Citation Score: 177.738822
- Max Citation Score: 185.04344
- Similarity Product: 97.76755732940197

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test