PATENT CLAIM ANALYSIS

Application Number: 15916513
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "192000"]

Abstract:
A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.

Claim (Index 14):
A semiconductor device comprising:\n a first conductivity type finFET device comprising:\n a first active fin; \n a first gate structure intersecting the first active fin and extending in a first direction; \n first embedded sources/drains that comprise a first material having a first etch rate and are on the first active fin; and \n first contact plugs partially covering the first embedded sources/drains, respectively, \n wherein each of the first embedded sources/drains comprises an upper surface comprising a recessed portion that extends parallel to the first direction and an outer raised portion that is raised relative to the recessed portion and is between the recessed portion and the first gate structure, \n wherein each of the recessed portions of the first embedded sources/drains extends beyond a corresponding one of the first contact plugs in the first direction, and \n wherein each of the first embedded sources/drains comprises opposing ends that are spaced apart from each other in the first direction, and each of the recessed portions of the first embedded sources/drains extends from a first one of the opposing ends to a second one of the opposing ends; and \n a second conductivity type finFET device comprising second embedded sources/drains,\n wherein the second embedded sources/drains comprise a second material having a second etch rate that is greater than the first etch rate, and \n wherein each of the second embedded sources/drains comprises an upper surface that is at a different level than upper surfaces of the outer raised portions of the first conductivity type finFET device.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.65
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14990863', '15093145', '15697689', '15145924', '15413472']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9201415029205614
- 35 USC 102 Novelty (BERT): 0.4942514413081872
- Combined Prediction Score: 0.877552496759324
- Mean Citation Score: 241.169052
- Max Citation Score: 252.98322
- Similarity Product: 196.0389638736427

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test