PATENT CLAIM ANALYSIS

Application Number: 16296448
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["257", "190000"]

Abstract:
A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Claim (Index 1):
A semiconductor device comprising:\n a semiconductor substrate with a surface; a channel region in the semiconductor substrate; a gate electrode over the channel region and the surface of the semiconductor substrate, the gate electrode tapering in a cross section; in the cross section a gate insulating film within which is positioned the gate electrode, the gate insulating film having a bottom portion between the gate electrode and the channel region and side portions on opposite sides of the gate electrode, the side portions thinning proceeding away for the channel region in accordance with the tapering of the gate electrode; a source region in the semiconductor substrate at a source side of the channel region and a drain region in the semiconductor substrate at a drain side of the channel region; a first stress-introducing layer in the semiconductor substrate, the source region and the drain region being between the first stress-introducing layer and the surface of the semiconductor substrate; a second stress-introducing layer; and a first side-wall insulating film between the second stress-introducing layer and the gate electrode, wherein,\n in a gate length direction in the cross section, the source region and the drain region are within the first stress-introducing layer, and \n in the gate length direction in the cross section, ends of the first stress-introducing layer are positioned inward of outer ends of the first side-wall insulating layer.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 99.0
- Lexical Diversity: 2.42222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15416739', '15907936', '15091146', '14819115', '12783248']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.945753662654512
- 35 USC 102 Novelty (BERT): 0.5303661938882018
- Combined Prediction Score: 0.904214915777881
- Mean Citation Score: 356.37344
- Max Citation Score: 359.09192
- Similarity Product: 292.2782459056425

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test