PATENT CLAIM ANALYSIS

Application Number: 15927044
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "230010"]

Abstract:
A circuit includes a data line, a first cell in a first row of a memory array, and a second cell in a second row of the memory array. The first cell is electrically coupled with the data line and the second cell is electrically coupled with the data line. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a first read operation on the first row.

Claim (Index 16):
A method of configuring a memory circuit, the method comprising:\n identifying a weak row of cells of the memory circuit based on a speed of a test read operation on the weak row meeting a first speed criterion; storing address information corresponding to an address of the weak row in a storage device; and during subsequent read operations on the weak row, simultaneously reading data from the weak row and from a second row of cells of the memory circuit based on the stored address information.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.70968
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13273705', '14995387', '13489055', '14958149', '11476023']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7795712857611307
- 35 USC 102 Novelty (BERT): 0.4670170864301848
- Combined Prediction Score: 0.7483158658280361
- Mean Citation Score: 162.932648
- Max Citation Score: 165.30700000000004
- Similarity Product: 119.8024223442674

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test