PATENT CLAIM ANALYSIS

Application Number: 15997389
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "189050"]

Abstract:
Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. The method can include storing the first bit-vector in a number of memory cells coupled to the first access line and a second number of sense lines and storing the second bit-vector in a number of memory cells coupled to the first access line and a third number of sense lines, wherein a quantity of the first number of sense lines is less than a quantity of the second and third number of sense lines.

Claim (Index 32):
The method of  claim 31 , further comprising storing the second bit-vector in the number of memory cells coupled to the first access line and a third, fourth, seventh, and eighth ordered sense lines of the number of sense lines.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 94.0
- Lexical Diversity: 3.5
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15179338', '15645238', '14834065', '15063986', '15905083']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7928959838538442
- 35 USC 102 Novelty (BERT): 0.5129805727453931
- Combined Prediction Score: 0.7649044427429991
- Mean Citation Score: 279.84903
- Max Citation Score: 303.18826
- Similarity Product: 212.3992824568272

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test