PATENT CLAIM ANALYSIS

Application Number: 15968219
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-04
Patent Classification: ["365", "193000"]

Abstract:
A semiconductor device includes: a clock generation circuit suitable for generating first and second write clocks that correspond respectively to a rising clock and a falling clock of an external clock during a write leveling operation, and for generating an input clock based on a delay of a write command by a delay time based on the rising clock during a write operation; a first transmission line suitable for transmitting the first write clock or the input clock as a first transmission clock; and a second transmission line suitable for transmitting the second write clock as a second transmission clock.

Claim (Index 11):
The semiconductor device of  claim 9 , wherein the write leveling control block includes:\n a first driving unit suitable for driving a first common node based on the first comparison signal; a second driving unit suitable for driving the first common node based on the second comparison signal; a third driving unit suitable for driving a second common node based on the third comparison signal; a fourth driving unit suitable for driving the second common node based on the fourth comparison signal; and a determining unit suitable for determining whether voltages of the first and second common nodes are the same or different to generate the leveling control signal when the mode control signal is activated.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 93.0
- Lexical Diversity: 2.33333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12965092', '12856131', '11878074', '12584937', '10189577']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8170948613170101
- 35 USC 102 Novelty (BERT): 0.4847985129296397
- Combined Prediction Score: 0.7838652264782731
- Mean Citation Score: 222.151356
- Max Citation Score: 233.74838
- Similarity Product: 177.00920958855153

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test