PATENT CLAIM ANALYSIS

Application Number: 15768546
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["365", "148000"]

Abstract:
A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

Claim (Index 12):
The circuit of  claim 11 , wherein the reference cell in the LRS is selected when the read voltage is applied to the reference cell via the memory row address.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 91.0
- Lexical Diversity: 3.2
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15325040', '15111194', '14678889', '14297446', '13844923']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7794802988905384
- 35 USC 102 Novelty (BERT): 0.4978704325196881
- Combined Prediction Score: 0.7513193122534534
- Mean Citation Score: 203.893062
- Max Citation Score: 209.1135
- Similarity Product: 136.0045750072897

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test