PATENT CLAIM ANALYSIS

Application Number: 16029603
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Claim (Index 2):
The method according to  claim 1 , wherein the first evaluate transistor and the second evaluate transistor are a single evaluate transistor, the third node and the interconnecting node of the decoder are pulled to the low state, by the single evaluate transistor, based on being in the evaluation phase of the evaluation clock.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 95.0
- Lexical Diversity: 1.79592
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16029604', '16029577', '15796819', '16029607', '15613185']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.783609071905306
- 35 USC 102 Novelty (BERT): 0.5753782777908124
- Combined Prediction Score: 0.7627859924938567
- Mean Citation Score: 465.365266
- Max Citation Score: 497.16586
- Similarity Product: 443.575762620616

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test