PATENT CLAIM ANALYSIS

Application Number: 15961547
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "005000"]

Abstract:
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Claim (Index 9):
The method of  claim 8 , wherein forming the plurality of first cavities comprises:\n removing, through the plurality of first vias, a portion of the placeholder material from the placeholder layer.

Metadata:
- Claim Count in Document: 132.0
- Percentile: 91.0
- Lexical Diversity: 1.9625
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15660829', '15925536', '15893100', '15687038', '12194243']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917753856751308
- 35 USC 102 Novelty (BERT): 0.4897580026164242
- Combined Prediction Score: 0.8749542713378197
- Mean Citation Score: 169.62562599999995
- Max Citation Score: 182.24725
- Similarity Product: 128.09069528099894

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test