PATENT CLAIM ANALYSIS

Application Number: 16408808
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-12
Patent Classification: ["341", "158000"]

Abstract:
An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an n th  input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2 (n) *a unit capacitance (C UNIT ). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

Claim (Index 9):
An adder circuit configured to draw a sum output node to a voltage proportional to a sum of received binary numbers, the adder circuit comprising:\n a plurality of sections including a most significant (MS) section, each section of the plurality of sections having a respective local sum node and a local reset device configured to draw, in response to receiving a reset signal, the respective local sum node to a reference voltage, the local sum node of the MS section being the sum output node; a plurality of attenuation capacitors, each attenuation capacitor of the plurality of attenuation capacitors having first and second terminals electrically interconnected to respective local sum nodes of electrically adjacent sections of the plurality of sections; a first set of scaled capacitors including at least one capacitor located within each section of the plurality of sections, the first set of scaled capacitors further including a first MS capacitor located within the MS section, the first MS capacitor having an input terminal electrically connected to an MS input of a first set of inputs, each capacitor of the first set of scaled capacitors having an input terminal electrically connected to a corresponding input of the first set of inputs, an output terminal electrically connected to a respective local sum node; a second set of scaled capacitors including at least one capacitor located within each section of the plurality of sections, the second set of scaled capacitors further including a second MS capacitor located within the MS section, the second MS capacitor having an input terminal electrically connected to an MS input of the second set of inputs, each capacitor of the second set of scaled capacitors having an input terminal electrically connected to a corresponding input of a second set of inputs, an output terminal electrically connected to a respective local sum node; and a reference capacitor electrically connected to a reference voltage, and further electrically connected to a local sum node of a least significant (LS) section of the plurality of sections, a reference capacitor value equal to a sum of values of each of the LS scaled capacitors of the first and second sets of scaled capacitors.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.1831
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16018108', '16408881', '16018113', '16162431', '16162437']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6269247383528554
- 35 USC 102 Novelty (BERT): 0.574417682699787
- Combined Prediction Score: 0.6216740327875486
- Mean Citation Score: 392.237716
- Max Citation Score: 457.00742
- Similarity Product: 413.7263754227209

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test