PATENT CLAIM ANALYSIS

Application Number: 15922332
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["326", "030000"]

Abstract:
A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

Claim (Index 13):
A memory system comprising:\n a memory module including an external resistor and a plurality of memory devices including a first memory device and a second memory device, wherein the external resistor is formed in a module board and the plurality of memory devices are commonly connected to the external resistor; and a memory controller configured to control the memory module, wherein each of the plurality of memory devices comprises: a first reception pad associated with receiving an impedance calibration command; a first transmission pad associated with transmitting the impedance calibration command; an impedance pad connected to the external resistor; a selection pad; and an impedance calibration circuit connected to the first reception pad, the first transmission pad the impedance pad, and the selection pad, wherein each of the plurality of memory devices is configured to transfer the impedance calibration command to the first memory device, which is selected as a master among the plurality of memory devices, through a ring topology constituted by the first reception pad and the first transmission pad, wherein the first memory device is configured to perform an impedance calibration operation for the first memory device, to determine a resistance and a target output high level (VOH) voltage of an output driver, in response to the impedance calibration command, and is configured to transfer the impedance calibration command to the second memory device adjacent to the first memory device through the first transmission pad of the first memory device after performing the impedance calibration operation for the first memory device, and wherein the impedance calibration circuit comprises: a detector connected to the selection pad and configured to generate a detection signal; a command controller connected to the first reception pad and the first transmission pad, wherein the command controller is configured to receive the impedance calibration command from one of the first reception pad and a corresponding command detector; and a calibration circuit connected to the external resistor through the impedance pad, wherein the calibration circuit is configured to perform the impedance calibration operation in response to a calibration enable signal from the command controller to output a pull-up control code and a pull-down control code to the output driver and is configured to provide the command controller with a first comparison signal and a second comparison signal which indicate a completion of the impedance calibration operation.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 2.52632
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15390851', '14723614', '15426603', '14460764', '15729771']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6821923405345642
- 35 USC 102 Novelty (BERT): 0.5214492874731315
- Combined Prediction Score: 0.666118035228421
- Mean Citation Score: 269.301476
- Max Citation Score: 354.9375
- Similarity Product: 278.96547822654253

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test