PATENT CLAIM ANALYSIS

Application Number: 15911901
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["714", "798000"]

Abstract:
There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.

Claim (Index 1):
A synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises:\n a data path; a hard macro having a macro input; a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input; a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit; wherein during normal operation the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 90.0
- Lexical Diversity: 2.66667
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12888367', '13838053', '09466665', '13078151', '12167073']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2989158798760518
- 35 USC 102 Novelty (BERT): 0.5016893898996172
- Combined Prediction Score: 0.3191932308784084
- Mean Citation Score: 239.705508
- Max Citation Score: 258.43552
- Similarity Product: 195.79492686443328

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test