PATENT CLAIM ANALYSIS

Application Number: 15913387
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["363", "041000"]

Abstract:
Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θ e *. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.

Claim (Index 15):
The method of  claim 11 , wherein the turn-on time values and switching sequence are predetermined for each sector and region.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 1.70238
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15493978', '15694135', '13547562', '12394613', '15315128']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8380476433623619
- 35 USC 102 Novelty (BERT): 0.5294631681976032
- Combined Prediction Score: 0.8071891958458861
- Mean Citation Score: 252.825876
- Max Citation Score: 398.51974
- Similarity Product: 274.1803077355349

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test