PATENT CLAIM ANALYSIS

Application Number: 16128819
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "369000"]

Abstract:
A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect transistor (nFET), the nFET including a high-k dielectric layer on an interlayer. The CMOS circuit also includes a p-channel field effect transistor (pFET), the pFET including the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal. Metal atoms from the cap layer do not intermix with the interlayer.

Claim (Index 13):
The method according to  claim 1 , wherein the maintaining the temperature minimizes a change in threshold voltage of the device over a period of use.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 97.0
- Lexical Diversity: 1.92157
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14585401', '15068940', '14947350', '15254192', '15178189']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926650972369886
- 35 USC 102 Novelty (BERT): 0.4967762290056533
- Combined Prediction Score: 0.8836634980334628
- Mean Citation Score: 241.841232
- Max Citation Score: 293.26575
- Similarity Product: 291.0118786899448

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test