PATENT CLAIM ANALYSIS

Application Number: 16023120
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "329000"]

Abstract:
A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.

Claim (Index 9):
The method as recited in  claim 1 , wherein the vertical transistor is a part of a logic device and the logic device connects to the bottom side and the top side metallization structures.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.29268
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15676461', '15403297', '15164420', '15615248', '15921930']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9282382613716388
- 35 USC 102 Novelty (BERT): 0.5404786308766445
- Combined Prediction Score: 0.8894622983221394
- Mean Citation Score: 278.812924
- Max Citation Score: 383.2441
- Similarity Product: 350.01442948559514

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test