PATENT CLAIM ANALYSIS

Application Number: 16054784
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["710", "263000"]

Abstract:
Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.

Claim (Index 11):
The semiconductor integrated circuit device according to  claim 10 , wherein the comparison circuit includes:\n a first flag register to which a value indicating whether the data stored in the first buffer is valid is set; a second flag register to which a value indicating whether the data stored in the second buffer is valid is set; and a clear signal generating circuit which generates a clear signal for clearing the values indicating that the data respectively set to the first flag register and the second flag register are valid, wherein when the first value or the second value is set to the first transfer mode setting field, and the count value of the comparison frequency counter is a value smaller by one than the number of times of the transfer set to the transfer frequency setting field, the clear signal generating circuit outputs the clear signal to the first flag register when the first data and the second data are compared, and when the third value is set to the first transfer mode setting field, the clear signal generating circuit outputs the clear signal to the first flag register each time the first data and the second data are compared, and wherein when the first value or the second value is set to the second transfer mode setting field, and the count value of the comparison frequency counter is a value smaller by one than the number of times of the transfer set to the transfer frequency setting field, the clear signal generating circuit outputs the clear signal to the second flag register when the first data and the second data are compared, and when the third value is set to the second transfer mode setting field, the clear signal generating circuit outputs the clear signal to the second flag register each time the first data and the second data are compared.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 96.0
- Lexical Diversity: 3.07547
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13437297', '12595381', '11037092', '10887843', '13305133']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6850030289860563
- 35 USC 102 Novelty (BERT): 0.487089457286163
- Combined Prediction Score: 0.6652116718160669
- Mean Citation Score: 168.776876
- Max Citation Score: 178.21396
- Similarity Product: 115.84325496868132

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test