PATENT CLAIM ANALYSIS

Application Number: 15924835
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["327", "156000"]

Abstract:
A circuit device includes a drive circuit configured to drive a physical quantity transducer by a drive signal, a PLL circuit configured to generate a clock signal by using a drive signal as a reference signal, and a measurement circuit that includes a circuit which is operated by an operation signal based on the clock signal and performs measurement processing based on a measurement signal from the physical quantity transducer, and the PLL circuit generates the clock signal having a frequency of j×fdr≠fck/i in a case where it is set that a frequency of the drive signal is fdr, a frequency of the clock signal is fck, i is an integer of 1 or more, j is an integer of 1 or more, and a frequency of the operation signal is fck/i.

Claim (Index 7):
The circuit device according to  claim 1 ,\n wherein the PLL circuit includes a voltage-controlled oscillator (VCO), and the VCO is any one of a CR oscillation circuit, an LC oscillation circuit, and a ring oscillator.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 90.0
- Lexical Diversity: 2.59259
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14996524', '15082319', '14552979', '15901044', '14564554']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7996209951772535
- 35 USC 102 Novelty (BERT): 0.4923240093430229
- Combined Prediction Score: 0.7688912965938304
- Mean Citation Score: 215.43433
- Max Citation Score: 252.78914
- Similarity Product: 195.6253419442952

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test