PATENT CLAIM ANALYSIS

Application Number: 16232945
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["711", "159000"]

Abstract:
Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.

Claim (Index 7):
The data storage system of  claim 1 , wherein:\n one or more of the memory blocks have pages forming a first group of memory locations (BA) and a second group of memory locations (DA), wherein the processor is configured to: write data into the pages of the BA changing the pages in the BA from a free page to a live page; increment a write counter or pointer (WP) for each write operation to the BA causing the WP to count or point to a next free page in the BA; when the WP reaches the end of the BA, continue to write data into pages of the DA changing the pages in the DA from free pages to live pages; increment the WP for each write operation to the DA causing the WP to point to a next free page in the DA; and for each write operation to the DA, also move a live page of data out of the BA to another memory page location changing the live page of data in the BA to a dead page of data to reduce a number of live pages in the BA that have to be moved prior to scheduling an erase operation for the memory block.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 98.0
- Lexical Diversity: 1.82558
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16052513', '14965339', '15046182', '12273410', '13863149']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5835781164431825
- 35 USC 102 Novelty (BERT): 0.5500587984731491
- Combined Prediction Score: 0.5802261846461791
- Mean Citation Score: 270.10574599999995
- Max Citation Score: 426.1860400000001
- Similarity Product: 366.7368376666117

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test