PATENT CLAIM ANALYSIS

Application Number: 15891351
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "185170"]

Abstract:
According to one embodiment, a semiconductor memory device comprises a first memory cell array including a first block and a second block, the first block including a first memory cell, and the second block including a second memory cell; and a controller that performs, in a first period of time in writing, a first program in the first memory cell and the second memory cell.

Claim (Index 2):
The device of  claim 1 , wherein the controller performs, in a second period of time after the first period of time, a first verify in the first memory cell.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.48276
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15459542', '15695470', '13837814', '15700864', '15710381']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8002503218910788
- 35 USC 102 Novelty (BERT): 0.4613455688828587
- Combined Prediction Score: 0.7663598465902568
- Mean Citation Score: 160.13489199999995
- Max Citation Score: 161.67757
- Similarity Product: 124.09800740671156

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test