PATENT CLAIM ANALYSIS

Application Number: 16418617
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["257", "331000"]

Abstract:
A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Claim (Index 1):
A semiconductor device in a face-down, chip-size package, including: a semiconductor substrate that is rectangular and includes an impurity of a first conductivity type; a low-concentration impurity layer that is in contact with a top surface of the semiconductor substrate and includes an impurity of the first conductivity type in a lower concentration than a concentration of the impurity of the first conductivity type included in the semiconductor substrate; and a metal layer that is in contact with a bottom surface of the semiconductor substrate and includes a metal material, the semiconductor device comprising:\n a first vertical metal oxide semiconductor (MOS) transistor in a first region of the low-concentration impurity layer; and a second vertical MOS transistor in a second region of the low-concentration impurity layer adjacent to the first region, wherein the first vertical MOS transistor includes, on a surface of the low-concentration impurity layer, a first gate electrode and a first group of source electrodes, the second vertical MOS transistor includes, on the surface of the low-concentration impurity layer, a second gate electrode and a second group of source electrodes, in a plan view of the semiconductor substrate, the first group of source electrodes and the second group of source electrodes are arranged in stripes extending along a lengthwise direction of the semiconductor substrate, the first group of source electrodes includes two first source electrodes respectively disposed in regions near two long sides of the semiconductor substrate, and two second source electrodes respectively disposed in regions farther inward of the semiconductor substrate from the two long sides than the two first source electrodes, the second group of source electrodes includes two third source electrodes respectively disposed in regions near the two long sides of the semiconductor substrate, and two fourth source electrodes respectively disposed in regions farther inward of the semiconductor substrate from the two long sides than the two third source electrodes, a length of each of the two second source electrodes in a lengthwise direction of the two second source electrodes is shorter than a length of each of the two first source electrodes in a lengthwise direction of the two first source electrodes, a length of each of the two fourth source electrodes in a lengthwise direction of the two fourth source electrodes is shorter than a length of each of the two third source electrodes in a lengthwise direction of the two third source electrodes, a center of the first gate electrode is located between lengthwise extensions of the two second source electrodes, and a center of the second gate electrode is located between lengthwise extensions of the two fourth source electrodes.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 100.0
- Lexical Diversity: 3.7027
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16146272', '14846947', '12893297', '13381605', '14991877']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9205622648557034
- 35 USC 102 Novelty (BERT): 0.566048697112277
- Combined Prediction Score: 0.8851109080813607
- Mean Citation Score: 266.31983
- Max Citation Score: 440.96924
- Similarity Product: 421.2991163027334

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test