PATENT CLAIM ANALYSIS

Application Number: 15863566
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["716", "108000"]

Abstract:
An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.

Claim (Index 20):
The non-transitory computer readable storage medium of  claim 11 , wherein the instructions to configure the emulator to output the edge on the clock signal comprise instructions that configure the emulator to:\n wait for at least one system fast clock cycles to pass; and output the edge after the at least one system fast clock cycles have past.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.59259
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14952656', '14703727', '14507687', '15179893', '12630629']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3099212934422127
- 35 USC 102 Novelty (BERT): 0.5112931116658168
- Combined Prediction Score: 0.3300584752645731
- Mean Citation Score: 193.302972
- Max Citation Score: 310.6329
- Similarity Product: 202.65840890212647

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test