PATENT CLAIM ANALYSIS

Application Number: 15921715
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Claim (Index 7):
A method comprising:\n doping a substrate to have an active region bordered by an isolation region; doping the active region to have a channel area; growing a gate insulator on and contacting the channel area; patterning a first gate conductor on and contacting the gate insulator, the gate insulator is between the first gate conductor and the channel area, the first gate conductor is patterned to extend from the active region to the isolation region, the first gate conductor is patterned to have a first section, a second section, and a third section, the second section of the first gate conductor is between the first section and the third section of the first gate conductor, the first section of the first gate conductor is within the active region and has a first width, the third section of the first gate conductor is within the isolation region and has a second width that is greater than the first width, and the second section of the first gate conductor is within the active region and has a tapered width that tapers from the first width to the second width; patterning a second gate conductor perpendicular to the first gate conductor, the gate insulator is between the substrate and the second gate conductor, the second gate conductor has a fourth section within the active region, and the fourth section of the second gate conductor faces the first section of the first gate conductor; forming undercut regions in the first section and the second section of the first gate conductor where a corner of the first gate conductor contacts the gate insulator, and in the fourth section of the second gate conductor where the second gate conductor contacts the second gate insulator, wherein the third section of the first gate conductor lacks the undercut regions; forming additional amounts of the gate insulator in the undercut regions, the gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the first gate conductor lacks the undercut regions in the isolation region; and doping the active region to have a source area and a drain area, the channel area is between the source area and the drain area.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.96296
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14982459', '13289051', '14493749', '11728111', '11764751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8959516478355934
- 35 USC 102 Novelty (BERT): 0.5444281872873391
- Combined Prediction Score: 0.860799301780768
- Mean Citation Score: 232.737716
- Max Citation Score: 381.51627
- Similarity Product: 306.67907748661105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test