PATENT CLAIM ANALYSIS

Application Number: 16384819
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-10
Patent Classification: ["712", "201000"]

Abstract:
According to some embodiments, a dataflow accelerator comprises a control/command core, a scratchpad and a coarse grain reconfigurable array (CGRA). The scratchpad comprises a write controller to transmit data to an input vector port interface and to receive data from the input vector port interface. The CGRA receives data from the input vector port interface where the CGRA comprising a plurality of interconnects and a plurality of functional units.

Claim (Index 18):
A non-transitory computer-readable medium comprising processor executable instructions that when executed by a processor perform a method of flow control through a coarse grain reconfigurable array (CGRA), the method comprising:\n receiving data from a plurality of stream engines at a CGRA including a plurality of interconnects and a plurality of functional units; delaying the received data to control flow through the CGRA; processing the data via the functional units; and outputting a result to a plurality of output vector ports.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 100.0
- Lexical Diversity: 1.80952
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13012945', '14330675', '13929762', '15215374', '15216624']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5365775553310066
- 35 USC 102 Novelty (BERT): 0.467185944640085
- Combined Prediction Score: 0.5296383942619145
- Mean Citation Score: 135.25886200000002
- Max Citation Score: 148.15508
- Similarity Product: 107.72688119871616

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test