PATENT CLAIM ANALYSIS

Application Number: 15910152
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["323", "271000"]

Abstract:
A regulator amplifier circuit of an embodiment includes a differential amplifier circuit, an nMOS transistor, and a pMOS transistor. The differential amplifier circuit includes a differential circuit and a transistor. The differential circuit includes a differential MOS transistor circuit, and the transistor includes a gate voltage controlled by the differential circuit. The nMOS transistor includes a drain connected to a drain on minus side of the differential MOS transistor, and a gate connected to a source of the transistor. The nMOS transistor operates in a weak inversion region. The pMOS transistor includes a source connected to a source of the AMOS transistor, and a drain connected to a voltage lower than a source voltage of the nMOS transistor. The pMOS transistor operates in the weak inversion region.

Claim (Index 8):
The regulator amplifier circuit according to  claim 7 , wherein the other of the first and second nMOS transistors is provided with a load current and a load capacitance.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 3.65789
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13064935', '11195263', '13038163', '12822832', '12754860']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7530813654867308
- 35 USC 102 Novelty (BERT): 0.4842777935169664
- Combined Prediction Score: 0.7262010082897543
- Mean Citation Score: 211.082544
- Max Citation Score: 214.70003
- Similarity Product: 157.0625737546849

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test