PATENT CLAIM ANALYSIS

Application Number: 15959162
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["710", "010000"]

Abstract:
Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Claim (Index 10):
A control method for controlling a plurality of memory modules, each of the memory modules comprising a memory unit, a display unit and a micro control unit configured to control the display unit, the micro control units being connected to a central processing unit through a bus, and the control method comprising:\n instructing the micro control units by the central processing unit to initialize the display units; transmitting a control signal from the central processing unit to the micro control units according to a preset bus address after the initialization of the display units is completed; and based on the control signal, synchronously controlling the display units by the micro control units; wherein each of the micro control units comprises a bus address that is the same as the preset bus address.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 2.04255
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14148962', '12372123', '15641950', '12400343', '10998170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6553515949360352
- 35 USC 102 Novelty (BERT): 0.4590808280930662
- Combined Prediction Score: 0.6357245182517383
- Mean Citation Score: 150.02821
- Max Citation Score: 161.60112
- Similarity Product: 127.05132820238111

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test