PATENT CLAIM ANALYSIS

Application Number: 16024562
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "106000"]

Abstract:
A semiconductor device and a method for fabricating a semiconductor device are disclosed. The semiconductor device includes a tunnel field-effect transistor and a planar device. The tunnel field-effect transistor includes a first substrate and a first electrical element, and the first electrical element is formed on one side of the first substrate; the planar device includes a second substrate and a second electrical element, the second substrate and the first substrate are an integrated structure and form a main substrate, the second electrical element is formed on one side of the second substrate, and the second electrical element and the first electrical element are disposed on a same side of the main substrate; and the planar device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.

Claim (Index 4):
The semiconductor device according to  claim 3 , wherein:\n the first electrical element further comprises a first drain region, a second drain region, a first source region, a first insulation layer, a first gate dielectric layer, and a first gate region; the first drain region and the second drain region are embedded into the first substrate from the first surface; one end of the first drain region is flush with the first surface; one end of the second drain region is flush with the first surface; the first drain region and the second drain region are opposite to each other, separated by apart of the first substrate, and disposed between the first shallow trench isolation region and the second shallow trench isolation region; the first drain region is in contact with the first shallow trench isolation region; the second drain region is in contact with the second shallow trench isolation region; the first source region is disposed in a protruding manner on the first surface, and the first source region is located between the first drain region and the second drain region; the first insulation layer is disposed in a protruding manner on the first surface; the first insulation layer is symmetrically disposed on both sides of the first source region, and connected to a region between the first drain region and the first source region and a region between the second drain region and the first source region, and a thickness of the first insulation layer is less than a height of the first source region; the first gate dielectric layer is symmetrically disposed on the both sides of the first source region and is attached to a surface of the first source region and a surface of the first insulation layer; and the first gate region is disposed around the first gate dielectric layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 94.0
- Lexical Diversity: 3.30233
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13144182', '11133086', '13138053', '15238696', '11450112']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9287066698836588
- 35 USC 102 Novelty (BERT): 0.4981998492570626
- Combined Prediction Score: 0.8856559878209992
- Mean Citation Score: 249.302326
- Max Citation Score: 265.21716000000004
- Similarity Product: 212.9831887425471

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test