PATENT CLAIM ANALYSIS

Application Number: 15987075
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "774000"]

Abstract:
Provided are a semiconductor device and a method of manufacturing the same. The method may, for example, comprise forming an interposer on a dummy substrate; forming a conductive pillar on the interposer; contacting the top of the interposer with at least one semiconductor die; encapsulating the conductive pillar and the at least one semiconductor die with an encapsulant; forming a redistribution layer that is electrically connected to the conductive pillar, on the semiconductor die; removing the dummy substrate from the interposer; attaching the interposer, which has the at least one semiconductor die in contact, to a substrate and testing the at least one semiconductor die; and contacting a stacked semiconductor device with the redistribution layer.

Claim (Index 36):
A method of manufacturing a semiconductor device, the method comprising:\n providing a dummy substrate comprising a first surface; building a first multilayer structure directly on the first surface of the dummy substrate, the building comprising:\n providing a first circuit pattern directly on the first surface of the dummy substrate, \n applying a dielectric material that surrounds the first circuit pattern, and \n providing a second circuit pattern electrically connected to the first circuit pattern; \n positioning a first end of a conductive pillar on a first portion of the second circuit pattern exposed by the dielectric material; providing a conductive terminal on a bond pad of a semiconductor die to electrically connect a second portion of the second circuit pattern exposed by the dielectric material to the bond pad of the semiconductor die; encapsulating the conductive pillar, the semiconductor die, and the second surface of the first multilayer structure, with an encapsulant; providing a second multilayer structure over\n an exposed second end of the conductive pillar opposite the first end of the conductive pillar, \n an exposed second surface of the semiconductor die opposite the first surface of the semiconductor die, and \n a top surface of the encapsulant, \n to electrically interconnect the second multilayer structure to the second circuit pattern of the first multilayer structure via the conductive pillar; \n removing at least a portion of the dummy substrate to expose the first circuit pattern of the first multilayer structure; and attaching a conductive element of a stacked semiconductor device to an exposed circuit pattern of the second multilayer structure.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 2.48077
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14719539', '13863457', '15429591', '15207287', '14313724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9248343222704416
- 35 USC 102 Novelty (BERT): 0.4885437864024525
- Combined Prediction Score: 0.8812052686836426
- Mean Citation Score: 234.527334
- Max Citation Score: 253.8373
- Similarity Product: 211.07335396695137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test