PATENT CLAIM ANALYSIS

Application Number: 16027336
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["710", "062000"]

Abstract:
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Claim (Index 8):
The data-width translator of  claim 2 , further comprising an address translator to translate the temporal addresses into data-mask signals.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 95.0
- Lexical Diversity: 1.60256
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12606727', '11292407', '13282184', '14194923', '13627870']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6950842173143491
- 35 USC 102 Novelty (BERT): 0.4950357493940266
- Combined Prediction Score: 0.6750793705223169
- Mean Citation Score: 256.97587400000003
- Max Citation Score: 272.65536000000003
- Similarity Product: 214.28763102081305

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test