PATENT CLAIM ANALYSIS

Application Number: 16040419
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-04
Patent Classification: ["365", "207000"]

Abstract:
The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Claim (Index 19):
The memory device according to  claim 18 , wherein the time-to-discharge measurement circuit further comprises:\n an input stage having an input coupled to the signal node, and having an output coupled to the delay line, said input stage configured to generate a timing signal on its output when the signal node has fallen to a predetermined percentage of an initial voltage value.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 95.0
- Lexical Diversity: 1.65455
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16040442', '11715413', '12760262', '12710661', '10617046']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8158368186087925
- 35 USC 102 Novelty (BERT): 0.4907916368156169
- Combined Prediction Score: 0.783332300429475
- Mean Citation Score: 197.374626
- Max Citation Score: 261.6359
- Similarity Product: 209.4185566958428

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test