PATENT CLAIM ANALYSIS

Application Number: 16160622
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["361", "767000"]

Abstract:
An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Claim (Index 2):
The circuit board assembly of  claim 1 , wherein a ratio of grounded vias to a stacked via for a corresponding communication channel is greater than one to one.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 2.10959
- Patent Class: 361.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15474945', '15861877', '15627018', '11188080', '15187739']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8073081309615664
- 35 USC 102 Novelty (BERT): 0.6309523987748753
- Combined Prediction Score: 0.7896725577428974
- Mean Citation Score: 263.354102
- Max Citation Score: 561.7655
- Similarity Product: 559.0485548166632

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test