PATENT CLAIM ANALYSIS

Application Number: 15770020
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["257", "296000"]

Abstract:
A three-dimensional semiconductor device includes: A peripheral circuit, distributed on a substrate; a plurality of memory cells above the peripheral circuit, each of which includes: a common source region, between the memory cell and the peripheral circuit; a channel layer, distributed in a direction perpendicular to the surface of the substrate; at least one substrate contact layer, extending horizontally from the central portion of the channel layer parallel to the surface of the substrate, each comprising at least one substrate contact region; a plurality of insulating layers, located on sidewalls of the channel layer; a plurality of control gates, sandwiched between adjacent insulating layers; a gate dielectric layer, located between the channel layer and the control gates; a drain region, located at top of the channel layer; a substrate contact lead-out line, electrically connected to the substrate contact regions; and a bit line wiring, electrically connected to the drain region of each memory cell and the peripheral circuit. The substrate contact regions are formed in the middle of the memory strings, improving the erase/write performance and reliability of the memory, increasing the density of the storage array, reducing the entire memory chip area and saving the costs.

Claim (Index 6):
A three-dimensional semiconductor device manufacturing method, comprising the steps of:\n (a) forming a peripheral circuit on a substrate; (b) forming a common source region on the peripheral circuit; (c) forming a insulating layer stack, which comprises a plurality of first material layers and a plurality of second material layers alternately stacked; (d) etching the insulation layer stack to form a plurality of vertical openings, forming a gate dielectric layer on sidewalls of the openings, and forming a channel layer on sidewalls of each openings and top of the insulation layer stack; (e) recycling steps c and d until at least one substrate contact layer is formed in the channel layer on top of the adjacent insulating layer stacks; (f) forming a drain region on top of the channel layer; (g) selectively etching to remove the second material layers, and then forming a plurality of control gates in recesses between every two of the remaining first material layers; (h) etching the first material layers and the control gates to form a plurality of openings exposing the substrate contact layers, forming a substrate contact region at bottom of each of the openings, forming a substrate contact lead-out line in each of the openings; (i) forming a plurality of bit line wirings, electrically connecting the drain region and the peripheral circuit.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 2.64706
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15503833', '15306225', '15311000', '15211401', '13669021']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9023574382468104
- 35 USC 102 Novelty (BERT): 0.5001661149784153
- Combined Prediction Score: 0.8621383059199708
- Mean Citation Score: 227.289328
- Max Citation Score: 249.8829
- Similarity Product: 194.47002120591404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test