PATENT CLAIM ANALYSIS

Application Number: 15966032
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["438", "637000"]

Abstract:
Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

Claim (Index 4):
The method of  claim 3 , further comprising, prior to the etching the wire trench opening and the via opening, removing the mask barrier layer, exposing the patterned wire trench hard mask layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.10959
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15912975', '10379757', '10963268', '14540367', '10246061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.87145378055888
- 35 USC 102 Novelty (BERT): 0.5303132143388323
- Combined Prediction Score: 0.8373397239368753
- Mean Citation Score: 286.899104
- Max Citation Score: 356.33475
- Similarity Product: 212.94748842997848

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test