PATENT CLAIM ANALYSIS

Application Number: 16206539
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["438", "283000"]

Abstract:
A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

Claim (Index 4):
The system of  claim 2 , wherein the second pattern is configured to define a second contact-line-blocking pattern that partially defines borders for a second Vcc contact and a first Vss contact.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 98.0
- Lexical Diversity: 2.21277
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15691868', '14958592', '13446220', '12827690', '12823860']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8328902230867821
- 35 USC 102 Novelty (BERT): 0.5190617041223192
- Combined Prediction Score: 0.8015073711903358
- Mean Citation Score: 180.248024
- Max Citation Score: 284.82416
- Similarity Product: 206.7158789438629

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test