PATENT CLAIM ANALYSIS

Application Number: 15767605
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["257", "431000"]

Abstract:
The present disclosure relates to a semiconductor device, an array substrate, and a method for fabricating the semiconductor device. The semiconductor device comprises a substrate, a thin film transistor formed on the substrate, and a first light detection structure adjacent to the thin film transistor, wherein the first light detection structure includes a first bottom electrode, a top electrode, and a first photo-sensing portion disposed between the first bottom electrode and the first top electrode, one of a source electrode and a drain electrode of the thin film transistor is disposed in the same layer as the first bottom electrode of the first light detection structure; the other of the source electrode and the drain electrode of the thin film transistor is used as the first top electrode.

Claim (Index 15):
The method for fabricating a semiconductor device according to  claim 14 , wherein,\n forming the first sub-conductive layer and the second sub-conductive layer on the substrate comprises: forming a first conductive layer on the substrate; patterning the first conductive layer to form the first sub-conductive layer and the second sub-conductive layer separated by the space, forming the first spacing layer and forming the second spacing layer comprises: disposing a first capping layer on the space, the first side surface, a top surface of the first top electrode and the second side surface; patterning the first capping layer such that the patterned first capping layer comprises a first opening on the top surface of the first top electrode to form the first spacing layer and the second spacing layer spaced apart by the first opening, forming the first semiconductor layer and the second semiconductor layer comprises: forming a layer of semiconductor material on the first spacing layer and the second spacing layer; patterning the layer of semiconductor material such that the patterned layer of semiconductor material comprises a second opening on the top surface of the first top electrode to form the first semiconductor layer and the second semiconductor layer spaced apart by the second opening, and wherein the second opening and the first opening are aligned and the first semiconductor layer is in contact with the first top electrode.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 91.0
- Lexical Diversity: 2.78
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11011778', '16077846', '12331361', '15866309', '12472979']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9223288925384336
- 35 USC 102 Novelty (BERT): 0.4826459125932139
- Combined Prediction Score: 0.8783605945439116
- Mean Citation Score: 191.910618
- Max Citation Score: 196.76344
- Similarity Product: 146.7917522209263

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test