PATENT CLAIM ANALYSIS

Application Number: 15954864
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-06
Patent Classification: ["365", "145000"]

Abstract:
A vertical ferroelectric thin film storage transistor and a data write and read method thereof are disclosed. The vertical ferroelectric thin film storage transistor includes a substrate having a first surface, a first conductive structure, a first insulating layer, a second conductive structure, and a second insulating layer sequentially disposed above a first surface of a substrate, and a vertical hole penetrates through the layers in a direction substantially perpendicular to the first surface of the substrate. A channel layer is disposed on a wall surface of the vertical hole and in electrical contact with the first conductive structure and the second conductive structure. An inner dielectric layer is disposed on one side of the channel layer. A ferroelectric layer is disposed on one side of the inner dielectric layer. A gate structure is disposed on one side of the ferroelectric layer. A third conductive structure is disposed above the second insulating layer or in the substrate, and in electrical contact with the third conducting structure and the gate structure.

Claim (Index 1):
A vertical ferroelectric thin film storage transistor, comprising:\n a substrate having a first surface; a first conductive structure disposed above the first surface of the substrate; a first insulating layer disposed above the first conductive structure; a second conductive structure disposed above the first insulating layer; a second insulating layer disposed above the second conductive structure; a vertical hole penetrating through the second insulating layer, the second conductive structure, the first insulating layer, the first conductive structure and the substrate in a direction substantially perpendicular to the first surface; a channel layer disposed on a wall surface of the vertical hole and being in electrical contact with the first conductive structure and the second conductive structure; an inner dielectric layer disposed on one side of the channel layer in the vertical hole; a ferroelectric layer disposed on one side of the inner dielectric layer in the vertical hole; a gate structure disposed on one side of the ferroelectric layer in the vertical hole; and a third conductive structure disposed above the second insulating layer or in the substrate, and being in electrical contact with the gate structure.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 91.0
- Lexical Diversity: 3.10169
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10978431', '10978523', '11286951', '11544748', '13108340']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7972385639828604
- 35 USC 102 Novelty (BERT): 0.4797525391958593
- Combined Prediction Score: 0.7654899615041603
- Mean Citation Score: 219.559786
- Max Citation Score: 223.88702
- Similarity Product: 168.98254792021513

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test