PATENT CLAIM ANALYSIS

Application Number: 16185921
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["326", "008000"]

Abstract:
A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

Claim (Index 1):
A method for generating a bitstring for a physically unclonable function, the method comprising the steps of:\n measuring delay from logic paths of varying lengths; recording a digitized representation of the measured path delays, wherein the digitized representation comprises physically unclonable function numbers (PNs); determining one or more long path delays from the recorded path delays; applying a modulus operation to remove bias, the modulus operation removing higher order PNs of the one or more long path delays; and comparing path delays of an approximate length.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 98.0
- Lexical Diversity: 1.34615
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14913454', '15534116', '15109747', '16051427', '14907423']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6893000631019074
- 35 USC 102 Novelty (BERT): 0.5888438138789182
- Combined Prediction Score: 0.6792544381796084
- Mean Citation Score: 343.219078
- Max Citation Score: 532.3981
- Similarity Product: 434.95926843435166

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test