PATENT CLAIM ANALYSIS

Application Number: 15882250
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["438", "584000"]

Abstract:
A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.

Claim (Index 2):
The method recited in  claim 1  including chemically reducing the initial gate metal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 1.82927
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15438196', '15438148', '11557354', '14733465', '13849858']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8941059054670477
- 35 USC 102 Novelty (BERT): 0.5352271008433735
- Combined Prediction Score: 0.8582180250046804
- Mean Citation Score: 276.037412
- Max Citation Score: 369.94965
- Similarity Product: 203.2131498276829

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test