PATENT CLAIM ANALYSIS

Application Number: 15768710
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["345", "173000"]

Abstract:
The present invention is related to a gate driving circuit. The gate driving circuit may comprise at least two scan modules coupled to a same clock signal. Each of the at least two scan modules may have an input terminal, a reset terminal, and at least one stage of shift register unit. The reset terminal of at least one of the at least two scan modules is coupled to a touch control enable signal line.

Claim (Index 1):
A gate driving circuit comprising:\n at least two scan modules coupled to a same clock signal, each of the at least two scan modules having an input terminal, a reset terminal, and at least one stage of shift register unit, wherein the reset terminal of at least one of the at least two scan modules is coupled to a touch control enable signal line, and wherein each of the at least two scan modules is configured to enable the at least one stage of the shift register unit thereof to output a gate turning-on voltage stage by stage, starting from the first stage, in accordance with a flip of a level of the clock signal when the input terminal thereof receives an active level and to stop the last stage of the shift register unit thereof from outputting a gate turning-on voltage when the reset terminal thereof receives an active level.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 91.0
- Lexical Diversity: 1.97561
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15513154', '15133398', '15131470', '15502983', '14429026']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6733952164352204
- 35 USC 102 Novelty (BERT): 0.48888171829855
- Combined Prediction Score: 0.6549438666215535
- Mean Citation Score: 263.147496
- Max Citation Score: 268.4536
- Similarity Product: 239.0902234145641

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test