PATENT CLAIM ANALYSIS

Application Number: 15977826
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["341", "120000"]

Abstract:
An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

Claim (Index 10):
A method comprising:\n receiving a pair of differential input signals and a configuration signal; generating a pair of differential signals by processing the pair of differential input signals according to the configuration signal; and converting the pair of differential signals to a digital conversion code corresponding to a difference between the pair of differential input signals using a differential analog-to-digital converter (ADC), wherein the differential ADC comprises a voltage-controlled oscillator (VCO), two counters, and an error generator block, wherein the VCO included in the ADC receives the pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the pair of differential signals, wherein each of the two counters receives a respective pulse signal of the two pulse signals from the VCO and generates a digital counter value, and wherein the error generator block receives digital counter values from the two counters and generates a digital conversion code corresponding to a difference between the two digital counter values.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 2.82857
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15673234', '15951029', '15656978', '14801620', '15921201']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5311623773713037
- 35 USC 102 Novelty (BERT): 0.6214294669111122
- Combined Prediction Score: 0.5401890863252845
- Mean Citation Score: 295.471044
- Max Citation Score: 570.86456
- Similarity Product: 485.8926837089634

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test