PATENT CLAIM ANALYSIS

Application Number: 16275038
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-09
Patent Classification: ["365", "185170"]

Abstract:
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

Claim (Index 2):
A memory array, comprising:\n multiple strings of vertically arranged memory cells, each memory cell including a charge storage structure, each memory string extending between a source and a respective bit line of multiple bit lines, wherein the bit lines extend in a first direction; a first group of memory cell strings each selectively coupled to a first bit line through a respective select device in each memory cell string; a second group of memory cell strings each selectively coupled to a second bit line through a respective select device in each memory cell string, wherein the second bit line is stacked above the first bit line, and wherein the first and second groups of memory cell strings are interleaved with one another along the first direction in which the first and second bit lines extend; access lines coupled to respective memory cells in each of the first and second groups of memory cell strings, each access line configured to allow access to a respective memory cell in each of the first and second groups of memory cell strings to perform a memory operation involving such memory cell; a memory controller configured to perform a shielded bit line sensing operation, in which the first bit line is coupled to a shield potential during at least a portion of sensing interval in which the state of a selected memory cell in a selected memory cell string of the second group of memory cell strings is sensed, and wherein during the sensing interval the selected memory cell is coupled to the second bit line.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.52
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15676659', '14867948', '13919599', '12502771', '11432135']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7944428666464453
- 35 USC 102 Novelty (BERT): 0.4702225127596375
- Combined Prediction Score: 0.7620208312577644
- Mean Citation Score: 212.896042
- Max Citation Score: 257.62024
- Similarity Product: 253.43906681664467

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test