PATENT CLAIM ANALYSIS

Application Number: 16029188
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "738000"]

Abstract:
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Claim (Index 12):
An integrated circuit (IC) assembly comprising:\n a semiconductor package, comprising:\n a first die having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon; \n a redistribution layer having a die side and a package level interconnect side, the die side electrically coupled to the active side of the first die, and the package level interconnect side electrically coupled to a plurality of package level interconnects; \n a first via bar laterally adjacent to and spaced apart from a first edge of the first die, the first via bar coupled to the redistribution layer; \n a second via bar laterally adjacent to and spaced apart from a second edge of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer; \n a first encapsulation layer laterally surrounding the first die; \n a second die above the first die, the second die having an active side and a backside opposite the active side, the active side of the second die having a plurality of die level interconnects thereon, the backside of the second die facing the backside of the first die; \n a third die above the second die, the third die having an active side and a backside opposite the active side, the active side of the third die having a plurality of die level interconnects thereon, the backside of the third die facing the active side of the second die; \n a first wire bond coupling one of the plurality of die level interconnects of the second die to the first via bar; \n a second wire bond coupling one of the plurality of die level interconnects of the third die to the second via bar; and \n a second encapsulation layer laterally adjacent the second die, the third die, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third die; and \n a circuit board having a plurality of electrical routing features disposed therein and a plurality of pads disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package level interconnects.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 95.0
- Lexical Diversity: 2.56897
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14768209', '15915769', '14811261', '15503377', '15590890']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8993163503486934
- 35 USC 102 Novelty (BERT): 0.4986078774233949
- Combined Prediction Score: 0.8592455030561635
- Mean Citation Score: 214.86728
- Max Citation Score: 243.55884
- Similarity Product: 188.84126445040943

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test