PATENT CLAIM ANALYSIS

Application Number: 16167912
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "415000"]

Abstract:
An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.

Claim (Index 11):
The method according to  claim 10 , wherein the forming of the MEMS structure further comprises:\n forming an inter-device via extending through the planarized surface to the top wire of the BEOL interconnect structure, wherein the first-level electrode is electrically coupled to the top wire through the inter-device via.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 97.0
- Lexical Diversity: 2.5098
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15716676', '15363571', '15285032', '15218488', '15793965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9240630124360256
- 35 USC 102 Novelty (BERT): 0.4923356300200521
- Combined Prediction Score: 0.8808902741944282
- Mean Citation Score: 216.121728
- Max Citation Score: 256.5705
- Similarity Product: 215.79619634726643

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test