PATENT CLAIM ANALYSIS

Application Number: 15878806
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["365", "185130"]

Abstract:
A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Claim (Index 13):
A memory device comprising:\n a substrate; and a memory cell array stacked over the substrate in a first direction perpendicular to a top surface of the substrate,\n the memory cell array comprising: \n a memory block including channel structures which extend in the first direction and a plurality of gate lines which surround the channel structures and are stacked over the substrate along the first direction; and \n a wiring line stack including a plurality of wiring lines which are stacked over the substrate along the first direction \n wherein each of the plurality of wiring lines is formed at a layer of a respective gate line.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 86.0
- Lexical Diversity: 1.75676
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15792983', '15856933', '10944910', '15586307', '15792965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7875937254558044
- 35 USC 102 Novelty (BERT): 0.4807456286053723
- Combined Prediction Score: 0.7569089157707612
- Mean Citation Score: 191.060012
- Max Citation Score: 205.12762
- Similarity Product: 144.59463590907336

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test