PATENT CLAIM ANALYSIS

Application Number: 15990949
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device with improved reliability and a method for fabricating the same are provided. The semiconductor device includes a substrate, a first spacer defining a gate trench on the substrate, and a gate electrode in the gate trench, wherein a height of an upper surface of the gate electrode adjacent to the first spacer increases in a direction away from the first spacer.

Claim (Index 13):
A semiconductor device comprising:\n a substrate; a gate structure on the substrate, wherein the gate structure includes a gate electrode and a gate insulating film between the gate electrode and the substrate; and a spacer on a sidewall of the gate structure, wherein an upper surface of the gate structure has an uppermost portion higher than an uppermost portion of an upper surface of the spacer, and wherein the upper surface of the gate structure and the upper surface of the spacer are connected to each other to form a convex upper surface of the gate structure with respect to an upper surface of the substrate, and the spacer includes a concave upper surface with respect to the upper surface of the substrate.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 93.0
- Lexical Diversity: 1.725
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15444550', '15353163', '14165721', '15001568', '15869522']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9177730369781434
- 35 USC 102 Novelty (BERT): 0.493656507872394
- Combined Prediction Score: 0.8753613840675685
- Mean Citation Score: 226.94729
- Max Citation Score: 238.52533
- Similarity Product: 175.78412332992315

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test