PATENT CLAIM ANALYSIS

Application Number: 15743847
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "288000"]

Abstract:
A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Claim (Index 31):
The method of  claim 27 , further comprising:\n forming a sacrificial material layer on the microelectronic substrate and forming a hard mask material layer on the sacrificial material layer prior to forming a source region and a drain region in the microelectronic substrate; patterning an etch block structure on the hard mask material layer, wherein the etch block structure has low etch selectively to the hard mask material layer; etching the sacrificial material layer and the hard mask material layer to form a sacrificial gate material structure with a hard mask thereon, wherein the etch block structure shrinks during the etching process to form curved surfaces of the hard mask prior to forming of the interlayer dielectric material; planarizing the interlayer dielectric material to expose a portion of the hard mask; selectively etching a trench through a portion of the sacrificial gate material structure, wherein a portion of the interlayer dielectric material abutting the hard mask curved surfaces extends over and protects a portion of the hard mask and a portion of the sacrificial gate material structure that remains after the selective etching of the trench; forming a gate dielectric layer and the gate electrode in the trench, wherein the gate dielectric layer is disposed between the gate electrode and the microelectronic substrate; and removing the portion of the sacrificial gate material remaining after selectively etching the trench to form the airgap spacers.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 86.0
- Lexical Diversity: 1.84314
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13992542', '14274592', '14916093', '13997161', '14802902']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9113338021315368
- 35 USC 102 Novelty (BERT): 0.4928817588162545
- Combined Prediction Score: 0.8694885978000085
- Mean Citation Score: 194.271688
- Max Citation Score: 208.80855
- Similarity Product: 141.22026937483548

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test