PATENT CLAIM ANALYSIS

Application Number: 15914944
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["327", "530000"]

Abstract:
An integrated circuit comprises a timebase generator that comprises a linear feedback shift register (LFSR) and a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the timebase generator.

Claim (Index 15):
An integrated circuit, comprising:\n a timebase generator that comprises:\n a Fibonacci linear feedback shift register (LFSR), an output of an exclusive OR (XOR) gate of the Fibonacci LFSR coupled to an input of a register of the Fibonacci LFSR and two inputs of the XOR gate coupled to two outputs of registers of the Fibonacci LFSR; \n a comparator, a first input of the comparator coupled to the Fibonacci LFSR, a second input of the comparator coupled to a voltage reference; \n a digital divider, an input of the digital divider coupled to an output of the comparator and an output of the digital divider coupled to a clock input of the Fibonacci LFSR; and \n a constant current source and a variable current source coupled to the comparator; and \n a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the output of the comparator of the timebase generator.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 90.0
- Lexical Diversity: 1.25
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12109354', '13737337', '13810036', '11233419', '13650588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7515241592820405
- 35 USC 102 Novelty (BERT): 0.4681676431294326
- Combined Prediction Score: 0.7231885076667798
- Mean Citation Score: 168.53414400000003
- Max Citation Score: 174.6885
- Similarity Product: 131.99121111845972

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test