PATENT CLAIM ANALYSIS

Application Number: 16234065
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["365", "203000"]

Abstract:
Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

Claim (Index 28):
A computing system comprising:\n a printed circuit board (PCB); a memory device mounted to the PCB, the memory device including:\n a bitcell array; \n a set dominant latch coupled to a global bitline (GBL) node; and \n read merge circuitry coupled to the bitcell array and the set dominant latch, the read merge circuitry including:\n clipper circuitry coupled to a local bitline (LBL) node and coupled to a read port node of the bitcell array, the clipper circuitry to provide a voltage drop between the read port node and the LBL node; \n precharge circuitry coupled to the LBL node and a power supply that provides an input voltage, the precharge circuitry to precharge the LBL node to the input voltage based on a precharge signal; \n keeper circuitry coupled to the LBL node and the power supply, the keeper circuitry to maintain a value of the LBL node; \n a first NAND gate coupled to the keeper circuitry and the LBL node, the first NAND gate to control the keeper circuitry based on a value of the LBL node; and \n a second NAND gate coupled to the LBL node and coupled to the GBL node for the set dominant latch, the second NAND gate to drive a value of the GBL node based on the value of the LBL node.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 98.0
- Lexical Diversity: 2.42857
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15485059', '15072278', '15604519', '15176069', '14283209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8047369725612787
- 35 USC 102 Novelty (BERT): 0.536730069631394
- Combined Prediction Score: 0.7779362822682903
- Mean Citation Score: 259.085932
- Max Citation Score: 396.76147
- Similarity Product: 319.2187652831816

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test