PATENT CLAIM ANALYSIS

Application Number: 16229250
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "777000"]

Abstract:
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

Claim (Index 10):
A package comprising:\n a package substrate comprising:\n first conductive features at a top surface of the package substrate; \n second conductive features at a bottom surface of the package substrate; and \n a core between the top surface and the bottom surface, wherein the core comprises:\n a core dielectric layer made of a first dielectric material, the core dielectric layer having a first sidewall and a second sidewall; \n conductive vias extending through the core dielectric layer; and \n an upper dielectric layer overlying the core dielectric layer, the upper dielectric layer having a first sidewall flush with the first sidewall of the core dielectric layer, the upper dielectric layer having a second sidewall flush with the second sidewall of the core dielectric layer, \n \n a lower dielectric layer underlying the core dielectric layer, the lower dielectric layer having a first sidewall that extends beyond the first sidewall of the core dielectric layer, the upper dielectric layer having a second sidewall that extends beyond the second sidewall of the core dielectric layer; a first die over and bonded to the package substrate; and a molding material molding the first die therein, wherein the molding material encapsulates the first die, the first and second sidewalls of the upper dielectric layer and the first and second sidewalls of the core dielectric layer, and further wherein the molding material has a first sidewall that is flush with the first sidewall of the lower dielectric layer and the molding material a second sidewall that is flush with the second sidewall of the lower dielectric layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 3.12195
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15919897', '14132709', '14323960', '13789866', '15272491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.900769613456295
- 35 USC 102 Novelty (BERT): 0.4956343538913285
- Combined Prediction Score: 0.8602560874997984
- Mean Citation Score: 214.150304
- Max Citation Score: 257.70383
- Similarity Product: 221.8672843654633

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test