PATENT CLAIM ANALYSIS

Application Number: 16181625
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["327", "158000"]

Abstract:
Disclosed is a phase-locked loop and a delay-locked loop. When the phase-locked loop switches from a sleep state to an active state, a frequency of a reference signal is the same as a frequency of a reference signal which has been synchronized in a previous active state. The phase-locked loop alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal, when the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a capacitor.

Claim (Index 14):
The delay-locked loop of  claim 13 , wherein information corresponding to the delay time of the output signal which has been synchronized in the previous active state is stored in a capacitor.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 3.39535
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12360552', '11187992', '13301402', '14955802', '11622214']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8037953864586116
- 35 USC 102 Novelty (BERT): 0.5002164107283015
- Combined Prediction Score: 0.7734374888855806
- Mean Citation Score: 254.5638
- Max Citation Score: 261.79932
- Similarity Product: 185.96806423749447

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test