PATENT CLAIM ANALYSIS

Application Number: 16000448
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "298000"]

Abstract:
In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Claim (Index 9):
The digitally controlled delay line of  claim 6 , wherein the plurality of unit delay circuits include a first unit delay circuit and a second unit delay circuit adjacent to each other, and\n wherein a first output signal of the first unit delay circuit is input as a first input signal of the second unit delay circuit and a second output signal of the second unit delay circuit is input as a second input signal of the first unit delay circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13051204', '15234954', '15602239', '15198564', '12491567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7390396849261625
- 35 USC 102 Novelty (BERT): 0.4704043339167222
- Combined Prediction Score: 0.7121761498252184
- Mean Citation Score: 155.301334
- Max Citation Score: 173.3582
- Similarity Product: 138.6108525131464

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test