PATENT CLAIM ANALYSIS

Application Number: 16046100
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "759000"]

Abstract:
The present disclosure provides a packaged semiconductor device and a method for preparing the same. The packaged semiconductor device includes a chip having a conductive pad; a first insulating layer disposed on the chip; a second insulating layer disposed on the first insulating layer; a conductive film disposed on the second insulating layer, a redistribution layer disposed on the conductive film; a probe pad disposed on the redistribution layer; and a third insulating, layer disposed on the redistribution layer and the second insulating layer, wherein the third insulating layer covers a portion of the probe pad, and there is no undercut at a region between the redistribution layer and the probe pad. The size of the probe pad is not limited by the undercut, as the size of the probe pad needs to be reduced in order to meet the requirement of continuous minimization of chip size.

Claim (Index 20):
The method of  claim 12 , further comprising:\n removing the second patterned mask, wherein there is no undercut at a region between the redistribution layer and the probe pad.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 2.75862
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15353249', '15205414', '12484497', '15286253', '14750009']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9156944308585157
- 35 USC 102 Novelty (BERT): 0.4994478882518613
- Combined Prediction Score: 0.8740697765978502
- Mean Citation Score: 214.85970000000003
- Max Citation Score: 221.15712
- Similarity Product: 142.41984520248408

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test