PATENT CLAIM ANALYSIS

Application Number: 15749653
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["327", "053000"]

Abstract:
The present disclosure relates to a current memory circuit for minimizing clock feedthrough, the circuit including: a first memory capacitor implemented as a first conductive type MOS; a second memory capacitor implemented as a second conductive type MOS; and a dummy capacitor for connecting the first memory capacitor and the second memory capacitor to each other, wherein the first memory capacitor and the second memory capacitor are current mirrors. Accordingly, a current memory circuit with a more accurate performance, low power consumption, and an integration capability can be provided.

Claim (Index 7):
The current memory circuit of  claim 1 , wherein the first memory capacitor and the second memory capacitor are disposed to allow an incoming current of the first memory capacitor to be equal to an output current of the second memory capacitor.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.02041
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11669156', '11637687', '14856540', '09712104', '11614127']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7733031059824356
- 35 USC 102 Novelty (BERT): 0.4807734817538032
- Combined Prediction Score: 0.7440501435595723
- Mean Citation Score: 163.54502200000005
- Max Citation Score: 176.66924
- Similarity Product: 122.14370898884296

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test