PATENT CLAIM ANALYSIS

Application Number: 16025223
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-10
Patent Classification: ["257", "392000"]

Abstract:
An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.

Claim (Index 2):
The integrated circuit of  claim 1 , wherein the turn on voltage of the second PMOS transistor is at least 50 mV lower than the turn on voltage of the first PMOS transistor.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 95.0
- Lexical Diversity: 2.68421
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14031738', '14573006', '15706935', '12347173', '14196517']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9218002387490344
- 35 USC 102 Novelty (BERT): 0.5046937652248403
- Combined Prediction Score: 0.8800895913966149
- Mean Citation Score: 207.451546
- Max Citation Score: 232.93402000000003
- Similarity Product: 150.08949286924366

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test