PATENT CLAIM ANALYSIS

Application Number: 16291367
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-12
Patent Classification: ["257", "401000"]

Abstract:
An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.

Claim (Index 10):
The method of  claim 9 , wherein the embedded source regions and the cladded drain regions are grown simultaneously.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 1.35294
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16016454', '15808869', '16278693', '16016477', '15847894']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9241645138195262
- 35 USC 102 Novelty (BERT): 0.5447212287755975
- Combined Prediction Score: 0.8862201853151334
- Mean Citation Score: 326.077484
- Max Citation Score: 389.8225
- Similarity Product: 222.88052067279816

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test