PATENT CLAIM ANALYSIS

Application Number: 16174196
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "057000"]

Abstract:
A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

Claim (Index 3):
The Fin FET device of  claim 1 , wherein the first and second seed layers include amorphous silicon.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 2.92593
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15409014', '14833022', '14687815', '15227134', '15807317']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9151065649410992
- 35 USC 102 Novelty (BERT): 0.5173459131786956
- Combined Prediction Score: 0.8753304997648588
- Mean Citation Score: 248.600426
- Max Citation Score: 286.58646
- Similarity Product: 210.0952176736593

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test