PATENT CLAIM ANALYSIS

Application Number: 16069517
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["257", "072000"]

Abstract:
A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.

Claim (Index 30):
The thin film transistor array panel of  claim 29 , wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%.

Metadata:
- Claim Count in Document: 77.0
- Percentile: 95.0
- Lexical Diversity: 2.41538
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15071172', '15071173', '16069171', '15086098', '15071170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9283619469010028
- 35 USC 102 Novelty (BERT): 0.4743915543554647
- Combined Prediction Score: 0.8829649076464491
- Mean Citation Score: 204.867034
- Max Citation Score: 221.03186
- Similarity Product: 193.95612852381944

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test