PATENT CLAIM ANALYSIS

Application Number: 16503447
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-11
Patent Classification: ["712", "014000"]

Abstract:
Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.

Claim (Index 16):
The data processing system recited in  claim 15 , wherein the data processing system is configured to process input data arranged in an array, wherein each processing element is configured to receive a respective sub-array of the input data, each sub-array having a first sub-dimension length and a second sub-dimension length, wherein the sub-dimension lengths are selected such that a height of the array is one processing element.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 1.48571
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15703677', '14074925', '15460755', '10689366', '15276370']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5319898154250604
- 35 USC 102 Novelty (BERT): 0.5111455403894645
- Combined Prediction Score: 0.5299053879215009
- Mean Citation Score: 173.213896
- Max Citation Score: 313.1798
- Similarity Product: 308.88858076771487

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test