PATENT CLAIM ANALYSIS

Application Number: 15918673
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "463000"]

Abstract:
Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Claim (Index 9):
A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:\n forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; patterning the mask with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process comprising a first pass along a center scribing path, a second pass along a first edge scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the first edge scribing path, and a sixth pass along the center scribing path, wherein the first pass is performed prior to the second pass, the second pass is performed prior to the third pass, the third pass is performed prior to the fourth pass, the fourth pass is performed prior to the fifth pass, and the fifth pass is performed prior to the sixth pass; and plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 2.63934
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14148499', '13851442', '14589918', '15060224', '13160713']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8988775994156181
- 35 USC 102 Novelty (BERT): 0.5540229148331421
- Combined Prediction Score: 0.8643921309573704
- Mean Citation Score: 417.84445
- Max Citation Score: 429.59332
- Similarity Product: 372.9739720217228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test