PATENT CLAIM ANALYSIS

Application Number: 16134573
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185220"]

Abstract:
A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

Claim (Index 28):
The method according to  claim 27 , wherein the first and second verification voltages are between two adjacent threshold voltages.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 97.0
- Lexical Diversity: 2.47619
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15639411', '15710381', '15919492', '15688846', '15690256']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8075845876576091
- 35 USC 102 Novelty (BERT): 0.514538519584777
- Combined Prediction Score: 0.7782799808503259
- Mean Citation Score: 225.998802
- Max Citation Score: 317.35077
- Similarity Product: 218.8426668923378

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test