PATENT CLAIM ANALYSIS

Application Number: 16123162
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-08
Patent Classification: ["365", "189150"]

Abstract:
According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

Claim (Index 9):
The memory of  claim 8 , wherein\n the plurality of first memory cells and the plurality of second memory cells include a plurality of flag cells, in a read operation to the first page, the controller determines data that is read from the plurality of flag cells by taking a majority vote or performing error correction on the data that is read from the flag cells.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 97.0
- Lexical Diversity: 3.15
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15915506', '10764828', '11469279', '10988592', '15908449']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8224270557781469
- 35 USC 102 Novelty (BERT): 0.4982969020509522
- Combined Prediction Score: 0.7900140404054274
- Mean Citation Score: 243.625928
- Max Citation Score: 255.46931
- Similarity Product: 173.69581984916687

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test