PATENT CLAIM ANALYSIS

Application Number: 16043738
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["710", "261000"]

Abstract:
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Claim (Index 1):
A processor comprising:\n a memory controller; a first plurality of cores; a second plurality of cores, the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores; an interconnect to couple the first plurality of cores and the second plurality of cores; a shared cache memory coupled to at least the first plurality of cores; a cryptographic accelerator separate from the first plurality of cores and the second plurality of cores; a video accelerator separate from the first plurality of cores and the second plurality of cores; and logic to cause a core of the second plurality of cores to execute an operation, wherein based at least in part on a performance level of the core of the second plurality of cores, the logic is to cause an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation, wherein the logic is to cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.0
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15134756', '15192134', '15134770', '13992361', '13227686']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6669276549213606
- 35 USC 102 Novelty (BERT): 0.4182482926355448
- Combined Prediction Score: 0.642059718692779
- Mean Citation Score: 136.16516399999998
- Max Citation Score: 138.35994
- Similarity Product: 134.8564940343046

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test