PATENT CLAIM ANALYSIS

Application Number: 16374126
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-10
Patent Classification: ["718", "100000"]

Abstract:
Disclosed is a data accelerated processing system including a processing device, a storage device, an interface device and a control device. The processing device is configured to realize accelerated operation processing of data. The storage device is electrically connected to the processing device for storing the data sent by a server. The interface device is electrically connected to the processing device for data transmission between the processing device and the server. The control device is configured to regulate the status of the processing device. During an operation process, a large number of operating tasks in the server may be transmitted to the processing device for operating through the interface device, and large amounts of buffered data may be stored in the storage device. The data accelerated processing system improves data reading speed and operation efficiency through the cooperation of the processing device, the storage device and the interface device.

Claim (Index 19):
The data accelerated processing system of  claim 1 ,\n wherein each of the one or more processors include a primary processing circuit and a plurality of secondary processing circuits, wherein the plurality of secondary processing circuits are arranged in a form of an array, wherein each of the secondary processing circuits is electrically connected to other adjacent secondary processing circuits, wherein the primary processing circuit is electrically connected to k secondary processing circuits of the plurality of secondary processing circuits, the k secondary processing circuits being: n secondary processing circuits in a first row, n secondary processing circuits in a m th  row, and m secondary processing circuits in a first column, wherein each of the primary processing circuits is configured to divide input data into a plurality of data blocks and send at least one of the data blocks and at least one of a plurality of operation instructions to the k secondary processing circuits, wherein the k secondary processing circuits are configured to forward data and instructions between the primary processing circuit and other plurality of secondary processing circuits, wherein the plurality of secondary processing circuits are configured to execute operations on the received data blocks according to the operation instructions to obtain intermediate results, and transmit the operation results to the k secondary processing circuits, and wherein the primary processing circuit is configured to process the intermediate results sent from the k secondary processing circuits to obtain the result of the operation instructions.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 100.0
- Lexical Diversity: 3.03774
- Patent Class: 718.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15094939', '14725811', '15201175', '15700018', '15144734']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4312086419235983
- 35 USC 102 Novelty (BERT): 0.5056548695089076
- Combined Prediction Score: 0.4386532646821292
- Mean Citation Score: 148.094162
- Max Citation Score: 149.59808
- Similarity Product: 99.61867995117188

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test