PATENT CLAIM ANALYSIS

Application Number: 15869287
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["711", "103000"]

Abstract:
According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.

Claim (Index 7):
The memory controller according to  claim 1 , wherein the protocol is any one of an MESIF protocol, a QPI protocol, an MESI protocol, an MOESI protocol, or an MSI protocol.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.4717
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15240212', '13333795', '12487915', '12330822', '13234837']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5227913087727386
- 35 USC 102 Novelty (BERT): 0.4875192450421747
- Combined Prediction Score: 0.5192641023996822
- Mean Citation Score: 156.887246
- Max Citation Score: 161.85838
- Similarity Product: 103.54783799620392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test