PATENT CLAIM ANALYSIS

Application Number: 15980833
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["438", "197000"]

Abstract:
A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.

Claim (Index 13):
The computer usable program product of  claim 1 , wherein the divot fill layer is formed of a silicon nitride (SiN) material.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 3.27083
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15659400', '15942971', '15880757', '15967524', '15868003']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8885455095762207
- 35 USC 102 Novelty (BERT): 0.5602008795910929
- Combined Prediction Score: 0.8557110465777079
- Mean Citation Score: 334.13516
- Max Citation Score: 447.64136
- Similarity Product: 349.23983892005447

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test