PATENT CLAIM ANALYSIS

Application Number: 16101699
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["327", "333000"]

Abstract:
In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Claim (Index 7):
The level shifter circuit of  claim 1 , wherein the third transistor pair is configured to alternatively turn-on and turn-off, wherein the fourth transistor pair is configured to alternatively turn-on and turn-off.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 96.0
- Lexical Diversity: 3.97297
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11168035', '11159005', '10692098', '11280644', '12588150']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7963917006363549
- 35 USC 102 Novelty (BERT): 0.4916611754804652
- Combined Prediction Score: 0.7659186481207659
- Mean Citation Score: 231.755864
- Max Citation Score: 242.69167
- Similarity Product: 181.20632377152617

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test