PATENT CLAIM ANALYSIS

Application Number: 15909404
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["365", "185030"]

Abstract:
A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.

Claim (Index 2):
The semiconductor memory device according to  claim 1 , wherein the controller is further configured to, during the verification operation:\n apply the second voltage to the bit line connected to first memory cell while the second verification voltage is being applied to the word line if the first memory cell fails verification at the first verification voltage.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.51282
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15405098', '15690256', '15908449', '15195560', '14630505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7936518467962381
- 35 USC 102 Novelty (BERT): 0.504082957264624
- Combined Prediction Score: 0.7646949578430767
- Mean Citation Score: 251.253478
- Max Citation Score: 284.98608
- Similarity Product: 231.18694860777856

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test