PATENT CLAIM ANALYSIS

Application Number: 15947831
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Claim (Index 20):
The machine of  claim 19  further comprising a network interface to couple the plurality of cores to a network.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.08
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13729579', '14498353', '15370904', '13539044', '15602603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5099796338804194
- 35 USC 102 Novelty (BERT): 0.5080455225352102
- Combined Prediction Score: 0.5097862227458986
- Mean Citation Score: 201.898608
- Max Citation Score: 253.76993
- Similarity Product: 154.8014457824588

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test