PATENT CLAIM ANALYSIS

Application Number: 15987735
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185010"]

Abstract:
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Claim (Index 7):
The method of  claim 5 , wherein the positive voltage applied to the one of the erase gate lines is at least double than that of the positive voltage applied to the others of the control gate lines.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 3.52381
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15374588', '15593231', '14190010', '11593398', '15158460']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8368555245938492
- 35 USC 102 Novelty (BERT): 0.5621972781175886
- Combined Prediction Score: 0.8093896999462231
- Mean Citation Score: 386.168134
- Max Citation Score: 483.21915
- Similarity Product: 435.1225135506034

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test