PATENT CLAIM ANALYSIS

Application Number: 15904346
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["257", "306000"]

Abstract:
This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Claim (Index 3):
The semiconductor device according to  claim 1 , further comprising a third insulating layer that is in contact with side walls of the first semiconductor layer and the first insulating layer and that surrounds the first semiconductor layer and the first insulating layer in plan view.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 3.52632
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15212331', '14860700', '15266914', '15239193', '14869988']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9203939946006136
- 35 USC 102 Novelty (BERT): 0.5055288423342847
- Combined Prediction Score: 0.8789074793739808
- Mean Citation Score: 247.054064
- Max Citation Score: 278.07376
- Similarity Product: 204.1114678085136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test