PATENT CLAIM ANALYSIS

Application Number: 15917867
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["348", "501000"]

Abstract:
A video interface conversion apparatus comprises a video interface circuit, a video clock adjustment information generation circuit and a video clock recovery circuit. The video interface circuit generates at least one original synchronization signal according to a control signal, and fetches video data from a data signal according to a video synchronization signal. The video clock adjustment information generation circuit generates video clock adjustment information and the video synchronization signal according to the original video synchronization signal and a video clock. The video clock recovery circuit receives an original clock and the video clock adjustment information, and recovers the video clock by adjusting the original clock according to the video clock adjustment information.

Claim (Index 6):
The video interface conversion apparatus according to  claim 5 , wherein the free-run timing generator comprises:\n a counting circuit, having an enable terminal, a reset terminal, a clock terminal and a output terminal, wherein the enable terminal of the counting circuit is coupled to the video timing generator to receive an original vertical synchronization signal among the at least one original synchronization signal, and the clock terminal of the counting circuit is coupled to the video clock recovery circuit to receive the video clock; and a comparison circuit, having a first input terminal, a second input terminal and a output terminal, wherein the first input terminal of the comparison circuit is coupled to the output terminal of the counting circuit to receive a count value of the counting circuit, the second input terminal of the comparison circuit receives a first threshold, and the output terminal of the comparison circuit outputs a free-run vertical synchronization signal served as the video synchronization signal and provides the free-run vertical synchronization signal to the reset terminal of the counting circuit.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 3.33333
- Patent Class: 348.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14500360', '11126030', '12010374', '13137144', '14582318']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.640384298026626
- 35 USC 102 Novelty (BERT): 0.4673263675518067
- Combined Prediction Score: 0.6230785049791441
- Mean Citation Score: 177.58723999999995
- Max Citation Score: 184.65761
- Similarity Product: 151.37076646792468

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test