PATENT CLAIM ANALYSIS

Application Number: 16019070
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-07
Patent Classification: ["327", "175000"]

Abstract:
A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Claim (Index 10):
The method of  claim 8 , wherein the extracting is further performed by a digital differentiator of the duty cycle calibration circuit.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 94.0
- Lexical Diversity: 1.89706
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15980467', '12273557', '13364185', '12519691', '14674680']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7845212479241209
- 35 USC 102 Novelty (BERT): 0.4987903578688437
- Combined Prediction Score: 0.7559481589185932
- Mean Citation Score: 202.783546
- Max Citation Score: 219.64273
- Similarity Product: 138.43274501037536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test