PATENT CLAIM ANALYSIS

Application Number: 16250275
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "051000"]

Abstract:
A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA 0 , WLB 0 , WLB 1 , WLA 1 , WLA 2 . Further, a pitch d 2  between WLA-WLA and between WLB-WLB is made smaller than a pitch d 1  between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d 2  on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d 1  on the other.

Claim (Index 1):
A semiconductor device comprising:\n first and second static memory cells, first, second, third and fourth word lines, and first and second bit lines, wherein each of the first and second static memory cells includes a first inverter and a second inverter, a first access transistor and a second access transistor coupled to the first inverter, and a third access transistor and a fourth access transistor coupled to the second inverter, wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor, wherein the first word line is electrically coupled to the first and third access transistors of the first static memory cell, the second word line is electrically coupled to the second and fourth access transistors of the first static memory cell, the third word line is electrically coupled to the second and fourth access transistors of the second static memory cell, and the fourth word line is electrically coupled to the first and third access transistors of the second static memory cell, wherein the first bit line is electrically coupled to the first access transistor of each of the first and second static memory cells, and the second bit line is electrically coupled to the second access transistor of each of the first and second static memory cells, wherein the first and third access transistors and the first driver transistor of each of the first and second static memory cells are disposed in a first well of a first conductive type, wherein the first and the second load transistors of the first and second static memory cells are disposed in a second well of a second conductive type, wherein the second and fourth access transistors and the second driver transistor of each of the first and second static memory cells are disposed in a third well of the first conductive type, wherein the first, second and third wells are arranged in a first direction such that the second well is arranged between the first well and the third well, wherein the first and second static memory cells are arranged adjacently to each other, wherein the first and second bit lines extend along a first direction, wherein the first, second, third and fourth word lines extend along a second direction perpendicular to the first direction and are arranged over the first and second bit lines, wherein the second word line and the third word line are arranged between the first word line and the fourth word line such that the second word line and the third word line are arranged adjacently, and wherein a first distance between the first word line and the second word line is longer than a second distance between the second word line and third word line.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 99.0
- Lexical Diversity: 2.22388
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13900127', '15795502', '13080991', '14490235', '15190263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8634708381783426
- 35 USC 102 Novelty (BERT): 0.6332109752118544
- Combined Prediction Score: 0.8404448518816937
- Mean Citation Score: 597.669638
- Max Citation Score: 603.07214
- Similarity Product: 577.8345231335306

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test