PATENT CLAIM ANALYSIS

Application Number: 16210412
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "368000"]

Abstract:
A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.

Claim (Index 3):
The integrated circuit structure of  claim 2  further comprising an additional CVss landing pad in the first metal layer and overlapped by the CVss landing pad, wherein the additional CVss landing pad extends to the first boundary of the first SRAM cell, and is spaced apart from the second boundary of the first SRAM cell.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.08889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15641013', '15047927', '16188411', '15089947', '15061573']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9230104642289724
- 35 USC 102 Novelty (BERT): 0.562874075821687
- Combined Prediction Score: 0.8869968253882438
- Mean Citation Score: 381.1742780000001
- Max Citation Score: 443.2953
- Similarity Product: 352.531987081182

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test