PATENT CLAIM ANALYSIS

Application Number: 16161553
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "432000"]

Abstract:
Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device.

Claim (Index 5):
A manufacturing method of a solid-state imaging device, the method comprising:\n forming at least a pixel array and a multilayer wiring layer in an area to serve as a first semiconductor chip section in a first semiconductor wafer; forming at least a logic circuit and a multilayer wiring layer in an area to serve as a second semiconductor chip section in a second semiconductor wafer; forming a light blocking layer by an electrically-conductive film of the same layer as a layer of a connected interconnect in the multilayer wiring layer of one or both of the first semiconductor wafer and the second semiconductor wafer; bonding two or more semiconductor wafers including at least the first and second semiconductor wafers in such a manner that the multilayer wiring layers of the first semiconductor wafer and the second semiconductor wafer are opposed to each other and interconnects of both wafers are electrically connected to each other; processing the first semiconductor wafer into a thin film form; and processing the bonded semiconductor wafers into a chip.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.31818
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13362758', '14168524', '15892887', '15342081', '14867476']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9245036762064835
- 35 USC 102 Novelty (BERT): 0.5508620527048349
- Combined Prediction Score: 0.8871395138563187
- Mean Citation Score: 385.632224
- Max Citation Score: 400.46664
- Similarity Product: 368.9327746015693

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test