PATENT CLAIM ANALYSIS

Application Number: 15874997
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "074000"]

Abstract:
A method for manufacturing a 3D integrated circuit is provided. A manufacturing system provides a first integrated circuit having a first surface and a first via extending to the first surface. The manufacturing system applies a first controlled collapse chip connection (C4) solder bump to the first via. The manufacturing system provides a second integrated circuit having a second surface and a second via extending to the second surface. The manufacturing system applies a second C4 solder bump to the second via. The manufacturing system overturns the second integrated circuit onto the first integrated circuit and aligns the first C4 solder bump with the second C4 bump. The manufacturing system heats the first C4 solder bump and the second C4 solder bump until the first via contact is soldered to the second via.

Claim (Index 6):
The method of  claim 1 , wherein the first integrated circuit comprises a first portion of first circuitry of a first one or more functionality and the second integrated circuit comprises second portion of first circuitry.

Metadata:
- Claim Count in Document: 66.0
- Percentile: 86.0
- Lexical Diversity: 3.46341
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14524637', '13553882', '13448775', '14824409', '13243605']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9213281471169688
- 35 USC 102 Novelty (BERT): 0.4936533889148429
- Combined Prediction Score: 0.8785606712967562
- Mean Citation Score: 196.06239
- Max Citation Score: 203.38837
- Similarity Product: 137.85366701938153

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test