PATENT CLAIM ANALYSIS

Application Number: 16002077
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-06
Patent Classification: ["257", "066000"]

Abstract:
An array substrate is disclosed, including a thin film transistor including a substrate, a first gate, a first insulating layer, an active layer, a source, a drain, a second and a third insulating layers, and a second gate. The first gate is disposed on the substrate, the first insulating layer is disposed on the first gate and the substrate, and the active layer is disposed on the first insulating layer, the source and the drain disposed on the active layer form a channel with the active layer, the second insulating layer, the third insulating layer, and the second gate are sequentially disposed in the channel region, a distance between an edge of the second insulating layer and the source and the drain is greater than a distance between an edge of the third insulating layer and the source and the drain.

Claim (Index 3):
A fabricating method of an array substrate, comprising the following steps:\n providing a substrate and forming a first gate on the substrate, covering a first insulating layer on the first gate and the substrate, and stacking an active layer on the first insulating layer; forming a second insulating layer material on the first insulating layer and the active layer and sequentially depositing a third insulating layer material and a photoresist layer material on the second insulating layer material; patterning the photoresist layer from a side of the substrate away from the first gate by using the first gate as a mask to form a photoresist layer so as to make the photoresist layer coincide with an orthographic projection of the first gate; etching the second insulating layer material and the third insulating layer material to form a second insulating layer and a third insulating layer, so as to make the third insulating layer coincide with an orthographic projection of the photoresist layer after patterning, and a distance between an edge of the second insulating layer and the source and the drain is greater than a distance between an edge of the third insulating layer and the source and the drain; and removing the photoresist layer after patterning, depositing a metal layer on the active layer to form a source, a second gate, and a drain simultaneously, and subsequently depositing other functional layers and pixel electrode to obtain an array substrate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 3.85366
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15073278', '14731081', '10615840', '15865433', '15129735']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8995126943473054
- 35 USC 102 Novelty (BERT): 0.4847320561258013
- Combined Prediction Score: 0.858034630525155
- Mean Citation Score: 204.327232
- Max Citation Score: 206.37718
- Similarity Product: 162.76779661867974

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test