PATENT CLAIM ANALYSIS

Application Number: 15905722
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-05
Patent Classification: ["257", "668000"]

Abstract:
A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

Claim (Index 15):
The chip package of  claim 8 , wherein the redistribution circuit structure is a semiconductor circuit substrate, and the integrated fan-out package further comprises:\n connecting wirings, encapsulated in the encapsulant, wherein the at least one second semiconductor chip and the at least third semiconductor chip are electrically connected to the semiconductor circuit substrate through the connecting wirings.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 88.0
- Lexical Diversity: 2.94595
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15854720', '15854736', '15716494', '15706767', '15253887']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9134572878585304
- 35 USC 102 Novelty (BERT): 0.5008298172946312
- Combined Prediction Score: 0.8721945408021406
- Mean Citation Score: 231.939568
- Max Citation Score: 247.83237000000003
- Similarity Product: 195.2478249576652

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test