PATENT CLAIM ANALYSIS

Application Number: 15958021
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["235", "462010"]

Abstract:
A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.

Claim (Index 4):
The method of  claim 3  further comprising forming a second high-k dielectric layer in contact with the second set of spacers.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 1.48936
- Patent Class: 235.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15603982', '15958018', '15275565', '15412499', '15802021']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.65366293659188
- 35 USC 102 Novelty (BERT): 0.569401698178787
- Combined Prediction Score: 0.6452368127505708
- Mean Citation Score: 408.115888
- Max Citation Score: 493.32593
- Similarity Product: 443.3809173664636

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test