PATENT CLAIM ANALYSIS

Application Number: 15914168
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["257", "298000"]

Abstract:
A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Claim (Index 17):
The non-volatile memory device of  claim 12 , wherein the non-volatile memory device is configured to apply a power supply voltage associated with the peripheral circuit to the first upper substrate based on an operation signal associated with an operation of the memory cell array being applied to the memory cell region.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 90.0
- Lexical Diversity: 3.32258
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14574079', '15608076', '15426081', '15388369', '15385152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9250664458809924
- 35 USC 102 Novelty (BERT): 0.4940352545394225
- Combined Prediction Score: 0.8819633267468355
- Mean Citation Score: 217.691482
- Max Citation Score: 231.87033
- Similarity Product: 171.01639501643837

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test