PATENT CLAIM ANALYSIS

Application Number: 16285081
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-09
Patent Classification: ["361", "764000"]

Abstract:
Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

Claim (Index 15):
A computer module, comprising:\n a module substrate having a first side, a second side opposite the first side, an aperture extending between the first and second sides, a first plurality of bond sites adjacent to the aperture at the first side, a second plurality of bond sites adjacent to the aperture at the second side, and a third plurality of bond sites along an outer edge of the module substrate operably connected to the first and second pluralities of bond sites and configured to electrically couple with a computer socket; a first microelectronic package having a first stack of semiconductor dies and a first package substrate carrying the first stack of semiconductor dies, the first package substrate having a first plurality of contact pads corresponding to and electrically coupled to the first plurality of bond sites adjacent to the aperture at the first side, wherein at least a portion of the first stack of semiconductor dies is inside the aperture, and wherein the first stack of semiconductor dies includes at least a first memory controller die and a first memory die, each of the first memory die and the first memory controller die being electrically coupled with the third plurality of bond sites through the first plurality of bond sites; and a second microelectronic package having a second stack of semiconductor dies and a second package substrate carrying the second stack of semiconductor dies, the second package substrate having a second plurality of contact pads corresponding to and aligned with the second plurality of bond sites adjacent to the aperture at the second side, wherein at least a portion of the second stack of semiconductor dies is inside the aperture, and wherein the second stack of semiconductor dies includes at least a second memory controller die and a second memory die, each of the second memory die and the second memory controller die being electrically coupled with the third plurality of bond sites through the second plurality of bond sites.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 99.0
- Lexical Diversity: 1.86957
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15626843', '14171584', '12353773', '14617523', '11509291']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8344140393371479
- 35 USC 102 Novelty (BERT): 0.4909353801160465
- Combined Prediction Score: 0.8000661734150377
- Mean Citation Score: 253.599958
- Max Citation Score: 275.7716
- Similarity Product: 258.96393433995246

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test