PATENT CLAIM ANALYSIS

Application Number: 16186739
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "185020"]

Abstract:
Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

Claim (Index 2):
A memory device, comprising:\n an array of memory cells; and a controller configured to cause the memory device to perform a method comprising:\n applying a particular programming pulse to an access line coupled to a grouping of memory cells of the array of memory cells during a write operation, wherein the grouping of memory cells comprises a plurality of subsets of memory cells, and wherein each subset of memory cells of the plurality of subsets of memory cells has a respective desired data state of a plurality of data states for the write operation; \n while applying the particular programming pulse to the access line, inhibiting memory cells of a first subset of memory cells of the plurality of subsets of memory cells from programming, inhibiting memory cells of a second subset of memory cells of the plurality of subsets of memory cells from programming, and enabling memory cells of a third subset of memory cells of the plurality of subsets of memory cells for programming; and \n after applying the particular programming pulse to the access line and without determining whether any memory cell of the plurality of subsets of memory cells has reached the respective desired data state for its respective subset of memory cells in response to applying the particular programming pulse to the access line, applying a subsequent programming pulse to the access line while inhibiting the memory cells of the first subset of memory cells from programming and while enabling the memory cells of the second subset of memory cells and the third subset of memory cells for programming.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 2.82353
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15437584', '15933498', '14724945', '13305795', '16023042']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7943404734970603
- 35 USC 102 Novelty (BERT): 0.5321402010583076
- Combined Prediction Score: 0.768120446253185
- Mean Citation Score: 322.618712
- Max Citation Score: 372.9724
- Similarity Product: 287.84628607401845

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test