PATENT CLAIM ANALYSIS

Application Number: 16036751
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["365", "154000"]

Abstract:
Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline. The integrated circuit may include a write driver coupled to the bitline for writing data to the bitcell. The write driver may have an inverter and a clamping device that are arranged to clamp current after data has been written to the bitcell.

Claim (Index 11):
The integrated circuit of  claim 9 , wherein the clamping circuit restricts at least one of current and voltage of the bitline during read operations to provide increased stability of read operations when data is read from the bitcell.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 95.0
- Lexical Diversity: 1.63158
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15960475', '13784830', '15760681', '15393552', '15823490']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8008505122213266
- 35 USC 102 Novelty (BERT): 0.4993711783635936
- Combined Prediction Score: 0.7707025788355534
- Mean Citation Score: 183.23022
- Max Citation Score: 196.55577
- Similarity Product: 111.81427240344286

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test