PATENT CLAIM ANALYSIS

Application Number: 16212626
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "407000"]

Abstract:
The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

Claim (Index 6):
The method of  claim 1 , wherein the bottom barrier layer comprises a titanium nitride (TiN) or a tantalum nitride (TaN) layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 2.86538
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15641312', '15009808', '14537840', '14836966', '13454337']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913704630032907
- 35 USC 102 Novelty (BERT): 0.4891329080628307
- Combined Prediction Score: 0.8712474578358994
- Mean Citation Score: 226.223616
- Max Citation Score: 240.6971
- Similarity Product: 211.5980747151256

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test