PATENT CLAIM ANALYSIS

Application Number: 15885972
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["712", "220000"]

Abstract:
A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.

Claim (Index 14):
The processing system of  claim 13 , wherein:\n at least one of said groupings spans multiple different chips; each respective one of said chips is configured to produce a respective exit state resulting from the instances of the exit instruction being executed by all of the plurality of worker threads on each of a plurality of participating tiles on the respective chip; the interconnect comprises an external interconnect connecting together the multiple chips; the synchronization logic comprises, in the external interconnect, a respective sync block associated with each of the multiple chips; the external interconnect is operable such that the sync block associated with one of the multiple chips acts as a master of the group, and the external interconnect connects the multiple chips together via their sync blocks in a topology of one or more chains leading toward the master; in the or each chain, the sync block associated with each chip is configured to propagate a running aggregate of the respective exit states along the chain toward the master, and the master is configured to produce a global aggregate aggregating the exit state of the master's chip and the running aggregate or aggregates from the or each chain, and to propagate the global aggregate back down the or each chain to the multiple chips; from each chip to the next in the or each chain, the connection between the associated sync block comprises a first synchronization request wire, a second synchronization request wire, a first synchronization acknowledgment wire and a second synchronization acknowledgement wire; the sync blocks are configured to use a selected one of the first and second synchronization wires to propagate the synchronization request, and to use a selected one of the first and second synchronization acknowledgement wires to propagate the synchronization acknowledgment request from the second chip to the first chip; the running aggregate is signalled as either a first value or a second value by the selection of the first or second synchronization request wire respectively when propagating said synchronization request, and the global exit state is signalled as either a first value or a second value by the selection of the first or second synchronization acknowledgment wire respectively when propagating said synchronization acknowledgment.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 2.23077
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15886185', '15886138', '15886099', '15885955', '15886340']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6862556540888511
- 35 USC 102 Novelty (BERT): 0.5477368863164642
- Combined Prediction Score: 0.6724037773116125
- Mean Citation Score: 380.575198
- Max Citation Score: 433.3508
- Similarity Product: 317.6485300918579

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test