PATENT CLAIM ANALYSIS

Application Number: 15996365
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-09
Patent Classification: ["365", "193000"]

Abstract:
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.

Claim (Index 1):
A double data rate (DDR) memory controller, comprising:\n a core_clock circuit configured to generate a core_clock; a core_clock delay element communicatively coupled to the core_clock circuit, the core_clock delay element configured to generate a capture clock; a read data path configured to receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; a first core domain register communicatively coupled to the core_clock delay element and the read data path, the first core domain register configured to be responsive to the DQ signal or the signal derived from the DQ signal, and to be clocked based, at least in part, on the capture clock; a second core domain register communicatively coupled to the first core domain register and the core_clock circuit, the second core domain register configured to be responsive to the first core domain register, and to be clocked based, at least in part, on the core_clock; and a self-configuring logic circuit communicatively coupled to the core_clock delay element, the first core domain register, and the second core domain register, the self-configuring logic circuit configured to be responsive to at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register, for setting a delay of the core_clock delay element; wherein the double data rate (DDR) memory controller is configured such that the delay of the core_clock delay element is set by the self-configuring logic circuit during a power-on initialization calibration operation.

Metadata:
- Claim Count in Document: 80.0
- Percentile: 94.0
- Lexical Diversity: 2.90625
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15722209', '15926902', '13172740', '12157081', '14752903']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8631596998036889
- 35 USC 102 Novelty (BERT): 0.6181647296435208
- Combined Prediction Score: 0.8386602027876722
- Mean Citation Score: 610.6998120000002
- Max Citation Score: 622.7399
- Similarity Product: 515.7411109592617

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test