PATENT CLAIM ANALYSIS

Application Number: 15871452
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["714", "033000"]

Abstract:
Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

Claim (Index 2):
The computer-implemented method of  claim 1 , further comprising implementing a global time incremented on a processor cycle and used for timestamping.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 1.91139
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15010088', '15197534', '12328242', '14829773', '14037958']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2739414688681241
- 35 USC 102 Novelty (BERT): 0.5460016750119085
- Combined Prediction Score: 0.3011474894825026
- Mean Citation Score: 286.594624
- Max Citation Score: 408.71185
- Similarity Product: 300.9087089328408

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test