PATENT CLAIM ANALYSIS

Application Number: 16006571
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["257", "076000"]

Abstract:
A semiconductor device fabrication method includes forming first and second spaced apart base regions and source regions in a substrate with a portion of a drift region therebetween. The method further includes forming at least a first trench extending laterally through the base region, the drift region and the source region, the first trench extending vertically partially through the source region. The method also includes forming a first oxide layer over the trenched upper surface, and forming a polysilicon layer over the first oxide layer. The polysilicon layer is patterned to form the gate conductor, and a drain contact is formed on a bottom surface of the semiconductor substrate.

Claim (Index 9):
A method of fabricating a semiconductor device, comprising:\n a) providing a semiconductor substrate having a bottom layer having a first dopant type and first dopant concentration, and a top layer having the first dopant type and a second dopant concentration that is less than the first dopant concentration; b) forming first and second spaced apart base strips in the top layer with at least a strip of a drift region therebetween, the base strips and strip of the drift region extending lengthwise and in a parallel manner in a first direction; c) forming first and second spaced apart source strips extending lengthwise the first direction, and such that a portion of each of the first and second base strips is disposed between each corresponding first and second source strip and the strip of the drift region; d) forming at least a first trench extending transverse the first direction through the base strips, the strip of the drift region and the source strips, the first trench extending vertically partially through the source strips, thereby forming a trenched upper surface exposing portions of the first and second source strips, the strip of the drift region, and first and second base strips; e) forming a first oxide layer over the trenched upper surface; f) forming a polysilicon layer over the first oxide layer; g) patterning the polysilicon layer to form a gate conductor, the gate conductor disposed vertically above the drift layer, and laterally positioned to overlap in the lateral direction with the first and second source strips; h) forming a drain contact on a bottom surface of the bottom layer.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 94.0
- Lexical Diversity: 2.08929
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15027629', '10946547', '14154790', '14154736', '15239093']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9027578196356676
- 35 USC 102 Novelty (BERT): 0.5089072570286052
- Combined Prediction Score: 0.8633727633749613
- Mean Citation Score: 226.437496
- Max Citation Score: 283.4025
- Similarity Product: 229.95148675382129

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test