PATENT CLAIM ANALYSIS

Application Number: 15966697
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["398", "208000"]

Abstract:
A coherent optical receiver in which the channel equalizer and the clock-recovery circuit are connected in a nested-loop configuration, wherein the channel estimate generated by the equalizer is used to adjust the phase of the clock signal generated by the clock-recovery circuit. The channel equalizer can be implemented using a bank of time-domain or frequency-domain FIR filters. In an example embodiment, the clock-recovery circuit is configured to track the phase rotation corresponding to the equalized signals in a frequency-dependent manner; track the phase rotation in the channel equalizer either in a frequency-dependent manner or based on the mean signal delay therein; and adjust the phase of the clock signal based on an effective difference between these two phase rotations. The clock-recovery circuit enhances the clock tone by applying a Fourier transform to the squared absolute values of the equalized signals outputted by the channel equalizer.

Claim (Index 1):
An apparatus comprising an optical data receiver that comprises:\n an optical front end that comprises:\n an optical hybrid configured to mix an optical data signal and an optical local-oscillator signal to generate a plurality of mixed optical signals; and \n a plurality of photodetectors configured to generate a plurality of electrical digital measures of the optical data signal in response to the mixed optical signals; and \n a digital signal processor that comprises:\n a digital equalizing filter configured to generate a second plurality of digital samples by digitally filtering a first plurality of digital samples, said filtering being based on a transfer function, said first plurality of digital samples being generated in response to the plurality of electrical digital measures and a clock signal, the digital equalizing filter being configured to generate a control signal carrying a plurality of values representing the transfer function; \n a clock-recovery circuit configured to generate the clock signal using at least some of the second plurality of digital samples and in response to the control signal generated by the digital equalizing filter; and \n a signal decoder configured to recover data encoded in the optical data signal using the second plurality of digital samples.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 91.0
- Lexical Diversity: 2.01316
- Patent Class: 398.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14319866', '14500239', '15376319', '15376337', '15376361']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6318782266303177
- 35 USC 102 Novelty (BERT): 0.4980395516105739
- Combined Prediction Score: 0.6184943591283433
- Mean Citation Score: 202.845026
- Max Citation Score: 208.35687
- Similarity Product: 170.89156559140918

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test