PATENT CLAIM ANALYSIS

Application Number: 15972510
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["327", "212000"]

Abstract:
A memory circuit includes, a latch circuit that includes a first node, a second node, a first inverter having an input coupled to the first node and an output coupled to the second node, and a second inverter having an input coupled to the second node and an output coupled to the first node, a writing circuit that includes a first transistor coupled to the first node and a second transistor coupled to the second node and executes writing to the latch circuit using the first transistor and the second transistor, a command circuit detects the execution of the writing to the latch circuit and output a command signal to increase the potential of the second node before the termination of the writing of a low level to the first node, and a potential control circuit increases the potential of the second node based on the command signal.

Claim (Index 10):
The memory circuit according to  claim 1 ,\n wherein the command circuit stops outputting the command signal so that the potential control circuit terminates an operation of increasing the potential of the second node before the start of the writing of the low level to the first node.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 3.9
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11510733', '10486638', '12036938', '15603284', '11153113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7701391267719783
- 35 USC 102 Novelty (BERT): 0.5008732535228804
- Combined Prediction Score: 0.7432125394470684
- Mean Citation Score: 163.525448
- Max Citation Score: 170.29054
- Similarity Product: 93.97172197270392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test