PATENT CLAIM ANALYSIS

Application Number: 15912405
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["711", "207000"]

Abstract:
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Claim (Index 8):
The system of  claim 7  wherein the execution circuitry is to execute a third TLB management instruction having an operand to identify a specific guest physical address, the execution circuitry to invalidate at least one TLB entry associated with the guest physical address.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 90.0
- Lexical Diversity: 2.02632
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14675325', '15620663', '14867024', '14867018', '14675292']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.604074199435906
- 35 USC 102 Novelty (BERT): 0.5251295618324876
- Combined Prediction Score: 0.5961797356755643
- Mean Citation Score: 340.357226
- Max Citation Score: 342.1339
- Similarity Product: 247.4387081623733

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test