PATENT CLAIM ANALYSIS

Application Number: 15957263
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "189090"]

Abstract:
A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Claim (Index 15):
The semiconductor device according to  claim 14 , wherein the capacitive element is formed as a MOS capacitor.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 91.0
- Lexical Diversity: 2.32353
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15373783', '15134981', '14658163', '15234910', '15782662']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8481240080339292
- 35 USC 102 Novelty (BERT): 0.5663890923006094
- Combined Prediction Score: 0.8199505164605972
- Mean Citation Score: 391.859318
- Max Citation Score: 472.00775
- Similarity Product: 384.3914160641879

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test