PATENT CLAIM ANALYSIS

Application Number: 15947991
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

Claim (Index 8):
A method comprising:\n depositing a gate stack; depositing an interlayer dielectric layer over the gate stack; forming a first opening in the interlayer dielectric layer that penetrates through the gate stack to cut the gate stack into a first section and a second section; depositing a first dielectric material in the first opening to form a pillar arranged between the first section of the gate stack and the second section of the gate stack; after filling the first opening with the first dielectric material, forming a second opening and a third opening in the interlayer dielectric layer that penetrate to the gate stack and that are arranged on opposite sides of the pillar; and forming a first contact in the second opening that is coupled with the first section of the gate stack and a second contact in the third opening that is coupled with the second section of the gate stack, wherein the pillar self-aligns the formation of second opening and the third opening relative to the first section and the second section of the gate stack.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 91.0
- Lexical Diversity: 3.04
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15658835', '15928783', '15800563', '15427594', '15586621']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9179828421775408
- 35 USC 102 Novelty (BERT): 0.4879648268159779
- Combined Prediction Score: 0.8749810406413844
- Mean Citation Score: 227.61442
- Max Citation Score: 235.51648
- Similarity Product: 184.2538623756409

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test