PATENT CLAIM ANALYSIS

Application Number: 16220174
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "618000"]

Abstract:
Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.

Claim (Index 7):
The method of  claim 6 , wherein the forming the third pattern feature over the target layer includes:\n forming a patterned resist layer over the target layer, the first pattern feature, the second pattern feature, and the second spacer layer, wherein the patterned resist layer includes a trench that exposes the first portion of the second spacer layer disposed along the sidewall of the first pattern feature, the second portion of the second spacer layer disposed along the sidewall of the second pattern feature, and the portion of the space defined between the first portion of the second spacer layer and the second portion of the second spacer layer; depositing a material layer over the patterned resist layer, the exposed first portion of the second spacer layer, the exposed second portion of the second spacer layer, and the portion of the space defined between the first portion of the second spacer layer and the second portion of the second spacer layer, wherein the material layer fills the trench; etching back the material layer, such that the material layer is removed from over the patterned resist layer, the exposed first portion of the second spacer layer, and the exposed second portion of the second spacer layer; and removing the patterned resist layer, wherein the material layer remaining after the depositing and the etching back defines the third pattern feature.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.84906
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15668930', '15173840', '14262279', '14266878', '15174131']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9151459947195218
- 35 USC 102 Novelty (BERT): 0.5211807874348021
- Combined Prediction Score: 0.8757494739910499
- Mean Citation Score: 254.466194
- Max Citation Score: 285.2498
- Similarity Product: 191.298325313592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test