PATENT CLAIM ANALYSIS

Application Number: 16194781
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor chip includes: a memory cell having a bit line, a word line, and a power supply node; a first conductive line formed in a first conductive layer, and the first conductive line electrically coupled to the bit line; a second conductive line formed in a second conductive layer different from the first conductive layer, and the second conductive line electrically coupled to the word line; and a third conductive line formed in a third conductive layer different from the first conductive layer and the second conductive layer, and the third conductive line electrically coupled to the power supply node; wherein the second conductive line has a thickness which is thicker than those of the first conductive line and the third conductive line.

Claim (Index 4):
The semiconductor chip of  claim 1 , further comprising:\n a fourth conductive line formed in a fourth conductive layer different from the first conductive layer, the second conductive layer, and the third conductive layer, and the fourth conductive line electrically coupled to the second conductive line.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 98.0
- Lexical Diversity: 3.29268
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15462259', '14969730', '15409090', '14978487', '09996574']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.906294064642463
- 35 USC 102 Novelty (BERT): 0.5702116506335451
- Combined Prediction Score: 0.8726858232415712
- Mean Citation Score: 302.2068680000001
- Max Citation Score: 456.2161
- Similarity Product: 372.35953730234496

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test