PATENT CLAIM ANALYSIS

Application Number: 15941995
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["711", "122000"]

Abstract:
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.

Claim (Index 18):
The system of  claim 1 , further comprising an audio processor coupled with the processor core by at least an interconnect.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 90.0
- Lexical Diversity: 3.14583
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15942046', '15433500', '14335006', '14969249', '13838544']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5445307403629268
- 35 USC 102 Novelty (BERT): 0.5775872783478124
- Combined Prediction Score: 0.5478363941614154
- Mean Citation Score: 397.42178
- Max Citation Score: 505.02063
- Similarity Product: 382.0678260165435

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test