PATENT CLAIM ANALYSIS

Application Number: 15982024
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185110"]

Abstract:
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Claim (Index 3):
The memory system of  claim 2 , wherein\n in a case that an error is detected after the first read, the control unit is configured to set the second voltage in the second read, and in a case that the second voltage is set in the second read and an error is not detected after the second read, the control unit is configured to record the data.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.4
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14565522', '15343484', '15673512', '13462022', '15459294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7859013403290692
- 35 USC 102 Novelty (BERT): 0.4953245540233001
- Combined Prediction Score: 0.7568436616984923
- Mean Citation Score: 222.890298
- Max Citation Score: 248.09294
- Similarity Product: 190.6932656235849

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test