PATENT CLAIM ANALYSIS

Application Number: 16282682
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "750000"]

Abstract:
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Claim (Index 4):
The method of  claim 3 , wherein at the point where the preliner layer and the top surface of the metal wire are adjacent to each other, no step is formed between the uppermost surface of the preliner layer and the top surface of the metal wire.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 99.0
- Lexical Diversity: 2.16129
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14815225', '14247234', '14802086', '15667118', '14802467']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9251395965631372
- 35 USC 102 Novelty (BERT): 0.521568340523944
- Combined Prediction Score: 0.8847824709592179
- Mean Citation Score: 232.05178
- Max Citation Score: 240.70013
- Similarity Product: 118.30169409860908

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test