PATENT CLAIM ANALYSIS

Application Number: 15963747
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["375", "240260"]

Abstract:
Systems and methods are described for processing data from a sequential series of groups of frames to achieve a target average processing bit rate for a particular group of frames in the series. In an example, a look-ahead buffer circuit can be populated with a number of frames from a particular group of frames, and a bit allocation can be determined for a frame in the look-ahead buffer circuit using bit request information about all of the frames in the buffer. The look-ahead buffer circuit can be populated with streaming frame information in a first-in-first-out manner, and bit allocation processing can be performed for each frame, in a particular group of frames, based on a frame position in the look-ahead buffer circuit and further based on bit requests associated with other frames in the look-ahead buffer circuit.

Claim (Index 18):
The system of  claim 15 , wherein the bit allocation processor circuit is configured to determine the first bit allocation based on constraints associated with one or more frames in the first group of frames F 1  or in another group of frames.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.45763
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12131268', '10665228', '10183197', '13091414', '10214786']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5060736486611324
- 35 USC 102 Novelty (BERT): 0.5014012374942511
- Combined Prediction Score: 0.5056064075444442
- Mean Citation Score: 205.01348
- Max Citation Score: 215.37404
- Similarity Product: 136.50100484731436

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test