PATENT CLAIM ANALYSIS

Application Number: 15950000
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-04
Patent Classification: ["257", "659000"]

Abstract:
A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least a portion of the semiconductor chip; and a connection member including an insulating layer disposed on the active surface of the semiconductor chip, a signal pattern disposed in the insulating layer, first ground patterns disposed to be spaced apart from the signal pattern on both sides of the signal pattern, second ground patterns disposed to be spaced apart from the signal pattern in an upper portion and a lower portion of the signal pattern, and line vias connecting the first ground patterns and the second ground patterns to each other and having a line shape.

Claim (Index 16):
The semiconductor package of  claim 15 , wherein the connection member includes:\n a first insulating layer disposed on the active surface of the semiconductor chip; a first via penetrating through the first insulating layer and connected to the connection pad; a first redistribution layer disposed on the first insulating layer and including a first ground pattern; a second insulating layer disposed on the first insulating layer and covering the first redistribution layer; a second via penetrating through the second insulating layer, connected to the first redistribution layer, and including first line vias connected to the first ground pattern; a second redistribution layer disposed on the second insulating layer, and including the signal pattern and second ground patterns disposed to be spaced apart from the signal pattern and connected to the first line vias; a third insulating layer disposed on the second insulating layer and covering the second redistribution layer; a third via penetrating through the third insulating layer and connected to the second redistribution layer, and including second line vias connected to the second ground patterns; and a third redistribution layer disposed on the third insulating layer and including a third ground pattern connected to the second line vias.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 91.0
- Lexical Diversity: 2.42593
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15941334', '15943200', '15819541', '15946109', '15413713']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9401374868983844
- 35 USC 102 Novelty (BERT): 0.5152279882936807
- Combined Prediction Score: 0.897646537037914
- Mean Citation Score: 297.966728
- Max Citation Score: 314.6857
- Similarity Product: 250.99758182105413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test