PATENT CLAIM ANALYSIS

Application Number: 15905979
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-10
Patent Classification: ["712", "221000"]

Abstract:
A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

Claim (Index 1):
A semiconductor device, comprising:\n a load store unit configured to transmit image data to a memory device and to receive image data from the memory device; an internal register configured to store the received image data provided from the load store unit; a data arrange layer configured to rearrange the stored image data from the internal register into N number of data rows, wherein the N number of data rows each have a plurality of lanes; and a plurality of arithmetic logic units (ALUs) comprising N number of ALU groups, the N number of ALU groups respectively configured to process the rearranged image data of the N number of data rows.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.35484
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15717989', '14649859', '10846788', '10846821', '11973738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5200565862289663
- 35 USC 102 Novelty (BERT): 0.5469322559516145
- Combined Prediction Score: 0.5227441532012311
- Mean Citation Score: 229.329524
- Max Citation Score: 407.75513
- Similarity Product: 286.0611489415253

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test