PATENT CLAIM ANALYSIS

Application Number: 15972096
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["438", "059000"]

Abstract:
The present disclosure provides a display panel, its manufacturing method and a display device. The manufacturing method of the display panel comprises: forming, on a substrate, a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode; forming a hydrogen diffusion barrier layer that covers the entire substrate, wherein the hydrogen diffusion barrier layer is electrically conductive and is electrically connected to the drain electrode; and forming a photosensitive structure layer on the hydrogen diffusion barrier layer.

Claim (Index 10):
The method according to  claim 1 , wherein the step of forming the thin film transistor on the substrate comprises:\n forming, on the substrate, the gate electrode and a signal line, and a first insulating layer covering the gate electrode and the signal line; forming the active layer on the first insulating layer, wherein the active layer is an oxide active layer; forming a second insulating layer covering the oxide active layer, wherein the second insulating layer has two first via holes that run through the second insulating layer to expose the oxide active layer, and a second via hole that runs through the first insulating layer and the second insulating layer to expose the signal line; forming the source electrode, the drain electrode and a connecting electrode on the second insulating layer, wherein the source electrode and the drain electrode are electrically connected to the oxide active layer through the two first via holes, respectively, and the connecting electrode is electrically connected to the signal line through the second via hole; and forming a third insulating layer covering the source electrode, the drain electrode and the connecting electrode, wherein the third insulating layer has a third via hole that runs through the third insulating layer to expose the drain electrode, and a fourth via hole that runs through the third insulating layer to expose the connecting electrode.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 2.02128
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13995424', '15851148', '12292095', '14354204', '15504030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8603155220639533
- 35 USC 102 Novelty (BERT): 0.5108768647215883
- Combined Prediction Score: 0.8253716563297169
- Mean Citation Score: 262.77206
- Max Citation Score: 273.1833
- Similarity Product: 209.8943326882481

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test