PATENT CLAIM ANALYSIS

Application Number: 15922258
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-08
Patent Classification: ["711", "146000"]

Abstract:
A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

Claim (Index 18):
A memory interface according to  claim 16 , in which the reverse translation module comprises a reverse translation data structure configured to maintain a mapping from the physical address space to the virtual address space.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.21739
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10814154', '12113262', '11093152', '13587420', '12126674']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5617868352667266
- 35 USC 102 Novelty (BERT): 0.4964847432039393
- Combined Prediction Score: 0.5552566260604479
- Mean Citation Score: 225.40566200000004
- Max Citation Score: 227.55988
- Similarity Product: 154.84319322064874

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test