PATENT CLAIM ANALYSIS

Application Number: 15981505
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "369000"]

Abstract:
A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.

Claim (Index 10):
A SRAM device manufacturing method, comprising:\n providing a substrate structure, comprising:\n a substrate; \n a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with the first semiconductor column and the second semiconductor column on the substrate and separated by a space; and \n a first separation material layer on the substrate at least partially filling the space between the first semiconductor column and the second semiconductor column; \n conducting an etch-back process on the first separation material layer to form a first separation region, wherein the first separation region comprises a first region and a second region, with the first region adjacent to both the first semiconductor column and the second semiconductor column, the second region on the first region and separated from the first semiconductor column and the second semiconductor column; and forming a gate stack structure, wherein the gate stack structure comprises:\n a gate dielectric layer comprising a first part and a second part, wherein the first part is on a portion of a side surface of the first semiconductor column and the second part is on a portion of a side surface of the second semiconductor column, and the gate dielectric layer exposes an upper portion of the first semiconductor column and an upper portion of the second semiconductor column; \n a P-type work function regulation layer comprising a first area and a second area adjacent to each other, with the first area on the first part of the gate dielectric layer, and the second area on a first portion of the first separation region; \n a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other, with the third area on the second part of the gate dielectric layer, and the fourth area on a second portion of the first separation region; and \n a gate on the P-type work function regulation layer and the N-type work function regulation layer.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 2.60938
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15916729', '14165930', '14621440', '14271909', '15455203']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.910237827852656
- 35 USC 102 Novelty (BERT): 0.4610122444994156
- Combined Prediction Score: 0.8653152695173321
- Mean Citation Score: 164.915688
- Max Citation Score: 173.95296000000005
- Similarity Product: 144.28999188514717

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test