PATENT CLAIM ANALYSIS

Application Number: 16102391
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-07
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

Claim (Index 1):
A semiconductor package comprising:\n a lower chip including a lower chip body, first through silicon vias (TSVs) extending vertically through the lower chip body, and pads on an upper surface of the lower chip body, the pads being electrically connected to the first TSVs, respectively; an upper chip on the lower chip, the upper chip including an upper chip body, and bumps on a lower surface of the upper chip body, the bumps directly bonded to corresponding ones of the pads of the lower chip, respectively, and each of the bumps including a pillar and a solder layer; and an adhesive layer between the lower chip body and the upper chip body, wherein each of the pillars of the bumps, the first TSVs and the pads has a centerline extending in a direction perpendicular to the upper surface of the lower chip body, the centerlines of the pillars of the bumps extend through geometric centers of the pillars, respectively, as viewed in a plan view of the semiconductor package, the centerlines of the first TSVs extend through axial centers of the first TSVs, respectively, the centerlines of the pads extend vertically through geometric centers of the pads, respectively, as viewed in a plan view of the semiconductor package, the centerlines of the pillars of the bumps are aligned with the centerlines of the first TSVs, respectively, and in a peripheral region of the lower chip, the centerline of the pillar of a bump is offset from the centerline of the corresponding one of the pads to which the bump is bonded.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 96.0
- Lexical Diversity: 2.65217
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12907028', '15493096', '13188554', '15943072', '10424096']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9216878173130212
- 35 USC 102 Novelty (BERT): 0.4983914784036034
- Combined Prediction Score: 0.8793581834220795
- Mean Citation Score: 252.506064
- Max Citation Score: 268.55466
- Similarity Product: 210.7794311708343

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test