PATENT CLAIM ANALYSIS

Application Number: 15997849
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["174", "262000"]

Abstract:
The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

Claim (Index 13):
An interposer substrate, comprising:\n a second dielectric material layer having opposing first and second surfaces; a first wiring layer embedded in the second dielectric material layer and exposed from the first surface of the second dielectric material layer; a first dielectric material layer formed on the first surface of the second dielectric material layer and the first wiring layer, wherein the first dielectric material layer has a plurality of openings, from which a portion of the first wiring layer is exposed; a plurality of first conductive blocks embedded in the second dielectric material layer and having first terminal surfaces connected to the first wiring layer and second terminal surfaces opposing to the first terminal surfaces and flush with the second surface of the second dielectric material layer; a second wiring layer formed on the second surface of the second dielectric material layer and having a first side connected to the second terminal surfaces of the first conductive blocks and a second side opposing to the first surface of the second wiring layer; a plurality of second conductive blocks formed on the second side of the second wiring layer; and an insulative protection layer formed on the second surface of the second dielectric material layer, the second wiring layer and the second conductive blocks, wherein an end of the second conductive blocks is exposed from the insulative protection layer, and the insulative protection layer has at least a concave portion formed between two of the second conductive blocks.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 94.0
- Lexical Diversity: 2.6
- Patent Class: 174.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14706101', '14541688', '13588030', '14810523', '13074467']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8436440973694337
- 35 USC 102 Novelty (BERT): 0.5044301645462991
- Combined Prediction Score: 0.8097227040871202
- Mean Citation Score: 254.37162200000003
- Max Citation Score: 316.51376
- Similarity Product: 304.1946906672287

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test