PATENT CLAIM ANALYSIS

Application Number: 16267307
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "737000"]

Abstract:
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Claim (Index 19):
A semiconductor device comprising:\n a semiconductor substrate; a multilayer wiring formed over the semiconductor substrate and including an uppermost wiring formed in an uppermost layer thereof; a first pad electrode formed in the same layer as the uppermost wiring; a second pad electrode formed in the same layer as the uppermost wiring; dummy patterns formed in the same layer as the uppermost wiring; an insulating film formed over the uppermost wiring, the first pad electrode, the second pad electrode and the dummy patterns, the insulating film having a first opening and a second opening; a first bump electrode formed over the insulating film and electrically connected with the first pad electrode through the first opening; and a second bump electrode formed over the insulating film and electrically connected with the second pad electrode through the second opening, wherein the first bump electrode is disposed in a region different from the dummy patterns in plan view, wherein the first bump electrode overlaps the uppermost wiring, and wherein the second bump electrode overlaps the uppermost wiring and the dummy patterns in plan view.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 99.0
- Lexical Diversity: 2.16923
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14953390', '14320686', '14953382', '12239810', '15264588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9416280104315736
- 35 USC 102 Novelty (BERT): 0.6034929883286384
- Combined Prediction Score: 0.9078145082212802
- Mean Citation Score: 537.659462
- Max Citation Score: 544.57916
- Similarity Product: 470.9671058716774

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test