PATENT CLAIM ANALYSIS

Application Number: 15956090
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "288000"]

Abstract:
Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

Claim (Index 13):
A field effect transistor comprising:\n source/drain regions and a channel region positioned laterally between the source/drain regions; a gate adjacent to the channel region, wherein the gate has a first top surface and a first sidewall; a sidewall spacer positioned laterally adjacent to the first sidewall of the gate, wherein the sidewall spacer has a second sidewall and a second top surface and wherein the first top surface of the gate and the second top surface of the sidewall spacer are essentially co-planar; an interlayer dielectric layer positioned laterally adjacent to the second sidewall of the sidewall spacer, the interlayer dielectric layer having a third top surface that is below a level of the first top surface and the second top surface; and a dielectric cap layer on the interlayer dielectric layer, the sidewall spacer and gate, wherein the dielectric cap layer has an essentially uniform thickness and a portion that is above the third top surface of the interlayer dielectric layer, that is positioned laterally immediately adjacent to the second sidewall of the sidewall spacer and that has a fourth top surface below a level of the first top surface of the gate.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15878486', '15851774', '15388400', '15354212', '15468170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9391547308772537
- 35 USC 102 Novelty (BERT): 0.5449922734084399
- Combined Prediction Score: 0.8997384851303722
- Mean Citation Score: 405.260168
- Max Citation Score: 414.2269
- Similarity Product: 322.7519048439741

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test