PATENT CLAIM ANALYSIS

Application Number: 15904292
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "230020"]

Abstract:
Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

Claim (Index 7):
The integrated circuit of  claim 6 , wherein the transistor is coupled between the sense amplifier circuitry and the tristate inverter.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 88.0
- Lexical Diversity: 2.70588
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15891212', '15789715', '15256200', '15477516', '15490352']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7653767428148363
- 35 USC 102 Novelty (BERT): 0.4955191235188412
- Combined Prediction Score: 0.7383909808852368
- Mean Citation Score: 171.0528
- Max Citation Score: 210.76051
- Similarity Product: 142.78078811905442

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test