PATENT CLAIM ANALYSIS

Application Number: 16132984
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["438", "588000"]

Abstract:
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Claim (Index 17):
A method for forming a string of memory cells, comprising:\n forming respective charge storage structures in multiple levels of control gate material, the multiple levels of control gate material alternating with multiple dielectric levels above a source and a source select gate material; forming a first opening through the multiple alternating levels of control gate control gate material and dielectric, the first opening extending adjacent multiple charge storage structures; forming a semiconductor pillar within the first opening, the semiconductor pillar extending adjacent the multiple charge storage structures adjacent the first opening; removing the first semiconductor pillar to expose sidewalls defining the first opening; and forming a monolithic semiconductor liner along the sidewalls, the monolithic semiconductor liner electrically contacting the source and extending adjacent to the charge storage structures, wherein the multiple charge storage structures are separated from the monolithic semiconductor liner by a tunnel dielectric, the monolithic semiconductor liner defining a second opening within the liner; forming an insulator material within the second opening; and forming a conductive plug over the insulator material such that the plug connects to a top portion of the monolithic semiconductor liner.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 97.0
- Lexical Diversity: 2.76271
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15221131', '14069574', '14069553', '14808229', '14824942']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8290653888396075
- 35 USC 102 Novelty (BERT): 0.4932057581759699
- Combined Prediction Score: 0.7954794257732437
- Mean Citation Score: 213.76065
- Max Citation Score: 261.02896
- Similarity Product: 238.06376378169065

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test