PATENT CLAIM ANALYSIS

Application Number: 15989491
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["438", "268000"]

Abstract:
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Claim (Index 11):
A method, comprising:\n forming first and second gate structures each comprising:\n a fin body composed of semiconductor material, the fin body having a first end and a second end opposite the first end; \n a top portion of semiconductor material on the second end of the fin body and having a width larger than that of the fin body; \n a first silicide contact at the first end of the fin body; \n a second silicide contact at the top portion of the semiconductor material on the second end of the fin body; \n a gate dielectric material on a sidewall of the fin body; and \n a gate material on the gate dielectric material.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 93.0
- Lexical Diversity: 1.68571
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15296577', '14965988', '14560672', '14965985', '15452818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8551233653244843
- 35 USC 102 Novelty (BERT): 0.4897594622111877
- Combined Prediction Score: 0.8185869750131547
- Mean Citation Score: 253.057292
- Max Citation Score: 257.8275
- Similarity Product: 221.65535297557707

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test