PATENT CLAIM ANALYSIS

Application Number: 15919053
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "226000"]

Abstract:
A power management integrated circuit (PMIC) that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

Claim (Index 9):
The power management integrated circuit of  claim 6 , wherein the first functionalities comprise generating control signals for switches.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.74667
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15918627', '12841515', '13957316', '13533088', '14017389']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7782872439351711
- 35 USC 102 Novelty (BERT): 0.4617646963448982
- Combined Prediction Score: 0.7466349891761439
- Mean Citation Score: 101.45157
- Max Citation Score: 115.52766
- Similarity Product: 80.30264404610753

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test