PATENT CLAIM ANALYSIS

Application Number: 16175066
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["714", "727000"]

Abstract:
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Claim (Index 1):
An integrated circuit comprising:\n a first circuit block including a first TAP and having a first test clock input, a first test mode input, a first test data input and first test data output coupled to the first TAP; a second circuit block including a second TAP and having a second test clock input, a second test mode input, a second test data input and second test data output coupled to the second TAP; a selector including a register and having a plurality of control outputs coupled to the register: and a scan router having control inputs coupled to the plurality of control outputs, a scanin input, a scanout output, a first scanin output coupled to said first test data input, a first scanout input coupled to said first test data output, a second scanin output coupled to said second test data input and a second scanout input coupled to the second test data output, the scan router being configurable in response to the control inputs either: (i) to couple the scanin input to the first scanin output and couple the scanout output to the first scanout input, (ii) to couple the scanin input to the second scanin output and couple the scanout output to the second scanout input, and (iii) to couple the scanin input to the first scanin output, couple the first scanout input to the second scanin output, and couple the scanout output to the second scanout input.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 1.98551
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16003858', '14612833', '12846287', '15015885', '11762893']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4500086394005972
- 35 USC 102 Novelty (BERT): 0.5953131568208608
- Combined Prediction Score: 0.4645390911426236
- Mean Citation Score: 643.559328
- Max Citation Score: 644.81085
- Similarity Product: 430.7477034732164

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test