PATENT CLAIM ANALYSIS

Application Number: 16278349
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A MOS (“metal-oxide-semiconductor”) transistor in addition to a capacitor or transistor acting as a capacitor can also be included. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. A floating gate of an NMOS transistor can be connected to the other side of the selector device, and a second NMOS transistor can be connected in series with the first NMOS transistor.

Claim (Index 3):
A method for operating a device including a memory circuit comprising a transistor and a volatile selector device comprising a first electrode and a second electrode, wherein the first electrode of the selector device is coupled to a gate of the transistor, and the volatile selector device is characterized by a low resistance state in response to a threshold voltage greater than zero applied across the first electrode and the second electrode and is characterized by a high resistance state in response to a voltage of smaller magnitude than the threshold voltage, and greater than zero, applied across the first electrode and the second electrode, the method comprising:\n applying a first voltage to the memory circuit to thereby cause the selector device to enter into the low resistance state and to thereby induce at least a first charge upon the gate of the transistor, wherein a magnitude of the first charge is in response to a magnitude of the first voltage; and removing the first voltage from the memory circuit to thereby cause the selector device to enter into the high resistance state and to thereby trap the first charge upon the gate of the transistor; wherein the transistor enters a first state in response to the first charge trapped upon the gate of the transistor; and wherein the transistor is characterized by a first source to drain resistance in response to the transistor being in the first state.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 99.0
- Lexical Diversity: 2.125
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15256007', '14717185', '14795105', '15469179', '14726071']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5900071910299232
- 35 USC 102 Novelty (BERT): 0.5098362098780412
- Combined Prediction Score: 0.581990092914735
- Mean Citation Score: 277.139524
- Max Citation Score: 333.4531
- Similarity Product: 276.05500678541057

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test