PATENT CLAIM ANALYSIS

Application Number: 16166603
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

Claim (Index 17):
A method of forming a memory cell, comprising:\n forming a dielectric layer over a substrate; forming a sacrificial dielectric layer contacting an upper surface of the dielectric layer; forming a select gate contacting the upper surface of the dielectric layer and along a side of the sacrificial dielectric layer; forming a charge trapping layer on the select gate; and forming a memory gate on the charge trapping layer.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 97.0
- Lexical Diversity: 2.03704
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14296496', '15167070', '14182952', '14933046', '14493568']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9115312621501264
- 35 USC 102 Novelty (BERT): 0.4700612424702675
- Combined Prediction Score: 0.8673842601821404
- Mean Citation Score: 181.86874000000003
- Max Citation Score: 187.40468
- Similarity Product: 149.89047023987294

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test