PATENT CLAIM ANALYSIS

Application Number: 16124182
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["710", "052000"]

Abstract:
A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

Claim (Index 15):
A method, comprising:\n receiving a second Peripheral Component Interconnect Exchange (PCIe) transaction from a storage device at an acceleration module; determining whether the second PCIe transaction was received at a first downstream root port of the acceleration module or a second downstream root port of the acceleration module; based at least in part on determining that the second PCIe transaction was received at the first downstream root port of the acceleration module, delivering the second PCIe transaction to a processor using an upstream endpoint of the acceleration module; and based at least in part on determining that the second PCIe transaction was received at the second downstream root port of the acceleration module, processing the second PCIe transaction at an Acceleration Platform Manager (APM-F) of the acceleration module. wherein the acceleration module supports performing an acceleration instruction on application data on the storage device for an application program without loading the application data into a memory associated with the processor, and wherein the processor, the acceleration module, and the storage device communicate using a PCIe bus.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.35897
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16122865', '16124179', '16124183', '12975944', '14019841']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7162027575265267
- 35 USC 102 Novelty (BERT): 0.5987916789791419
- Combined Prediction Score: 0.7044616496717883
- Mean Citation Score: 376.810618
- Max Citation Score: 543.5762
- Similarity Product: 486.93899131793967

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test