PATENT CLAIM ANALYSIS

Application Number: 15992008
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["375", "359000"]

Abstract:
A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

Claim (Index 12):
The apparatus of  claim 11 , further comprising:\n a synchronizer placed between a request output of the first FIFO block and a request input of the second FIFO block, wherein the synchronizer is to synchronize signals output from the first clock domain to the second clock domain; and a fixed delay placed between the request output of the first FIFO block and the second FIFO block.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 1.48
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15481407', '13306828', '12193609', '14749905', '12966888']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4852431698404666
- 35 USC 102 Novelty (BERT): 0.5768015720514168
- Combined Prediction Score: 0.4943990100615617
- Mean Citation Score: 289.8562780000001
- Max Citation Score: 498.61905
- Similarity Product: 399.2943856964797

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test