PATENT CLAIM ANALYSIS

Application Number: 15958460
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["365", "189090"]

Abstract:
A random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the sensing circuit judges a storage state of the selected cell according to a first charging current of the bit line and a second charging current of the inverted bit line, and determines a bit of a random code according to the storage state of the selected cell.

Claim (Index 14):
A sensing method for a random code generator, the random code generator comprising a memory cell array and a sensing circuit, the memory cell array comprising plural antifuse differential cells, the sensing method comprising steps of:\n selecting a first antifuse differential cell of the memory cell array as a selected cell; providing a first read voltage to a first antifuse control line of the selected cell, providing a second read voltage to a second antifuse control line of the selected cell, connecting a bit line of the selected cell to an input terminal of the sensing circuit, and connecting an inverted bit line of the selected cell to an inverted input terminal of the sensing circuit; pre-charging the bit line and the inverted bit line of the selected cell to a ground voltage; generating a first charging current to charge the bit line, and generating a second charging current to charge the inverted bit line; if a first voltage of the bit line is higher than a second voltage of the inverted bit line, discharging the second voltage of the inverted bit line to enhance a voltage difference between the bit line and the inverted bit line; if the second voltage of the inverted bit line is higher than the first voltage of the bit line, discharging the first voltage of the bit line to enhance the voltage difference between the bit line and the inverted bit line; and judging a storage state of the selected cell according to the voltage difference, and determining a bit of a random code according to the storage state of the selected cell.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 91.0
- Lexical Diversity: 3.17391
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15209079', '15643525', '15726470', '13566575', '12385198']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7805687134244189
- 35 USC 102 Novelty (BERT): 0.5129187517486432
- Combined Prediction Score: 0.7538037172568414
- Mean Citation Score: 275.09455
- Max Citation Score: 318.0738
- Similarity Product: 260.6848833578468

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test