PATENT CLAIM ANALYSIS

Application Number: 15911180
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "777000"]

Abstract:
The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

Claim (Index 12):
A package structure, comprising:\n a first die and a second die, both the first die and the second die comprise:\n a first surface; \n a second surface disposed opposite to the first surface; and \n at least two sidewalls disposed between the first surface and the second surface; and \n an underfill layer covering the first surface of the first die, the first surface of the second die and at least one sidewall of the first die, wherein at least one sidewall of the first die is not covered by the underfill layer.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.02703
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14287065', '15677339', '14323960', '14103411', '13280368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9116740157528868
- 35 USC 102 Novelty (BERT): 0.5019003701380256
- Combined Prediction Score: 0.8706966511914006
- Mean Citation Score: 184.131426
- Max Citation Score: 220.267
- Similarity Product: 137.46218175429107

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test