PATENT CLAIM ANALYSIS

Application Number: 15918933
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["327", "111000"]

Abstract:
Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Claim (Index 2):
A high speed high voltage (HSHV) open drain driver comprising:\n a main stack of N transistors of a first type coupled between a reference voltage and an output node of the HSHV driver, the N transistors comprising a first transistor as an input transistor of the HSHV open drain driver and an Nth transistor as an output transistor of the HSHV open drain driver, N being an integer equal to or greater than three; a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of N\u22121 transistors of a second type; wherein: a gate node of the first transistor of the main stack is coupled to a drain node of a first transistor of the biasing stack, gate nodes of a second to the (N\u22121)th transistor of the main stack are coupled to respective N\u22122 common source-drain nodes of the transistors of the biasing stack, a gate node of the Nth transistor of the main stack is coupled to a source node of the (N\u22121)th transistor of the biasing stack, N\u22121 common source-drain nodes of transistors of the main stack are coupled to respective N\u22121 gate nodes of transistors of the biasing stack, the output node is a drain node of the output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and transistors of the main stack and the biasing stack have operating voltages substantially smaller than the high voltage.

Metadata:
- Claim Count in Document: 57.0
- Percentile: 90.0
- Lexical Diversity: 1.90411
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15701304', '15066647', '15627196', '15690115', '15268297']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7516570086100153
- 35 USC 102 Novelty (BERT): 0.576011784601085
- Combined Prediction Score: 0.7340924862091223
- Mean Citation Score: 342.2240920000001
- Max Citation Score: 486.97345
- Similarity Product: 396.5406810555607

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test