PATENT CLAIM ANALYSIS

Application Number: 15980341
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "189070"]

Abstract:
A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.

Claim (Index 12):
The method according to  claim 11 , wherein the enabling of only the second bit line comprises enabling the second bit line included in the second mat in response to a column address indicating the first bit line.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 93.0
- Lexical Diversity: 4.05556
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15378308', '13231687', '12549948', '13777818', '13655077']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7932665319589244
- 35 USC 102 Novelty (BERT): 0.5127699166233385
- Combined Prediction Score: 0.7652168704253659
- Mean Citation Score: 176.87782199999995
- Max Citation Score: 295.0853600000001
- Similarity Product: 186.23341827390684

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test