PATENT CLAIM ANALYSIS

Application Number: 16291367
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-12
Patent Classification: ["257", "401000"]

Abstract:
An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.

Claim (Index 18):
A method of fabricating an asymmetric field-effect transistor device, comprising:\n obtaining a semiconductor substrate including a plurality of parallel semiconductor fins, each of the semiconductor fins including sidewalls and a channel region; forming a plurality of dummy gates on the semiconductor substrate; forming first recesses within the semiconductor fins between first pairs of the dummy gates; forming second recesses within the semiconductor fins between second pairs of the dummy gates, wherein the first recesses are deeper than the second recesses; epitaxially growing source regions on the semiconductor fins within the first recesses; epitaxially growing drain regions on the semiconductor fins within the second recesses; and replacing at least one of the dummy gates with gate metal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 1.35294
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16016454', '15808869', '16278693', '16016477', '15847894']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9141459254499258
- 35 USC 102 Novelty (BERT): 0.5463152636544193
- Combined Prediction Score: 0.8773628592703752
- Mean Citation Score: 326.077484
- Max Citation Score: 389.8225
- Similarity Product: 332.28491001307964

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test