PATENT CLAIM ANALYSIS

Application Number: 16049059
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

Claim (Index 9):
The semiconductor device of  claim 1 , wherein the first FinFET is first conductivity type and the second FinFET is second conductivity type different from the first conductivity type.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 95.0
- Lexical Diversity: 2.39216
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16049715', '15602807', '15620063', '15653068', '15649909']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9311232967217348
- 35 USC 102 Novelty (BERT): 0.4884950719432521
- Combined Prediction Score: 0.8868604742438866
- Mean Citation Score: 229.223676
- Max Citation Score: 243.76762
- Similarity Product: 201.0674551865256

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test