PATENT CLAIM ANALYSIS

Application Number: 16149249
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "314000"]

Abstract:
A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

Claim (Index 3):
The memory device of  claim 1 , wherein the common source line includes a first part and a second part that are alternately arranged in the first direction and have different heights.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.8
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15393775', '15942683', '14987835', '15626395', '14599933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9165255235692726
- 35 USC 102 Novelty (BERT): 0.5504715330127214
- Combined Prediction Score: 0.8799201245136176
- Mean Citation Score: 286.5270700000001
- Max Citation Score: 400.7107
- Similarity Product: 285.2366158277036

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test