PATENT CLAIM ANALYSIS

Application Number: 15988125
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["716", "115000"]

Abstract:
A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.

Claim (Index 7):
The method according to  claim 6 , further comprising performing timing analysis on the integrated circuit design that includes the cumulative coupled noise associated with each of the plurality of nets.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.66102
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11417862', '13970695', '12391241', '10313866', '14067720']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3796183214552192
- 35 USC 102 Novelty (BERT): 0.4990626420738249
- Combined Prediction Score: 0.3915627535170797
- Mean Citation Score: 296.163672
- Max Citation Score: 311.28296
- Similarity Product: 210.46939803941729

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test