PATENT CLAIM ANALYSIS

Application Number: 16109955
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "738000"]

Abstract:
An embedded silicon substrate fan-out type 3D packaging structure, comprising: a silicon substrate; and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface of the silicon substrate, the pad surface of the at least one functional chip, and at least one gap between the at least one chip and the at least one groove are covered with a polymer material, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole is formed on the silicon substrate; and the silicon substrate further includes electrical interconnect structures, a first metal re-wiring and a second metal re-wiring.

Claim (Index 1):
An embedded silicon substrate fan-out type 3D packaging structure, comprising:\n a silicon substrate and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface and of the silicon substrate, the pad surface of the at least one functional chip, as well as at least one gap between the at least one functional chip and the at least one groove are covered with a polymer material, the polymer material is photosensitive, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole penetrating the silicon substrate and electrically connected to the pads is formed on the silicon substrate except for at least one position where the at least one groove is located; and the silicon substrate further includes electrical interconnect structures located on both the front surface and a back surface of the silicon substrate, and a first metal re-wiring located on the front surface and a second metal re-wiring located on the back surface, the pads are electrically connected to the electrical interconnect structures located on the front surface and the at least one conductive through hole through the first metal re-wiring, and the electrical interconnect structures located on the back surface are electrically connected to the at least one conductive through hole through the second metal re-wiring.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 96.0
- Lexical Diversity: 2.91071
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13024083', '15411889', '13984967', '12591812', '11219315']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8969279167083906
- 35 USC 102 Novelty (BERT): 0.5035769416101551
- Combined Prediction Score: 0.8575928191985671
- Mean Citation Score: 201.305592
- Max Citation Score: 224.55862
- Similarity Product: 152.50104632609248

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test