PATENT CLAIM ANALYSIS

Application Number: 15869888
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "326000"]

Abstract:
A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Claim (Index 31):
The semiconductor device of  claim 21 , further comprising a memory cell array disposed on the memory cell array region, wherein the memory cell array includes:\n a channel layer extending in a vertical direction on the second substrate; and at least one ground selection line, at least one word line, and at least one string selection line spaced apart in the vertical direction along a sidewall of the channel layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.96667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14534352', '15018477', '11541756', '14695249', '14974567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9030266199468452
- 35 USC 102 Novelty (BERT): 0.5132710966424181
- Combined Prediction Score: 0.8640510676164024
- Mean Citation Score: 239.10362
- Max Citation Score: 282.26797
- Similarity Product: 209.99512643709

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test