PATENT CLAIM ANALYSIS

Application Number: 15772410
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

Claim (Index 12):
The shift register circuitry according to  claim 3 ,\n wherein the first pull-down circuit comprises a twelfth transistor, a thirteenth transistor, and a third capacitor; wherein a control electrode of the twelfth transistor is connected to the pull-down point, a first electrode of the twelfth transistor is connected to the first pull-up point, and a second electrode of the twelfth transistor is connected to the third voltage terminal; wherein a control electrode of the thirteenth transistor is connected to the pull-down point, a first electrode of the thirteenth transistor is connected to the first output signal terminal, and a second electrode of the thirteenth transistor is connected to the third voltage terminal; wherein the third capacitor is coupled between the pull-down point and the third voltage terminal, wherein the second pull-down circuit comprises a fourteenth transistor and a fifteenth transistor; wherein a control electrode of the fourteenth transistor is connected to the pull-down point, a first electrode of the fourteenth transistor is connected to the second pull-up point, and a second electrode of the fourteenth transistor is connected to the third voltage terminal; and wherein a control electrode of the fifteenth transistor is connected to the pull-down point, a first electrode of the fifteenth transistor is connected to the second output signal terminal, and a second electrode of the fifteenth transistor is connected to the third voltage terminal.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.97778
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15680452', '15232095', '15761749', '15780157', '15750679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7248764386241013
- 35 USC 102 Novelty (BERT): 0.5075022838406008
- Combined Prediction Score: 0.7031390231457513
- Mean Citation Score: 288.8553100000001
- Max Citation Score: 305.9340200000001
- Similarity Product: 267.97513019415857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test