PATENT CLAIM ANALYSIS

Application Number: 15776780
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["327", "355000"]

Abstract:
A self-reconfigurable returnable mixer includes a self-reconfigurable transconductance stage. The input RF voltage signal is converted into RF current through the self-reconfigurable transconductance stage. The RF current is converted into an IF signal through down-conversion and low-pass filtering. The IF signal is fed back to the reconfigurable transconductance stage; the self-reconfigurable transconductance stage presents an open-loop structure to the input RF voltage signal, and the self-reconfigurable transconductance stage presents the topology structure of the negative feedback amplifier to the fed-back IF signal. The self-reconfigurable transconductance stage circuit achieves a high-linearity IF gain while providing a high bandwidth for the RF signal, effectively alleviating the contradiction between the conversion gain and the IF linearity in the conventional returnable structure.

Claim (Index 3):
The self-reconfigurable returnable mixer according to  claim 2 , further comprising:\n a double balanced switch and a load stage, the double balanced switch and the load stage comprise a seventh PMOS transistor MP 7 , an eighth PMOS transistor MP 8 , a ninth PMOS transistor MP 9 , a tenth PMOS transistor MP 10 , a third NMOS transistor MN 3 , a fourth NMOS transistor MN 4 , an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , a fourteenth resistor R 14 , a thirteenth capacitor C 13 , a fourteenth capacitor C 14 , a fifteenth capacitor C 15 , a sixteenth capacitor C 16  and a seventeenth capacitor C 17 ; a gate of the seventh PMOS transistor MP 7  is connected to a negative terminal of a local oscillator, a source of the MP 7  is connected to the lower electrode plate of the fifth capacitor C 5 , a drain of the MP 7  is connected to a drain of the third NMOS transistor MN 3 ; a gate of the eighth PMOS transistor MP 8  is connected to the negative terminal of the local oscillator, a source of the MP 8  is connected to the lower electrode plate of the sixth capacitor C 6 , a drain of the  1 \\MP 8  is connected to a drain of the fourth NMOS transistor MN 4 ; a source of the ninth PMOS transistor MP 9  is connected to the lower electrode plate of the fifth capacitor C 5 , a gate of the MP 9  is connected to the positive terminal of the local oscillator, a drain of the MP 9  is connected to the drain of the fourth NMOS transistor MN 4 ; a source of the tenth PMOS transistor MP 10  is connected to the lower electrode plate of the sixth capacitor C 6 , a gate of the MP 10  is connected to the positive terminal of the local oscillator, a drain of the MP 10  is connected to the drain of the third NMOS transistor MN 3 ; a gate of the third NMOS transistor MN 3  is interconnected with a gate of the fourth NMOS MN 4 ; a source of the third NMOS transistor MN 3  is grounded, the drain of the MN 3  is connected to the negative terminal of the ninth resistor R 9 ; a source of the fourth NMOS transistor MN 4  is grounded, the drain of the MN 4  is connected to the negative terminal of the tenth resistor R 10 ; a positive terminal of the eleventh resistor R 11  is connected to the drain of the third NMOS transistor MN 3 , a negative terminal of the R 11  is connected to the gate of the third NMOS transistor MN 3 ; a positive terminal of the twelfth resistor R 12  is connected to the drain of the fourth NMOS transistor MN 4 , a negative terminal of the R 12  is connected to the gate of the fourth NMOS transistor MN 4 ; a positive terminal of the thirteenth resistor R 13  is connected to the drain of the fifth NMOS transistor MN 5 , a negative terminal of the R 13  is connected to a positive terminal of the output voltage; a positive terminal of the fourteenth resistor R 14  is connected to the drain of the fourth NMOS transistor MN 4 , a negative terminal of the R 14  is connected to a negative terminal of the output voltage; a positive terminal of the thirteen capacitor C 13  is connected to the drain of the third NMOS transistor MN 3 , a negative terminal of the C 13  is connected to the drain of the fourth NMOS transistor MN 4 ; a positive terminal of the fourteenth capacitor C 14  is connected to the drain of the third NMOS transistor MN 3 , a negative terminal of the C 14  is grounded; a positive terminal of the fifteenth capacitor C 15  is connected to the drain of the fourth NMOS transistor MN 4 , a negative terminal of the C 15  is grounded; a positive terminal of the sixteenth capacitor C 16  is connected to the negative terminal of the thirteenth resistor R 13 , a negative terminal of the C 16  is grounded; a positive terminal of the seventeenth capacitor C 17  is connected to the negative terminal of the fourteenth resistor R 14 , a negative terminal of the C 17  is grounded.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.17241
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15509202', '13978864', '13980355', '11567114', '14407027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7968764080023217
- 35 USC 102 Novelty (BERT): 0.514143931734756
- Combined Prediction Score: 0.7686031603755652
- Mean Citation Score: 303.3156140000001
- Max Citation Score: 331.42685
- Similarity Product: 263.3001200713426

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test