PATENT CLAIM ANALYSIS

Application Number: 15915718
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-06
Patent Classification: ["327", "543000"]

Abstract:
An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.

Claim (Index 10):
The ORing circuit according to  claim 9 , wherein the second BJT and the third BJT are contained in a 6-pin SOT-363 package or in two 3-pin SOT-23 packages respectively.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 4.82353
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11493992', '13983766', '14371725', '13034518', '15009438']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.789555652987793
- 35 USC 102 Novelty (BERT): 0.5069430068565262
- Combined Prediction Score: 0.7612943883746663
- Mean Citation Score: 220.457076
- Max Citation Score: 244.18417
- Similarity Product: 146.33674151840626

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test