PATENT CLAIM ANALYSIS

Application Number: 15859863
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "401000"]

Abstract:
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Claim (Index 15):
The method of  claim 14 , wherein the removing the portion of the template dielectric regions is performed until a dielectric layer directly underlying the template dielectric regions is exposed, and the dielectric layer is formed of a material different from a material of the template dielectric regions and a material of isolation regions on opposite sides of the semiconductor strip.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 86.0
- Lexical Diversity: 2.60976
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14739294', '15221123', '14851535', '15726074', '14325768']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9168569982346804
- 35 USC 102 Novelty (BERT): 0.5229289017650111
- Combined Prediction Score: 0.8774641885877135
- Mean Citation Score: 258.01823399999995
- Max Citation Score: 283.4181200000001
- Similarity Product: 179.93006156805518

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test