PATENT CLAIM ANALYSIS

Application Number: 16167903
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "231000"]

Abstract:
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Claim (Index 2):
The method of  claim 1 , further comprising forming first and second stress liners on the integrated circuit where a dual stress liner (DSL) boundary between the first and second stress liners lies between the NMOS active area and the PMOS active area.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 1.66667
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14576659', '15409842', '14584348', '11849798', '13288664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8630900673015351
- 35 USC 102 Novelty (BERT): 0.5181223962590334
- Combined Prediction Score: 0.8285933001972849
- Mean Citation Score: 255.28350200000008
- Max Citation Score: 318.36716
- Similarity Product: 230.14004000461105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test