PATENT CLAIM ANALYSIS

Application Number: 15923501
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185170"]

Abstract:
A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

Claim (Index 1):
A semiconductor memory device, comprising:\n a first interconnect; a second interconnect; a first NAND string and a second NAND string sharing a channel and being connected in parallel between the first interconnect and the second interconnect; and a drive circuit, the first and second NAND strings each including a plurality of memory cell transistors connected in series, when reading a value from a first memory cell transistor of the plurality of memory cell transistors belonging to the first NAND string, the drive circuit performing\n applying a first potential to a gate of a second memory cell transistor of the plurality of memory cell transistors belonging to the first NAND string other than the first memory cell transistor, \n applying a second potential to a gate of a third memory cell transistor of the plurality of memory cell transistors belonging to the second NAND string, the third memory cell transistor opposing the first memory cell transistor, an absolute value of a potential difference between the second potential and a potential of the first interconnect being less than an absolute value of a potential difference between the first potential and the potential of the first interconnect, \n applying the first potential to a gate of at least one of fourth memory cell transistors of the plurality of memory cell transistors belonging to the second NAND string, the fourth memory cell transistor opposing the second memory cell transistor and being nonadjacent to the third memory cell transistor, and \n sweeping a gate potential of the first memory cell transistor between the second potential and the first potential.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 3.04545
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13619118', '14096371', '12603099', '15868718', '14849082']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7977363752184112
- 35 USC 102 Novelty (BERT): 0.4611330831708184
- Combined Prediction Score: 0.764076046013652
- Mean Citation Score: 206.628214
- Max Citation Score: 210.59702
- Similarity Product: 183.49307932970524

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test