PATENT CLAIM ANALYSIS

Application Number: 15939128
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["327", "427000"]

Abstract:
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V GS  is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V GS  type, or a mix of positive-logic and zero V GS  type FETs with end-cap FETs of the zero V GS  type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Claim (Index 7):
The invention of  claim 3 , further including at least one capacitor coupled between the source and the drain of a corresponding end-cap FET.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 1.81915
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15939144', '15585345', '15401903', '15401936', '15285431']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7032533586975517
- 35 USC 102 Novelty (BERT): 0.6487193355150334
- Combined Prediction Score: 0.6977999563792998
- Mean Citation Score: 361.679162
- Max Citation Score: 680.5834
- Similarity Product: 581.8073843708277

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test