PATENT CLAIM ANALYSIS

Application Number: 15884471
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["323", "280000"]

Abstract:
Power supply rejection (PSR) peaking in Low Dropout (LDO) voltage regulators can lead to reduced bandwidth and efficiency. This paper presents a new design method by combining power transmission lines (PTL) with LDOs for enhancing its bandwidth and efficiency. This approach is applicable for LDOs regulating high speed I/O drivers. The PTL combined with decoupling capacitors on the package or board are used to mitigate the PSR peaking. This methodology is demonstrated using printed circuit board test vehicles with off-the-shelf components. When compared to conventional approaches, the PTL solution showed ˜80% lower power supply noise.

Claim (Index 1):
A power delivery system for providing power to I/O circuits, the power system comprising:\n a. a power source; b. a voltage regulator module (VRM) connected to the power source; c. a low dropout voltage regulator (LDO); and d. a single dimension power delivery network (PDN) connected to and placed between the VRM and the LDO, wherein the combination of the VRM, LDO, and PDN allow the LDO to deliver clean power to the I/O circuits while maintaining energy efficiency.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 1.37975
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13830478', '14173742', '14776349', '14713312', '14204035']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6878531151269683
- 35 USC 102 Novelty (BERT): 0.4918814540635579
- Combined Prediction Score: 0.6682559490206272
- Mean Citation Score: 207.61921
- Max Citation Score: 216.22464
- Similarity Product: 154.074652940712

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test