PATENT CLAIM ANALYSIS

Application Number: 15990517
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["375", "376000"]

Abstract:
A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.

Claim (Index 11):
The system of  claim 10 , further comprising:\n a second frequency doubler configured to produce a second half-rate clock signal and an inverse of the second half-rate clock signal responsive to the quarter-rate clock signal, the inverse of the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal, wherein the quarter-rate clock signal is 0 degree phase quarter-rate clock signal, the quadrature of the quarter-rate clock signal is a 90 degree quarter-rate clock signal, the inverse of the quarter-rate clock signal is a 180 degree quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal is a 270 degree phase quarter-rate clock signal, and wherein the PLL is further configured to produce a 45 degree phase quarter-rate clock signal, a 135 degree phase quarter-rate clock signal, a 225 degree phase quarter-rate clock signal, and a 315 degree quarter-rate clock signal; and a third frequency doubler configured to produce a third half-rate clock signal and an inverse of the third half-rate clock signal responsive to the 45 degree phase quarter-rate clock signal, the 135 degree phase quarter-rate clock signal, the 225 degree phase quarter-rate clock signal, and the 315 degree quarter-rate clock signal; and a receiver deserializer configured to deserialize a received serial data stream using an aligned clock from a clock data recovery (CDR) circuit, wherein the CDR circuit is configured to align the aligned clock responsive to the second half-rate clock signal, the inverse of the second half-rate clock signal, the third half-rate clock signal, and the inverse of the third half-rate clock signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 1.2
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14320736', '15479423', '15273621', '15667251', '15367071']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4905646532078761
- 35 USC 102 Novelty (BERT): 0.5036589206802774
- Combined Prediction Score: 0.4918740799551162
- Mean Citation Score: 234.69520000000003
- Max Citation Score: 248.81186
- Similarity Product: 163.8935559518051

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test