PATENT CLAIM ANALYSIS

Application Number: 15974748
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "190000"]

Abstract:
A method for forming a semiconductor structure is disclosed. The method provides a substrate with an insulator pad overlying at least a top portion of the substrate. The method further includes forming a plurality of dielectric columns overlying the substrate and the dielectric pad. Each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect-ration trapping (ART) trenches. The insulator pad spans a bottom portion of a first ART trench of the plurality of ART trenches. A portion of the substrate spans a bottom portion of a second ART trench of the plurality of ART trenches. The method further includes forming a III-V semiconductor material stack in the second ART trench. The method further includes forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.

Claim (Index 3):
The method of  claim 1 , wherein forming the III-V semiconductor material stack comprises epitaxially growing the III-V semiconductor material stack in the second ART trench.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 93.0
- Lexical Diversity: 2.63793
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14994738', '15408053', '15494099', '15264688', '14643360']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9152913807120472
- 35 USC 102 Novelty (BERT): 0.5153521022743868
- Combined Prediction Score: 0.8752974528682811
- Mean Citation Score: 254.976784
- Max Citation Score: 281.411
- Similarity Product: 208.21031073051688

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test