PATENT CLAIM ANALYSIS

Application Number: 16058687
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.

Claim (Index 8):
A system, comprising:\n a memory array; an input/output (I/O) circuit associated with writing data into the memory array; a command input circuit associated with reading data from the memory array; a first driver configured to provide clock signals for the command input circuit; a second driver configured to provide clock signals for the I/O circuit; and circuitry configured to determine that data is not to be read from the memory array, and configured to adjust operation of the second driver to no longer provide the clock signals based on the determination that data is not to be read from the memory array.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 96.0
- Lexical Diversity: 2.0
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10328154', '15624491', '12795602', '11218170', '13923656']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4292021147362223
- 35 USC 102 Novelty (BERT): 0.4769566736114879
- Combined Prediction Score: 0.4339775706237488
- Mean Citation Score: 114.61606880000002
- Max Citation Score: 116.07027
- Similarity Product: 73.51033987829089

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test