PATENT CLAIM ANALYSIS

Application Number: 16110992
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "185230"]

Abstract:
A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

Claim (Index 12):
The semiconductor device of  claim 11 , comprising:\n a common data path configured to transmit data; a common read command path configured to transmit a read command signal; and a common write command path configured to transmit a write command signal, wherein each of the plurality of mode registers is coupled to the common data path, the common read command path and the common write command path.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 3.19048
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15691217', '13593018', '12167719', '11106741', '14968898']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7794000538699424
- 35 USC 102 Novelty (BERT): 0.4962964799412159
- Combined Prediction Score: 0.7510896964770698
- Mean Citation Score: 183.632692
- Max Citation Score: 267.74112
- Similarity Product: 195.44337853048327

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test