PATENT CLAIM ANALYSIS

Application Number: 16012715
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["365", "230060"]

Abstract:
Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.

Claim (Index 18):
The shifter of  claim 17 , wherein the multiplexer includes a first input end, a second input end, and an output end, and wherein the first input end of the multiplexer is coupled to the output node of the input register, the second input end of the multiplexer is coupled to the output node of the fourth register, and the output node of the multiplexer is coupled to the input node of the output register.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 1.11111
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11594807', '15063229', '12585428', '14698550', '11896788']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8057348651290968
- 35 USC 102 Novelty (BERT): 0.4643294246728475
- Combined Prediction Score: 0.7715943210834719
- Mean Citation Score: 158.75661200000005
- Max Citation Score: 165.16328
- Similarity Product: 124.38862675239562

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test