PATENT CLAIM ANALYSIS

Application Number: 15945588
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "337000"]

Abstract:
A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.

Claim (Index 18):
A method for forming a semiconductor device, the method comprising:\n providing a substrate; forming an active region over the substrate, the active region comprising one or more active fingers and one or more diode fingers; forming within one or more of the active fingers, a FET having a FET source region, a FET drain region, and a lateral FET gate electrode; forming within one or more of the diode fingers, a diode having a diode anode region, a diode cathode region, and a lateral diode gate electrode; electrically coupling the FET source region to the diode anode region; electrically coupling the FET drain region to the diode cathode region; and electrically coupling the lateral diode gate electrode to the diode anode region; wherein: the one or more diode fingers are dummy fingers of the semiconductor device; the lateral FET gate electrode is electrically isolated from the lateral diode gate electrode; the diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region the FET further comprises a FET body region, and a FET buried well region; the diode anode region further comprises a diode body region, and a diode buried well region; the FET source region, the FET drain region, and the diode cathode region are of a first conductivity type; and the FET body region, the FET buried well region, the diode body region, and the diode buried well region, are of a second conductivity type.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 3.41304
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15228213', '13887704', '14082742', '15850854', '13365983']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9067424414732838
- 35 USC 102 Novelty (BERT): 0.5062936246593436
- Combined Prediction Score: 0.8666975597918898
- Mean Citation Score: 254.438758
- Max Citation Score: 260.5234
- Similarity Product: 193.5124639278173

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test