PATENT CLAIM ANALYSIS

Application Number: 15882502
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "315000"]

Abstract:
After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.

Claim (Index 19):
The semiconductor structure of  claim 17 , wherein the non-volatile memory transistor further comprises a second gate spacer located on sidewalls of the second gate stack, wherein sidewalls of the tunneling oxide portion, the floating gate electrode and the control oxide portion are in contact with lower portions of the second gate spacer, and vertical portions of the second high-k gate dielectric are in contact with upper portions of the second gate spacer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.13725
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15241759', '15331440', '15866077', '15347326', '15670367']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9330815011465884
- 35 USC 102 Novelty (BERT): 0.5975861536640675
- Combined Prediction Score: 0.8995319663983363
- Mean Citation Score: 421.45490800000016
- Max Citation Score: 524.27484
- Similarity Product: 442.503892560196

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test