PATENT CLAIM ANALYSIS

Application Number: 15938393
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["365", "189090"]

Abstract:
A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.

Claim (Index 7):
The circuit of  claim 3 , wherein\n the logic circuit further comprises a second input terminal configured to receive an enable signal, and the switching circuit is configured to couple the voltage node with the bit line further responsive to the enable signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.21429
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13804405', '13780772', '14659642', '15434541', '14504596']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8072308309840139
- 35 USC 102 Novelty (BERT): 0.4640268564776479
- Combined Prediction Score: 0.7729104335333774
- Mean Citation Score: 185.340002
- Max Citation Score: 191.39548
- Similarity Product: 155.9266134585619

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test