PATENT CLAIM ANALYSIS

Application Number: 15903557
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["370", "236000"]

Abstract:
Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Claim (Index 1):
A hardware element incorporated into a Network on Chip (NoC), comprising:\n a plurality of physical links and virtual links; a queue for transmission of output messages to output ports of the hardware element; an arbiter configured to process input messages from input ports to the queue based on a logic scheme; bypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter; and a plurality of configurable bypass links bypassing the queue and the arbiter, the plurality of configurable bypass links providing a pathway from the bypass logic to the output ports through the physical links.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 1.40909
- Patent Class: 370.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14493018', '14726235', '14612807', '15438674', '13794273']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5954556398375833
- 35 USC 102 Novelty (BERT): 0.5075217043869049
- Combined Prediction Score: 0.5866622462925155
- Mean Citation Score: 288.700128
- Max Citation Score: 300.2489
- Similarity Product: 223.8514552483976

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test