PATENT CLAIM ANALYSIS

Application Number: 16101603
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["704", "243000"]

Abstract:
In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Claim (Index 1):
An integrated circuit comprising:\n one or more processors; at least one memory controller; and a first circuit coupled to the one or more processors and to the memory controller, wherein:\n the first circuit is configured to remain powered up during times that the one or more processors and the memory controller are powered down; \n the first circuit is configured to receive audio samples captured by one or more audio input devices and to detect a predetermined pattern in the audio samples during a time that the one or more processors and the memory controller are powered down; \n the first circuit is configured to cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern; \n the first circuit is configured to write the audio samples that match the predetermined pattern and subsequently-received samples to memory through the memory controller subsequent to powering up the memory controller in response to detecting the predetermined pattern; and \n the first circuit comprises a buffer configured to store a plurality of the audio samples, wherein a number of the plurality of audio samples is sufficient to store the audio samples that match the predetermined pattern and the subsequently-received samples until the memory controller is available to receive writes of the audio samples to the memory.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.22222
- Patent Class: 704.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14109101', '14621093', '15482142', '14458885', '14289775']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.270319348923958
- 35 USC 102 Novelty (BERT): 0.5171130904546057
- Combined Prediction Score: 0.2949987230770227
- Mean Citation Score: 260.582838
- Max Citation Score: 326.93613
- Similarity Product: 316.7438514988375

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test