PATENT CLAIM ANALYSIS

Application Number: 15919805
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["710", "316000"]

Abstract:
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Claim (Index 12):
A method for operating a slave device for a serial synchronous full duplex bus system, the method comprising:\n receiving a medium voltage data bus signal from a master device of the bus system and providing a medium voltage data signal using a data input stage, wherein the medium voltage data signal is supplied to a data signal level down shifter configured to produce a low voltage data signal corresponding to the medium voltage data signal; receiving a medium voltage clock bus signal from the master device of the bus system and providing a medium voltage clock signal using a clock input stage, wherein the medium voltage clock signal is supplied to a clock signal level down shifter configured to produce a low voltage clock signal corresponding to the medium voltage clock signal; receiving the low voltage data signal and the low voltage clock signal and carrying out one or more logical operations using an interface logic in order to produce one or more low voltage output data signals based on the low voltage data signal and based on the low voltage clock signal; using a synchronization delay flip-flop having a delay flip-flop data input, a delay flip-flop clock input and a delay flip-flop data output, wherein an asynchronous medium voltage output data signal, which is based on the one or more low voltage output data signals, is supplied to the delay flip-flop data input, wherein a medium voltage output clock signal derived from the medium voltage clock bus signal in a medium voltage portion of the slave device is supplied to the delay flip-flop clock input and wherein the delay flip-flop data output provides a synchronous medium voltage output data signal; and transmitting a medium voltage data bus signal to the master device of the bus system using a data output stage, wherein the synchronous medium voltage output signal is supplied to the data output stage.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14848472', '14028806', '11715478', '10764406', '14217510']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6187386801937472
- 35 USC 102 Novelty (BERT): 0.5699990319798178
- Combined Prediction Score: 0.6138647153723543
- Mean Citation Score: 245.13131600000008
- Max Citation Score: 441.9628
- Similarity Product: 430.21910102889535

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test