PATENT CLAIM ANALYSIS

Application Number: 15945913
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "777000"]

Abstract:
The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Claim (Index 18):
A multilayer substrate panel for manufacturing a plurality of chip modules with a plurality of discrete electronic devices embedded therein, the plurality of discrete electronic devices peripherally distributed around each one of the chip modules, the multilayer substrate panel comprising:\n a plurality of chip modules, each chip module comprising: a part of the multilayer substrate panel with a horizontal top surface, a horizontal bottom surface and one or more vertical side surfaces extending peripherally between the top surface and the bottom surface; one or more of the plurality of chip modules being configured to receive one or more of the plurality of discrete electronic devices to be mounted onto the horizontal top surface, the chip module further being configured to be mounted on a printed circuit board; a plurality of horizontal electrically conductive layers with adjacent electrically conductive layers of the plurality of horizontal electrically conductive layers being separated from each other by a horizontal electrically non-conductive layer; a plurality of predefined electrically non-conductive portions for embedding a second device of the plurality of discrete electronic devices, each of the plurality of predefined portions extending vertically through a plurality of horizontal electrically conductive layers; for each predefined portion a first of the plurality of horizontal electrically conductive layers comprises an electrically non-conductive clearance along a first part of a circumferential boundary of the respective predefined portion and an electrically conductive structure reaching to a second part of the circumferential boundary of the respective predefined portion; for each predefined portion a second of the electrically conductive layers comprises an electrically non-conductive clearance along the second part of the circumferential boundary of the respective predefined portion and an electrically conductive structure reaching to the first part of the circumferential boundary of the respective predefined portion; and a size of each predefined portion being configured to be provided with a recess for receiving a discrete electronic device comprising a first and a second electrical contact spaced apart from each other such that a first electrically conductive connection is established between the first electrical contact and the electrically conductive structure of the first of the plurality of horizontal electrically conductive layers, and such that a second electrically conductive connection is established between the second electrical contact and the second of the plurality of electrically conductive structures of the second electrically conductive layer.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 2.34848
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15214565', '15494672', '14918678', '15175378', '14188555']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9008344263929486
- 35 USC 102 Novelty (BERT): 0.5559549123574193
- Combined Prediction Score: 0.8663464749893958
- Mean Citation Score: 267.453234
- Max Citation Score: 405.03473
- Similarity Product: 386.4468519485444

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test