PATENT CLAIM ANALYSIS

Application Number: 15867118
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["438", "014000"]

Abstract:
Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

Claim (Index 10):
The method of  claim 1 , wherein the distinct offset vector for each circuit die of the IC wafer along a shared axis has a same offset orientation.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 2.43103
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15346512', '15168479', '15802121', '13692414', '15657438']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8703877250180628
- 35 USC 102 Novelty (BERT): 0.5038387450163229
- Combined Prediction Score: 0.8337328270178889
- Mean Citation Score: 216.570688
- Max Citation Score: 252.14272000000005
- Similarity Product: 177.43513299713138

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test