PATENT CLAIM ANALYSIS

Application Number: 16049403
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "401000"]

Abstract:
Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

Claim (Index 18):
The method of  claim 17 ,\n wherein the isolation layer comprises a silicon oxide material and wherein the first portion of the spacer comprises a first layer that comprises a silicon nitride material and a second layer that comprises a silicon boron carbon nitride material.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 95.0
- Lexical Diversity: 2.46
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13304936', '16005915', '15145924', '15639721', '14820564']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921819888154748
- 35 USC 102 Novelty (BERT): 0.4883348697046716
- Combined Prediction Score: 0.8784713863097403
- Mean Citation Score: 191.015024
- Max Citation Score: 195.55112
- Similarity Product: 137.2480192240763

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test