PATENT CLAIM ANALYSIS

Application Number: 15918719
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.

Claim (Index 3):
The method of  claim 2 , further comprising:\n forming a first hardmask layer on the dummy gate structure and the first and second initial gate structures; forming spacers on sidewalls of the dummy gate structure and on sidewalls of the first and second initial gate structures.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 90.0
- Lexical Diversity: 2.42857
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15612805', '15473183', '15400201', '15471983', '15918674']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.925708657209564
- 35 USC 102 Novelty (BERT): 0.5166715640719449
- Combined Prediction Score: 0.884804947895802
- Mean Citation Score: 292.5070740000001
- Max Citation Score: 321.7745700000001
- Similarity Product: 245.9365772047002

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test