PATENT CLAIM ANALYSIS

Application Number: 15977622
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "774000"]

Abstract:
Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.

Claim (Index 15):
A method used in forming integrated circuitry comprising DRAM, comprising:\n providing a substrate comprising an array region comprising memory cells individually comprising an array transistor having a pair of source/drain regions and a gate comprising a wordline, a capacitor electrically coupled to one of the source/drain regions, and the other of the source/drain regions electrically coupled to a digitline; the wordline comprising conductively-doped polysilicon directly above and directly against metal material; providing a peripheral-circuitry region adjacent the array region, the peripheral-circuitry region comprising a peripheral transistor, the wordline and the digitline extending from the array region into the peripheral-circuitry region, insulative material being directly above the wordline, the digitline, and the peripheral transistor in the peripheral-circuitry region; forming a first contact opening through the insulative material in the peripheral-circuitry region to elemental-form silicon of a source/drain region of the peripheral transistor in a vertical cross-section while the wordline and the digitline are completely covered with masking material in the peripheral-circuitry region in the vertical cross-section; in a single masking step, forming a second contact opening through the insulative material in the peripheral-circuitry region to conductive material of the digitline in the vertical cross-section and a third contact opening through the insulative material in the peripheral-circuitry region to the conductively-doped polysilicon of the wordline in the vertical cross-section while the elemental-form silicon of the source/drain region of the peripheral transistor is completely covered with masking material in the peripheral-circuitry region in the vertical cross-section; within the third contact opening and while the second contact opening is outwardly exposed, etching through the conductively-doped polysilicon to the wordline-metal material selectively relative to the conductive material of the digitline; the elemental-form silicon of the source/drain region of the peripheral transistor being completely covered with masking material in the vertical cross-section during said etching; and after said etching, forming conductive material in the first, second, and third contact openings.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.95652
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15890503', '15965632', '15903254', '12419807', '15404995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9037243482791988
- 35 USC 102 Novelty (BERT): 0.49204455014533
- Combined Prediction Score: 0.862556368465812
- Mean Citation Score: 224.72827200000003
- Max Citation Score: 234.77356
- Similarity Product: 189.37675769070864

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test