PATENT CLAIM ANALYSIS

Application Number: 15878009
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["700", "121000"]

Abstract:
A method of generating a layout of an IC includes identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell, and determining whether or not the target pin is capable of being extended into the second cell. Based on a determination that the target pin is capable of being extended into the second cell, the target pin is modified to include an extension into the second cell, the target pin thereby crossing the shared boundary. At least one of the identifying, determining, or modifying is executed by a processor of a computer.

Claim (Index 6):
The method of  claim 5 , wherein the increasing the spacing comprises applying a metal zero cut to the boundary pin.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 86.0
- Lexical Diversity: 2.30769
- Patent Class: 700.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14809698', '13908096', '14011790', '14528314', '13352738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3999386006622607
- 35 USC 102 Novelty (BERT): 0.4902259963051559
- Combined Prediction Score: 0.4089673402265502
- Mean Citation Score: 126.35477799999998
- Max Citation Score: 129.55418
- Similarity Product: 72.80340750481724

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test