PATENT CLAIM ANALYSIS

Application Number: 16132675
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185170"]

Abstract:
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Claim (Index 31):
A semiconductor memory array comprising:\n a plurality of NAND string configurations, each said NAND string configuration comprising: a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells; a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and a select gate source device connected an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device; wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a third region in electrical contact with said floating body region and spaced apart from said first and second regions; wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region; wherein each said at least one of said plurality of semiconductor memory cells has only one gate; wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals; and wherein said semiconductor memory array comprises at least one of: at least two of said select gate drain devices connected to a common bit line; or at least two of said select gate source devices connected to a common source line.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 1.47619
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15161493', '15628931', '14267112', '13244839', '12797320']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8038567015408821
- 35 USC 102 Novelty (BERT): 0.5690261853595556
- Combined Prediction Score: 0.7803736499227495
- Mean Citation Score: 370.400324
- Max Citation Score: 451.741
- Similarity Product: 441.8557891219258

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test