PATENT CLAIM ANALYSIS

Application Number: 15969855
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "288000"]

Abstract:
Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets.

Claim (Index 9):
A method of fabricating adjacent semiconductor devices, the method comprising:\n performing fabrication operations to form a first nanosheet field effect transistor (FET) device and a second nanosheet FET on a substrate; wherein the fabrication operations to form the first nanosheet FET include:\n forming a first gate spacer along a first gate region of the first nanosheet FET device; \n forming first channel nanosheets to a desired first final channel nanosheet width dimension (F-Wf) for each of the first channel nanosheets; and \n forming a first inner spacer between the first channel nanosheets; \n wherein the fabrication operations to form the second nanosheet FET include:\n forming a second gate spacer along a second gate region of the second nanosheet FET device; \n forming second channel nanosheets to a desired second final channel nanosheet width dimension (S-Wf) for each of the second channel nanosheets; and \n forming a second inner spacer between the second channel nanosheets; \n wherein the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer comprise the same type of spacer material; \n wherein forming the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer comprises, subsequent to forming the first channel nanosheets to the F-Wf and forming the second channel nanosheets to the S-Wf, conformally depositing a layer of the spacer material having a first thickness dimension to extend along a sidewall of the first gate region, a sidewall of the second gate region, sidewalls of the first channel nanosheets, sidewalls of the second channel nanosheets, within a space between the first channel nanosheets, and within a space between the second channel nanosheets; \n wherein forming the first gate spacer further comprises trimming a portion of the layer of the spacer material that is along the sidewall of the first gate region such that the portion of the spacer layer that is along the sidewall of the first gate region comprises a second thickness dimension that is less than the first thickness dimension; \n wherein forming the second gate spacer further comprises trimming a portion of the layer of the spacer material that is along the sidewall of the second gate region such that the portion of the spacer layer that is along the sidewall of the second gate region comprises a third thickness dimension that is less than the first thickness dimension; \n wherein the first gate spacer comprises the portion of the layer of the spacer material that comprises the second thickness dimension and is along the sidewall of the first gate region; \n wherein the first inner spacer comprises a portion of the layer of the spacer material that is within the space between the first channel nanosheets; \n wherein the second gate spacer comprises the portion of the layer of the spacer material that comprises the third thickness dimension and is along the sidewall of the second gate region; \n wherein the second inner spacer comprises a portion of the layer of the spacer material that is within the space between the second channel nanosheets.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 2.74138
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15944322', '15926664', '15924799', '15468755', '15629306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281290931735858
- 35 USC 102 Novelty (BERT): 0.5481507211032836
- Combined Prediction Score: 0.8901312559665556
- Mean Citation Score: 350.451002
- Max Citation Score: 408.97647
- Similarity Product: 363.3706836978704

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test