PATENT CLAIM ANALYSIS

Application Number: 15878121
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "185170"]

Abstract:
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Claim (Index 28):
The apparatus of  claim 27 , wherein the substantially equal voltage level is different from a ground reference potential.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 86.0
- Lexical Diversity: 1.875
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15692512', '15164400', '14813711', '13774522', '13245587']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.780518374434074
- 35 USC 102 Novelty (BERT): 0.5149155782784532
- Combined Prediction Score: 0.753958094818512
- Mean Citation Score: 223.94029800000004
- Max Citation Score: 275.64645
- Similarity Product: 173.16078622523548

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test