PATENT CLAIM ANALYSIS

Application Number: 15867686
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "503000"]

Abstract:
Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

Claim (Index 6):
The semiconductor package of  claim 1 , further comprising:\n a first power pattern on the semiconductor chip and coupled to the second electrode; and a second power pattern on the semiconductor chip and coupled to the second electrode pattern, wherein, when viewed in plan, the conductive pattern is provided between and is spaced apart from the first power pattern and the second power pattern.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 3.76923
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15825188', '12868091', '13274176', '13602811', '15302632']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913423667888744
- 35 USC 102 Novelty (BERT): 0.4666127153753804
- Combined Prediction Score: 0.8687425726374076
- Mean Citation Score: 180.419804
- Max Citation Score: 183.5992
- Similarity Product: 151.09795283002853

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test