PATENT CLAIM ANALYSIS

Application Number: 16004061
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["348", "300000"]

Abstract:
A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.

Claim (Index 19):
An imaging device, comprising:\n a semiconductor substrate including a first side as a light-receiving side, and a second side opposite to the first side; a plurality of photoelectric conversion regions in the semiconductor substrate, the plurality of the photoelectric conversion regions comprising;\n a first photoelectric conversion region, \n a second photoelectric conversion region, \n a third photoelectric conversion region, and \n a fourth photoelectric conversion region; wherein \n the first photoelectric conversion region is adjacent to the second photoelectric conversion region in a first direction in a plan view, and the first photoelectric conversion region is adjacent to the third photo electric conversion region in a second direction in the plan view;\n a floating diffusion region shared by the first, the second, the third and the fourth photoelectric conversion regions; \n a first element isolation region disposed between the first photoelectric conversion region and the second photoelectric conversion region; \n a second element isolation region disposed between the first photoelectric conversion region and the third photoelectric conversion region; \n a first light-shielding film disposed over the first element isolation region; \n a second light-shielding film disposed over the second element isolation region; and \n a multilayer wiring layer disposed at the second side of the semiconductor substrate, wherein \n the first element isolation region comprises a first void region, and \n the second element isolation region comprises a second void region.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 1.61818
- Patent Class: 348.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15065437', '15380461', '14260118', '13196127', '15647093']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6409666915118076
- 35 USC 102 Novelty (BERT): 0.540800264821742
- Combined Prediction Score: 0.6309500488428011
- Mean Citation Score: 352.721712
- Max Citation Score: 382.57227
- Similarity Product: 283.643688514477

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test