PATENT CLAIM ANALYSIS

Application Number: 15903999
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "149000"]

Abstract:
According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.

Claim (Index 2):
The device of  claim 1 , further comprising:\n a first voltage generating circuit which generates a first voltage; a first distributor which generates a second voltage based on the first voltage and supplies the second voltage to the gate of the first transistor of the first bank; and a second distributor which generates a third voltage based on the first voltage and supplies the third voltage to the gate of the first transistor of the second bank.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.85
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15065449', '15455906', '15261680', '15702298', '12409666']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7740863366462482
- 35 USC 102 Novelty (BERT): 0.4546542309074519
- Combined Prediction Score: 0.7421431260723685
- Mean Citation Score: 141.43437
- Max Citation Score: 149.34566
- Similarity Product: 115.27246396466258

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test