PATENT CLAIM ANALYSIS

Application Number: 16135778
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["710", "038000"]

Abstract:
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Claim (Index 32):
The electronic memory device of  claim 17  wherein each column address accesses a row of memory cells having access width and wherein the data word equals the access width.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14267190', '11072106', '09872478', '12910867', '14492551']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6753701013467338
- 35 USC 102 Novelty (BERT): 0.4978936392157203
- Combined Prediction Score: 0.6576224551336325
- Mean Citation Score: 166.558238
- Max Citation Score: 245.9379
- Similarity Product: 171.84250108832714

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test