PATENT CLAIM ANALYSIS

Application Number: 15972216
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-10
Patent Classification: ["257", "296000"]

Abstract:
The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.

Claim (Index 8):
A method for forming a bit line gate structure, comprising:\n providing a substrate; forming an amorphous silicon layer on the substrate; performing an ion doping step to form a first doped region in the amorphous silicon layer, wherein an oxide layer is formed on the surface of the amorphous silicon layer after the ion doping step is performed; performing an etching step to completely remove the oxide layer; forming a titanium silicon nitride (TiSiN) layer on the amorphous silicon layer; and performing a rapid thermal process (RTP) to diffuse the first doped region into the TiSiN layer, and to form a second doped region within the TiSiN layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.08824
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14792979', '13796449', '12944896', '10708530', '12330282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8881862190095223
- 35 USC 102 Novelty (BERT): 0.4757792141207929
- Combined Prediction Score: 0.8469455185206494
- Mean Citation Score: 141.0078
- Max Citation Score: 151.8289
- Similarity Product: 112.007733864218

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test