PATENT CLAIM ANALYSIS

Application Number: 16184794
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["327", "115000"]

Abstract:
Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

Claim (Index 14):
An apparatus comprising:\n a pair of interconnects; a first die including:\n a clock multiplier; \n a phase locked loop (PLL) coupled to the clock multiplier; and \n a clock distribution network coupled to an input and output of the PLL; and \n a second die, wherein the pair of interconnects is to couple the first die to the second die, and wherein the clock multiplier is to receive an input from the second die which includes a clock synchronization circuit.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 98.0
- Lexical Diversity: 1.77419
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15214364', '16102113', '15064799', '14059366', '11112162']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.706430394420591
- 35 USC 102 Novelty (BERT): 0.5445397633617375
- Combined Prediction Score: 0.6902413313147057
- Mean Citation Score: 197.455896
- Max Citation Score: 390.76187
- Similarity Product: 330.74807584172606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test