PATENT CLAIM ANALYSIS

Application Number: 16264195
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["257", "738000"]

Abstract:
Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

Claim (Index 1):
A package assembly comprising:\n a package substrate; and an integrated circuit (IC) die including: a semiconductor substrate; a transistor layer disposed on the semiconductor substrate forming one or more hard intellectual property (HIP) I/O blocks; an electrically insulative material disposed on the transistor layer; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals to and from the HIP I/O blocks through the electrically insulative material; a plurality of metal features coupled with the plurality of electrical routing features, wherein the plurality of metal features have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations, and wherein the HIP I/O blocks are designed to align with the I/O density; and a plurality of interconnect structures disposed on the die, the plurality of interconnect structures coupled with the plurality of metal features, wherein the interconnect structures electrically couple the IC die with the package substrate.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 99.0
- Lexical Diversity: 2.19444
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15127708', '15503377', '14768209', '15636117', '14132774']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8869599298147667
- 35 USC 102 Novelty (BERT): 0.4540672825537321
- Combined Prediction Score: 0.8436706650886632
- Mean Citation Score: 136.9501078
- Max Citation Score: 178.35323
- Similarity Product: 167.2494412577009

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test