PATENT CLAIM ANALYSIS

Application Number: 15880349
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-04
Patent Classification: ["257", "798000"]

Abstract:
A method for integrating heterogeneous elements with elements residing on a target wafer is described. A source die including a compound semiconductor substrate, an etch stop layer and at least one active semiconductor element is provided. The etch stop layer is between the active semiconductor element(s) and the substrate. The etch stop layer is resistant to a plasma etch for the substrate. A bonding agent is provided on a surface of the target wafer. The source die is aligned to and placed on the part of the surface of the target wafer such that the active semiconductor element(s) are between the target wafer's surface and the substrate. The bonding agent is between the source die and the surface of the target wafer. The source die is bonded to the target wafer using the bonding agent. The substrate of the source die is removed, the removal includes performing the plasma etch.

Claim (Index 20):
A semiconductor device including a target substrate and comprising:\n a plurality of components fabricated on the target substrate; at least one active semiconductor element integrated with the plurality of components on the target substrate, a bonding agent residing between the active semiconductor element and a portion of the target substrate, the at least one active semiconductor element being provided from a source die including a compound semiconductor (CS) substrate, an etch stop layer and at least one active semiconductor element precursor, the etch stop layer residing between the at least one active semiconductor element and the CS substrate, the etch stop layer being resistant to a plasma etch for the CS substrate, the source die being singulated prior to being bonded to the target substrate, source die being integrated into the semiconductor device by providing the bonding agent on at least a portion of a surface of a target wafer including the target substrate, aligning the source die to the portion of the surface of the target wafer, placing the source die on the portion of the surface of the target wafer such that the at least one active semiconductor element precursor is between the surface of the target wafer and the CS substrate, applying a force to at least one of the source die and the target wafer such that the bonding agent has a bond thickness, curing the bonding agent and removing the CS substrate of the source die using the removal process, the at least one active semiconductor element precursor being the at least one active semiconductor element or a portion of the at least one active semiconductor element.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.84746
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15592704', '14707367', '15480239', '15209309', '11046912']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8854857855263385
- 35 USC 102 Novelty (BERT): 0.4909869425186194
- Combined Prediction Score: 0.8460359012255666
- Mean Citation Score: 180.33566
- Max Citation Score: 186.92772
- Similarity Product: 131.16882489910122

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test