PATENT CLAIM ANALYSIS

Application Number: 16251419
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["365", "185110"]

Abstract:
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Claim (Index 2):
A memory comprising:\n a first memory cell array including a plurality of memory strings, the memory strings including a first memory string and a second memory string,\n the first memory string including a first memory cell transistor and a first select gate transistor, and \n the second memory string including a second memory cell transistor and a second select gate transistor; \n a bit line connected to one end of the first memory string and one end of the second memory string; a source line connected to the other end of the first memory string and the other end of the second memory string; a first word line connected to a gate of the first memory cell transistor and a gate of the second memory cell transistor; a first select gate line connected to a gate of the first select gate transistor; and a second select gate line connected to a gate of the first select gate transistor, wherein when a program operation on the first memory cell transistor is performed,\n a first voltage is applied to the first word line on a first timing, \n a second voltage is applied to the second select gate transistor at the first timing to turn on the second select gate transistor, \n a third voltage is applied to the second select gate transistor at a second timing after the first timing to turn off the second select gate transistor, \n a fourth voltage is applied to the first select gate transistor at a third timing after the second timing to turn on the first select gate transistor, and \n a fifth voltage is applied to the first word line at a fourth timing after the third timing.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 99.0
- Lexical Diversity: 2.15517
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15367361', '14191172', '14994203', '15916332', '13738633']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8304708869451777
- 35 USC 102 Novelty (BERT): 0.564406873683504
- Combined Prediction Score: 0.8038644856190104
- Mean Citation Score: 443.870068
- Max Citation Score: 447.97333
- Similarity Product: 422.47391731615295

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test