PATENT CLAIM ANALYSIS

Application Number: 15871436
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "031000"]

Abstract:
A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.

Claim (Index 1):
An assembly for a quantum computing device comprising:\n a housing configured as an enclosure having a bottom part, a top part, and a block, the block connecting the top and bottom parts; a quantum bus plane including a first set of recesses; a readout plane including a second set of recesses, wherein the block is configured to position the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses; and a plurality of qubit chips each having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.2619
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15175454', '14737707', '15347160', '15871443', '15827718']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9364900757295694
- 35 USC 102 Novelty (BERT): 0.5771946355414063
- Combined Prediction Score: 0.9005605317107531
- Mean Citation Score: 411.820278
- Max Citation Score: 469.85675
- Similarity Product: 453.1105507189929

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test