PATENT CLAIM ANALYSIS

Application Number: 15918432
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["714", "776000"]

Abstract:
This application discloses a data processing method and apparatus. The method includes: distributing, by a first distribution circuit, a first bit stream to FEC encoders  1  to N in a round robin fashion, where digital signals  1  to N that are output after being encoded by the FEC encoders  1  to N are in a one-to-one correspondence with a least significant bit to a most significant bit of an input signal of a PAM circuit, a coding gain G X  of an FEC encoder X is greater than a coding gain G Y  of an FEC encoder Y, 1≤X<Y≤N, N≥2, and X, Y, and N are all integers. In the method, different FEC coding gains can be provided for links with different bit error rates, so that a requirement of a high-rate Ethernet for a high gain during long-distance data transmission is met, and physical-layer resources occupied by FEC are reduced.

Claim (Index 14):
A data processing apparatus, comprising:\n a forward error correction (FEC) encoding circuit; a first distribution circuit; and a data processing circuit, wherein: the FEC encoding circuit is configured to perform FEC encoding on a first bit stream to obtain a second bit stream; the first distribution circuit is configured to distribute the second bit stream to N channels in a round robin fashion, wherein:\n the N channels are represented by channels  1  to N, respectively, \n the second bit stream comprises N digital signals, \n the N digital signals are represented by digital signals  1  to N, respectively, \n the digital signals  1  to N are transmitted to N subcircuits of the data processing circuit by using the channels  1  to N, respectively, \n the N subcircuits are represented by subcircuits  1  to N, respectively, \n the digital signals  1  to N are in a one-to-one correspondence with the channels  1  to N, \n the channels  1  to N are in a one-to-one correspondence with the subcircuits  1  to N, \n L subcircuits of the N subcircuits are L FEC encoders, \n W subcircuits of the N subcircuits are W delayers, and \n the L FEC encoders do not intersect with the W delayers; \n the data processing circuit is configured to process the digital signals  1  to N by using the subcircuits  1  to N, respectively, to obtain N processed digital signals, wherein the N processed digital signals are represented by bit streams  1  to N, respectively, and the bit streams  1  to N are in a one-to-one correspondence with the digital signals  1  to N, wherein the L FEC encoders perform FEC encoding processing on L input digital signals, respectively, to obtain L bit streams, and the W delayers perform delay processing on W input digital signals, respectively, to obtain W bit streams, wherein coding gains of the subcircuits  1  to N are represented by G 1  to G N , respectively, a coding gain of a subcircuit X is G X , a coding gain of a subcircuit Y is G Y , G X >G Y , L+W=N, L\u22651, W\u22650, 1\u2264X\u2264Y\u2264N, N\u22652, and L, W, X, Y, and N are integers; and the data processing circuit is further configured to send the bit streams  1  to N to a pulse amplitude modulation (PAM) circuit, wherein the PAM circuit is configured to modulate the bit streams  1  to N, the bit streams  1  to N are an input signal of the PAM circuit, and the bit streams  1  to N are in a one-to-one correspondence with a least significant bit to a most significant bit of the input signal.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 90.0
- Lexical Diversity: 1.89888
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15789284', '15644350', '15476323', '15200930', '14536303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2516614016606197
- 35 USC 102 Novelty (BERT): 0.4974800575082098
- Combined Prediction Score: 0.2762432672453787
- Mean Citation Score: 200.285826
- Max Citation Score: 255.5279
- Similarity Product: 199.02263126584887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test