PATENT CLAIM ANALYSIS

Application Number: 16214965
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["331", "034000"]

Abstract:
A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

Claim (Index 10):
The locked loop circuit of  claim 9 , wherein the first selected error value and the second selected error value are based on desired power parameters.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 98.0
- Lexical Diversity: 2.56522
- Patent Class: 331.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15224280', '15224199', '15224296', '15224258', '15224224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8487482910904721
- 35 USC 102 Novelty (BERT): 0.5545576392736189
- Combined Prediction Score: 0.8193292259087868
- Mean Citation Score: 452.53471
- Max Citation Score: 467.0776
- Similarity Product: 307.85390673308376

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test