PATENT CLAIM ANALYSIS

Application Number: 15780601
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["330", "253000"]

Abstract:
An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.

Claim (Index 7):
The amplifier arrangement according to one of  claim 1 , further comprising\n a third differential stage comprising a first, a second, a third and a fourth transistor, said third differential stage being coupled between the first and the second differential stage such that said first and second transistor having a common source connection coupled to a drain terminal of the first transistor of the first differential stage, and said third and fourth transistor having a common source connection coupled to a drain terminal of the second transistor of the first differential stage; a third complementary differential stage comprising a first, a second, a third and a fourth complementary transistor having opposite conductivity type compared to the transistors of the third differential stage, said third complementary differential stage being coupled between the first complementary and the second complementary differential stage such that said first and second complementary transistor having a common source connection coupled to a drain terminal of the first complementary transistor of the first complementary differential stage, and said third and fourth complementary transistor having a common source connection coupled to a drain terminal of the second complementary transistor of the first complementary differential stage; wherein\n gate terminals of the transistors of the third differential stage are coupled to a fifth pair of input terminals; and \n gate terminals of the complementary transistors of the third complementary differential stage are coupled to a sixth pair of input terminals.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 3.22917
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15100278', '11002616', '13661883', '11339716', '14837364']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8038547011508572
- 35 USC 102 Novelty (BERT): 0.4948034997685331
- Combined Prediction Score: 0.7729495810126249
- Mean Citation Score: 239.920512
- Max Citation Score: 246.97672000000003
- Similarity Product: 191.9102617225076

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test