PATENT CLAIM ANALYSIS

Application Number: 15938819
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["327", "153000"]

Abstract:
Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

Claim (Index 1):
An apparatus comprising:\n a first semiconductor die, wherein the first semiconductor die comprises:\n a first terminal supplied with a first signal; \n first circuitry coupled to the first terminal and configured to provide a second signal related to the first signal, the first circuitry comprising a first delay circuit; \n a second terminal supplied with a third signal; \n second circuitry coupled to the second terminal and configured to provide to a third terminal a fourth signal related to the third signal; \n a fourth terminal supplied with a fifth signal indicative of a difference in phase between a sixth signal related to the third signal and a seventh signal related to the fourth signal; and \n third circuitry configured to control the first delay circuit responsive, at least in part, to the fifth signal; and \n a second semiconductor die coupled to the first semiconductor die, wherein the second semiconductor comprises:\n a fifth terminal through which the second semiconductor die supplies the first signal to the first terminal of the first semiconductor die; \n a sixth terminal through which the second semiconductor die supplies the third signal to the second terminal of the first semiconductor die; \n a seventh terminal through which the second semiconductor die receives the fourth signal from the third terminal of the first semiconductor die; \n an eighth terminal through which the second semiconductor die supplies the fifth signal to the fourth terminal of the first semiconductor die; \n fourth circuitry configured to provide the sixth signal related to the third signal and the seventh signal related to the fourth signal, the fourth circuitry comprising a second delay circuit; and \n a phase detector configured to compare phases between the sixth signal and the seventh signal to provide the fifth signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15176442', '13566882', '15138042', '15449688', '13291733']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.746847550158153
- 35 USC 102 Novelty (BERT): 0.4630598576579087
- Combined Prediction Score: 0.7184687809081285
- Mean Citation Score: 140.914518
- Max Citation Score: 154.5303
- Similarity Product: 115.88131149047614

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test