PATENT CLAIM ANALYSIS

Application Number: 15957272
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["712", "222000"]

Abstract:
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

Claim (Index 3):
The computer program product of  claim 1 , wherein each of the first fraction value, the second fraction value and the third fraction value consists of any one of 56 bits or 112 bits, wherein each of the first exponent value, the second exponent value and the third exponent value consists of 14 bits.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 1.90323
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15175140', '14486228', '15635703', '10435982', '13083760']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6737340419333322
- 35 USC 102 Novelty (BERT): 0.6004172044608364
- Combined Prediction Score: 0.6664023581860827
- Mean Citation Score: 491.409824
- Max Citation Score: 506.1344
- Similarity Product: 501.23252866935735

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test