PATENT CLAIM ANALYSIS

Application Number: 15922908
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["330", "251000"]

Abstract:
A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.

Claim (Index 6):
The quaternary/ternary modulation selecting circuit of  claim 1 , wherein the ternary signal comprises a positive ternary wave and a negative ternary wave, and the detecting circuit comprises:\n a first counting circuit, arranged to generate a first counting signal according to the positive ternary wave and the negative ternary wave, wherein the first counting signal has a first logic value when a predetermined number of pulses in the positive ternary wave have been counted while no pulse in the negative ternary wave has been counted; a second counting circuit, arranged to generate a second counting signal according to the positive ternary wave and the negative ternary wave, wherein the second counting signal has a second logic value when a predetermined number of pulses in the negative ternary wave have been counted while no pulse in the positive ternary wave has been counted; a pulse loss determining circuit, coupled to the first counting circuit and the second counting circuit, wherein the pulse loss determining circuit is arranged to generate a determining signal according to at least the first counting signal and the second counting signal; an output circuit, coupled to the pulse loss determining circuit, wherein the output circuit is arranged to generate the mode selecting signal according to at least the determining signal; and a reset circuit, coupled to the pulse loss determining circuit, wherein the reset circuit is arranged to generate a reset signal to the pulse loss determining circuit according to the positive ternary wave and the negative ternary wave; wherein when the reset signal has a third logic value, the pulse loss determining circuit is reset, and the determining signal indicates the first counting signal does not have the first logic value and the second counting signal does not have the second logic value is outputted to the output circuit; wherein when the determining signal which indicates the first counting signal does not have the first logic value and the second counting signal does not have the second logic value is received, the mode selecting signal instructs the selecting circuit to select and output the ternary signal to the output stage of the amplifier.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 3.14706
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14656731', '14986737', '15220705', '14295587', '14594329']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7907279223099994
- 35 USC 102 Novelty (BERT): 0.5126269606477822
- Combined Prediction Score: 0.7629178261437777
- Mean Citation Score: 208.05603
- Max Citation Score: 288.2550700000001
- Similarity Product: 218.62026304721127

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test