PATENT CLAIM ANALYSIS

Application Number: 15883289
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "368000"]

Abstract:
A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Claim (Index 8):
A method of manufacturing a semiconductor device, comprising:\n forming a first gate electrode of a first transistor in a first region and a second gate electrode of a second transistor in a second region over a substrate; forming an offset spacer film over the substrate in the first and the second region to cover the first gate electrode and the second gate electrode; selectively etching the offset spacer film formed in the second region to expose an upper surface of the second gate electrode and an upper surface of the substrate around the second gate electrode in the second region, while leaving the offset spacer film formed in the first region and the offset spacer film formed on sides of the second gate electrode; forming a first insulating film on the offset spacer film formed in the first region, the second gate electrode, the offset spacer film formed on the sides of the second gate electrode and the substrate in the second region; forming a second insulating film to cover the first insulating film; forming first sidewalls on sides of the offset spacer film formed on the first gate electrode and second sidewalls on sides of the offset spacer film formed on the sides of the second gate electrode by etching back the first and the second insulating film; and implanting ions in the substrate by using the first gate electrode, the offset spacer film formed on the sides of the first gate electrode, the first sidewalls, the second gate electrode, the offset spacer film formed on the sides of the second gate electrode, and the second sidewalls as a mask, thereby to form a first diffusion layer for a source and a drain of the first transistor and a second diffusion layer for a source and a drain of the second transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.11765
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13858142', '15430413', '14739065', '12882038', '15412465']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9128371237532446
- 35 USC 102 Novelty (BERT): 0.5071418983971698
- Combined Prediction Score: 0.8722676012176371
- Mean Citation Score: 217.28186600000004
- Max Citation Score: 300.6483
- Similarity Product: 252.14697229589223

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test