PATENT CLAIM ANALYSIS

Application Number: 16057829
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "191000"]

Abstract:
A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.

Claim (Index 3):
The PMOS device of  claim 1 , wherein a percentage of the Ge content in the SiGe middle layer is between 30% to 50%.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 96.0
- Lexical Diversity: 3.12727
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15429194', '11201990', '10383709', '10389145', '15334112']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9173626402680892
- 35 USC 102 Novelty (BERT): 0.5003810476536971
- Combined Prediction Score: 0.8756644810066502
- Mean Citation Score: 190.307844
- Max Citation Score: 289.0121
- Similarity Product: 265.40798620004654

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test