PATENT CLAIM ANALYSIS

Application Number: 15961123
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "738000"]

Abstract:
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

Claim (Index 14):
The semiconductor chip package of  claim 9 , wherein each of the plural interconnects comprises a bumpless interconnect including a bond pad of the first semiconductor and a bond pad of the metallization stack bonded to and directly contacting the bond pad of the first semiconductor chip, the semiconductor chip device further comprising an insulating bonding layer physically connecting the first semiconductor chip to the metallization stack.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 91.0
- Lexical Diversity: 1.9375
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15961222', '15826054', '13436066', '15844575', '13456968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918888955836194
- 35 USC 102 Novelty (BERT): 0.4879504881363591
- Combined Prediction Score: 0.8757951090662105
- Mean Citation Score: 229.102828
- Max Citation Score: 241.5264
- Similarity Product: 193.4149087177277

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test