PATENT CLAIM ANALYSIS

Application Number: 15890921
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["711", "123000"]

Abstract:
Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Claim (Index 7):
The apparatus of  claim 6 , wherein a position in the ordering of a particular in-progress operation is before the first operation if the particular in-progress operation was initiated by the second module.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.14085
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14542136', '14541616', '15193535', '13705318', '14541807']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5383773126059425
- 35 USC 102 Novelty (BERT): 0.5582110047798207
- Combined Prediction Score: 0.5403606818233303
- Mean Citation Score: 288.447562
- Max Citation Score: 444.74594
- Similarity Product: 336.3090666090156

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test