PATENT CLAIM ANALYSIS

Application Number: 16011445
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "534000"]

Abstract:
MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.

Claim (Index 1):
A monolithic structure including one or more metal-insulator-semiconductor (MIS) capacitors, the monolithic structure comprising:\n a semiconductor substrate having a highly doped top surface region; a plurality of parallel, highly doped semiconductor fins extending vertically from the substrate, the semiconductor fins being separated from one another by spaces and electrically connected to the highly doped top surface region; a first doped layer within the substrate, the first doped layer being directly beneath at least base portions of the highly doped semiconductor fins and the highly doped top surface region of the substrate and having a first conductivity type, the semiconductor fins and the highly doped top surface region of the substrate having a second conductivity type opposite from the first conductivity type; a capacitor dielectric layer directly on the semiconductor fins and the highly doped top surface region of the substrate; a metal layer on the capacitor dielectric layer and extending into the spaces separating the semiconductor fins such that the metal layer, the capacitor dielectric layer, and the semiconductor fins and highly doped top surface region form a metal-insulator-semiconductor capacitor; a second dielectric layer on the metal layer and a portion of the highly doped top surface region; a first contact within the second dielectric layer that electrically communicates with the highly doped top surface region of the substrate, and a second contact within the second dielectric layer that electrically communicates with the metal layer; wherein the first doped layer is parallel to the highly doped top surface region of the substrate.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 1.86
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15334058', '15668230', '14930107', '15232482', '15214647']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9221958624248774
- 35 USC 102 Novelty (BERT): 0.5389419073738987
- Combined Prediction Score: 0.8838704669197796
- Mean Citation Score: 301.644646
- Max Citation Score: 381.11734
- Similarity Product: 303.3038673846638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test