PATENT CLAIM ANALYSIS

Application Number: 15887695
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["714", "718000"]

Abstract:
Disclosed are methods and apparatus for implementing a memory controller, such as a bus integrated memory controller (BIMC) that includes a memory built-in-self-test (MBIST) controller or logic. The MBIST controller is configured for testing at least one memory device, such as stacked low power double data rate (LPDDR) memories in a system on a chip or similar constructions that make external testing of the memory device difficult. The MBIST controller may be implemented within a standard memory controller and includes a memory translation logic configured to translate signals for testing the at least one memory device into signals in a format that is usable by the at least one memory device, where the translation logic serves to effectuate a memory representation.

Claim (Index 19):
The method of  claim 18 , wherein the MBIST logic is configured to provide approximately two times the data at an output of the MBIST logic to the at least one memory device for each MC clock cycle.

Metadata:
- Claim Count in Document: 80.0
- Percentile: 88.0
- Lexical Diversity: 1.92754
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['10779205', '12400664', '11773554', '14671558', '14656966']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3212518526596811
- 35 USC 102 Novelty (BERT): 0.4807559443981197
- Combined Prediction Score: 0.337202261833525
- Mean Citation Score: 200.754056
- Max Citation Score: 207.7462
- Similarity Product: 154.9447598518729

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test