PATENT CLAIM ANALYSIS

Application Number: 15981355
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "072000"]

Abstract:
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Claim (Index 13):
A semiconductor device according to  claim 1 ,\n wherein the first wiring is arranged next to the second wiring.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 93.0
- Lexical Diversity: 2.06667
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14981195', '15716639', '15367829', '14321169', '14026575']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.857004083322746
- 35 USC 102 Novelty (BERT): 0.5826513039381466
- Combined Prediction Score: 0.8295688053842861
- Mean Citation Score: 487.03654000000006
- Max Citation Score: 501.04446
- Similarity Product: 435.5044655387271

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test