PATENT CLAIM ANALYSIS

Application Number: 15971159
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "316000"]

Abstract:
A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

Claim (Index 1):
A method of fabricating a split-gate memory cell on an integrated circuit, comprising:\n forming common source/drain in a semiconductor substrate; forming a first dielectric layer on a surface of a semiconductor substrate; forming a first gate stack on the first dielectric layer, the first gate stack including a first control gate over a first floating gate; forming a second gate stack on the first dielectric layer, the second gate stack including a second control gate over a second floating gate, wherein at least a portion of the common source/drain is between the first and second gate stacks; forming a first gate electrode layer over the first gate stack, over the second gate stack, and over a logic region of the integrated circuit; forming a patterned capping dielectric layer over a portion of the first gate electrode layer that is over the logic region of the integrated circuit; forming a first spacer-shaped select gate along a sidewall of the first gate stack and a second space-shaped select gate along a sidewall of the second gate stack by performing etching that etches the first gate electrode layer to form the first and second space-shaped select gates; removing the patterned capping dielectric layer; forming a first bitline source/drain in the semiconductor substrate, the first bitline source/drain being adjacent to the first select gate; and forming a second source/drain in the semiconductor surface, the second bitline source/drain being adjacent to the second select gate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.61702
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15375952', '14669886', '15098425', '15681442', '15947488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9106999077725788
- 35 USC 102 Novelty (BERT): 0.5418063265251177
- Combined Prediction Score: 0.8738105496478328
- Mean Citation Score: 301.434898
- Max Citation Score: 377.11496
- Similarity Product: 322.44428963867665

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test