PATENT CLAIM ANALYSIS

Application Number: 16197692
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "203000"]

Abstract:
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

Claim (Index 11):
The circuit of  claim 9 , wherein a drain terminal of the at least one p-type vertical FET is coupled to the output line.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 98.0
- Lexical Diversity: 3.28
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15848151', '15497608', '15617472', '15937006', '15137036']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9430456536201842
- 35 USC 102 Novelty (BERT): 0.5566100618406296
- Combined Prediction Score: 0.9044020944422289
- Mean Citation Score: 391.35102400000005
- Max Citation Score: 454.25565
- Similarity Product: 323.369459986487

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test