PATENT CLAIM ANALYSIS

Application Number: 15937006
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "329000"]

Abstract:
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

Claim (Index 5):
The vertical transistor of  claim 1 , further comprising:\n a spacer layer in contact with the first doped layer and a portion of the fin structure.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 90.0
- Lexical Diversity: 3.28
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15617472', '15137036', '15497608', '15848151', '15838456']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.923650229731284
- 35 USC 102 Novelty (BERT): 0.5671463830504713
- Combined Prediction Score: 0.8879998450632027
- Mean Citation Score: 368.205912
- Max Citation Score: 439.52457
- Similarity Product: 433.5317137948733

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test