PATENT CLAIM ANALYSIS

Application Number: 16023089
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["711", "125000"]

Abstract:
The present disclosure is directed to systems and methods for preventing or mitigating the effects of a cache-timing based side channel attack, such as a Meltdown type attack. In response to a speculatively executed data access by an unretired or incomplete instruction, rather than transferring data to the CPU cache, the data is instead transferred to data transfer buffer circuitry where the data is held in the form of a record until the instruction requesting the data is successfully completed or retired. Upon retirement of the instruction requesting the data access, the data included in the record may be transferred to the CPU cache. Each record held in the data transfer buffer circuitry may include: a data source identifier; a physical/virtual address of the data; a cache line that includes the data; and an instruction identifier associated with the instruction initiating the data access.

Claim (Index 5):
The system of  claim 1  wherein the cache circuitry comprises multi-level cache circuitry that includes:\n Level 1 (L1) cache circuitry; \n Level 2 (L2) cache circuitry; and \n Last Level Cache (LLC) circuitry.

Metadata:
- Claim Count in Document: 57.0
- Percentile: 94.0
- Lexical Diversity: 2.0
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16023717', '15640060', '09340074', '14137432', '14216493']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4413990725714111
- 35 USC 102 Novelty (BERT): 0.5466533062550759
- Combined Prediction Score: 0.4519244959397775
- Mean Citation Score: 229.206432
- Max Citation Score: 387.83182
- Similarity Product: 308.52143040638924

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test