PATENT CLAIM ANALYSIS

Application Number: 16057316
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "148000"]

Abstract:
Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode.

Claim (Index 2):
The memory cell according to  claim 1 , wherein the data storage material layer comprises one of a phase change material layer and a variable resistance material layer.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 96.0
- Lexical Diversity: 3.52174
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15380899', '13116002', '13595426', '10926470', '14968152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7924172990301608
- 35 USC 102 Novelty (BERT): 0.4959958447385684
- Combined Prediction Score: 0.7627751536010016
- Mean Citation Score: 231.42655
- Max Citation Score: 247.62608
- Similarity Product: 187.38822863372803

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test