PATENT CLAIM ANALYSIS

Application Number: 15967457
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-09
Patent Classification: ["438", "257000"]

Abstract:
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Claim (Index 44):
The NAND cell unit of  claim 41  wherein the string gate further comprises the electrically insulative material.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 91.0
- Lexical Diversity: 2.85455
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12128404', '12986487', '14225053', '15207275', '13605848']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8960612238941299
- 35 USC 102 Novelty (BERT): 0.5339596054234365
- Combined Prediction Score: 0.8598510620470605
- Mean Citation Score: 342.10536600000006
- Max Citation Score: 367.98383
- Similarity Product: 217.893455688982

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test