PATENT CLAIM ANALYSIS

Application Number: 15947667
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "596000"]

Abstract:
Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Claim (Index 20):
A semiconductor differential variable capacitor comprising:\n a first gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a second gate oxide layer comprising a third layer portion with a third thickness and a fourth layer portion with a fourth thickness; a first non-insulative region disposed above the first gate oxide layer and connected to a first signal terminal, wherein the gate oxide layer is either p+ doped or n+ doped; a second non-insulative region disposed above the second gate oxide layer and connected to a second signal terminal, wherein the gate oxide layer is either p+ doped or n+ doped; a first semiconductor region disposed beneath the first gate oxide layer, wherein the first semiconductor region is p doped; a second semiconductor region disposed beneath the second gate oxide layer, wherein the second semiconductor region is p doped; a third semiconductor region disposed beneath the first gate oxide layer and the second gate oxide layer and between the first semiconductor region and the second semiconductor region, wherein the third semiconductor region is n doped; a fourth semiconductor region disposed beneath the first, second, and third semiconductor regions and within a substrate, wherein the third semiconductor region is n doped; a third non-insulative region disposed within the first semiconductor region and connected to a third signal terminal, wherein the third non-insulative region is p+ doped; a fourth non-insulative region disposed within the second semiconductor region and connected to a fourth signal terminal, wherein the fourth non-insulative region is p+ doped; a fifth non-insulative region disposed within the substrate and connected to a ground terminal; and a control region disposed within the third semiconductor region and connected to a control terminal, wherein a first capacitance between the first non-insulative region and the third non-insulative region, as well as a second capacitance between the second non-insulative region and the fourth non-insulative region, is configured to be adjusted by varying a control voltage applied to the control region via the control terminal.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 2.76786
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15659718', '15583289', '15871638', '15706352', '15850118']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926020029372961
- 35 USC 102 Novelty (BERT): 0.5236405372544903
- Combined Prediction Score: 0.885782080161114
- Mean Citation Score: 302.225524
- Max Citation Score: 349.48895
- Similarity Product: 304.2499929072857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test