PATENT CLAIM ANALYSIS

Application Number: 15965733
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "205000"]

Abstract:
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Claim (Index 31):
A method, comprising:\n determining data values stored in a number of memory cells of a first row of an array of memory cells, each of the number of memory cells coupled to a respective sense line of a number of sense lines; and performing, in parallel, logical operations using the data values stored in the number of memory cells of the first row as a number of first inputs and data values stored in a number of memory cells of a second row of the array as a number of second inputs, wherein each of the number of memory cells of the second row are coupled to a respective sense line of the number of sense lines; wherein the logical operations are performed in parallel without transferring data from the sense lines onto input/output lines configured to transfer data out of sensing circuitry coupled to the array; wherein each of the number of sense lines is coupled to a respective sense amplifier of a number of sense amplifiers, and each of the number of sense amplifiers is coupled to one of a respective number of compute components; wherein each compute component comprises:\n a cross coupled latch; \n a pair of pass; and \n a pair of inverting transistors; and \n wherein performing the logical operations comprises:\n transferring the data values stored in the number of memory cells of the first row to the number of cross coupled latches during a first operation phase in which the pass transistors are enabled; \n determining the data values stored in the number of memory cells of the second row while the pass transistors are disabled; and \n subsequently enabling only one respective pass transistor of each of the pair of pass transistors such that each cross coupled latch of the number of cross coupled latches stores a respective data value corresponding to a logical operation result of a data value stored in a respective memory cell of the number of memory cells of the first row and a data value stored in a respective memory cell of the number of memory cells of the second row.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.125
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13784219', '14878452', '15270761', '13962399', '14725956']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8024385138215806
- 35 USC 102 Novelty (BERT): 0.4641454698075784
- Combined Prediction Score: 0.7686092094201804
- Mean Citation Score: 269.222382
- Max Citation Score: 275.8427
- Similarity Product: 256.5583587906956

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test