PATENT CLAIM ANALYSIS

Application Number: 15860266
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["320", "107000"]

Abstract:
The present disclosure provides a power adapter, an electronic device and a charging apparatus. In the process of charging a battery in a conventional charge mode after the power adapter is powered on, the power adapter carries out quick charge inquiry communication with the electronic device when an output current value of the power adapter is within a conventional current range for a preset time interval; after the electronic device sends a quick charge command to the power adapter, the power adapter adjusts the output voltage according to the battery voltage information fed back by the electronic device; and when the output voltage meets a voltage requirement for quick charge preset by the electronic device, the power adapter adjusts the output current and the output voltage for charging the battery in a quick charge mode.

Claim (Index 4):
The power adapter of  claim 1 , wherein,\n the potential regulation circuit comprises: a fifteenth resistor, a sixteenth resistor, a digital potentiometer, a seventeenth resistor, an eighteenth resistor, a fifth capacitor, a sixth capacitor and a nineteenth resistor; a junction of a first terminal of the fifteenth resistor, a first terminal of the sixteenth resistor, a power pin of the digital potentiometer and a first terminal of the fifth capacitor is configured as the power terminal of the potential regulation circuit; a second terminal of the fifth capacitor, a first terminal of the sixth capacitor, a ground pin of the digital potentiometer and a first terminal of the seventeenth resistor are jointly grounded; a second terminal of the sixth capacitor is coupled to the power pin of the digital potentiometer; a junction of a second terminal of the fifteenth resistor and a serial data pin of the digital potentiometer is configured as the data input terminal of the potential regulation circuit; a junction of a second terminal of the sixteenth resistor and a clock input pin of the digital potentiometer is configured as the clock input terminal of the potential regulation circuit; an address zero pin of the digital potentiometer is grounded; a first potential wiring pin of the digital potentiometer and a first terminal of the eighteenth resistor are jointly coupled to a second terminal of the seventeenth resistor; a second terminal of the eighteenth resistor and a second potential wiring pin of the digital potentiometer are jointly coupled to a first terminal of the nineteenth resistor; a second terminal of the nineteenth resistor is configured as the high-potential terminal of the potential regulation circuit; and a potential tap pin of the digital potentiometer is configured as the potential regulation terminal of the potential regulation circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.50877
- Patent Class: 320.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15113973', '15596009', '15596884', '15115203', '15115251']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7701778706120027
- 35 USC 102 Novelty (BERT): 0.5345830996685085
- Combined Prediction Score: 0.7466183935176534
- Mean Citation Score: 351.751086
- Max Citation Score: 371.28656
- Similarity Product: 362.77520680671694

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test