PATENT CLAIM ANALYSIS

Application Number: 16127068
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["716", "104000"]

Abstract:
Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Claim (Index 6):
The chip of  claim 5 , wherein the insertion of the repeater is based on at least one of a distance between the components corresponding to the two or more interfaces, wire length, capacitance, and resistance.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 1.45455
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15344441', '15344416', '15876047', '15876059', '15344420']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3447273008102647
- 35 USC 102 Novelty (BERT): 0.4774466401839848
- Combined Prediction Score: 0.3579992347476367
- Mean Citation Score: 212.818108
- Max Citation Score: 255.43489
- Similarity Product: 210.82747650657475

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test