PATENT CLAIM ANALYSIS

Application Number: 15941964
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["326", "030000"]

Abstract:
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.

Claim (Index 19):
The method of  claim 15 , further comprising generating a first intermediate signal in response to multiplying a magnitude of the digital signal by a first factor and generating a second intermediate signal in response to multiplying the magnitude of the digital signal with the delay by a second factor.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.35
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15464012', '15600378', '14847264', '15688532', '13030278']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6639746566424861
- 35 USC 102 Novelty (BERT): 0.5198060914549485
- Combined Prediction Score: 0.6495578001237323
- Mean Citation Score: 218.730686
- Max Citation Score: 342.45947
- Similarity Product: 235.73886255651595

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test