PATENT CLAIM ANALYSIS

Application Number: 16217122
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["345", "213000"]

Abstract:
A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Claim (Index 1):
A display device comprising:\n a plurality of pixels a plurality of scanning signal lines supplying a scanning signal to the plurality of pixels respectively, a driving circuit sequentially applying the scanning signal from one ends of the plurality of scanning signal lines, a first clock signal line supplying a first clock signal to the driving circuit, and a second clock signal line supplying a second clock signal to the driving circuit, wherein the driving circuit has multiple stages of circuit blocks which output the scanning signal to the plurality of scanning signal lines, wherein at least one stage of the circuit block in the multiple stages of circuit blocks includes, a first transistor that has a gate being connected to a first node having an active potential during an output period including a period in which the scanning signal is applied to the corresponding scanning signal line, and controls electrical conduction between the first clock signal line and the scanning signal line, a second transistor that has a gate being applied the second clock, and controls electrical conduction between the first node and an inactive potential, a third transistor that has a gate being applied the second clock, and controls electrical conduction between the scanning signal line and the inactive potential, a fourth transistor that has a gate being applied an output of the next stage of circuit blocks and controls electrical conduction between the first node and the inactive potential, a fifth transistor that has a gate being connected to a first node and controls electrical conduction between the second node and the second clock, wherein the second clock signal has an active potential at the time of termination of the output period and an inactive potential during the output period.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 3.02128
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14883338', '15358209', '14161723', '15097414', '16172003']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.643459217329811
- 35 USC 102 Novelty (BERT): 0.5310088181504659
- Combined Prediction Score: 0.6322141774118766
- Mean Citation Score: 310.1011220000001
- Max Citation Score: 354.85666000000015
- Similarity Product: 330.6030049733198

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test