PATENT CLAIM ANALYSIS

Application Number: 16207009
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["365", "189020"]

Abstract:
A semiconductor device includes: first and second terminal switches connected correspondingly between the first and second terminals of a sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows: during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered from corresponding selected ones of bit lines; and during a reuse phase in which the first and second gleaned charges are reused from correspondingly onto selected corresponding ones of the array of bit lines.

Claim (Index 1):
A semiconductor device comprising:\n a sense amplifier including first and second terminals; first and second terminal switches connected correspondingly between the first and second terminals of the sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes and a first reference voltage; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows:\n during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered correspondingly into the first and second capacitors from corresponding selected ones of bit lines arranged in an array, the bit lines being connected correspondingly to the first and second nodes and to corresponding memory cells; and \n during a reuse phase in which the first and second gleaned charges are reused from the first and second capacitors correspondingly through the first and second nodes onto selected corresponding ones of the array of bit lines.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.62069
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15877034', '15460687', '11797725', '14705604', '12115687']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.775297697711022
- 35 USC 102 Novelty (BERT): 0.4683678761631204
- Combined Prediction Score: 0.7446047155562319
- Mean Citation Score: 124.8141692
- Max Citation Score: 194.27379
- Similarity Product: 154.6615302985454

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test