PATENT CLAIM ANALYSIS

Application Number: 16444105
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["327", "541000"]

Abstract:
A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate ( 20 a ) are provided gate lines ( 13 G) and source lines. On the active-matrix substrate ( 20 a ) are further provided: gate drivers ( 11 ) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line ( 13 G); and lines ( 15 L 1 ) each for supplying a control signal to the associated gate driver ( 11 ). A control signal is supplied by a display control circuit ( 4 ) located outside the display region to the gate drivers ( 11 ) via the lines ( 15 L 1 ). In response to a control signal supplied, each gate driver ( 11 ) drives the gate line ( 13 G) to which it is connected.

Claim (Index 1):
An active-matrix substrate comprising:\n a plurality of data lines; a plurality of lines crossing the plurality of data lines and including at least gate lines; and a driving circuit connected with at least one of the plurality of lines for controlling a potential of this line in response to a control signal supplied from outside a display region that includes pixel regions defined by the data lines and the gate lines, wherein the driving circuit includes a plurality of switching elements, at least one of the plurality of switching elements is located in one of the pixel regions, the driving circuit is connected with one of the gate lines and controls the potential of this gate line by applying one of a selection voltage and a non-selection voltage to the gate line in response to the control signal, and the driving circuit is provided in each of K regions (K is a natural number, K\u22652) arranged in a direction in which the gate lines of the display region extend, each driving circuit being provided for every K gate lines, the driving circuits being provided on different gate lines in different regions.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 100.0
- Lexical Diversity: 2.48148
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15253152', '15710961', '14438941', '14775933', '15307040']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8079679839519114
- 35 USC 102 Novelty (BERT): 0.542606811663449
- Combined Prediction Score: 0.7814318667230651
- Mean Citation Score: 354.563968
- Max Citation Score: 405.3479
- Similarity Product: 381.07476641393305

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test