PATENT CLAIM ANALYSIS

Application Number: 15975206
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "148000"]

Abstract:
A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.

Claim (Index 1):
A method for managing the endurance of a non-volatile rewritable memory including a plurality of ordered stacks of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material of each stack being capable of switching between:\n a high resistance state, in which said dielectric material has a first resistance value, and a low resistance state, in which said dielectric material has a second resistance value, a switching between the high resistance state and the low resistance state allowing a writing in the memory and a switching between the low resistance state and the high resistance state allowing an erasure in said memory, the method comprising at least one of the following operations:\n at the end of each erasure operation: reading the first resistance value of the dielectric material, comparing said first resistance value with a first predetermined median resistance value, and determining the writing programming conditions from the results of said comparison; and \n at the end of each writing operation: reading the second resistance value of the material, comparing said second resistance value with a second predetermined median resistance value, and determining the erasure programming conditions from the results of said comparison, \n the first and second median resistance values following, respectively, a first and a second predetermined dependency laws, linking the programming conditions and the first and second read resistance values, said writing and erasure programming conditions being applied to the electrodes of the stack during, respectively, following writing and erasure operations in order to limit the generation of defects in the dielectric material.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 2.56452
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15975249', '14175320', '14175292', '14175271', '14489789']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7440738283536171
- 35 USC 102 Novelty (BERT): 0.520457852331981
- Combined Prediction Score: 0.7217122307514535
- Mean Citation Score: 206.527928
- Max Citation Score: 342.77878
- Similarity Product: 325.77846265609264

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test