PATENT CLAIM ANALYSIS

Application Number: 15898420
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["257", "369000"]

Abstract:
A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Claim (Index 15):
A method for providing a plurality of transistors on a semiconductor device, the method comprising:\n providing a source and a drain for each of the plurality of transistors, a channel for each of the plurality of transistors, being between the source and the drain; providing a gate structure on the channel for each of the plurality of transistors, the step of providing the gate structure comprising\n providing an interfacial oxide layer on at least the channel; \n providing a silicate layer on the interfacial oxide layer, a first portion of the plurality of transistors having a first thickness of the silicate layer, a second portion of the plurality of transistors having a second thickness of the silicate layer, the second thickness being different from the first thickness, the step of providing the silicate layer including\n depositing a first silicate layer on the first portion and the second portion of the plurality of structures; \n removing at least a portion of the first silicate layer from the first portion of the plurality of structures; and \n providing a second silicate layer on the first portion and the second portion of the plurality of structures, each of the first silicate layer and the second silicate layer including at least one of LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx, MgSiOx, LuSiOx, YSiOx, LaSiOx, BaSiOx, SrSiOx, AlSiOx, TiSiOx, HfSiOx, ZrSiOx, TaSiOx, ScSiOx and MgSiOx; \n \n providing a high dielectric constant layer on the silicate layer; \n providing a work function metal layer on the high dielectric constant layer, the work function metal layer including at least one of TiN, TaN, TiSiN, TiTaN, WN and TiTaSiN and having a work function metal thickness of not more than three nanometers; \n providing a reactive metal layer on at least a portion of the work function metal layer, the reactive metal layer including at least one of Si, Ti, Zr, Hf and La; \n performing a low temperature anneal after the step of providing the reactive metal layer, the low temperature anneal having an anneal temperature of at least two hundred degrees Celsius and not more than six hundred degrees Celsius; \n removing the reactive metal layer after the step of performing the low temperature anneal; \n providing a contact metal layer on the work function metal layer after the step of removing the reactive metal layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.34146
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11955491', '15455203', '14198976', '14047849', '15284567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9075264278216912
- 35 USC 102 Novelty (BERT): 0.475177823948023
- Combined Prediction Score: 0.8642915674343244
- Mean Citation Score: 161.625392
- Max Citation Score: 192.00551
- Similarity Product: 149.19748450651824

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test