PATENT CLAIM ANALYSIS

Application Number: 16048078
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-05
Patent Classification: ["711", "103000"]

Abstract:
Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Claim (Index 4):
The method of  claim 2 , wherein the one or more memory operation features comprises three features, and wherein the plurality of sets of latency values comprises three sets of latency values.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.19481
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15798083', '12570570', '15655177', '10831823', '11216953']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.476433642639576
- 35 USC 102 Novelty (BERT): 0.5145305764046971
- Combined Prediction Score: 0.4802433360160881
- Mean Citation Score: 176.58990799999995
- Max Citation Score: 298.27386
- Similarity Product: 246.53730099168064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test