PATENT CLAIM ANALYSIS

Application Number: 16114217
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["438", "396000"]

Abstract:
The present invention relates to a method of forming a memory capacitor. A substrate is provided with a plurality of storage node contacts. A patterned supporting structure is formed on the substrate, following by forming a bottom electrode conformally on surface of plural openings in the patterned supporting structure, thereby contacting the storage node contacts. A sacrificial layer is formed in the opening. A soft etching process is performed to remove the bottom electrode on top and partial sidewall of the patterned supporting structure, wherein the soft etching process includes using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound. The sacrificial layer is completely removed away. A capacitor dielectric layer and a top electrode are formed on the bottom electrode layer.

Claim (Index 6):
A method of forming a memory capacitor, comprising:\n providing a substrate, which comprises a plurality of storage node contacts; forming a patterned supporting structure on the substrate, wherein the patterned supporting structure comprises a plurality of openings, each of which corresponding to each of the storage node contacts; forming a bottom electrode layer on the patterned supporting layer, wherein the bottom electrode is conformally formed on the patterned supporting layer and sidewalls and bottom surfaces of the openings, and contacting the storage node contacts; forming a sacrificial layer on the bottom electrode layer, wherein the sacrificial layer is filled into the openings; performing a soft etching process for removing the bottom electrode on the patterned supporting layer and partials of sidewalls of the openings, thereby making atop surface of the bottom electrode layer lower than a top surface of the sacrificial layer and forming a plurality of recesses between the patterned support layer, the sacrificial layer and the bottom electrode; completely removing the sacrificial layer; removing partials of the patterned supporting layer; forming a capacitor dielectric layer on the bottom electrode layer; and forming a top electrode on the capacitor dielectric layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 96.0
- Lexical Diversity: 2.10606
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11173189', '11159130', '10904479', '12949870', '12640846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.825759054255231
- 35 USC 102 Novelty (BERT): 0.5050964542708299
- Combined Prediction Score: 0.793692794256791
- Mean Citation Score: 189.509082
- Max Citation Score: 197.33784
- Similarity Product: 122.42692793169022

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test