PATENT CLAIM ANALYSIS

Application Number: 15940800
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["365", "154000"]

Abstract:
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

Claim (Index 11):
A storage system, comprising:\n a memory cell having a voltage supply node and a bit line; a write assist circuit configured to use charge stored in a capacitor to both provide a lower supply voltage level at the voltage supply node and drive the bit line to a voltage level below ground; and a write driver configured to receive the voltage level below ground from the write assist circuit, wherein the capacitor of the write assist circuit is coupled between the ground and the write driver when the bit line is driven to the voltage level below ground.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 90.0
- Lexical Diversity: 1.92857
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15135133', '14077559', '12959883', '14594673', '15476746']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7840625854189048
- 35 USC 102 Novelty (BERT): 0.4814763330646893
- Combined Prediction Score: 0.7538039601834834
- Mean Citation Score: 192.171696
- Max Citation Score: 254.62741
- Similarity Product: 216.17974282736003

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test