PATENT CLAIM ANALYSIS

Application Number: 15870092
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "203000"]

Abstract:
A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.

Claim (Index 19):
The semiconductor device as set forth in  claim 18 , wherein:\n the p-channel semiconductor device and the n-channel semiconductor device have a stacked structure.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 2.90909
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15869917', '15185388', '12692133', '10188103', '14457185']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9148821073465968
- 35 USC 102 Novelty (BERT): 0.5304633157302417
- Combined Prediction Score: 0.8764402281849614
- Mean Citation Score: 254.12617400000005
- Max Citation Score: 289.8983
- Similarity Product: 157.06196347850562

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test