PATENT CLAIM ANALYSIS

Application Number: 15868274
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "347000"]

Abstract:
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Claim (Index 20):
The method of  claim 10 , wherein forming one of the source contact and the drain contact on the sloped sidewalls of the semiconductor fin further includes:\n forming the source contact on the sloped sidewalls of the semiconductor fin, the source contact formed outside of the first spacer and the second spacer; and forming the drain contact on the sloped sidewalls of the semiconductor fin, opposite the source contact, the drain contact formed outside of the first spacer and the second spacer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.11628
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14616018', '15868224', '15851149', '15387933', '15804303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9266052201098528
- 35 USC 102 Novelty (BERT): 0.5348400141516582
- Combined Prediction Score: 0.8874286995140332
- Mean Citation Score: 311.746478
- Max Citation Score: 365.04767
- Similarity Product: 290.0039782730311

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test