PATENT CLAIM ANALYSIS

Application Number: 15948761
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "185020"]

Abstract:
Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Claim (Index 18):
The apparatus of  claim 17 , wherein:\n the different voltages applied to the adjacent memory cell exceed the different verify voltages applied to the selected memory cell by a fixed amount.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 2.08108
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14500660', '14481304', '15814772', '15062661', '15678683']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8009691887576884
- 35 USC 102 Novelty (BERT): 0.5099706971951754
- Combined Prediction Score: 0.7718693396014371
- Mean Citation Score: 272.266206
- Max Citation Score: 301.26584
- Similarity Product: 241.8921479094029

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test