PATENT CLAIM ANALYSIS

Application Number: 16152237
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-08
Patent Classification: ["257", "668000"]

Abstract:
A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.

Claim (Index 17):
A fan-out semiconductor package, comprising:\n a first connection member comprising a first insulating layer, a first redistribution layer disposed on the first insulating layer, a second insulating layer disposed on the first redistribution layer, and a first via connected to the first redistribution layer and penetrating through the first insulating layer; a first semiconductor chip having a first active surface with first connection pads disposed thereon and a first non-active surface opposing the first active surface, the first semiconductor chip being disposed on the first insulating layer of the first connection member such that the first active surface faces the first insulating layer and the first connection pads are electrically connected to the first via; a second semiconductor chip having a second active surface with second connection pads disposed thereon and a second inactive surface opposing the second active surface, the second semiconductor chip being disposed on the second insulating layer of the first connection member such that the second inactive surface faces the second insulating layer; a second connection member comprising a second redistribution layer and a second via, the second connection member being disposed on the second active surface of the second semiconductor chip such that the second via electrically connects the second connection pads to the second redistribution layer; a first core member having a first through-hole disposed on the first insulating layer of the first connection member such that the first semiconductor chip is disposed in the first through-hole; a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip; and a second substrate surrounding the second semiconductor chip and having a first connection via penetrating through the second substrate and electrically connecting the first redistribution layer and the second redistribution layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 4.12821
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15946109', '15986212', '15882440', '16037724', '16010754']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922624190371706
- 35 USC 102 Novelty (BERT): 0.5255902204342058
- Combined Prediction Score: 0.882920793377956
- Mean Citation Score: 349.93819799999994
- Max Citation Score: 356.56927
- Similarity Product: 322.60370544162515

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test