PATENT CLAIM ANALYSIS

Application Number: 16201657
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["327", "436000"]

Abstract:
Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

Claim (Index 10):
The apparatus of  claim 1 , wherein the first through fourth transistors are PMOS, NMOS, PMOS, and NMOS transistors, respectively.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.75
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15217449', '15857144', '12628945', '14290591', '11537781']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7763400476800995
- 35 USC 102 Novelty (BERT): 0.4978548828580155
- Combined Prediction Score: 0.748491531197891
- Mean Citation Score: 183.97765
- Max Citation Score: 228.73236
- Similarity Product: 150.94997549087762

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test