PATENT CLAIM ANALYSIS

Application Number: 16117017
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["710", "106000"]

Abstract:
A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Claim (Index 1):
A method of purging an address translation cache included in a computing system, the method comprising:\n issuing, via an operating system running on the computing system, a command indicating a request to perform an input/output (I/O) transaction requiring one or more address translation entries; determining, via a host bridge, a total data length to be transferred during the I/O transaction corresponding to the one or more address translation entries, and an expected count value corresponding to the total data length to be transferred during the I/O transaction; selecting an address translation entry from an address translation table, adding the expected count data value to the address translation entry, and loading the address translation entry into the address translation cache; fetching the address translation entry and retrieving the expected count data value from the address translation entry; transferring data corresponding to the I/O transaction using the selected address translation entry; monitoring, via the host bridge, the amount of data transferred using the selected address translation entry, determining an actual count corresponding to the amount of data transferred, and comparing the actual count to the expected count value; and automatically purging the selected address translation entry without receiving a purge command from firmware in response to the actual count reaching the expected count value.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.44444
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15193905', '16103253', '15196503', '15149219', '15281690']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7171621092858459
- 35 USC 102 Novelty (BERT): 0.5335609686004147
- Combined Prediction Score: 0.6988019952173028
- Mean Citation Score: 322.653228
- Max Citation Score: 386.51486
- Similarity Product: 335.3391728484058

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test