PATENT CLAIM ANALYSIS

Application Number: 15897204
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "369000"]

Abstract:
Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.

Claim (Index 10):
A method of forming a semiconductor structure, comprising:\n forming a plurality of semiconductor fins over a semiconductor substrate; forming a gate dielectric layer over each of the fins; forming a first work function metal layer over the gate dielectric layer; forming a masking layer over the first work function metal layer; etching the masking layer to form a plurality of recesses extending partially through the masking layer, a first recess of the plurality of recesses overlying the first work function metal layer between adjacent fins within first device region of the substrate, and a second recess of the plurality of recesses overlying the first work function metal layer between adjacent fins within a second device region of the substrate; forming a first spacer layer over sidewalls of the plurality of recesses; etching the masking layer using the first spacer layer as a first etch mask to form a first gate cut opening within the first device region and a second gate cut opening within the second device region, wherein the first gate cut opening extends partially through the masking layer and the second gate cut opening extending entirely through the masking layer exposing the first work function metal layer at a first bottom of the second gate cut opening; forming a second spacer layer over sidewalls of the first and second gate cut openings; etching the masking layer using the second spacer layer as second etch mask to expose the first work function metal layer at a first bottom of the first gate cut opening; etching the first work function metal layer from the first bottom of the first and second gate cut openings and etching the gate dielectric layer thereunder, thereby forming a second bottom of the first gate cut opening and a second bottom of the second gate cut opening; and depositing an isolation dielectric layer within the first and second gate cut openings.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 1.64815
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15467536', '15830217', '15486387', '15860840', '15705888']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9283971888468192
- 35 USC 102 Novelty (BERT): 0.5146998632144107
- Combined Prediction Score: 0.8870274562835783
- Mean Citation Score: 309.4815040000001
- Max Citation Score: 321.95813
- Similarity Product: 260.4719041136795

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test