PATENT CLAIM ANALYSIS

Application Number: 15901992
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-04
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.

Claim (Index 4):
The semiconductor device structure as claimed in  claim 2 , wherein the work function metal layer has a material removal rate that is substantially the same as the material removal rate of the conductive sealing layer in the chemical mechanical polishing process.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.68519
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15335595', '15786427', '15428798', '15706764', '15660355']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.906771552500254
- 35 USC 102 Novelty (BERT): 0.4842894552005397
- Combined Prediction Score: 0.8645233427702825
- Mean Citation Score: 184.276074
- Max Citation Score: 187.951
- Similarity Product: 143.9372783383727

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test