PATENT CLAIM ANALYSIS

Application Number: 16225912
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["455", "090200"]

Abstract:
A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.

Claim (Index 13):
The amplifier linearization circuit assembly of  claim 11  wherein the envelope adjustor is further configured to adjust the magnitude of the second signal based at least in part on the tuned slope of the shaping function and a power level of the first signal.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 98.0
- Lexical Diversity: 2.64
- Patent Class: 455.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15817591', '15191960', '16221966', '15679518', '15191938']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7720435272660823
- 35 USC 102 Novelty (BERT): 0.5998020437326514
- Combined Prediction Score: 0.7548193789127392
- Mean Citation Score: 487.920246
- Max Citation Score: 539.6082
- Similarity Product: 449.23668146982186

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test