PATENT CLAIM ANALYSIS

Application Number: 16050428
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A package structure includes a metal carrier, a conductive adhesive layer disposed on the metal carrier, a conductive post disposed on the conductive adhesive layer, a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, and a redistribution layer disposed on the conductive post and the semiconductor chip. The semiconductor chip includes a first terminal at an upper surface of the semiconductor chip. The first terminal of the semiconductor chip is electrically connected to the bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer.

Claim (Index 11):
A package structure, comprising:\n first and second conductive adhesive layers, the second conductive adhesive layer being laterally spaced from the first conductive adhesive layer; first and second conductive posts disposed on the first and second conductive adhesive layers respectively; a first semiconductor chip disposed on the first conductive adhesive layer, wherein the first semiconductor chip comprises source, drain and gate terminals at an upper surface of the first semiconductor chip; a second semiconductor chip disposed on the second conductive adhesive layer, wherein the second semiconductor chip comprises source, drain and gate terminals at an upper surface of the second semiconductor chip; and a first redistribution layer disposed on the first and second conductive posts and the first and second semiconductor chips, wherein the source terminal of the first semiconductor chip is electrically connected to a bottom surface of the first semiconductor chip through the first redistribution layer, the first conductive post and the first conductive adhesive layer, wherein the source terminal of the first semiconductor chip is electrically connected to the drain terminal of the second semiconductor chip through the first redistribution layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 95.0
- Lexical Diversity: 2.89189
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14157379', '12899258', '14814524', '14747507', '12759699']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5890230155449697
- 35 USC 102 Novelty (BERT): 0.4799231701641234
- Combined Prediction Score: 0.5781130310068852
- Mean Citation Score: 228.263842
- Max Citation Score: 236.12268
- Similarity Product: 182.4117037195301

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test