PATENT CLAIM ANALYSIS

Application Number: 15873567
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "774000"]

Abstract:
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Claim (Index 18):
The method of  claim 17 , wherein at least partially filling the first plurality of via holes with conductive material includes at least partially filling the first plurality of via holes with copper.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 86.0
- Lexical Diversity: 2.35714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13707159', '14922425', '14663689', '15255351', '14818902']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9178258547617818
- 35 USC 102 Novelty (BERT): 0.5364656282052916
- Combined Prediction Score: 0.8796898321061328
- Mean Citation Score: 291.715658
- Max Citation Score: 352.04727
- Similarity Product: 252.87233823750444

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test