PATENT CLAIM ANALYSIS

Application Number: 16003403
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["327", "158000"]

Abstract:
A clocking system disclosed herein includes a delay locked loop (DLL) circuit with a plurality of delay elements, where the DLL circuit is configured to receive a clock input signal and generate a plurality of clock output signals. The clocking system also includes a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.

Claim (Index 11):
The system of  claim 1 , wherein the successive delay elements generate a phase A and a phase B signal that are substantially 180 degrees out of phase.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 94.0
- Lexical Diversity: 1.80435
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15666391', '11647656', '11371555', '11848599', '12127059']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7716084175402695
- 35 USC 102 Novelty (BERT): 0.5218233235758191
- Combined Prediction Score: 0.7466299081438246
- Mean Citation Score: 187.61544
- Max Citation Score: 342.0638
- Similarity Product: 296.7631841688752

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test