PATENT CLAIM ANALYSIS

Application Number: 16206501
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "774000"]

Abstract:
A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

Claim (Index 18):
A method of making a stacked chip layout, the method comprising:\n stacking a plurality of circuit block layers over a central processing chip, wherein stacking each of the plurality of circuit block layers comprises:\n stacking an active circuit block, and \n depositing a dielectric material on a same level as the active circuit block, \n wherein the active circuit block of each of the plurality of circuit block layers includes a first portion overlapping the active circuit block of every other circuit block layer of the plurality of circuit block layers, and a second portion exposed by the active circuit block of every other circuit block layer of the plurality of circuit block layers; and routing a global conductive element electrically connecting the central processing chip to the active circuit block of each of the plurality of circuit block layers, wherein the global conductive element is routed through the first portion of the active circuit block of each of the plurality of circuit block layers.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 98.0
- Lexical Diversity: 3.175
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15291474', '14015262', '14855494', '12716902', '10233149']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9211749663766082
- 35 USC 102 Novelty (BERT): 0.5232975426271226
- Combined Prediction Score: 0.8813872240016597
- Mean Citation Score: 274.04031000000003
- Max Citation Score: 346.05054
- Similarity Product: 292.3699374213195

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test