PATENT CLAIM ANALYSIS

Application Number: 16035394
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["327", "288000"]

Abstract:
A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.

Claim (Index 28):
The circuit of  claim 26 , wherein the capacitive device comprises a transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.76667
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15481053', '15153799', '15660527', '12713904', '13434321']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.808068376883308
- 35 USC 102 Novelty (BERT): 0.5432072149543344
- Combined Prediction Score: 0.7815822606904107
- Mean Citation Score: 266.754686
- Max Citation Score: 411.9902
- Similarity Product: 299.1286849955082

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test