PATENT CLAIM ANALYSIS

Application Number: 16137562
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["710", "009000"]

Abstract:
A bus node is capable of performing a method for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes of the data bus system in an assignment time period. After the assigning of bus node addresses to the bus nodes in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.

Claim (Index 13):
A method for feeding address currents into a bus line via a plurality of bus nodes of a serial data bus system comprising:\n the bus line; and a bus master connected on a downstream end of the bus line, wherein, the plurality of bus nodes are serially connected to the bus line, upstream from the bus master;\n wherein the plurality of bus nodes includes:\n a first bus node, connected to the bus line at a site upstream from, and closest to the bus master; \n a last bus node, connected to the bus line at a site upstream from, and farthest from the bus master; and \n zero or more middle bus nodes, connected to the bus line in between the first bus node and the last bus node; wherein: \n at least two of the plurality of bus nodes are addressable bus nodes to which a respective address is assigned by the bus master in the addressing phase; and \n zero or more of the plurality of bus nodes are standard bus nodes having a respective address that is fixed prior to performing the addressing phase; \n wherein, in said method:\n each not-yet-addressed addressable bus node is operative to feed a respective address current into the bus line; \n zero or more of the plurality of bus nodes is operative to feed a respective quiescent current into the bus line; \n each not-yet-addressed addressable bus node is operative to detect, with aid of a current measurement circuit, a respective bus current flowing through the respective not-yet-addressed addressable bus node as a sum of (1) the quiescent currents of all of the plurality of bus nodes arranged upstream, (2) its own address current, and (3) the address currents of all not-yet-addressed addressable bus nodes arranged upstream; \n during the addressing phase, by analysis of the address currents fed respectively by each not-yet-addressed addressable bus nodes, individual bus nodes from the not-yet-addressed addressable bus nodes are identified; \n one of the not-yet-addressed addressable bus nodes is operative to feed the address current or a test current into the bus line selectively at one of a first electrical node and a second electrical node coupled to the bus line, wherein the current measurement circuit of the not-yet-addressed addressable bus node is arranged between the first electrical node and the second electrical node, and \n for\u2014or with\u2014the one not-yet-addressed addressable bus node, the one of the first electrical node and second electrical node is selected for the feeding of the address current at which the current measurement circuit is operative to detect one of the address current and the test current which is selectively fed into one of the first electrical node and the second electrical node or successively into each of the first electrical node and second electrical node.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 97.0
- Lexical Diversity: 2.86792
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16137563', '16137561', '14043186', '16470585', '15048354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6643268970543562
- 35 USC 102 Novelty (BERT): 0.5736146453431478
- Combined Prediction Score: 0.6552556718832354
- Mean Citation Score: 325.28069
- Max Citation Score: 507.13895
- Similarity Product: 365.92247584140296

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test