PATENT CLAIM ANALYSIS

Application Number: 16009995
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["365", "185050"]

Abstract:
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

Claim (Index 6):
The apparatus of  claim 5 , wherein the source extends beneath the first select gate source transistor, the second select gate source transistor, and the multiple memory cells of the memory cell string; and wherein the bit line extends above the multiple memory cells of the memory cell string.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 94.0
- Lexical Diversity: 3.58974
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14456222', '15443548', '15131671', '11767234', '13450294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8295710083810898
- 35 USC 102 Novelty (BERT): 0.519288099462364
- Combined Prediction Score: 0.7985427174892172
- Mean Citation Score: 275.544808
- Max Citation Score: 336.94702
- Similarity Product: 239.6550364883757

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test