PATENT CLAIM ANALYSIS

Application Number: 15975886
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "051000"]

Abstract:
To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.

Claim (Index 13):
An electronic device comprising:\n a semiconductor memory device including n data terminals, and configured to store data input from the n data terminals; a semiconductor device configured to access the data stored in the semiconductor memory device; and a wiring substrate on which the semiconductor device and the semiconductor memory device are mounted, wherein the wiring substrate includes:\n a first power-supply wiring layer on which the semiconductor device and the semiconductor memory device are mounted, and to which a ground power-supply voltage is supplied; \n a second power-supply wiring layer to which a ground power-supply voltage is supplied; \n a third power-supply wiring layer to which a power supply voltage is supplied; \n a first wiring layer interposed between the first power-supply wiring layer and the second power-supply wiring layer, and electrically connecting the semiconductor device with m (0<m<n) of the n data terminals; and \n a second wiring layer interposed between the second power-supply wiring layer and the third power-supply wiring layer, and electrically connecting the semiconductor device with k (k=n\u2212m) of the n data terminals, \n wherein the semiconductor device includes a number of a plurality of external terminals arranged in a grid pattern, and wherein a half or more of the number of the external terminals arranged on the outermost perimeter of the semiconductor device are electrically connected to the first power-supply wiring layer.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 2.5102
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15178091', '15170535', '15552774', '11360808', '14696372']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7960814466898527
- 35 USC 102 Novelty (BERT): 0.5202538315525831
- Combined Prediction Score: 0.7684986851761257
- Mean Citation Score: 243.062838
- Max Citation Score: 357.6255
- Similarity Product: 313.7690109322965

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test