PATENT CLAIM ANALYSIS

Application Number: 16238142
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["257", "369000"]

Abstract:
Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.

Claim (Index 11):
The semiconductor device of  claim 10 , wherein the first FET device is a PFET device and the second FET device is a NFET device.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 99.0
- Lexical Diversity: 2.62963
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15826076', '15180314', '14659796', '14551260', '12823163']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.931811617128326
- 35 USC 102 Novelty (BERT): 0.5587843421312131
- Combined Prediction Score: 0.8945088896286147
- Mean Citation Score: 308.393474
- Max Citation Score: 442.7688
- Similarity Product: 347.87266247034074

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test