PATENT CLAIM ANALYSIS

Application Number: 15896499
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "368000"]

Abstract:
An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Claim (Index 22):
The integrated circuit structure of  claim 21 , further comprising a substrate including an active area overlying the substrate, wherein the first and second channel regions are in the active area.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.97826
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14662326', '14277150', '13312828', '13591663', '14713948']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9089773069500908
- 35 USC 102 Novelty (BERT): 0.4951220632256712
- Combined Prediction Score: 0.867591782577649
- Mean Citation Score: 177.43833999999995
- Max Citation Score: 180.73862
- Similarity Product: 111.20373277534364

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test