PATENT CLAIM ANALYSIS

Application Number: 15920002
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "738000"]

Abstract:
A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

Claim (Index 4):
The semiconductor chip of  claim 3 , wherein the second circuit block is coupled to at least one of the one or more second signal pins and is not coupled to any of the one or more first signal pins.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 90.0
- Lexical Diversity: 3.42857
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14686666', '10884055', '12625457', '10164495', '10301200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919522610380716
- 35 USC 102 Novelty (BERT): 0.4921634021230123
- Combined Prediction Score: 0.8767866895549457
- Mean Citation Score: 164.183052
- Max Citation Score: 168.39426
- Similarity Product: 106.05706730727913

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test