PATENT CLAIM ANALYSIS

Application Number: 15911208
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-12
Patent Classification: ["365", "185180"]

Abstract:
A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

Claim (Index 15):
The method of  claim 1 , wherein a memory cell having a smallest horizontal width among the memory cells of the second cell group is programmed with fewer bits than a memory cell having a largest horizontal width of the memory cells of the second cell group.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 90.0
- Lexical Diversity: 2.50909
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15601698', '15067620', '13650545', '14997730', '13152684']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8352462711681196
- 35 USC 102 Novelty (BERT): 0.4840081521282451
- Combined Prediction Score: 0.8001224592641321
- Mean Citation Score: 237.90497
- Max Citation Score: 241.43787000000003
- Similarity Product: 190.34377267720524

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test