PATENT CLAIM ANALYSIS

Application Number: 16110298
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["712", "007000"]

Abstract:
An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.

Claim (Index 18):
The method of  claim 14 , wherein the storage location indicated by the first source packed data operand is one of a register and memory location.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 96.0
- Lexical Diversity: 2.34921
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13992236', '15201391', '15445741', '13976427', '13992394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6449548659112151
- 35 USC 102 Novelty (BERT): 0.5125679624387142
- Combined Prediction Score: 0.6317161755639651
- Mean Citation Score: 299.62997800000005
- Max Citation Score: 305.3769
- Similarity Product: 215.6907321564317

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test