PATENT CLAIM ANALYSIS

Application Number: 16396937
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "324000"]

Abstract:
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Claim (Index 14):
An integrated circuit (IC) comprising:\n a semiconductor substrate including a periphery region and a memory cell region separated by a boundary region; a pair of split gate flash memory cells disposed on the memory cell region; a first gate electrode disposed over a first gate dielectric layer on the periphery region; a second gate electrode disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode, the second gate dielectric layer being thicker than the first gate dielectric layer; an interlayer dielectric (ILD) over the boundary region, over the pair of split gate flash memory cells, over the first gate electrode, and over the second gate electrode; and an inter-gate dielectric layer continuously extending over the boundary region between the periphery region and the memory cell region and spaced apart from the ILD.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 100.0
- Lexical Diversity: 1.64286
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15582889', '14324369', '14296496', '14547251', '14580454']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9135039359146838
- 35 USC 102 Novelty (BERT): 0.513327544461023
- Combined Prediction Score: 0.8734862967693178
- Mean Citation Score: 213.67021
- Max Citation Score: 261.62045
- Similarity Product: 214.4744383504897

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test