PATENT CLAIM ANALYSIS

Application Number: 16212193
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["327", "212000"]

Abstract:
Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

Claim (Index 10):
The semiconductor circuit of  claim 1 , wherein the latch further comprises\n an eleventh transistor gated to the inverted output node and configured to output a power voltage as the output data, and a twelfth transistor gated to the inverted output node and configured to output a ground voltage as the output data.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 3.60976
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15247430', '14645818', '15139949', '15077438', '13834603']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.817835001744832
- 35 USC 102 Novelty (BERT): 0.5401228363104285
- Combined Prediction Score: 0.7900637852013916
- Mean Citation Score: 329.062874
- Max Citation Score: 399.16455
- Similarity Product: 328.90114486580194

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test