PATENT CLAIM ANALYSIS

Application Number: 15862041
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["714", "719000"]

Abstract:
An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Claim (Index 4):
The semiconductor device according to  claim 2 , further comprising:\n a user circuit which includes a function in accordance with a user; and a system control circuit which performs a boot time control of the semiconductor device, wherein after the system control circuit controls the BIST circuit to perform a test after power supply of the semiconductor device, it does not boot the user circuit when the first signal is received from the judgment circuit, and it boots the user circuit when the second signal is received.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.10417
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15658734', '10699223', '10805227', '10739123', '10271533']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3002983347155444
- 35 USC 102 Novelty (BERT): 0.5091177221969703
- Combined Prediction Score: 0.321180273463687
- Mean Citation Score: 223.031606
- Max Citation Score: 266.2719
- Similarity Product: 156.665912499547

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test