PATENT CLAIM ANALYSIS

Application Number: 16229072
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "368000"]

Abstract:
An apparatus comprises a plurality of memory cells in rows and columns, a first word line electrically coupled to a first group of memory cells through a first word line strap structure comprising a first gate contact, a first-level via, a first metal line and a second-level via and a second word line electrically coupled to a second group of memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.

Claim (Index 4):
The apparatus of  claim 2 , further comprising a row of isolation transistors between the first memory cells in the first row and the second memory cells in the second row, wherein each isolation transistor of the row of isolation transistors is coupled between a respective first transistor and a respective second transistor, wherein the each isolation transistor comprises:\n a source coupled to the drain of the respective first transistor; a drain coupled to the drain of the respective second transistor; and a gate coupled to the first VSS line.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 98.0
- Lexical Diversity: 2.4
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14458850', '13436452', '14263634', '13446220', '13423968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921696723996906
- 35 USC 102 Novelty (BERT): 0.548601065345869
- Combined Prediction Score: 0.8843871581318025
- Mean Citation Score: 361.386596
- Max Citation Score: 409.19983
- Similarity Product: 284.2748790860999

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test