PATENT CLAIM ANALYSIS

Application Number: 15997124
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["438", "108000"]

Abstract:
Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Claim (Index 5):
The semiconductor package of  claim 1 , wherein the conductive pillar comprises a metal selected from the group consisting essentially of copper, gold, silver, palladium, tantalum, tin, lead, and alloys thereof.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 2.10959
- Patent Class: 438.0
- Transitional Phrase Type: half
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15065632', '13653618', '15497408', '13658895', '15456134']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8868537793687157
- 35 USC 102 Novelty (BERT): 0.5008282650043024
- Combined Prediction Score: 0.8482512279322744
- Mean Citation Score: 225.730234
- Max Citation Score: 249.41315
- Similarity Product: 182.03495911803543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test