PATENT CLAIM ANALYSIS

Application Number: 16388177
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["708", "530000"]

Abstract:
A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.

Claim (Index 2):
The method according to  claim 1 , further comprising:\n determining the binary expansion of the predetermined invariant rational.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 100.0
- Lexical Diversity: 1.55385
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15633883', '15633851', '14208591', '15606351', '13537527']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4279753513634162
- 35 USC 102 Novelty (BERT): 0.5920020374051197
- Combined Prediction Score: 0.4443780199675866
- Mean Citation Score: 241.825854
- Max Citation Score: 481.18338
- Similarity Product: 460.2824450013256

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test