PATENT CLAIM ANALYSIS

Application Number: 15919885
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["717", "140000"]

Abstract:
An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.

Claim (Index 5):
The parallel processing processor of  claim 2 , wherein the core comprises a pool of computers configured to process algorithms as needed for a particular calculation, based on output from the precompiler, and the field programmable gates are configured to complete tasks without any further overhead from the processing unit.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.68
- Patent Class: 717.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12403224', '11973184', '10523764', '10884589', '12570943']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4285316627097016
- 35 USC 102 Novelty (BERT): 0.5004890557591655
- Combined Prediction Score: 0.435727402014648
- Mean Citation Score: 148.97728
- Max Citation Score: 154.91838
- Similarity Product: 94.1295763099158

Labels:
- Claim Label 101: 0
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test