PATENT CLAIM ANALYSIS

Application Number: 15924945
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["341", "161000"]

Abstract:
The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.

Claim (Index 1):
A successive approximation analog-to-digital converter that has:\n a plurality of capacitive elements that sample an analog input signal and have weighted capacitance values; a comparator that compares the analog input signal and a reference analog signal to output a comparison result; a plurality of registers that store digital data based on the comparison result; and a DAC that generates the reference analog signal based on the contents of the plurality of registers, wherein the analog input signal is converted to a digital code by successively changing the digital data based on the output of the comparator, the successive approximation analog-to-digital converter comprising: a first timing signal generation unit that generates a first timing signal based on the output of an oscillation circuit; a second timing signal generation unit that generates a second timing signal based on the state change of the output of the comparator; and a selector circuit that selects the first timing signal or the second timing signal to feed the selected timing signal to the comparator.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 90.0
- Lexical Diversity: 2.58065
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13197931', '12879377', '14161790', '13794308', '14435940']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5808627125172249
- 35 USC 102 Novelty (BERT): 0.5326465663923227
- Combined Prediction Score: 0.5760410979047347
- Mean Citation Score: 308.420508
- Max Citation Score: 339.07178
- Similarity Product: 286.4302956922483

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test