PATENT CLAIM ANALYSIS

Application Number: 15937656
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["710", "119000"]

Abstract:
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

Claim (Index 6):
The method of  claim 4 , further comprising:\n selecting the first storage component from the first group of storage components based at least in part on a first clock pulse; and selecting the second storage component from the first group of storage components based at least in part on a second clock pulse, wherein the second clock pulse is consecutive to the first clock pulse.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.07273
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15463504', '13919758', '15194154', '12687895', '14132390']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6182889482663904
- 35 USC 102 Novelty (BERT): 0.5036015549419203
- Combined Prediction Score: 0.6068202089339434
- Mean Citation Score: 196.555188
- Max Citation Score: 264.209
- Similarity Product: 197.65396093517543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test