PATENT CLAIM ANALYSIS

Application Number: 16048262
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "758000"]

Abstract:
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.

Claim (Index 9):
The memory device of  claim 7 , wherein the first complementary bit line and the first bit line are on a first metal layer and wherein the second complementary bit line and the second bit line are on a second metal layer, the via and the another via extending from the first metal layer to the second metal layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 95.0
- Lexical Diversity: 2.66667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15353618', '15233054', '15338907', '13446220', '14458293']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9230707978046758
- 35 USC 102 Novelty (BERT): 0.5003843880687219
- Combined Prediction Score: 0.8808021568310804
- Mean Citation Score: 208.46679
- Max Citation Score: 262.41998
- Similarity Product: 202.84776701378345

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test