PATENT CLAIM ANALYSIS

Application Number: 16135778
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["710", "038000"]

Abstract:
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Claim (Index 24):
The electronic memory device of  claim 17  further including an address mask circuit within the housing selecting only a portion of an address word received through the at least one pin, wherein the address mask communicates with additional pins to receive address filter inputs describing a subset of addresses and wherein the serial interface communicates with the address filter to provide access to the at least one random access storage element only for addresses within the subset of addresses;\n whereby multiple electronic memory devices may share a given serial computer memory bus as defined by different address filter inputs from the additional pins.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14267190', '11072106', '09872478', '12910867', '14492551']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.67608059657551
- 35 USC 102 Novelty (BERT): 0.4942776316590077
- Combined Prediction Score: 0.6579003000838598
- Mean Citation Score: 166.558238
- Max Citation Score: 245.9379
- Similarity Product: 180.9298019567728

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test