PATENT CLAIM ANALYSIS

Application Number: 15907993
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["710", "317000"]

Abstract:
A data processing apparatus includes N apparatus input ends, an input switch, K cache areas, a first output switch, a second output switch, and M apparatus output ends. N input ends of the input switch are coupled to the N apparatus input ends, and K output ends of the input switch correspond to the K cache areas. K 1  input ends of the first output switch correspond to K 1  cache areas in the K cache areas, and M output ends of the first output switch are coupled to the M apparatus output ends. K 2  input ends of the second output switch correspond to K 2  cache areas in the K cache areas except the K 1  cache areas, and M output ends of the second output switch are coupled to the M apparatus output ends.

Claim (Index 11):
The data processing apparatus according to  claim 3 , further comprising a queue management circuit, wherein a first address end of the queue management circuit is coupled to a second address end of the write arbitration circuit, wherein a second address end of the queue management circuit is coupled to a second address end of the read arbitration circuit, and wherein the queue management circuit is configured to:\n obtain data information from the write arbitration circuit, wherein the data information comprises a source port, a destination port, and a storage address for storing the data that are of data obtained by the write arbitration circuit; generate a cell descriptor (CD) according to the data information; add the CD to an output queue; and output the CD to the read arbitration circuit using the output queue, wherein a source port of the output queue comprises the source port of the data, wherein a destination port of the output queue comprises the destination port of the data, wherein the N apparatus input ends comprise the source port of the data, wherein the M apparatus output ends comprise the destination port of the data, and wherein the read arbitration circuit is configured to:\n obtain the CD from the queue management circuit; \n control, according to the CD, an output switch to read the data stored at the storage address; \n send the storage address to the cache management circuit; and \n control the output switch corresponding to the storage address to output the data to the destination port of the data.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 4.80645
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15337612', '09919859', '15851283', '10449018', '12382524']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6691626306673863
- 35 USC 102 Novelty (BERT): 0.4613345971761631
- Combined Prediction Score: 0.648379827318264
- Mean Citation Score: 173.950294
- Max Citation Score: 192.5432
- Similarity Product: 161.95479492087367

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test