PATENT CLAIM ANALYSIS

Application Number: 16107036
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Claim (Index 1):
A semiconductor device comprising:\n a first projecting unit which is a part of a semiconductor substrate, projects from an upper surface of the semiconductor substrate, and extends in a first direction along a main surface of the semiconductor substrate; a first gate electrode which extends in a second direction orthogonal to the first direction, and is formed to cover an upper surface and a side surface of a first part of the first projecting unit through a first gate insulating film, and a first silicide layer forming apart of a first source region and a second silicide layer forming a part of a first drain region which are formed in a manner that the first part is sandwiched therebetween in the first direction.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 96.0
- Lexical Diversity: 2.14286
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16036324', '15482239', '15879257', '15626092', '15961334']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9255369637547046
- 35 USC 102 Novelty (BERT): 0.5111841126215946
- Combined Prediction Score: 0.8841016786413937
- Mean Citation Score: 291.9861420000001
- Max Citation Score: 322.3297
- Similarity Product: 294.0289518553138

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test