PATENT CLAIM ANALYSIS

Application Number: 15892593
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.

Claim (Index 33):
The semiconductor device of  claim 26 , wherein the first gate structure comprises a gate stack and a gate spacer on a sidewall of the gate stack, and the helmet layer is connected with the gate spacer.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 88.0
- Lexical Diversity: 2.11765
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15827709', '15706456', '15864525', '15130370', '14511412']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9199558243336978
- 35 USC 102 Novelty (BERT): 0.489703767159052
- Combined Prediction Score: 0.8769306186162332
- Mean Citation Score: 184.644846
- Max Citation Score: 206.73743
- Similarity Product: 148.1745975268149

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test