PATENT CLAIM ANALYSIS

Application Number: 16059777
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["257", "427000"]

Abstract:
A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.

Claim (Index 11):
The device of  claim 10 , wherein a thickness of a combination of the top etch stop layer and the bottom etch stop layer is greater than or equal to about 10 angstrom and smaller than or equal to about 1100 angstrom.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 3.44186
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15587140', '15825972', '15180799', '15048545', '14798213']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917609098286899
- 35 USC 102 Novelty (BERT): 0.4823443174950332
- Combined Prediction Score: 0.8740826202077124
- Mean Citation Score: 164.648276
- Max Citation Score: 166.67525
- Similarity Product: 115.49319529871644

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test