PATENT CLAIM ANALYSIS

Application Number: 16134103
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "380000"]

Abstract:
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Claim (Index 15):
The device of  claim 8 , wherein the passive device further includes a second electrode and a third electrode disposed within polysilicon feature, wherein the first electrode, the second electrode and the third electrode are spaced apart from each other by the polysilicon feature.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 97.0
- Lexical Diversity: 1.77778
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15925323', '15620241', '14543169', '12770166', '15651248']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9371098315046604
- 35 USC 102 Novelty (BERT): 0.5590119360319794
- Combined Prediction Score: 0.8993000419573924
- Mean Citation Score: 339.2571480000001
- Max Citation Score: 386.80173
- Similarity Product: 314.86355188680585

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test