PATENT CLAIM ANALYSIS

Application Number: 15969302
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "065000"]

Abstract:
Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

Claim (Index 20):
The method of  claim 15 , further comprising:\n discharging the plate node from the first voltage to a second voltage less than the first voltage based at least in part on activating a sense component coupled to the digit line.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 93.0
- Lexical Diversity: 2.68966
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15669785', '15674382', '15469865', '15845619', '15246249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.774760376746361
- 35 USC 102 Novelty (BERT): 0.5013634034449421
- Combined Prediction Score: 0.7474206794162191
- Mean Citation Score: 249.890858
- Max Citation Score: 262.2934
- Similarity Product: 188.86044824037555

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test