PATENT CLAIM ANALYSIS

Application Number: 15975628
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["365", "145000"]

Abstract:
Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

Claim (Index 8):
The apparatus of  claim 1 , further comprising:\n a plurality of ferroelectric memory cells coupled with the plate line, the first capacitor configured to apply the first voltage to the plurality of ferroelectric memory cells and the voltage source configured to apply the second voltage to the plurality of ferroelectric memory cells when the second switching component is activated.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 93.0
- Lexical Diversity: 2.38182
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15975624', '15689211', '15073989', '15071991', '15442182']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7665864912431591
- 35 USC 102 Novelty (BERT): 0.4655378701114602
- Combined Prediction Score: 0.7364816291299893
- Mean Citation Score: 210.46162200000003
- Max Citation Score: 214.48288
- Similarity Product: 194.2469102843476

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test