PATENT CLAIM ANALYSIS

Application Number: 15867646
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["711", "103000"]

Abstract:
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

Claim (Index 2):
A memory controller circuit for configuring connectivity of a memory device having a configurable width, the memory controller circuit comprising:\n a command/address link coupled to the memory device; a plurality of memory controller data pins coupled to respective memory device data pins of the memory device; a connectivity read circuit to transmit a connectivity read command over the command/address link, wherein read data is received at the memory controller data pins from the memory device in response to the connectivity read command; a connectivity logic circuit to determine a connectivity configuration between the plurality of data pins of the memory controller and one or more of the memory device data pins of the memory device based on the data received at the memory controller data pins of the memory controller matching one or more predetermined bit patterns; and a connectivity write circuit to transmit a connectivity write command to the memory device over the command/address link, the connectivity write command to configure the memory device based on the determined connectivity configuration, wherein configuring the memory device comprises causing the memory device to selectively associate one or more of a plurality of internal data buses of the memory device to one or more of the memory device data pins of the memory device.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 86.0
- Lexical Diversity: 2.2381
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14438865', '13514977', '13970606', '15857519', '14861451']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3351953517345312
- 35 USC 102 Novelty (BERT): 0.5450740744372495
- Combined Prediction Score: 0.356183224004803
- Mean Citation Score: 201.96538000000004
- Max Citation Score: 381.06918
- Similarity Product: 356.9970565874577

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test