PATENT CLAIM ANALYSIS

Application Number: 15889932
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["716", "106000"]

Abstract:
A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog. First and second output subsystem data is collected from at least one output of the first and second subsystem design representation of the at least two design representations caused by the analog stimulus to the at least one input of the first and second subsystem design representation. At least one parameter of said first and second input subsystem data is analyzed with respect to said first and second output subsystem data. The at least one parameter of the first subsystem design representation is compared with the at least one parameter of second subsystem design representation. The electronic design file of the electronic design is verified responsive to the determined analysis between the at least one input of the subsystem and the at least one output of the subsystem for each of the first and the second subsystem design representations.

Claim (Index 11):
The apparatus to passively verify said electronic design of  claim 10 ,\n said processor further configured to:\n determine at least one input variation of said at least one input to the first and second subsystem design representation to said at least one output of the first and second subsystem design representation; \n determine at least one output variation of said at least one output of the first and second subsystem design representation to said at least one output of the first and second subsystem design representation; and \n correlate said historical output variation to said historical input variation.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 88.0
- Lexical Diversity: 3.56757
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15871210', '14707723', '14707689', '15654469', '14788091']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4055146323214668
- 35 USC 102 Novelty (BERT): 0.4992105335928927
- Combined Prediction Score: 0.4148842224486094
- Mean Citation Score: 286.56808
- Max Citation Score: 300.95868
- Similarity Product: 201.7676751068616

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test