PATENT CLAIM ANALYSIS

Application Number: 15980794
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-02
Patent Classification: ["363", "132000"]

Abstract:
A method and a device for voltage balancing of DC bus capacitors of an NPC four-level inverter are disclosed. The method includes: determining an optimal zero-sequence voltage, determining an actual reference voltage of each phase based on the optimal zero-sequence voltage; comparing respectively three preset carrier signals with the actual reference voltage of each phase to obtain three first control signals; determining three duty-cycle adjustment values based on a voltage of the intermediate bus capacitor; adjusting correspondingly the three first control signals based the three duty-cycle adjustment values to obtain three second control signals; inputting correspondingly the three second control signals to three first switches of an upper bridge corresponding to each phase; and inputting correspondingly complementary signals of the three second control signals to three second switches of a lower bridge corresponding to each phase.

Claim (Index 20):
The device according to  claim 19 , wherein the control is configured to determine the adjustment direction of the duty ratio of each of the three first control signals based on the magnitude relationship between the voltage of the intermediate bus capacitor and the given voltage and based on the polarity of the load current, by acts of:\n when u d2 >E and i ox >0, or when u d2 <E and i ox <0, decreasing d x1 +d x3 \u22122d x2 , in which when 0\u2264u refx \u2032< 3/2, d x1  is equal to 0, d x2  is needed to increase and d x3  is needed to decrease, and when 3/2\u2264u refx \u2032\u22643, d x3  is equal to 1, d x2  is needed to increase and d x1  is needed to decrease, where u d2  represents the voltage of the intermediate bus capacitor, d x1 , d x2  and d x3  represent duty ratios of the three first control signals, E represents a rated voltage of each of the bus capacitors, and i ox  represents an output current corresponding to each phase; when u d2 >E and i ox <0, or when u d2 <E and i ox >0, increasing d x1 +d x3 \u22122d x2 , in which when 0\u2264u refx \u2032< 3/2, d x1  is equal to 0, d x2  is needed to decrease and d x3  is needed to increase, and when 3/2\u2264u refx \u2032\u22643, d x3  is equal to 1, d x2  is needed to decrease and d x1  is needed to increase.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.41667
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15109219', '15662044', '13912398', '14153103', '15823192']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7959909525315804
- 35 USC 102 Novelty (BERT): 0.5078892012797152
- Combined Prediction Score: 0.7671807774063939
- Mean Citation Score: 228.819082
- Max Citation Score: 246.3851
- Similarity Product: 165.8791405343175

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test