PATENT CLAIM ANALYSIS

Application Number: 15761497
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.

Claim (Index 14):
The gate driving circuit according to  claim 13 ,\n wherein:\n the reset terminal includes a first reset port and a second reset port, and \n the gating circuits are first gating circuits, \n the gate driving circuit further comprising:\n (N\u22121) second gating circuits, each of the (N\u22121) gating circuits being coupled to one of the 1st-stage to the (N\u22121)-th-stage shift registers, \n wherein:\n each of the second gating circuits includes an input terminal, a first control terminal, a second control terminal, a first output terminal, and a second output terminal, and is configured to electrically connect the input terminal to the first output terminal when the first control terminal of the second gating circuit receives an active signal, and to electrically connect the input terminal to the second output terminal when the second control terminal of the second gating circuit receives an active signal, \n the first control terminal of the second gating circuit at each stage is coupled to the first control line, \n the second control terminal of the second gating circuit at each stage is coupled to the second control line, \n the input terminal of an n-th-stage second gating circuit is coupled to the signal output terminal of an (n+1)-th-stage shift register, \n the first output terminal of the n-th-stage second gating circuit is coupled to the first reset port of the n-th-stage shift register, and \n the second output terminal of the n-th-stage second gating circuit is coupled to the second reset port of the n-th-stage shift register.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 4.09677
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15740121', '15518389', '15541622', '15542365', '15541426']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6916496700073351
- 35 USC 102 Novelty (BERT): 0.5158594035737752
- Combined Prediction Score: 0.6740706433639791
- Mean Citation Score: 313.09041400000007
- Max Citation Score: 322.13254
- Similarity Product: 243.29116947983985

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test