PATENT CLAIM ANALYSIS

Application Number: 15874893
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "737000"]

Abstract:
Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 μm.

Claim (Index 11):
A method of manufacturing a 3DIC structure, comprising:\n bonding a plurality of dies to a wafer; forming a dielectric layer on the wafer and the dies, covering top surfaces and sidewalls of the dies, wherein a top surface of the dielectric layer between the dies is lower than top surfaces of the dies; performing a first planarization process to remove a portion of the dielectric layer, so as to expose the top surfaces of the dies; and performing a second planarization process to remove another portion of the dielectric layer and portions of the dies, wherein top corners of the dies are covered by the dielectric layer during the first planarization process and the second planarization process.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 86.0
- Lexical Diversity: 1.81818
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14275488', '13215959', '12878112', '15799355', '15389738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9064981659194298
- 35 USC 102 Novelty (BERT): 0.4672365165343681
- Combined Prediction Score: 0.8625720009809237
- Mean Citation Score: 144.45195399999997
- Max Citation Score: 149.95879
- Similarity Product: 111.3666678044474

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test