PATENT CLAIM ANALYSIS

Application Number: 16184734
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "077000"]

Abstract:
A method of producing a semiconductor device including steps (A) and (B). Step (A) is preparing a semiconductor epitaxial wafer including a plurality of device regions, each including a body region contacting a semiconductor layer. Step (B) is forming a channel layer contacting at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer. The channel layer contains an impurity at a concentration ranging from 1×10 18  cm −3  to 1×10 19  cm −3 , inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the step (B), a condition for the epitaxial growth is controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the impurity in the channel layer are negatively correlated to each other.

Claim (Index 4):
A method of producing a semiconductor device, the method comprising steps of:\n (A) preparing a semiconductor epitaxial wafer which includes a semiconductor wafer, and a semiconductor layer disposed on a main surface of the semiconductor wafer, the semiconductor layer containing a first conductivity type impurity, the semiconductor epitaxial wafer including a plurality of device regions, each of which includes a body region of a second conductivity type in contact with the semiconductor layer, and a source region of the first conductivity type in contact with the body region; (B) forming a channel layer which is in contact with at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer; and (C) forming a gate insulation film on the channel layer, wherein: the channel layer contains the first conductivity type impurity at a concentration ranging from 1\u00d710 18  cm \u22123  to 1\u00d710 19  cm \u22123 , inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive, and in the steps of (B) and (C), a condition for the epitaxial growth and a condition for forming the gate insulation film are controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a thickness distribution in the gate insulation film are positively correlated to each other.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 2.34722
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15896490', '15397677', '14122823', '14897247', '15394950']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9290237641721696
- 35 USC 102 Novelty (BERT): 0.5810981213490761
- Combined Prediction Score: 0.8942311998898602
- Mean Citation Score: 344.54284399999995
- Max Citation Score: 478.881
- Similarity Product: 440.7003725187778

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test