PATENT CLAIM ANALYSIS

Application Number: 15869917
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "203000"]

Abstract:
A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.

Claim (Index 5):
The semiconductor device as set forth in  claim 4 , wherein:\n the first conductive type is n-type, the second conductive type is p-type the first gate voltage is between \u22120.25V and \u22121V, the second gate voltage is between \u22120.1V and 0.1V, the third gate voltage is between 0.25V and 1V, the first drain voltage is between 0.5V and 1.5V, and the second drain voltage is 0V.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.80952
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15185388', '15870092', '15394584', '11433753', '11261729']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9292873339666344
- 35 USC 102 Novelty (BERT): 0.5367228395773291
- Combined Prediction Score: 0.8900308845277038
- Mean Citation Score: 271.37967000000003
- Max Citation Score: 377.8438
- Similarity Product: 224.3044432205916

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test