PATENT CLAIM ANALYSIS

Application Number: 16173398
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-06
Patent Classification: ["341", "161000"]

Abstract:
The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

Claim (Index 16):
The successive approximation register analog to digital converter of  claim 14  wherein the successive approximation register sequencer is configured to couple more than one capacitor of the capacitor array to the pre-defined voltage based on the output of the flash analog to digital converter.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 1.89831
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15853779', '15849234', '16137876', '16159498', '14949423']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6246149016426009
- 35 USC 102 Novelty (BERT): 0.5328256246350205
- Combined Prediction Score: 0.6154359739418429
- Mean Citation Score: 264.440804
- Max Citation Score: 347.69278
- Similarity Product: 280.6282303088773

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test