PATENT CLAIM ANALYSIS

Application Number: 15903090
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["341", "158000"]

Abstract:
An analog to digital conversion device according to one or more embodiments may include sequential comparison type analog to digital converters, wherein each of the analog to digital converters converts an analog signal to a digital signal by repeating comparative voltage generation processing to generate a comparative voltage and comparison processing to compare the analog signal with the comparative voltage. Each of the analog to digital converters may include a noise notification part that generates a noise notification signal to give notification of noise production and inputs the noise notification signal to a different one of the analog to digital converters. At start of operation, based on the notification noise signal inputted from the different analog to digital converter, each of the analog to digital converters may be synchronized with the different analog to digital converter performing the comparative voltage generation processing and the comparison processing.

Claim (Index 3):
An analog to digital conversion device comprising:\n a first analog to digital converter and a second analog to digital converter, each comprising: a controller that generates a first processing clock, a second processing clock, and a third processing clock based on a reference clock signal and an enable signal; a sample and hold circuit that receives an analog signal and holds a signal level of the analog signal based on the enable signal; a comparator that receives the held signal level of the analog signal and a comparative voltage and compares the signal level with the comparative voltage based on the second processing clock; a sequential comparison register that stores a digital value corresponding to a comparison result obtained by the comparator based on the third processing clock and outputs a given digital signal; and a digital to analog converter that receives the first processing clock, and based on the first processing clock, generates the comparative voltage corresponding to the digital value stored in the sequential comparison register, wherein the controller of the first analog to digital converter generates a noise notification signal that gives notification of noise production, and the controller of the second analog to digital converter controls the first processing clock, the second processing clock, and the third processing clock based on the noise notification signal generated by the first analog to digital converter, and thereby synchronizes the second analog to digital converter with the first analog to digital converter.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.62069
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11889620', '13163872', '10945924', '13936563', '11098986']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5841984701329023
- 35 USC 102 Novelty (BERT): 0.4853847673414704
- Combined Prediction Score: 0.5743170998537591
- Mean Citation Score: 207.719324
- Max Citation Score: 220.75348
- Similarity Product: 179.57325574144363

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test