PATENT CLAIM ANALYSIS

Application Number: 15948220
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["712", "214000"]

Abstract:
Embodiments of the present invention disclose a method, a computer program product, and a computer system for system for executing instructions, comprising a processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In addition, the processor can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the processor can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.

Claim (Index 11):
The method of  claim 10 , wherein the pair of destructive instructions comprise a first instruction and a second instruction, wherein the second instruction depends on the value stored in the shared physical register by the first instruction.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.25
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13491781', '15051465', '13552108', '14313358', '13726746']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5380871066236019
- 35 USC 102 Novelty (BERT): 0.4878509433641979
- Combined Prediction Score: 0.5330634902976615
- Mean Citation Score: 163.585358
- Max Citation Score: 167.68303999999995
- Similarity Product: 113.90280306192396

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test