PATENT CLAIM ANALYSIS

Application Number: 15877661
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "189170"]

Abstract:
A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Claim (Index 12):
A memory system for reading and writing data to and from circuit registers, the system comprising:\n at least one memory control circuit configured to receive commands from a host and to output command and control signals; at least one memory device configured to store data; at least one data buffer circuit associated with the at least one memory control circuit and the at least one memory device, the data buffer circuit having data buffers and at least one register; a first data communications link for communicating data between the host and the at least one data buffer circuit, and a second data communications link between the at least one data buffer circuit and the at least one memory device, wherein the first data communications link is a high speed serial interface; a communications link between the host and the at least one memory control circuit, wherein the communications link is a high speed serial interface; a control communications link between the at least one memory control circuit, and the at least one data buffer circuit for transmitting signals of the memory system;\n wherein the system is configured so that data from register access operations is transferred over the high speed serial interfaces between the host and at least one of the group consisting of the memory control circuit, one or more of the data buffer circuits, and both the memory control circuit and one or more of the data buffer circuits.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.92157
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15825882', '15825909', '15825894', '09879658', '12952205']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8069266710380159
- 35 USC 102 Novelty (BERT): 0.4880808605556813
- Combined Prediction Score: 0.7750420899897825
- Mean Citation Score: 242.609394
- Max Citation Score: 278.40112
- Similarity Product: 241.46576366167068

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test