PATENT CLAIM ANALYSIS

Application Number: 16196507
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["174", "255000"]

Abstract:
A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in the bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.

Claim (Index 5):
A method for manufacturing a multi-row wiring member for semiconductor device configured of a plurality of wiring members for semiconductor devices arrayed in a matrix including:\n a step of forming, on a front surface of a metal sheet, a first resist mask having pattern-A openings and of forming, on a back surface of the metal sheet, a second resist mask having an opening at a site that is to be a margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix; a step of forming, in the pattern-A openings, a first plating layer, which is to become internal terminals, and a plating layer that is to become wiring portions, connected with the first plating layer, and of forming, in the opening at the site that is to be the margin around the aggregate of individual wiring members for semiconductor devices arrayed in a matrix, a plating layer that is to become a resist for forming a metal frame portion; a step of peeling off the first resist mask and the second resist mask formed on the respective surfaces of the metal sheet; a step of forming, on a front-surface side of the metal sheet, a third resist mask having pattern-B openings that leave uncovered partial areas within areas of the plating layer that is to become wiring portions and of forming a fourth resist mask covering an entirety of the back surface of the metal sheet; a step of forming a second plating layer, which is to become external terminals, in the pattern-B openings; a step of peeling off the third resist mask and the fourth resist mask respectively formed on the front surface and the back surface of the metal sheet; a step of forming a resin layer on the metal sheet and the plating layer that is to become wiring portions at sites free from the second plating layer to leave upper faces of the second plating layer uncovered; and a step of removing by etching, from a back-surface side of the metal sheet, metal except a portion covered with the plating layer that is to become a resist for forming a metal frame portion at the site that is to become the margin around the aggregate of individual wiring members for semiconductor devices arrayed in a matrix.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 98.0
- Lexical Diversity: 2.67797
- Patent Class: 174.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16196282', '16196718', '15539481', '15661479', '11350032']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8745041953665459
- 35 USC 102 Novelty (BERT): 0.5664874082655873
- Combined Prediction Score: 0.84370251665645
- Mean Citation Score: 351.82272400000005
- Max Citation Score: 442.8321
- Similarity Product: 438.84296713258624

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test