PATENT CLAIM ANALYSIS

Application Number: 16198046
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["257", "347000"]

Abstract:
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

Claim (Index 12):
The semiconductor device of  claim 10 , further comprising second insulating spacers disposed in the spaces, respectively.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.60417
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15725655', '15653068', '15407839', '15941798', '15986426']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9300755400777236
- 35 USC 102 Novelty (BERT): 0.5283259197219322
- Combined Prediction Score: 0.8899005780421445
- Mean Citation Score: 302.06832
- Max Citation Score: 353.0548
- Similarity Product: 278.5431407882452

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test