PATENT CLAIM ANALYSIS

Application Number: 16206500
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["438", "503000"]

Abstract:
A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Claim (Index 14):
The method of  claim 13 , wherein the first pressure is about 1000 Pa, and wherein the second pressure is about 20 Pa.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 2.3871
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15089153', '10959602', '10993024', '10841369', '15918434']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8583078290972042
- 35 USC 102 Novelty (BERT): 0.5037449064765492
- Combined Prediction Score: 0.8228515368351388
- Mean Citation Score: 197.240736
- Max Citation Score: 302.84164
- Similarity Product: 300.3264278838039

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test