PATENT CLAIM ANALYSIS

Application Number: 14897777
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["349", "047000"]

Abstract:
Provided is an LTPS array substrate and a liquid crystal display panel, wherein the LTPS array substrate comprises: a first common electrode layer; a passivation layer, which is formed on the first common electrode layer, and has a first via hole formed therein; a pixel electrode layer, which is formed on the passivation layer; and a second common electrode layer, which is formed on the passivation layer, located between pixel electrodes corresponding to two adjacent sub-pixels in the pixel electrode layer, electrically isolated from the pixel electrode layer, and electrically connected to the first common electrode layer through the first via hole. The array substrate is capable of significantly enhancing the intensity of an electric field at an edge region of the adjacent sub-pixels, thereby increasing the transmittance at this region.

Claim (Index 15):
The liquid crystal display panel according to  claim 10 , wherein the array substrate further includes, at a TFT switch position thereof:\n a transparent substrate; a light-shielding layer, which is formed on the transparent substrate; a second insulation layer, which is formed on the light-shielding layer and the transparent substrate; a polysilicon layer, which is formed on the second insulation layer and located directly above the light-shielding layer; a third insulation layer, which is formed on the polysilicon layer and the second insulation layer; a gate layer, which is formed on the third insulation layer and located directly above the light-shielding layer; a fourth insulation layer, which is formed on the gate layer and the third insulation layer; a source and drain layer, which is formed on the fourth insulation layer, and is electrically connected to the polysilicon layer through a second via hole formed in the third insulation layer and the fourth insulation layer; and a flat layer, which is formed on the source and drain layer and the fourth insulation layer, wherein the first common electrode layer is formed on the flat layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.35484
- Patent Class: 349.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14897672', '14889207', '14901250', '15114850', '15578109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8685367024830772
- 35 USC 102 Novelty (BERT): 0.5427625601943622
- Combined Prediction Score: 0.8359592882542057
- Mean Citation Score: 315.8924820000001
- Max Citation Score: 406.86945
- Similarity Product: 293.30037576828

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test