PATENT CLAIM ANALYSIS

Application Number: 15890981
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "077000"]

Abstract:
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Claim (Index 31):
The semiconductor device of  claim 30 , wherein the gate dielectric and the gate electrode extends at least to an outer edge of the first and second source regions in the X direction.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 1.92208
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14966476', '14456110', '14963381', '15793562', '14619742']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.938344351565144
- 35 USC 102 Novelty (BERT): 0.594069273657126
- Combined Prediction Score: 0.9039168437743424
- Mean Citation Score: 456.33589000000006
- Max Citation Score: 511.76236
- Similarity Product: 440.7917145815611

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test