PATENT CLAIM ANALYSIS

Application Number: 15882288
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["716", "124000"]

Abstract:
The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

Claim (Index 8):
The method of  claim 7 , wherein the base cell library with a second pin offset comprises a second pin location for the cell, and wherein the second pin location comprises another placement site offset relative to the placement site of the cell as defined in the base cell library.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.45312
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13070440', '15878818', '15145455', '11007039', '11757200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3309568581348326
- 35 USC 102 Novelty (BERT): 0.4646962790405325
- Combined Prediction Score: 0.3443308002254026
- Mean Citation Score: 112.671458
- Max Citation Score: 115.98021
- Similarity Product: 73.33923869606852

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test