PATENT CLAIM ANALYSIS

Application Number: 15870390
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["711", "103000"]

Abstract:
A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.

Claim (Index 19):
A method, comprising:\n storing configuration data comprising a plurality of sequencer vectors within a volatile random access memory (RAM) communicatively coupled to a sequencer circuit embodied within a non-volatile (NV) circuit structure; and implementing a series of sequencer vectors stored within the volatile RAM at the sequencer circuit in response to a request to implement an operation on NV memory cells of the NV circuit structure, comprising:\n transferring a data unit comprising a first sequencer vector of the series from the volatile RAM; and \n interpreting the bit values of the data unit according to a determined layout for the sequencer vectors stored within the volatile RAM, wherein first bit values comprise an output signal vector, second bit values comprise a mantissa, and third bit values comprise an exponent; \n executing the first sequencer vector, comprising:\n producing on-die memory control signals corresponding to the output signal vector of the first sequencer vector for a determined number of clock cycles, the on-die memory control signals configured to cause one or more functional modules of the control circuitry to implement at least a portion of the memory operation; \n wherein the determined number of clock cycles is calculated as m\u00d72 e , where m is the mantissa and e is the exponent of the first sequencer vector; and \n \n processing a next sequencer vector in the series in response to completing execution of the first sequencer vector.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.15789
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10486638', '15693390', '11818449', '14729659', '13915606']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5284599610516871
- 35 USC 102 Novelty (BERT): 0.4648929768603136
- Combined Prediction Score: 0.5221032626325498
- Mean Citation Score: 143.17608
- Max Citation Score: 145.96693
- Similarity Product: 106.45508602798284

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test