PATENT CLAIM ANALYSIS

Application Number: 15924032
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "148000"]

Abstract:
A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.

Claim (Index 15):
A method of using a memory device, the memory device comprising: a bottom contact; a memory layer connected to the bottom contact, wherein the memory layer has a variable resistance; a top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure; a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the first barrier layer is between the top electrode and the top contact, and wherein the first barrier layer has a resistivity less than 1E-4 Ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the second barrier layer is between the memory layer and the bottom contact, and wherein the first barrier layer has a resistivity less than 1E-4 Ohm-m, the method comprising:\n applying a first voltage difference across the bottom contact and the top contact, whereby an electric field is generated in the memory layer, and such that a resistivity state of the memory layer is changed; applying a second voltage difference across the bottom contact and the top contact; while the second voltage difference is applied, causing a first current to be conducted through the bottom contact, the second barrier layer, the memory layer, the top electrode, the first barrier layer, and the top contact; and determining the resistivity state of the memory layer based on the second voltage and the first current.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 3.39583
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15924014', '15923992', '13408103', '14829440', '10308843']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7657350806025172
- 35 USC 102 Novelty (BERT): 0.5520588016059891
- Combined Prediction Score: 0.7443674527028644
- Mean Citation Score: 275.42207399999995
- Max Citation Score: 422.68225
- Similarity Product: 354.1615954042078

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test