PATENT CLAIM ANALYSIS

Application Number: 16029604
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["326", "098000"]

Abstract:
A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Claim (Index 11):
The method according to  claim 1 , further comprising:\n based the plurality of inputs of the decoder not being in the predetermined input state and based on being in the evaluation phase, causing, by the decoder, the first node to be high; and based on the first node being high and based on being in the evaluation phase, causing, by the evaluate circuit, the second node to be low;

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.10638
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16029603', '16029577', '15796819', '16029607', '15613185']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7682699897232461
- 35 USC 102 Novelty (BERT): 0.5602413504291089
- Combined Prediction Score: 0.7474671257938325
- Mean Citation Score: 469.003724
- Max Citation Score: 498.23557
- Similarity Product: 375.9225544808304

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test