PATENT CLAIM ANALYSIS

Application Number: 15907570
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "185110"]

Abstract:
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.

Claim (Index 9):
The apparatus of  claim 1 , wherein:\n the multiple sub-blocks are connected to a control line; the erase circuit is configured to erase the group of memory cells by applying erase pulses the control line; each sub-block of the multiple sub-blocks has its own select gate that connect the respective to the control line; and the erase speed circuit is configured to adjust erase speed by adjusting voltages applied to the select gates.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 1.51515
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15337522', '15630389', '15191150', '15151951', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8207825701131715
- 35 USC 102 Novelty (BERT): 0.4743165442173027
- Combined Prediction Score: 0.7861359675235846
- Mean Citation Score: 226.306854
- Max Citation Score: 232.60359
- Similarity Product: 197.6064825224716

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test