PATENT CLAIM ANALYSIS

Application Number: 15976315
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["365", "145000"]

Abstract:
Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS −V G  hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS  states at V G =0.

Claim (Index 24):
The NVM device recited in  claim 1 , wherein:\n the circuit topology is configured as a backup and restore circuit (B&R circuit); the B&R circuit comprising:\n a first transistor, M 1 , M 1  having an M 1 -source, an M 1 -gate, and an M 1 -drain; \n a second transistor, M 2 , M 2  having an M 2 -source, an M 2 -gate, and an M 2 -drain; \n a third transistor, M 3 , M 3  having an M 3 -source, an M 3 -gate, and an M 3 -drain; \n a fourth transistor, M 4 , M 4  having an M 4 -source, an M 4 -gate, and an M 4 -drain; \n a first branch comprising M 1 , M 3 , and ground, GND; \n a second branch comprising M 2 , M 4 , and GND; \n each of M 1  and M 2  is a metal oxide semiconductor field effect transistor (MOSFET); \n each of M 3  and M 4  is a FeFET; \n M 1 -drain being connected to M 3 -source; \n M 1 -gate being connected to a restore signal input signal and M 2 -gate; \n M 1 -source being connected to GND; \n M 2 -drain being connected to M 4 -source; \n M 2 -gate being connected to M 1 -gate; \n M 3 -drain configured to be connected to a slave latch via the first branch; \n M 3 -drain being connected to M 4 -gate, M 4 -drain, M 3 -gate, and to the second branch; \n M 3 -gate being connected to M 4 -gate, M 4 -drain, M 3 -drain, and to the second branch; \n M 3 -source being connected to M 1 -drain; \n M 4 -drain configured to be connected to the slave latch via the second branch; \n M 4 -drain being connected to M 3 -gate, M 3 -drain, M 4 -gate, and to the first branch; \n M 4 -gate being connected to M 3 -gate, M 3 -drain, M 4 -drain, and to the first branch; and \n M 4 -source being connected to M 2 -drain.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 93.0
- Lexical Diversity: 1.77632
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12860253', '15594807', '13137566', '12856962', '13396272']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7778055449666997
- 35 USC 102 Novelty (BERT): 0.4697426756307193
- Combined Prediction Score: 0.7469992580331017
- Mean Citation Score: 165.774406
- Max Citation Score: 186.89499
- Similarity Product: 140.14441783874992

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test