PATENT CLAIM ANALYSIS

Application Number: 15746100
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "774000"]

Abstract:
The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.

Claim (Index 17):
A memory module comprising:\n a module substrate; a plurality of dynamic random access memory (DRAM) packages mounted on the module substrate; and a plurality of contact terminals, which are arranged at one side of the module substrate at regular intervals and electrically connect the DRAM packages, wherein each of the DRAM packages includes: an integrated substrate; a bottom package stacked on the integrated substrate, wherein an edge of a bottom substrate is exposed without being covered by a bottom protective member; a top package stacked on the bottom package through an adhesive member, wherein an edge of a top substrate is exposed without being covered by a top protective member; an integration wire configured to electrically connect the bottom package to the top package, wherein the integration wire electrically connects the exposed edge of the bottom substrate to the exposed edge of the top substrate; and an integration protective member configured to seal the integration wire.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.07407
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15435719', '14802750', '14028534', '12659391', '13313950']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.906638165594691
- 35 USC 102 Novelty (BERT): 0.490651766698792
- Combined Prediction Score: 0.8650395257051011
- Mean Citation Score: 161.118698
- Max Citation Score: 172.36106999999996
- Similarity Product: 109.3862189383256

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test