PATENT CLAIM ANALYSIS

Application Number: 15903999
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "149000"]

Abstract:
According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.

Claim (Index 15):
The device of  claim 13 , wherein\n the first distributor comprises: a third operational amplifier including a first input terminal to which the first voltage input; a fourth transistor including a gate electrically coupled to an output terminal of the third operational amplifier, one end electrically coupled to a power supply voltage, and the other end which outputs the second voltage; a third resistor including one end electrically coupled to the other end of the fourth transistor, and the other end electrically coupled to a second input terminal of the third operational amplifier; a fifth transistor including one end electrically coupled to the other end of the fourth transistor, and the other end electrically coupled to the second input terminal of the third operational amplifier; a fourth resistor including one end electrically coupled to the other end of the fifth transistor and the other end of the third resistor, and the other end electrically coupled to a ground voltage; a first address controller which supplies a signal in accordance with a row address to a gate of the fifth transistor, and the second distributor comprises: a fourth operational amplifier including a first input terminal to which the first voltage is input; a sixth transistor including a gate electrically coupled to an output terminal of the fourth operational amplifier, one end electrically coupled to the power supply voltage, and the other end which outputs the third voltage; a fifth resistor including one end electrically coupled to the other end of the sixth transistor, and the other end electrically coupled to a second input terminal of the fourth operational amplifier; a seventh transistor including one end electrically coupled to the other end of the sixth transistor, and the other end electrically coupled to the second input terminal of the fourth operational amplifier; a sixth resistor including one end electrically coupled to the other end of the seventh transistor and the other end of the fifth resistor, and the other end electrically coupled to the ground voltage; and a second address controller which supplies a signal in accordance with a row address to a gate of the seventh transistor.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.85
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15065449', '15455906', '15261680', '15702298', '12409666']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7944709234891466
- 35 USC 102 Novelty (BERT): 0.4553819737067674
- Combined Prediction Score: 0.7605620285109087
- Mean Citation Score: 141.43437
- Max Citation Score: 149.34566
- Similarity Product: 116.6234920201826

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test