PATENT CLAIM ANALYSIS

Application Number: 15870910
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "777000"]

Abstract:
A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.

Claim (Index 18):
A semiconductor package comprising:\n a package substrate including a substrate pad on an upper surface thereof; a first signal connection terminal electrically connected to the substrate pad; a first dummy connection terminal spaced apart from the substrate pad and the first signal connection terminal and disposed on the package substrate; a first semiconductor chip disposed on the first dummy connection terminal and the first signal connection terminal, the first semiconductor chip including a first via electrically connected to the first signal connection terminal; a second signal connection terminal connected to the first via and overlying the first semiconductor chip; a second dummy connection terminal spaced apart from the first via and the second signal connection terminal and overlying the first semiconductor chip; and a plurality of second semiconductor chips sequentially stacked on the second dummy connection terminal and the second signal connection terminal, each of the plurality of second semiconductor chips being electrically connected through a second via penetrating each of the plurality of second semiconductor chips, wherein a first area is a sum of an area in which the first signal connection terminal contacts the upper surface of the package substrate, and an area in which the first dummy connection terminal contacts the upper surface of the package substrate, wherein a second area is a sum of an area in which the second signal connection terminal contacts the first semiconductor chip, and an area in which the second dummy connection terminal contacts the first semiconductor chip, and wherein an absolute value of a difference between the first area and the second area is about 0.3 or less of the first area.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 86.0
- Lexical Diversity: 3.2449
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15798655', '12788901', '15786698', '14175162', '13599838']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9189581056258254
- 35 USC 102 Novelty (BERT): 0.4865681042876413
- Combined Prediction Score: 0.8757191054920069
- Mean Citation Score: 233.489502
- Max Citation Score: 247.67482
- Similarity Product: 207.6273343622732

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test