PATENT CLAIM ANALYSIS

Application Number: 16234864
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "336000"]

Abstract:
An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

Claim (Index 27):
The system of  claim 26 , wherein the determined level of current at the drain contact corresponds to a level of current that the lateral diffusion field effect transistor is sinking.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.60938
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15407174', '14574707', '15899911', '15888195', '10951259']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.931185513485692
- 35 USC 102 Novelty (BERT): 0.5567285810758076
- Combined Prediction Score: 0.8937398202447036
- Mean Citation Score: 299.389308
- Max Citation Score: 433.00058
- Similarity Product: 305.925179006492

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test