PATENT CLAIM ANALYSIS

Application Number: 15984426
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "407000"]

Abstract:
A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

Claim (Index 1):
A method for fabricating semiconductor device, comprising:\n forming a metal gate on a substrate and a spacer around the metal gate, wherein the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer; and removing part of the high-k dielectric layer to form an air gap between the work function metal layer and the spacer.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 93.0
- Lexical Diversity: 1.80488
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15172161', '15642324', '15678125', '15643488', '15342098']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91396077577761
- 35 USC 102 Novelty (BERT): 0.4750895499639495
- Combined Prediction Score: 0.870073653196244
- Mean Citation Score: 198.907452
- Max Citation Score: 214.96269
- Similarity Product: 179.58131435080645

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test