PATENT CLAIM ANALYSIS

Application Number: 16252211
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["708", "650000"]

Abstract:
A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. Each iteration includes generating hardware design components for mapping the input range to the target output range using each of a plurality of modulo preserving range reduction methods, synthesizing the generated hardware design components, and selecting one of the generated hardware design components based on the results of the synthesis.

Claim (Index 14):
The engine of  claim 13 , wherein the decision logic is configured to expand the desired input range by setting the desired input range to the maximum input range of the optimum hardware design component and increasing the desired input range to include at least one additional number.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 99.0
- Lexical Diversity: 2.04688
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15363360', '15797020', '16130691', '15163848', '15875176']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4017274985106737
- 35 USC 102 Novelty (BERT): 0.5833332886907234
- Combined Prediction Score: 0.4198880775286787
- Mean Citation Score: 241.027214
- Max Citation Score: 455.11115
- Similarity Product: 411.1444036215484

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test