PATENT CLAIM ANALYSIS

Application Number: 15977617
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "531000"]

Abstract:
Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.

Claim (Index 39):
The system of  claim 37 , further comprising a dielectric layer disposed on the second side of the package substrate, wherein the voltage reference plane is embedded in the dielectric layer.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 93.0
- Lexical Diversity: 2.63333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15766150', '12976903', '14969940', '13743252', '15640406']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9035989700028692
- 35 USC 102 Novelty (BERT): 0.4728696167154075
- Combined Prediction Score: 0.8605260346741231
- Mean Citation Score: 138.21558199999998
- Max Citation Score: 140.54698
- Similarity Product: 97.91498962295292

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test