PATENT CLAIM ANALYSIS

Application Number: 15906109
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.

Claim (Index 1):
A three-dimensional memory device, comprising:\n an alternating stack of insulating layers and electrically conductive layers located over a substrate; an insulating fill material layer and drain select gate electrodes located over the alternating stack; and a group of memory stack structures extending through the alternating stack and arranged as rows of memory stack structures, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, wherein each drain select gate electrode is laterally surrounded by the insulating fill material layer; and wherein the insulating fill material layer comprises: a drain select level isolation structure located between neighboring rows of memory stack structures within the group of memory stack structures, extending along a first horizontal direction, and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions that contact convex vertical sidewalls of the memory stack structures; and a drain select level field dielectric portion adjoined to the drain select level isolation portion and contacting sidewalls of the drain select gate electrodes that extend along a second horizontal direction that is perpendicular to the first horizontal direction; wherein: the insulating fill material layer has a homogeneous dielectric composition throughout; the group of memory stack structures is arranged as multiple rows of memory stack structures such that the rows are spaced apart along the second horizontal direction with a uniform inter-row pitch for an entirety of the group of memory stack structures; each of the select gate electrodes comprises a semiconductor material select gate electrode portion containing a doped semiconductor matrix and a doped semiconductor liner; and the doped semiconductor matrix and the doped semiconductor liner have a doping of a same conductivity type.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.07576
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15888714', '15286063', '15496359', '15296380', '15458200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9389472224264832
- 35 USC 102 Novelty (BERT): 0.5598881973763734
- Combined Prediction Score: 0.9010413199214724
- Mean Citation Score: 410.5057479999999
- Max Citation Score: 440.0459
- Similarity Product: 398.6086511376083

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test