PATENT CLAIM ANALYSIS

Application Number: 15882521
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Claim (Index 11):
The method of  claim 1 , wherein the spacer material layers are formed as sacrificial material layers, and the method further comprises:\n forming first and second backside trenches through the alternating stack, wherein the first backside trench straddles the intermediate region, the first memory array region, and the second memory array region, and the second backside trench straddles the connection region, the first memory array region, and the second memory array region; and removing the sacrificial material layers by introducing an etchant through the pair of backside contact trenches; wherein: the first backside trench has a sidewall that contacts a first subset of sidewalls of the alternating stack in the first memory array region, in the second memory array region, in the first terrace region, and in the second terrace region; and the second backside trench has a sidewall that contacts a second subset of sidewalls of the alternating stack in the first memory array region, in the second memory array region, in the connection region.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.26415
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15611220', '15877219', '15632983', '15488924', '15813579']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.945439430716484
- 35 USC 102 Novelty (BERT): 0.5551145516399515
- Combined Prediction Score: 0.9064069428088308
- Mean Citation Score: 405.285566
- Max Citation Score: 476.46417
- Similarity Product: 287.36647558922056

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test