PATENT CLAIM ANALYSIS

Application Number: 16038977
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "369000"]

Abstract:
A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Claim (Index 14):
A method comprising:\n forming an interlayer dielectric (ILD) over a silicon (Si) fin; forming first and second cavities in the ILD over and perpendicular to the Si fin, the first cavity having a greater width than the second cavity; forming a high-K dielectric layer to a thickness of 5 angstrom (\u212b) to 25 \u212b over the ILD and in the first and second cavities; forming a p-type work function (pWF) metal layer by atomic layer deposition (ALD) to a thickness of 5 \u212b to 50 \u212b in the first and second cavities; recessing the pWF metal layer by chamfering to a first height of 2 nanometers (nm) to 25 nm above the Si fin; forming an n-type work function (nWF) metal layer by ALD in the cavities over the exposed high-K dielectric layer and the pWF metal layer; recessing the nWF metal layer by chamfering to a second height of 4 nm to 30 nm above the Si fin, but covering an edge of the pWF metal layer; forming a barrier metal layer by metal organic chemical vapor deposition (MOCVD), ALD, physical vapor deposition (PVD) to a thickness of 25 \u212b to 75 \u212b over the high-K dielectric layer and the nWF metal layer; filling the first and second cavities with low-resistive metal; removing portions of the low resistive metal fill by chemical mechanical planarization (CMP); and performing reactive ion etching (RIE), recessing the barrier metal layer, the high-K dielectric layer, and the low-resistive metal to a third height 9 nm to 35 nm above the Si fin except for a low-resistive metal to bump or a final gate height extending to 14 nm to 40 nm above the Si fin at a center of each cavity.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 95.0
- Lexical Diversity: 2.92453
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15494119', '14017409', '15591814', '13654987', '16026840']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9226253039742924
- 35 USC 102 Novelty (BERT): 0.5923589224002865
- Combined Prediction Score: 0.8895986658168918
- Mean Citation Score: 336.71742400000005
- Max Citation Score: 585.5005
- Similarity Product: 418.4572675430178

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test