PATENT CLAIM ANALYSIS

Application Number: 15962941
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "145000"]

Abstract:
Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.

Claim (Index 24):
The method of  claim 23 , further comprising:\n comparing the voltage at the first node and a reference voltage associated with the sense component based at least in part on activating the transistor, wherein determining the logic state stored on the memory cell is based at least in part on comparing the voltage at the first node and the reference voltage.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 2.18333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15847583', '15957742', '15619158', '15687019', '15857091']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8049035999239043
- 35 USC 102 Novelty (BERT): 0.4813328346257359
- Combined Prediction Score: 0.7725465233940875
- Mean Citation Score: 249.23625
- Max Citation Score: 255.87912000000003
- Similarity Product: 216.34602278155805

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test