PATENT CLAIM ANALYSIS

Application Number: 15984263
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "314000"]

Abstract:
A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

Claim (Index 9):
The device of  claim 2 , wherein the nanowire includes a channel of a transistor.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 93.0
- Lexical Diversity: 1.6
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15191359', '15482610', '15177231', '14675536', '15939108']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9269881741209206
- 35 USC 102 Novelty (BERT): 0.579356322122648
- Combined Prediction Score: 0.8922249889210934
- Mean Citation Score: 302.166428
- Max Citation Score: 514.55853
- Similarity Product: 386.1065983797884

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test