PATENT CLAIM ANALYSIS

Application Number: 15951052
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["716", "106000"]

Abstract:
According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

Claim (Index 6):
The circuit simulator of  claim 1 , wherein the feature engine comprises a plurality of neurons, each neuron corresponding to one of the transistors of a plurality of representative and critical gates, the plurality of representative and critical gates being selected from among the transistors of the circuit in accordance with a decomposition method.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 91.0
- Lexical Diversity: 2.29787
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15715400', '15928843', '11563259', '15674224', '15174863']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3257246813215084
- 35 USC 102 Novelty (BERT): 0.482624624788445
- Combined Prediction Score: 0.3414146756682021
- Mean Citation Score: 209.84438400000005
- Max Citation Score: 215.11636
- Similarity Product: 150.4292530763841

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test