PATENT CLAIM ANALYSIS

Application Number: 15863754
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "316000"]

Abstract:
Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.

Claim (Index 16):
The method according to  claim 12 , wherein, providing the plurality of bit lines on the semiconductor substrate, the first interlayer dielectric layer, and forming the isolation layer structure comprises:\n providing a base substrate; forming a first interlayer dielectric film on the base substrate and a control gate layer on the first interlayer film; forming a patterned hard mask layer on the floating gate structure; etching the floating gate layer, the first dielectric film and a partial thickness of the base substrate using the patterned mask layer as an etching mask, wherein the etched floating gate layer is used as the floating gate structure, the etched first dielectric film is used as the first dielectric layer, and the etched based substrate is used as the semiconductor substrate and the bit lines; forming an isolation film with a top surface above the top surfaces of the bit lines and covering side surfaces of the bit lines on portions of the semiconductor substrate exposed by the bit lines; and removing a partial thickness of the isolation film to form the isolation structure.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 86.0
- Lexical Diversity: 2.80702
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14494873', '11728504', '11871877', '14825408', '14825506']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9266872126351504
- 35 USC 102 Novelty (BERT): 0.4954108591529887
- Combined Prediction Score: 0.8835595772869345
- Mean Citation Score: 232.541592
- Max Citation Score: 238.10461
- Similarity Product: 176.2317302669513

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test