PATENT CLAIM ANALYSIS

Application Number: 15923864
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "003000"]

Abstract:
Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Claim (Index 4):
A method of forming integrated circuitry, comprising:\n forming a structure having first conductive lines over a dielectric bonding region, having semiconductor material pillars extending upwardly from the first conductive lines, and having second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars; the first conductive lines extending along a first direction, and the second conductive lines extending along a second direction which intersects the first direction; the semiconductor material pillars comprising a first semiconductor material; the structure comprising a second semiconductor material under the dielectric bonding region; the first semiconductor material being monocrystalline silicon; forming memory structures over the semiconductor material pillars; the memory structures being within a memory array; forming third conductive lines over the memory structures; the third conductive lines extending along the first direction; individual memory structures of the memory array being uniquely addressed through combinations including the first, second and third conductive lines; wherein the first conductive lines are incorporated into bitlines or source lines; the third conductive lines are incorporated into the other of bitlines and source lines; and the second conductive lines are incorporated into wordlines; and wherein the memory structures are within a memory array; wherein the wordlines are coupled with wordline driver circuitry; wherein the wordlines comprise a set of even wordline components and a set of odd wordline components, with the even and odd wordline components alternating with one another across the array, and with each of the wordlines comprising one of the even components paired with one of the odd wordline components; wherein the semiconductor material pillars are arranged in rows across the memory array, with each row being between one of the even wordline components and one of the odd wordline components.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 2.86792
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14226643', '15064002', '15650274', '15391604', '13765643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8611800937337845
- 35 USC 102 Novelty (BERT): 0.4773794270311281
- Combined Prediction Score: 0.8228000270635188
- Mean Citation Score: 219.374328
- Max Citation Score: 225.80673
- Similarity Product: 192.19492180783507

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test