PATENT CLAIM ANALYSIS

Application Number: 16145598
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["326", "033000"]

Abstract:
Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

Claim (Index 4):
The circuit of  claim 1 , wherein the bias circuit is to set the calibrated voltage level of the calibrated gate voltage to be greater than, equal to, or less than the supply voltage based on the total leakage current.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 97.0
- Lexical Diversity: 2.53968
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15816766', '14826911', '11304142', '14491017', '15429690']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6713318256176988
- 35 USC 102 Novelty (BERT): 0.4803326343809131
- Combined Prediction Score: 0.6522319064940203
- Mean Citation Score: 163.41504600000005
- Max Citation Score: 171.84325
- Similarity Product: 116.0429815684557

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test