PATENT CLAIM ANALYSIS

Application Number: 16103244
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-06
Patent Classification: ["327", "153000"]

Abstract:
A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.

Claim (Index 5):
The memory device of  claim 4 , wherein the delay locked loop generates the first and second codes using a phase difference of the reference clock and the feedback clock.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 96.0
- Lexical Diversity: 2.04255
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15697885', '15599191', '10646718', '14204444', '15812420']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7982790795810882
- 35 USC 102 Novelty (BERT): 0.4803764689967472
- Combined Prediction Score: 0.7664888185226542
- Mean Citation Score: 230.135868
- Max Citation Score: 240.78232000000003
- Similarity Product: 205.0054728825617

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test