PATENT CLAIM ANALYSIS

Application Number: 15906355
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["257", "296000"]

Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

Claim (Index 3):
The vertical memory cell array of  claim 2 , wherein the metal layer and the dielectric layer are vertically recessed to below a top surface of the plurality of vertical nanowires such that they are electrically isolated from the silicide.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 88.0
- Lexical Diversity: 2.43284
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15078112', '14495639', '15399064', '15671632', '15092986']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9194450057846096
- 35 USC 102 Novelty (BERT): 0.520902893755712
- Combined Prediction Score: 0.8795907945817198
- Mean Citation Score: 211.357314
- Max Citation Score: 323.24182
- Similarity Product: 248.2476391127753

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test