PATENT CLAIM ANALYSIS

Application Number: 15992431
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-10
Patent Classification: ["257", "329000"]

Abstract:
A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

Claim (Index 11):
A vertical transistor device, comprising:\n a vertically-oriented channel semiconductor structure positioned above a semiconductor substrate; a first bottom spacer positioned above the semiconductor substrate and adjacent the vertically-oriented channel semiconductor structure, wherein the first bottom spacer extends around less than an entirety of a perimeter of the vertically-oriented channel semiconductor structure; a gate structure positioned around the vertically-oriented channel semiconductor structure, wherein only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of the perimeter of the vertically-oriented channel semiconductor structure; a protective insulating spacer positioned on at least the gate structure; and a second bottom spacer positioned above the semiconductor substrate, wherein an upper portion of the second bottom spacer contacts the protective insulating spacer such that the second bottom spacer seals the air gap, wherein the second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.77193
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15491420', '15840835', '15281227', '15171795', '15268796']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9208289432042746
- 35 USC 102 Novelty (BERT): 0.5309181153013199
- Combined Prediction Score: 0.881837860413979
- Mean Citation Score: 277.76565800000003
- Max Citation Score: 366.0647
- Similarity Product: 312.09698034812214

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test