PATENT CLAIM ANALYSIS

Application Number: 15921226
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "226000"]

Abstract:
A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

Claim (Index 1):
A semiconductor device comprising:\n a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically couples the first power source line with the second power source line, and electrically decouples the first power source line from the second power source line, in response to a control signal; a second switch which electrically couples the first power source line with the second power source line, and electrically decouples the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line, a plurality of word lines coupled with the memory cells respectively, and a plurality of a pair of bit lines coupled with the memory cells respectively, wherein a peripheral circuit includes an input/output circuit coupled with the plurality of a pair of bit lines and the first power source line, wherein the first and second switches each includes a first MOS transistor having a source coupled to the first power source line, and a second MOS transistor having a source coupled to the first power source line, and wherein a drain of the second MOS transistor is to be coupled to a drain of the first MOS transistor.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 3.69048
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15799073', '15389192', '14866544', '12360521', '13008448']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8248849434833929
- 35 USC 102 Novelty (BERT): 0.5208748890033198
- Combined Prediction Score: 0.7944839380353856
- Mean Citation Score: 302.23640400000005
- Max Citation Score: 363.47604
- Similarity Product: 349.1160073408841

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test