PATENT CLAIM ANALYSIS

Application Number: 15906453
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "148000"]

Abstract:
A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

Claim (Index 8):
A resistance change type memory device, comprising:\n a first bit line and a second bit line extending in parallel along a first direction perpendicular to a surface of a substrate, the first and the second bit lines being spaced from each other in a second direction parallel to the surface of the substrate; a first conductive layer and a second conductive layer extending in parallel along a third direction parallel to the surface of the substrate; a first memory cell at a crossing of the first bit line and the first conductive layer; a second memory cell at a crossing of the second bit line and the second conductive layer; a first selection transistor between the first memory cell and the substrate in the first direction, the first selection transistor having a first channel portion and a first gate portion connected to a first selection gate line; a second selection transistor between the second memory cell and the substrate in the first direction, the second selection transistor having a second channel portion and a second gate portion connected to a second selection gate line; a third selection transistor connected to a dummy selection gate line, the dummy selection gate line being adjacent to the first selection gate line in the second direction and having a third gate portion; and a control circuit configured to apply:\n when the first selection gate line is selected, a first voltage to the first selection gate line, and a second voltage to the dummy selection gate line, the second voltage being smaller than the first voltage, and \n when the second selection gate line is selected, the first voltage to the second selection gate line, the second voltage or a third voltage to the first selection gate line, and the third voltage to the dummy selection gate line, the third voltage being equal to or smaller than the second voltage.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 88.0
- Lexical Diversity: 3.97436
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11436701', '13335095', '13424812', '15693407', '15498029']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7551344467904888
- 35 USC 102 Novelty (BERT): 0.475872920330514
- Combined Prediction Score: 0.7272082941444914
- Mean Citation Score: 183.66675
- Max Citation Score: 197.43713
- Similarity Product: 153.53404183839322

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test