PATENT CLAIM ANALYSIS

Application Number: 15873089
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["710", "267000"]

Abstract:
In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Claim (Index 14):
The at least one computer readable storage medium of  claim 13  further comprising instructions that when executed enable the system to save the portion of the first execution state of the first thread in cache lines which map to a system management random access memory (SRAM) address region.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 1.67949
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14048451', '15270151', '12550737', '15176895', '11066752']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6804856654444217
- 35 USC 102 Novelty (BERT): 0.5026855200581941
- Combined Prediction Score: 0.6627056509057989
- Mean Citation Score: 235.290436
- Max Citation Score: 269.66473
- Similarity Product: 184.41973838916005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test