PATENT CLAIM ANALYSIS

Application Number: 15949940
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["711", "006000"]

Abstract:
An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.

Claim (Index 11):
The apparatus of  claim 7 , wherein receiving the indication that the TLB is to be flushed comprises receiving a flush request message, the flush request message being a first distributed virtual memory (DVM) request message.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 1.77465
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15907593', '15224302', '15417632', '14589693', '12508882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5947038280731516
- 35 USC 102 Novelty (BERT): 0.5327401365831576
- Combined Prediction Score: 0.5885074589241522
- Mean Citation Score: 316.555534
- Max Citation Score: 373.65195
- Similarity Product: 212.0161217237056

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test