PATENT CLAIM ANALYSIS

Application Number: 15949044
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-07
Patent Classification: ["327", "541000"]

Abstract:
A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Claim (Index 14):
The core power detection circuit of  claim 13 , wherein a configuration of the reference power bias circuit makes the DC power leakage current of the first supply voltage less than 2 nA.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 91.0
- Lexical Diversity: 2.78846
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14397750', '10952425', '12154285', '15694847', '12610750']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7846065097512729
- 35 USC 102 Novelty (BERT): 0.469850035470358
- Combined Prediction Score: 0.7531308623231815
- Mean Citation Score: 186.561646
- Max Citation Score: 195.6875
- Similarity Product: 157.50494783744216

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test