PATENT CLAIM ANALYSIS

Application Number: 16427320
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.

Claim (Index 1):
A programmable array logic, comprising:\n a plurality of programmable AND gates; a plurality of first signal lines and a plurality of second signal lines, wherein the second signal lines are respectively coupled to input terminals of programmable AND gates; a plurality of first control units, respectively coupled to the corresponding first signal line and the corresponding second signal line, wherein each of the first control units has at least one first resistive memory, and the first resistive memory is configured to permanently isolate a first signal line coupled thereto from a second signal line coupled thereto, and set a relationship between a voltage level of the corresponding first signal line and a voltage level of the corresponding second signal line; a plurality of programmable OR gates; a plurality of third signal lines and a plurality of fourth signal lines, wherein the third signal lines are respectively coupled to output terminals of the programmable AND gates, and the fourth signal lines are respectively coupled to input terminals of programmable OR gates; and a plurality of second control units, respectively coupled to the corresponding third signal line and the corresponding fourth signal line, wherein each of the second control units has a second resistive memory, and the second resistive memory is configured to permanently isolate a third signal line coupled thereto from a fourth signal line coupled thereto, and set a relationship between a voltage level of the corresponding third signal line and a voltage level of the corresponding fourth signal line.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 100.0
- Lexical Diversity: 3.875
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15610829', '13089835', '12903152', '14677991', '13980529']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.541141023239413
- 35 USC 102 Novelty (BERT): 0.4548510701027277
- Combined Prediction Score: 0.5325120279257445
- Mean Citation Score: 162.524802
- Max Citation Score: 164.9611
- Similarity Product: 130.9648513951838

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test