PATENT CLAIM ANALYSIS

Application Number: 16208660
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "773000"]

Abstract:
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Claim (Index 1):
An apparatus comprising:\n a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the plurality of first dielectric layers over the first substrate, a first surface of the plurality of first dielectric layers facing the first substrate; a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate; a conductive element extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip, the conductive element having a first portion extending through the first substrate, a second portion extending through the plurality of first dielectric layers, and a third portion extending into the plurality of second dielectric layers; and one or more dielectric liners interposed between the conductive element and the first substrate, the one or more dielectric liners not extending between the conductive element and the plurality of first dielectric layers, the conductive element contacting a portion of the first surface of the plurality of first dielectric layers.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 98.0
- Lexical Diversity: 1.98039
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14135153', '15231419', '15076115', '15944069', '14020370']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9143006621663442
- 35 USC 102 Novelty (BERT): 0.4523967473700898
- Combined Prediction Score: 0.8681102706867188
- Mean Citation Score: 173.841856
- Max Citation Score: 192.70398
- Similarity Product: 181.170007915206

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test