PATENT CLAIM ANALYSIS

Application Number: 15748647
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "433000"]

Abstract:
A semiconductor chip package and a semiconductor chip packaging method are provided. The package includes: a semiconductor chip having a functional region, a protective substrate located on one side of the semiconductor chip and covering the functional region, and a support unit located between the protective substrate and the semiconductor chip and enclosing the functional region. The support unit includes an outer support member and an inner support member located inside the outer support member. A receiving cavity is formed between the inner support member, the semiconductor chip and the protective substrate. A hollow cavity is formed between the inner support member, the outer support member, the semiconductor chip and the protective substrate. The inner support member is provided with at least one first ventilating structure, through which the receiving cavity is in communication with the hollow cavity.

Claim (Index 11):
A packaging method for the semiconductor chip package according to  claim 1 , comprising:\n providing a wafer to be packaged, wherein a plurality of semiconductor chips is arranged in an array on the wafer, and each of the plurality of semiconductor chips has a functional region; providing a protective substrate, and forming a plurality of support units arranged in an array on the protective substrate, wherein each of plurality of support units corresponds to one of the semiconductor chips; and aligning and laminating the protective substrate with the wafer, to bond the protective substrate and the wafer together, wherein the support units are arranged between the protective substrate and the wafer, wherein each of the support units comprises an outer support member and an inner support member arranged inside the outer support member, an accommodating cavity is formed among the inner support member, the semiconductor chip and the protective substrate, a hollow cavity is formed among the inner support member, the outer support member, the semiconductor chip and the protective substrate, and the inner support member is provided with at least one first ventilating structure, through which the accommodating cavity is in communication with the hollow cavity.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 2.96078
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15765968', '15765802', '15736253', '15326401', '15748651']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9085653940548536
- 35 USC 102 Novelty (BERT): 0.4769795593711814
- Combined Prediction Score: 0.8654068105864865
- Mean Citation Score: 170.41245
- Max Citation Score: 191.09563
- Similarity Product: 145.4675654168594

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test