PATENT CLAIM ANALYSIS

Application Number: 15778306
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "401000"]

Abstract:
Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as  -shape or  -shape, for example.

Claim (Index 11):
The integrated circuit of  claim 10 , wherein the layer, the lower portion of the gate structure, and the gate dielectric all have the same width between the first and second spacers.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 93.0
- Lexical Diversity: 2.44776
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15778304', '15232300', '15600919', '15790975', '15178229']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.899581666160235
- 35 USC 102 Novelty (BERT): 0.4968950688328097
- Combined Prediction Score: 0.8593130064274925
- Mean Citation Score: 159.405812
- Max Citation Score: 206.99034
- Similarity Product: 149.0250312913441

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test