PATENT CLAIM ANALYSIS

Application Number: 16130691
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["708", "201000"]

Abstract:
Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.

Claim (Index 1):
An apparatus comprising hardware logic arranged to perform modulo calculation with respect to a constant value b, the hardware logic comprising an addition unit arranged to receive an input n-bit value, group the bits of the value received by the unit into a plurality of strings, perform a multiplication of each string by a corresponding coefficient using adders and left-shifting, add together all resulting strings to generate an output value comprising a plurality of number bits and a sign bit and output the output value;\n wherein for at least one string in the addition unit, the corresponding coefficient comprises a selected one of 2 i mod b and(2 i mod b)\u2212b having a smaller absolute magnitude and where i is a bit index of a least significant input bit in the string.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 97.0
- Lexical Diversity: 1.94048
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15163848', '15797020', '10610536', '09854853', '11497496']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3774678547332221
- 35 USC 102 Novelty (BERT): 0.5502623719905998
- Combined Prediction Score: 0.3947473064589599
- Mean Citation Score: 222.492218
- Max Citation Score: 381.745
- Similarity Product: 352.5529531949759

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test