PATENT CLAIM ANALYSIS

Application Number: 15955230
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "774000"]

Abstract:
The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.

Claim (Index 13):
The semiconductor package of  claim 12 , wherein the second connection member includes a first insulating layer, a first redistribution layer in contact with the first connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and\n the first and second redistribution layers are electrically connected to the first and second connection pads at least through the redistribution layer of the first connection member.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 1.68889
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15666266', '15946109', '15297831', '15689861', '15944321']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9482097735275096
- 35 USC 102 Novelty (BERT): 0.546396481631458
- Combined Prediction Score: 0.9080284443379044
- Mean Citation Score: 388.701522
- Max Citation Score: 399.79132
- Similarity Product: 376.6073202173304

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test