PATENT CLAIM ANALYSIS

Application Number: 15913819
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["716", "121000"]

Abstract:
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Claim (Index 1):
A method for configuring a semiconductor chip, comprising:\n placing a first cell and a second cell in a side-by-side manner, each of the first cell and the second cell including linear-shaped conductive structures formed in a first chip level and linear-shaped conductive structures formed in a second chip level, the second chip level positioned above the first chip level, the linear-shaped conductive structures formed in the first chip level oriented to extend lengthwise in a first direction, the linear-shaped conductive structures formed in the second chip level oriented to extend lengthwise in the first direction, wherein the linear-shaped conductive structures in the first chip level are positioned along virtual lines of a first virtual grate, and wherein the linear-shaped conductive structures in the second chip level are positioned along virtual lines of a second virtual grate, wherein virtual lines of the first virtual grate extend in the first direction and are separated by a first pitch, and wherein virtual lines of the second virtual grate extend in the first direction are separated by a second pitch, wherein the first pitch and the second pitch are related by a factor that is a ratio of integers, and wherein the first virtual grate and the second virtual grate are positioned relative to each other such that some virtual lines of the second virtual grate periodically overlap some virtual lines of the first virtual grate, wherein a virtual line of the first virtual grate is positioned in the first chip level of the second cell at a first index distance from a boundary of the second cell that is positioned next to the first cell, the first index distance defined to provide for continuation of the first virtual grate in accordance with the first pitch from the first chip level of the first cell into the first chip level of the second cell, and wherein a virtual line of the second virtual grate is positioned in the second chip level of the second cell at a second index distance from the boundary of the second cell that is positioned next to the first cell, the second index distance defined to provide for continuation of the second virtual grate in accordance with the second pitch from the second chip level of the first cell into the second chip level of the second cell.

Metadata:
- Claim Count in Document: 58.0
- Percentile: 90.0
- Lexical Diversity: 2.5283
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12497052', '14605946', '13540529', '15243748', '14040590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4394360573389352
- 35 USC 102 Novelty (BERT): 0.5296451655740575
- Combined Prediction Score: 0.4484569681624474
- Mean Citation Score: 387.149236
- Max Citation Score: 401.93552
- Similarity Product: 376.9242501282024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test