PATENT CLAIM ANALYSIS

Application Number: 15898752
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["712", "209000"]

Abstract:
A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Claim (Index 3):
The method of  claim 2  wherein said setting of the first bit is performed prior to powering the processor.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 88.0
- Lexical Diversity: 1.65278
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12464027', '15012084', '13874878', '11567290', '13874838']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5901008486338732
- 35 USC 102 Novelty (BERT): 0.5113882343748464
- Combined Prediction Score: 0.5822295872079706
- Mean Citation Score: 237.740836
- Max Citation Score: 311.8705
- Similarity Product: 260.2804556592107

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test