PATENT CLAIM ANALYSIS

Application Number: 15911438
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "185290"]

Abstract:
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

Claim (Index 10):
A semiconductor memory device comprising:\n a substrate, a first well of a first conductively type being formed in the substrate, a second well of a second conductively type being formed in the first well; a first bit line; a second bit line; a sense amplifier; a first bit line select transistor, a first end of which is connected to the first bit line, and a second end of which is connected to the sense amplifier; a second bit line select transistor, a first end of which is connected to the second bit line, and a second end of which is connected to the sense amplifier; a third bit line select transistor, a first end of which is connected to the first bit line, and a second end of which is connected to a first node; a fourth bit line select transistor, a first end of which is connected to the second bit line, and a second end of which is connected to the first node; a first memory string including a plurality of series-connected first memory cells of the first conductivity type, a first end of which is connected to the first bit line, and a second end of which is connected to a first source line; a second memory string including a plurality of series-connected second memory cells of the first conductivity type, a first end of which is connected to the second bit line, and a second end of which is connected to a second source line, wherein the first and second memory cells and the first to fourth bit line select transistors are formed in the second well.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.94595
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15459516', '12817697', '14812771', '13608713', '11836378']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8526910199540264
- 35 USC 102 Novelty (BERT): 0.577165255716204
- Combined Prediction Score: 0.8251384435302442
- Mean Citation Score: 452.306852
- Max Citation Score: 504.29395
- Similarity Product: 446.2622675308704

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test