PATENT CLAIM ANALYSIS

Application Number: 16128161
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "149000"]

Abstract:
The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.

Claim (Index 5):
The memory device of  claim 1 , further comprising:\n a second parity memory IC coupled to the write logic circuit and to the read logic circuit, wherein the parity memory is configured to selectively operate as one of the group comprising: a parity memory and a data memory.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 97.0
- Lexical Diversity: 1.39286
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15713439', '15340883', '13732783', '15851197', '10632199']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8024812023953698
- 35 USC 102 Novelty (BERT): 0.5567420869686169
- Combined Prediction Score: 0.7779072908526945
- Mean Citation Score: 286.179726
- Max Citation Score: 455.60583
- Similarity Product: 368.95835855990407

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test