PATENT CLAIM ANALYSIS

Application Number: 16132790
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-12
Patent Classification: ["327", "011000"]

Abstract:
A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected. The reset FET is coupled to return the input to the first binary value responsive to detection of a short

Claim (Index 15):
The circuit as recited in  claim 14  further comprising a feedback circuit that comprises a first resistor coupled in series with a second resistor between the second node and the third node, a point between the first and second resistors being coupled to provide a second input for the driver circuit.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.47541
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13946345', '10825481', '11422926', '14087246', '13754543']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7401709881321322
- 35 USC 102 Novelty (BERT): 0.5022192519576715
- Combined Prediction Score: 0.7163758145146862
- Mean Citation Score: 228.60297200000005
- Max Citation Score: 239.31808
- Similarity Product: 162.82891530990602

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test