PATENT CLAIM ANALYSIS

Application Number: 15996816
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-08
Patent Classification: ["257", "072000"]

Abstract:
The present disclosure provides an array substrate and a display panel containing the array substrate. The array substrate includes a plurality of pixel regions, and pixel electrodes and thin film transistors one-to-one corresponding thereto. Each pixel electrode includes a pixel sub-electrode and an electrode connecting structure disposed in a corresponding pixel region, and a drain electrode of each thin film transistor is electrically connected to a corresponding pixel sub-electrode. The plurality of pixel regions includes at least one first-color pixel region and at least one second-color pixel region alternately arranged along a first direction and at least one third-color pixel region and at least one highlight pixel region alternately arranged along a first direction. A drain electrode is electrically connected to a pixel sub-electrode disposed in one of the at least one third-color pixel region is disposed in a highlight pixel region adjacent to the third-color pixel region.

Claim (Index 14):
A display panel, comprising an array substrate, wherein the array substrate comprises:\n a plurality of gate lines arranged along a first direction; a plurality of data lines arranged along a second direction, wherein the plurality of gate lines intersects the plurality of data lines to define a plurality of pixel regions; a plurality of pixel electrodes, each comprising a pixel sub-electrode and an electrode connecting structure connected to the pixel electrode, wherein the plurality of pixel electrodes corresponds to the plurality of pixel regions in one-to-one correspondence, such that each pixel sub-electrode is disposed in a corresponding pixel region of the plurality of pixel regions; and a plurality of thin film transistors, wherein the plurality of thin film transistors corresponds to the plurality of pixel electrodes in one-to-one correspondence, and a drain electrode of each of the plurality of thin film transistors is electrically connected to a pixel sub-electrode of a corresponding pixel electrode of the plurality of pixel electrodes through a first through-hole and an electrode connecting structure of a corresponding pixel electrode of the plurality of pixel electrodes, wherein the plurality of pixel regions comprise at least one first-color pixel region, at least one second-color pixel region, at least one third-color pixel region, and at least one highlight pixel region; the at least one first-color pixel region and the at least one second-color pixel region are alternately arranged along the first direction, the at least one third-color pixel region and the at least one highlight pixel region are alternately arranged along the first direction; the at least one first-color pixel region and the at least one second-color pixel region have a same area, and the at least one third-color pixel region and the at least one highlight pixel region have a same area; both the area of the highlight pixel region and the area of the third-color pixel region are smaller than both the area of the first-color pixel region and the area of the second-color pixel region, wherein a drain electrode, which is electrically connected to a pixel sub-electrode disposed in one third-color pixel region of the at least one third-color pixel region, is disposed in a highlight pixel region adjacent to the one third-color pixel region.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.76786
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15508796', '15326572', '13343351', '10731950', '15274216']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9170902490636336
- 35 USC 102 Novelty (BERT): 0.4775148305106724
- Combined Prediction Score: 0.8731327072083374
- Mean Citation Score: 214.05792
- Max Citation Score: 219.09062000000003
- Similarity Product: 180.76664394065853

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test