PATENT CLAIM ANALYSIS

Application Number: 16113443
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "076000"]

Abstract:
The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Claim (Index 13):
A method of manufacturing a high electron mobility transistor (HEMT), comprising:\n providing a substrate; epitaxially growing a first III-V compound layer over the substrate; epitaxially growing a second III-V compound layer on the first III-V compound layer; epitaxially growing a third III-V compound layer on the second III-V compound layer; forming a source region on the third III-V compound layer; forming a drain region on the third III-V compound layer; depositing a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; forming a gate region on the first dielectric layer, wherein the third III-V compound layer is free from overlapping the first dielectric layer from a top view perspective, the third III-V compound layer is in direct contact with the second III-V compound layer, and a percentage of aluminum (Al) of the third III-V compound layer is greater than that of the second III-V compound layer;\n the third III-V compound layer comprises laterally separated first portion and second portions arranged on a first side and a second side of the gate region, respectively, \n the source region and the drain region reside on the first side and the second side of the gate region, respectively, \n a side wall of the first portion of the third III-V compound layer and a first side wall of the first dielectric layer are laterally separated from each other by a first distance, \n a side wall of the second portion of the third III-V compound layer and a second side wall of first dielectric layer are laterally separated from each other by a second distance, \n the first side wall and the second side wall of the first dielectric layer are arranged on the first side and the second side of the gate region, respectively, \n the first distance is smaller than the second distance.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.69444
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15017234', '13774614', '13777701', '14515392', '15377622']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9130132705567232
- 35 USC 102 Novelty (BERT): 0.4736917043335911
- Combined Prediction Score: 0.86908111393441
- Mean Citation Score: 194.722876
- Max Citation Score: 220.77654
- Similarity Product: 191.36388287989857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test