PATENT CLAIM ANALYSIS

Application Number: 15862397
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "185130"]

Abstract:
A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

Claim (Index 13):
The method according to  claim 7 , wherein the first and second dividing capacitors are parasitic capacitors associated with the first bitline and where in the third and fourth dividing capacitors are parasitic capacitors associated with the second bitline.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 2.72414
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15275362', '15212211', '13746653', '15475609', '12883072']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8138096954572076
- 35 USC 102 Novelty (BERT): 0.5303649610103799
- Combined Prediction Score: 0.7854652220125249
- Mean Citation Score: 253.401934
- Max Citation Score: 376.0495
- Similarity Product: 360.88499538418654

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test