PATENT CLAIM ANALYSIS

Application Number: 15995896
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "401000"]

Abstract:
Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

Claim (Index 9):
The device of  claim 8 , wherein the at least one pillar is positioned parallel to the at least two fins.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 94.0
- Lexical Diversity: 2.31746
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15248889', '14616226', '15443522', '14740872', '14681428']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9231239204741344
- 35 USC 102 Novelty (BERT): 0.5220658907591252
- Combined Prediction Score: 0.8830181175026335
- Mean Citation Score: 222.60483000000005
- Max Citation Score: 312.0301
- Similarity Product: 214.27184657905104

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test