PATENT CLAIM ANALYSIS

Application Number: 15778304
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "401000"]

Abstract:
Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape,  -shape,  -shape, ⊥-shape, L-shape, or J-shape, for example.

Claim (Index 6):
The integrated circuit of claim  54 , wherein the third and fourth spacers includes an air gap.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 2.55224
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15778306', '15949634', '15178229', '12827936', '15774064']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9120485972122444
- 35 USC 102 Novelty (BERT): 0.5044618254388186
- Combined Prediction Score: 0.871289920034902
- Mean Citation Score: 150.736468
- Max Citation Score: 218.00816
- Similarity Product: 136.48486519376758

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test