PATENT CLAIM ANALYSIS

Application Number: 15968835
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "043000"]

Abstract:
The present disclosure provides an array substrate, a fabricating method thereof, and a display device. The array substrate includes a base substrate which has a first region and a second region respectively provided with a first transistor and a second transistor. The first transistor has a first active layer of low-temperature polysilicon, and the second transistor has a second active layer of metal oxide semiconductor. The first active layer, an interlayer dielectric layer and the second active layer are sequentially disposed on the base substrate, and a barrier layer is disposed between the interlayer dielectric layer and the second active layer.

Claim (Index 5):
The array substrate according to  claim 1 , wherein the first transistor is of a top-gate structure.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.44444
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16302850', '14422343', '15544023', '13165854', '16080207']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.934937400797638
- 35 USC 102 Novelty (BERT): 0.502855795200944
- Combined Prediction Score: 0.8917292402379685
- Mean Citation Score: 252.449268
- Max Citation Score: 255.57979
- Similarity Product: 182.8383949028504

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test