PATENT CLAIM ANALYSIS

Application Number: 15871919
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "401000"]

Abstract:
Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Claim (Index 2):
The semiconductor arrangement of  claim 1 , wherein the first region and the second region of the first ILD layer are disposed within an overlay region of the semiconductor arrangement.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.59375
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14920923', '14014479', '14865179', '14604885', '15345928']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.915423530776375
- 35 USC 102 Novelty (BERT): 0.4864307715309647
- Combined Prediction Score: 0.8725242548518339
- Mean Citation Score: 161.323262
- Max Citation Score: 214.58553
- Similarity Product: 164.3374135800952

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test