PATENT CLAIM ANALYSIS

Application Number: 15909261
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "154000"]

Abstract:
Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

Claim (Index 3):
The memory circuit of  claim 2 , wherein the initial period expires prior to a logic state flipping time of the memory cell and the application of the under voltage level expires after the logic state flipping time.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.1194
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15447853', '13279375', '15214253', '13610859', '15629489']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8126461335497741
- 35 USC 102 Novelty (BERT): 0.5375067473781565
- Combined Prediction Score: 0.7851321949326124
- Mean Citation Score: 247.64839600000005
- Max Citation Score: 392.37097
- Similarity Product: 326.24848411062834

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test