PATENT CLAIM ANALYSIS

Application Number: 16236892
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-08
Patent Classification: ["710", "313000"]

Abstract:
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Claim (Index 12):
The system of  claim 10 , wherein the memory controller comprises a field programmable gate array (FPGA).

Metadata:
- Claim Count in Document: 4.0
- Percentile: 98.0
- Lexical Diversity: 2.37778
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15071072', '14539641', '15424638', '14656488', '15090818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6495975084668889
- 35 USC 102 Novelty (BERT): 0.5257334071508921
- Combined Prediction Score: 0.6372110983352892
- Mean Citation Score: 215.749338
- Max Citation Score: 321.9290200000001
- Similarity Product: 222.1233092695797

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test