PATENT CLAIM ANALYSIS

Application Number: 15971159
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "316000"]

Abstract:
A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

Claim (Index 3):
The method of  claim 2 , wherein the etching includes an anisotropic etch.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.61702
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15375952', '14669886', '15098425', '15681442', '15947488']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9208315708600524
- 35 USC 102 Novelty (BERT): 0.5429521064353029
- Combined Prediction Score: 0.8830436244175773
- Mean Citation Score: 301.434898
- Max Citation Score: 377.11496
- Similarity Product: 215.7375497548485

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test