PATENT CLAIM ANALYSIS

Application Number: 16275380
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "043000"]

Abstract:
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-1th sub memory cell. [Selected Drawing] FIG.  8

Claim (Index 14):
The semiconductor device according to  claim 12 ,\n wherein the bit line includes a plug.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 99.0
- Lexical Diversity: 2.36
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14637542', '15591150', '14645566', '14578919', '15164133']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9115973316448828
- 35 USC 102 Novelty (BERT): 0.5396469637112762
- Combined Prediction Score: 0.8744022948515222
- Mean Citation Score: 263.110488
- Max Citation Score: 360.37042
- Similarity Product: 245.5054760767269

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test