PATENT CLAIM ANALYSIS

Application Number: 16004864
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "208000"]

Abstract:
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.

Claim (Index 35):
The method of claim  14 , wherein the method comprises using a reduced instructions set computer (RISC) type controller on the logic die as the control logic to cause the logical operations to be performed on the sensing circuitry.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 94.0
- Lexical Diversity: 2.45098
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15066831', '15693390', '15077318', '15077171', '15669590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8448958923281078
- 35 USC 102 Novelty (BERT): 0.518625129181595
- Combined Prediction Score: 0.8122688160134565
- Mean Citation Score: 297.4536839999999
- Max Citation Score: 342.64056
- Similarity Product: 240.2141837107372

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test