PATENT CLAIM ANALYSIS

Application Number: 15938860
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "329000"]

Abstract:
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Claim (Index 6):
The method of  claim 3 , wherein a top of the vertical gate of the vertical FET and a top of the planar gate of the planar FET are co-planar.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.38806
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14971105', '15289024', '15274087', '15853071', '15148341']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9322850865295476
- 35 USC 102 Novelty (BERT): 0.5224505208490783
- Combined Prediction Score: 0.8913016299615008
- Mean Citation Score: 245.27101
- Max Citation Score: 302.51868
- Similarity Product: 182.570314480834

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test