PATENT CLAIM ANALYSIS

Application Number: 16197871
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "189050"]

Abstract:
A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

Claim (Index 7):
The apparatus of  claim 5 , wherein the interface circuitry is configured to output the gated data in response to a second rising edge of the inverted clock signal.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 98.0
- Lexical Diversity: 2.97619
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15652986', '09938206', '15850744', '11824440', '15691394']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7711789080367398
- 35 USC 102 Novelty (BERT): 0.5375716600803254
- Combined Prediction Score: 0.7478181832410984
- Mean Citation Score: 219.970498
- Max Citation Score: 376.78958
- Similarity Product: 282.0936981522608

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test