PATENT CLAIM ANALYSIS

Application Number: 15896404
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["438", "300000"]

Abstract:
A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Claim (Index 16):
A method of manufacturing a Fin Field Effect Transistor (FinFET), the method comprising:\n providing a substrate; forming an elevated source and an elevated drain on the substrate; forming a gate oxide layer on the substrate; forming a first dielectric layer on the gate oxide layer, the first dielectric layer being U-shaped; forming a metal buffer layer on the first dielectric layer, the metal buffer layer being U-shaped; forming a metal gate on the metal buffer layer; forming a first spacer between the elevated source and the first dielectric layer, and a second spacer between the elevated drain and the first dielectric layer; performing a chemical mechanical planarization (CMP) process on an upper surface of the first dielectric layer, an upper surface of the metal buffer layer and an upper surface of the metal gate; removing the first spacer to generate a first opening, and the second spacer to generate a second opening; and filling the first opening to form a second dielectric layer, and the second opening to form a third dielectric layer, wherein\n a first portion of the first dielectric layer is disposed between the metal buffer layer and the second dielectric layer, and blocks the metal buffer layer to contact the second dielectric layer, and \n a second portion of the first dielectric layer is disposed between the metal buffer layer and the third dielectric layer, and blocks the metal buffer layer to contact the third dielectric layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 88.0
- Lexical Diversity: 1.78261
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15299864', '14492595', '11583500', '15274087', '15354212']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8390372425409317
- 35 USC 102 Novelty (BERT): 0.5238103548452961
- Combined Prediction Score: 0.8075145537713682
- Mean Citation Score: 252.74455200000003
- Max Citation Score: 320.2966
- Similarity Product: 249.61486411556007

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test