PATENT CLAIM ANALYSIS

Application Number: 15980486
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["327", "225000"]

Abstract:
In one embodiment, a method includes receiving an output of a first combinational logic at an enable terminal of a first flip-flop. The first combinational logic inputs include a disable first clock signal from a clock switchover circuit and a disable second clock signal from the clock switchover circuit. A set terminal of the first flip-flop receives an output of a logic gate, and the logic gate receives a select signal and a first clock signal. An input terminal of the first flip-flop receives, an output of a second flip-flop. A reset terminal of the first flip-flop receives an output of a second combinational logic. The second combinational logic inputs include a first clock stopped signal, a power-on-reset signal, and the select signal, the first clock stopped signal indicating a stop in the first clock signal. An output terminal of the first flip-flop outputs a modified select signal.

Claim (Index 2):
The apparatus of  claim 1 , wherein the flip-flop is a D flip-flop.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 93.0
- Lexical Diversity: 3.5
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11162160', '15338181', '11744386', '11771998', '14156770']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7650903255736281
- 35 USC 102 Novelty (BERT): 0.5038284144137117
- Combined Prediction Score: 0.7389641344576365
- Mean Citation Score: 233.220924
- Max Citation Score: 235.98343
- Similarity Product: 159.95218500826894

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test