PATENT CLAIM ANALYSIS

Application Number: 16267307
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "737000"]

Abstract:
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Claim (Index 30):
The semiconductor device according to the  claim 19 ,\n wherein the semiconductor device is an LCD driver.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 99.0
- Lexical Diversity: 2.16923
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14953390', '14320686', '14953382', '12239810', '15264588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9491545523362298
- 35 USC 102 Novelty (BERT): 0.5892939399686522
- Combined Prediction Score: 0.913168491099472
- Mean Citation Score: 537.659462
- Max Citation Score: 544.57916
- Similarity Product: 401.7658362105609

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test