PATENT CLAIM ANALYSIS

Application Number: 16026081
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["323", "280000"]

Abstract:
A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V fb . The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor M P  is connected to the output terminal of the error amplifier, the source terminal of the power transistor M P  is connected to an input voltage V IN , and the drain terminal of the power transistor M P  is grounded.

Claim (Index 4):
The ripple pre-amplification based fully integrated low dropout regulator according to  claim 1 , wherein\n the error amplifier comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein a gate terminal of the seventh NMOS transistor and a gate terminal of the eighth NMOS transistor are connected to each other and serve as the negative input terminal of the error amplifier; a width to length ratio of the seventh NMOS transistor and the eighth NMOS transistor is K 2 ; a gate terminal of the sixth NMOS transistor and a gate terminal of the ninth NMOS transistor are connected to each other and serve as a positive input terminal of the error amplifier; a width to length ratio of the sixth NMOS transistor and the ninth NMOS transistor is K 2 ; a gate terminal and a drain terminal of the tenth PMOS transistor are short-circuited and connected to a gate terminal of the seventh PMOS transistor and a drain terminal of the eleventh NMOS transistor; a gate terminal of the tenth NMOS transistor is connected to a gate terminal of the eleventh NMOS transistor and drain terminals of the seventh NMOS transistor and the eighth PMOS transistor; a drain terminal of the tenth NMOS transistor is connected to source terminals of the seventh NMOS transistor and the ninth NMOS transistor; a gate terminal of the twelfth NMOS transistor is connected to a gate terminal of the thirteenth NMOS transistor and drain terminals of the sixth NMOS transistor and the ninth PMOS transistor; a drain terminal of the twelfth NMOS transistor is connected to source terminals of the sixth NMOS transistor and the eighth NMOS transistor; a gate terminal of the eighth PMOS transistor and a gate terminal of the ninth PMOS transistor are connected to a bias voltage; a drain terminal of the seventh PMOS transistor and a drain terminal of the thirteenth NMOS transistor are connected to each other and serve as the output terminal of the error amplifier; source terminals of the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are connected to the ground; and source terminals of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor and drain terminals of the eighth NMOS transistor and the ninth NMOS transistor are connected to the input voltage.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 95.0
- Lexical Diversity: 3.41667
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15690290', '15387678', '15509202', '15776780', '11775105']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7980814638809168
- 35 USC 102 Novelty (BERT): 0.5586138739968103
- Combined Prediction Score: 0.7741347048925062
- Mean Citation Score: 378.515386
- Max Citation Score: 461.67987
- Similarity Product: 362.3538495082534

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test