PATENT CLAIM ANALYSIS

Application Number: 15980561
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Claim (Index 9):
The method of  claim 6 , further comprising:\n after the gap fill material layer has been removed, removing one or more metal layers of the gate structures within the at least second channel region.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 93.0
- Lexical Diversity: 2.52542
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15867834', '15964573', '15957317', '15657659', '15422572']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921045911280594
- 35 USC 102 Novelty (BERT): 0.510127598294306
- Combined Prediction Score: 0.8799540799819654
- Mean Citation Score: 256.27591199999995
- Max Citation Score: 271.78363
- Similarity Product: 176.17004510733784

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test