PATENT CLAIM ANALYSIS

Application Number: 15902065
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-11
Patent Classification: ["365", "156000"]

Abstract:
Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Claim (Index 1):
A method for alleviating cell bias, comprising:\n empirically testing for a digital state of a plurality of cells within an array of static random access memory (SRAM) to determine unbalanced cell bias, wherein the SRAM contains a plurality of field-effect transistors (FETs), and wherein the plurality of FETs comprise an inorganic insulator; determining which cells, within the array of SRAM, fail to hold a certain bit pattern, wherein determining cells within the array of SRAM which fail to hold the certain bit pattern, comprises:\n determining that the cells have a fixed bias for the digital state; and \n determining that the cells have a partial bias for the digital state; \n responsive to determining which cells within the array of SRAM fail to hold a certain bit pattern, switching a state of a bit, wherein the bit resides in a negative margin cell among the plurality of cells within the array of SRAM, wherein the bit is either in a zero state or a one state, and the negative margin cell fails to hold the certain bit pattern; responsive to switching the state of the bit, trapping a plurality of charge carriers in the inorganic insulator; responsive to trapping the plurality of charge carriers in the inorganic insulator, balancing a cell bias of the negative margin cell to an improved margin, wherein balancing a cell bias of the negative margin cell to an improved margin, comprises:\n identifying negative margin cells and positive margin cells among the plurality of cells within the array of SRAM utilizing power cycling, wherein:\n the negative margin cells are cells identified as failing to hold a certain bit pattern, \n the positive margin cells are identified as not failing to hold a certain bit pattern, wherein\n the certain bit pattern is an associated threshold for a one state and another associated threshold for a zero state, \n targeting a voltage shift for the negative margin cells, \n responsive to targeting the voltage shift for the negative margin cells, modifying an electric field locally to in turn increase a voltage of a FET within the array of SRAM, \n utilizing an even time bias for the zero state and the one state for balanced cells, \n utilizing an uneven time bias for the zero state and the one state for unbalanced cells, \n noting that a bias of the identified negative margin cell favors the zero state over the one state, and \n noting that a bias of the identified negative margin cell favors the one state over the zero state; \n \n \n responsive to balancing the cell bias of negative margin cell, ceasing bias stressing of the negative margin cell and maintaining balance stressing of the negative margin cell; writing a state into a cell corresponding to cells determined to have the fixed bias or the partial bias for the digital state by at least one of:\n increasing a supply voltage with a balancing state in each cell among the determined cells within the array of SRAM which fail to hold the certain bit pattern; and \n increasing temperature with the balancing state in each cell within the array of SRAM which fail to hold the certain bit pattern; \n responsive to writing the state into the cell corresponding to the cell determined to have the fixed bias or the partial bias for the digital state, implement selective biasing where:\n an upper field effect transistor of a first set of complementary metal oxide semiconductor (CMOS) devices is biased, and \n a lower field effect transistor of a second set of CMOS devices is biased; and \n skewing a bit within a first node to a second node, wherein the second node is contained within a corresponding bias to the first node.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.9
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15589071', '15826990', '14607023', '14590834', '14740209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7738206438707981
- 35 USC 102 Novelty (BERT): 0.505351336544506
- Combined Prediction Score: 0.7469737131381688
- Mean Citation Score: 198.489032
- Max Citation Score: 319.65155
- Similarity Product: 305.18005873455405

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test