PATENT CLAIM ANALYSIS

Application Number: 15891353
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "193000"]

Abstract:
Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.

Claim (Index 8):
The memory device of  claim 7 , wherein the selection circuitry comprises a switch that selectively connects the gating voltage to the gating circuitry.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 88.0
- Lexical Diversity: 2.42623
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15891356', '15880994', '15826404', '15730233', '15826236']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8190014044267253
- 35 USC 102 Novelty (BERT): 0.5078112856991935
- Combined Prediction Score: 0.7878823925539722
- Mean Citation Score: 241.374022
- Max Citation Score: 313.3691
- Similarity Product: 260.7765537419677

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test