PATENT CLAIM ANALYSIS

Application Number: 16051772
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["029", "852000"]

Abstract:
A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.

Claim (Index 2):
The method according to  claim 1  when said multiple layers of said PCB include copper, copper clad core and partially cured dielectric (pre-preg).

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 1.56757
- Patent Class: 29.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12483223', '14205331', '15723086', '12190551', '14205337']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8713048865648818
- 35 USC 102 Novelty (BERT): 0.5015700611489396
- Combined Prediction Score: 0.8343314040232875
- Mean Citation Score: 174.645696
- Max Citation Score: 186.86516
- Similarity Product: 108.7026652303362

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test