PATENT CLAIM ANALYSIS

Application Number: 16290102
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-06
Patent Classification: ["365", "097000"]

Abstract:
A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Claim (Index 5):
A semiconductor device, comprising:\n a plurality of word lines;\n a plurality of bit lines crossing the plurality of word lines, the plurality of bit lines including first bit lines and second bit lines, the second bit lines spaced apart from the first bit lines in a direction of extension of the plurality of word lines; \n a plurality of first memory cells connected between the plurality of word lines and the first bit lines, each of the plurality of first memory cells including a first memory element and a first selection element, the first memory element and the first selection element connected to each other; and \n a plurality of second memory cells connected between the plurality of word lines and the second bit lines, each of the plurality of second memory cells including a second memory element and a second selection element, the second memory element and the second selection element connected to each other, \n wherein the first memory element includes a first magnetic tunnel junction, and the second memory element includes a second magnetic tunnel junction, each of the first and second magnetic tunnel junctions including a pinned layer, a free layer, and a tunnel barrier layer between the pinned layer and the free layer, \n wherein the tunnel barrier layers of a first portion of the second magnetic tunnel junctions have an irreversible resistance state, \n the device further comprising: \n a first peripheral circuit electrically connected to the plurality of first memory cells through the first bit lines; and \n a second peripheral circuit electrically connected to the plurality of second memory cells through the second bit lines, \n wherein the second peripheral circuit includes at least one second peripheral transistor configured to operate according to a voltage higher than a first peripheral transistor of the first peripheral circuit, \n wherein the first peripheral transistor includes a first peripheral gate dielectric layer and a first peripheral gate electrode, and the at least one second peripheral transistor includes a second peripheral gate dielectric layer and a second peripheral gate electrode, and \n wherein the second peripheral gate electrode has a width greater than a width of the first peripheral gate electrode.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 99.0
- Lexical Diversity: 2.14706
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15293782', '14526489', '15078182', '15227334', '14639183']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7947946787794771
- 35 USC 102 Novelty (BERT): 0.5440282850989243
- Combined Prediction Score: 0.7697180394114218
- Mean Citation Score: 276.65533400000004
- Max Citation Score: 405.81754
- Similarity Product: 395.97413016384127

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test