PATENT CLAIM ANALYSIS

Application Number: 16412210
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "382000"]

Abstract:
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Claim (Index 3):
The integrated circuit structure of  claim 2 , wherein the first conductive contact structure, the second conductive contact structure, and the third conductive contact structure have substantially a same length along the second direction.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 100.0
- Lexical Diversity: 2.79167
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15624036', '13995678', '14827510', '14951726', '14854590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.934373902968172
- 35 USC 102 Novelty (BERT): 0.5518607474230468
- Combined Prediction Score: 0.8961225874136596
- Mean Citation Score: 332.48802
- Max Citation Score: 452.26398
- Similarity Product: 284.75728464105606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test