PATENT CLAIM ANALYSIS

Application Number: 15885452
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["365", "189011"]

Abstract:
A semiconductor memory apparatus may include a first memory apparatus and a second memory apparatus, and may perform various operation modes. The first and second memory apparatuses may independently perform a write operation and a read operation in a first operation mode. The first memory apparatus may perform a write operation and a read operation and the second memory apparatus may perform a write operation in a second operation mode. The second memory apparatus may perform a write operation and a read operation in a third operation mode.

Claim (Index 9):
The semiconductor memory apparatus according to  claim 8 , wherein the second command circuit comprises:\n a control circuit configured to generate a chip select control signal based on the command signal; a second chip select signal generator configured to generate the second internal chip select signal from the first chip select signal and the second chip select signal based on the chip select control signal; and a command decoder configured to generate the internal command signal based on the second internal chip select signal and the command signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 3.72
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13942141', '13189969', '12170221', '15696865', '15662525']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8022564851013969
- 35 USC 102 Novelty (BERT): 0.4662276185997241
- Combined Prediction Score: 0.7686535984512296
- Mean Citation Score: 168.991268
- Max Citation Score: 171.73023999999995
- Similarity Product: 129.86095665689464

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test