PATENT CLAIM ANALYSIS

Application Number: 16000448
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["327", "298000"]

Abstract:
In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Claim (Index 14):
The digitally controlled delay line of  claim 12 , wherein the first control circuit generates the selection code using the input code when the input code is not less than the previous code by an amount greater than or equal to the threshold value.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13051204', '15234954', '15602239', '15198564', '12491567']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7382497587348317
- 35 USC 102 Novelty (BERT): 0.4743140846058657
- Combined Prediction Score: 0.7118561913219351
- Mean Citation Score: 155.301334
- Max Citation Score: 173.3582
- Similarity Product: 134.2034756757021

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test