PATENT CLAIM ANALYSIS

Application Number: 15760681
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "154000"]

Abstract:
The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell ( 100 ). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Claim (Index 12):
The memory according to  claim 1 , wherein each of the WBLs of the memory is coupled to a further boost circuit arranged to increase a voltage level of the WBL to a voltage level being higher than a level of the first voltage.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 1.4
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15096563', '14976065', '15096434', '13539577', '11614231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8187689498508329
- 35 USC 102 Novelty (BERT): 0.5013447564330752
- Combined Prediction Score: 0.7870265305090571
- Mean Citation Score: 231.226824
- Max Citation Score: 238.97003
- Similarity Product: 145.97012254660905

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test