PATENT CLAIM ANALYSIS

Application Number: 16236431
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["327", "541000"]

Abstract:
Biasing architectures and methods for lower loss switches. In some embodiments, a switching device can include a series arm having transistors implemented in a stack configuration between first and second nodes. The switching device can further include a shunt arm having transistors implemented in a stack configuration between the first node and a ground node. The switching device can further include a bias architecture having a series arm bias circuit and a shunt arm bias circuit. The series arm bias circuit can be configured to bias the transistors of the series arm and include a gate-gate resistor that couples each pair of neighboring transistors. The shunt arm bias circuit can be configured to bias the transistors of the shunt arm and include a gate-gate resistor that couples each pair of neighboring transistors.

Claim (Index 13):
A switching die comprising:\n a semiconductor substrate; and a switch implemented on the semiconductor substrate, and including a series arm having a plurality of transistors implemented in a stack configuration between a first node and a second node, each transistor having a source, a drain and a gate, the transistors configured to be in an ON state or an OFF state to respectively allow or inhibit passage of a signal between the first and second nodes, the switch further including a shunt arm having a plurality of transistors implemented in a stack configuration between the first node and a ground node, each transistor having a source, a drain and a gate, the transistors of the shunt arm configured to be in an ON state when the transistors of the series arm are in the OFF state, or an OFF state when the transistors of the series arm are in the ON state, the switch further including a bias architecture having a series arm bias circuit and a shunt arm bias circuit, the series arm bias circuit configured to bias the transistors of the series arm and including a gate-gate resistor that couples each pair of neighboring transistors, the shunt arm bias circuit configured to bias the transistors of the shunt arm and including a gate-gate resistor that couples each pair of neighboring transistors.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.78
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15497120', '15002170', '14737455', '15851810', '14737453']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7975663231995019
- 35 USC 102 Novelty (BERT): 0.5035284088455287
- Combined Prediction Score: 0.7681625317641045
- Mean Citation Score: 292.40480799999995
- Max Citation Score: 302.58984
- Similarity Product: 244.02195607761385

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test