PATENT CLAIM ANALYSIS

Application Number: 16243249
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["345", "209000"]

Abstract:
A differential amplifier circuit includes a differential input stage, a first current mirror, a second current mirror, a first current source circuit, and a second current source circuit. The first current source circuit has a first transistor of a first conductivity type with a control terminal supplied with a first bias voltage, and a second transistor of a second conductivity type with a control terminal supplied with a second bias voltage. An output amplifier circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. A control circuit has a fifth transistor of the first conductivity type with a first terminal connected to a connection point between the other end of the second current source circuit and the control terminal of the fourth transistor in the output amplifier circuit, with a second terminal connected to an output node of the second current mirror, and with a control terminal receiving the first bias voltage.

Claim (Index 11):
An output circuit for successively outputting alternate ones of positive and negative voltages comprising:\n a differential amplifier circuit for amplifying a difference between an input signal and an output signal; an output amplifier circuit for generating the output signal; a control circuit for controlling the output signal; an input terminal for receiving the input signal; an output terminal for output of the output signal; a first power supply terminal supplied with a first power supply voltage; a second power supply terminal supplied with a second power supply voltage; and a third power supply terminal supplied with a third power supply voltage having a voltage value between the first power supply voltage and the second power supply voltage, wherein the differential amplifier circuit includes:\n a differential input stage for producing differential currents corresponding to a difference between the input signal and the output signal; \n a first current mirror connected to the first power supply terminal and including a transistor pair of a first conductivity type; \n a second current mirror connected to the second power supply terminal and including a transistor pair of a second conductivity type having a conductivity type opposite to the first conductivity type; \n a first current source circuit connected between an input node of the first current mirror and an input node of the second current mirror; and \n a second current source circuit connected between an output node of the first current mirror and an output node of the second current mirror, at least one of the first and second current mirrors receiving the differential currents of the differential input stage, \n the first current source circuit includes:\n a first transistor of the first conductivity type with a control terminal for receiving a first bias voltage; and \n a second transistor of the second conductivity type that is connected in series to the first transistor and has a control terminal for receiving a second bias voltage, \n the output amplifier circuit includes:\n a third transistor of the first conductivity type connected between the third power supply terminal and the output terminal and having a control terminal connected to one end of the second current source circuit; and \n a fourth transistor of the second conductivity type connected between the second power supply terminal and the output terminal and having a control terminal connected to a connection point between the output node of the second current mirror and the other end of the second current source circuit, and \n the control circuit includes a fifth transistor of the second conductivity type with a first terminal connected to a connection point between the one end of the second current source circuit and the control terminal of the third transistor in the output amplifier circuit and with a second terminal connected to the output node of the first current mirror and with a control terminal receiving the second bias voltage.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 3.82222
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15818628', '13204403', '13317858', '14664076', '11648530']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6612111936074128
- 35 USC 102 Novelty (BERT): 0.5758834622258224
- Combined Prediction Score: 0.6526784204692537
- Mean Citation Score: 374.23268
- Max Citation Score: 450.50867
- Similarity Product: 442.7099784882045

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test