PATENT CLAIM ANALYSIS

Application Number: 15863988
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "072000"]

Abstract:
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The method involves a reduced number of masks.

Claim (Index 1):
A method for producing a low temperature poly-silicon (LTPS) array substrate, comprising:\n forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a buffer layer and a negative photoresist layer on the substrate one by one; exposing one side of the substrate that is opposite to the gate to remove a portion of the negative photoresist layer that is located exactly above the gate; removing a first portion of the buffer layer located above the gate such that a second portion of the buffer layer that is disposed on the substrate and away from the gate is preserved on substrate and the gate is exposed outside the buffer layer; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane; exposing one side of the substrate that is opposite to the gate to form a polycrystalline silicon layer through a process comprising the following sub-steps:\n (1) exposing one side of the substrate that is opposite to the gate to remove a first portion of the positive photoresist layer such that a second portion of the positive photoresist layer that is located in a first section corresponding in position to the gate is preserved, \n (2) injecting impurity ions into a portion of the semiconductor layer outside the first section, and \n (3) completely removing the positive photoresist layer; \n forming a second insulating layer on the substrate of the polycrystalline silicon layer such that first contact holes are formed in the second insulating layer to respectively expose two opposite ends of the polycrystalline silicon layer; and forming a source and a drain of the TFT on the second insulating layer so that the source and the drain are electrically connected to the polycrystalline silicon layer via the first contact holes, respectively.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.38596
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15863991', '14760750', '15863993', '14762458', '14779089']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9320783251003248
- 35 USC 102 Novelty (BERT): 0.54068613553684
- Combined Prediction Score: 0.8929391061439762
- Mean Citation Score: 353.737566
- Max Citation Score: 392.1625
- Similarity Product: 358.0395190738142

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test