PATENT CLAIM ANALYSIS

Application Number: 15951621
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["438", "199000"]

Abstract:
At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

Claim (Index 6):
The method of  claim 1 , wherein performing at least one subsequent processing step comprises:\n removing the first dummy gate; replacing a void resulting from the removing of the first dummy gate with a dielectric material; and performing a replacement metal gate process on the second dummy gate.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.95918
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15920303', '15890246', '15673232', '15423326', '15638087']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.882973635040832
- 35 USC 102 Novelty (BERT): 0.5063088343234288
- Combined Prediction Score: 0.8453071549690917
- Mean Citation Score: 269.484058
- Max Citation Score: 281.62073
- Similarity Product: 217.2007964216161

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test