PATENT CLAIM ANALYSIS

Application Number: 15885449
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["365", "154000"]

Abstract:
A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

Claim (Index 1):
A circuit comprising:\n a memory cell array which includes:\n a plurality of memory cells; \n a plurality of word lines coupled to the memory cells, respectively, and \n a plurality of bit lines coupled to the memory cells, \n an address control circuit which includes:\n a first latch circuit into which a first address signal is input and from which a first output signal is output; \n a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; \n a second latch circuit into which the second output signal is input and from which a third output signal is output; \n a decode circuit which decodes the third output signal and outputs a fourth output signal; and \n a word line drive circuit which drives and thereby activates one of the word lines selected based on the fourth output signal for reading data stored in one of the memory cells or for writing data to one of the memory cells, \n wherein the word line drive circuit drives the selected one of the word lines at a timing which is based on a word line control signal, and wherein the second latch circuit latches the second output signal at the timing which is based on the word line control signal.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 3.26531
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15613882', '15281947', '15606562', '11282333', '11338670']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.802619172567092
- 35 USC 102 Novelty (BERT): 0.4812655333593156
- Combined Prediction Score: 0.7704838086463144
- Mean Citation Score: 228.15422200000003
- Max Citation Score: 240.236
- Similarity Product: 189.4673994731903

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test