PATENT CLAIM ANALYSIS

Application Number: 16029840
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["710", "305000"]

Abstract:
A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Claim (Index 3):
The switch controller of  claim 1 , wherein:\n the first signaling protocol includes a non-return-to zero (NRZ) protocol; and the backplane signaling protocol includes a pulse-amplitude modulation protocol (PAM4).

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 1.58209
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15082204', '13628067', '13739782', '14614829', '12381205']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6968162087393254
- 35 USC 102 Novelty (BERT): 0.5965974079708578
- Combined Prediction Score: 0.6867943286624787
- Mean Citation Score: 356.912026
- Max Citation Score: 556.6637599999998
- Similarity Product: 431.1828724627875

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test