PATENT CLAIM ANALYSIS

Application Number: 15918536
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["711", "154000"]

Abstract:
A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Claim (Index 3):
The semiconductor memory apparatus according to  claim 1 , wherein the data control circuit comprises:\n a control signal generator configured to generate a first bit select signal and a second bit select signal based on the operation control signal and an operation setting signal; and a majority determiner configured to generate the data control flag signal by determining levels of all bits or some bits of the data based on the first and second bit select signals.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 90.0
- Lexical Diversity: 2.83871
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15706218', '15017994', '12232719', '15597795', '12459106']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5390052585225249
- 35 USC 102 Novelty (BERT): 0.4672613589189661
- Combined Prediction Score: 0.5318308685621691
- Mean Citation Score: 177.27008800000004
- Max Citation Score: 182.9408
- Similarity Product: 147.87148815460202

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test