PATENT CLAIM ANALYSIS

Application Number: 15951571
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "774000"]

Abstract:
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and the connection pads of the second semiconductor chip are electrically connected to the redistribution layer of the first interconnection member by wires.

Claim (Index 12):
A fan-out semiconductor package comprising:\n a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a first encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; a second encapsulant encapsulating at least portions of the second semiconductor chip; a backside redistribution layer disposed on the first encapsulant; and a backside via penetrating through the first encapsulant and electrically connecting the backside redistribution layer and the redistribution layer of the first interconnection member to each other, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and the backside redistribution layer includes wire pads connected to the connection pads of the second semiconductor chip by wires and wiring patterns redistributing the connection pads of the second semiconductor chip.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 3.31915
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15437766', '15377402', '15837611', '15468606', '15459322']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9384303194237952
- 35 USC 102 Novelty (BERT): 0.5433738560152641
- Combined Prediction Score: 0.8989246730829421
- Mean Citation Score: 386.940248
- Max Citation Score: 395.08307
- Similarity Product: 381.3502186377944

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test