PATENT CLAIM ANALYSIS

Application Number: 15972949
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "356000"]

Abstract:
A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.

Claim (Index 9):
The semiconductor device as claimed in  claim 8 , wherein the first guard ring and the second guard ring have a plate-shaped structure, excluding a nanowire structure.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 93.0
- Lexical Diversity: 3.29787
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15921643', '13557923', '11624656', '12801076', '14173457']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9286946371182374
- 35 USC 102 Novelty (BERT): 0.505985395498161
- Combined Prediction Score: 0.8864237129562298
- Mean Citation Score: 250.683404
- Max Citation Score: 273.4609
- Similarity Product: 202.0386637105941

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test