PATENT CLAIM ANALYSIS

Application Number: 15903203
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["365", "174000"]

Abstract:
A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU 1  and PU 2 ) transistors, and first and second pull-down (PD 1  and PD 2 ) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU 1  and PU 2 . A second bottom electrode connects bottom SD regions of PD 1  and PD 2 . A first shared contact connects the top SD region of PU 2  to the gate structure of PU 1 . A second shared contact connects the top SD region of PD 1  to the gate structure of PD 2 . A first top electrode is connected to the top SD regions of PG 1 , PU 1  and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG 2 , PU 2  and the first shared contact to define a second storage node of the memory cell.

Claim (Index 10):
A memory cell, comprising:\n a plurality of vertical transistors including first and second pass gate transistors, first and second pull-up transistors, and first and second pull-down transistors, each of said plurality of vertical transistors comprising a pillar of semiconductor material formed above a substrate, a first source/drain region on a lower portion of said pillar, a gate structure disposed around said pillar above said first source/drain region, and a second source/drain region on a top portion of said pillar above said structure; a first bottom electrode defined in said substrate and connecting said source/drain regions of said first and second pull-up transistors; a second bottom electrode defined in said substrate and connecting said source/drain regions of said first and second pull-down transistors; a first routing gate connecting said gate structures of said first pull-up transistor and said first pull-down transistor; a second routing gate connecting said gate structures of said second pull-up transistor and said second pull-down transistor; a third routing gate connected to said gate structure of said second pull-up transistor; a fourth routing gate connected to said gate structure of said first pull-up transistor; a first shared contact connecting said top source/drain region of said second pull-up transistor and said third routing gate; a second shared contact connecting said top source/drain region of said first pull-down transistor to said fourth routing gate; a first top electrode connected to said top source/drain regions of said first pass gate transistor and said first pull-up transistor, and to said second shared contact to define a first storage node of said memory cell; and a second top electrode connected to said top source/drain regions of said second pass gate transistor and said second pull-down transistor, and to said first shared contact to define a second storage node of said memory cell.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 88.0
- Lexical Diversity: 4.25581
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15634227', '15654190', '15790035', '12721476', '15804556']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8101657014128877
- 35 USC 102 Novelty (BERT): 0.4963931915328704
- Combined Prediction Score: 0.778788450424886
- Mean Citation Score: 274.47711400000003
- Max Citation Score: 287.63766
- Similarity Product: 235.97822761146423

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test