PATENT CLAIM ANALYSIS

Application Number: 15943466
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "369000"]

Abstract:
In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is formed in the dummy gate layer, and has an etching selectivity with respect to the other portion of the dummy gate layer. Etching masks are formed on portions of the hard mask layer. The hard mask layer and the dummy gate layer are etched to pattern the first doped portion and the other portion of the dummy gate layer into first dummy gates and second dummy gates. The first dummy gates and the second dummy gates have different widths. A dielectric layer is formed to peripherally enclose each of the first dummy gates and each of the second dummy gates. The first dummy gates and the second dummy gates are replaced with first metal gates and second metal gates.

Claim (Index 19):
The integrated circuit of  claim 16 , wherein the first width is in a range of from about 3 nm to about 300 nm and the second width is in the range of from about 3 nm to about 300 nm.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.88889
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14954380', '14083533', '12701698', '12756662', '15484837']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9022232150789964
- 35 USC 102 Novelty (BERT): 0.4942928928182978
- Combined Prediction Score: 0.8614301828529266
- Mean Citation Score: 173.594722
- Max Citation Score: 196.52386
- Similarity Product: 140.43417509731174

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test