PATENT CLAIM ANALYSIS

Application Number: 16015168
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["365", "001000"]

Abstract:
Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is performed on at least one memory cell in a first group of memory cells out of a plurality of groups of memory cells coupled to a line. A first voltage is applied across the first group of memory cells for the operation and a lower second voltage is applied across the other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells. These steps may repeated until the operations covers all the groups.

Claim (Index 1):
In a volatile memory array having i anode lines, j cathode lines, and an array of thyristor memory cells, each memory cell having only one thyristor, the thyristor having a first electrode coupled to an anode line and a second electrode coupled to a cathode line, and in which N thyristor memory cells are connected to a selected anode line, a method of reducing current in the selected anode line to be accessed for an operation comprising:\n (a) dividing the N thyristor memory cells coupled to the selected anode line into M groups each of k thyristor memory cells where k is greater than 1; (b) for a first group of k thyristor memory cells upon at least one of which a desired operation is to be performed, applying a first voltage to cathode lines coupled to the k thyristor memory cells; (c) for all other of the N thyristor memory cells except the first group of k thyristor memory cells, applying a second voltage to cathode lines coupled to all the other N thyristor memory cells, where the second voltage is higher than the first voltage; (d) performing the desired operation on at least one of the k thyristor memory cells; (e) selecting a second group of k thyristor memory cells from the M groups of thyristor memory cells; (f) for the second group of k thyristor memory cells upon at least one of which the desired operation is to be performed, applying the first voltage to cathode lines coupled to the k thyristor memory cells; (g) for all other of the N thyristor memory cells except the second group of k thyristor memory cells, applying the second voltage to cathode lines coupled to all the other N thyristor memory cells; and (h) performing the desired operation on at least one of the second group of k thyristor memory cells.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 94.0
- Lexical Diversity: 2.17544
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14841615', '15426909', '16015156', '16015164', '14841521']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8213532409082402
- 35 USC 102 Novelty (BERT): 0.5796987422392736
- Combined Prediction Score: 0.7971877910413436
- Mean Citation Score: 431.216638
- Max Citation Score: 480.605
- Similarity Product: 454.8016534861923

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test