PATENT CLAIM ANALYSIS

Application Number: 16058687
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2020-02
Patent Classification: ["null", "null"]

Abstract:
Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.

Claim (Index 15):
The system of  claim 8 , further comprising:\n a counter configured to receive a first external clock signal and a second external clock signal that is complementary to the first external clock signal, and configured to generate a first frequency divided clock signal that is a fraction of a frequency of the first external clock signal and to generate a second frequency divided clock signal that is the fraction of the frequency of the second external clock signal, and both the first driver and the second driver provide the clock signals based on the first frequency divided clock signal and the second frequency divided clock signal.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 96.0
- Lexical Diversity: 2.0
- Patent Class: nan
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10328154', '15624491', '12795602', '11218170', '13923656']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4342336666891011
- 35 USC 102 Novelty (BERT): 0.4584002319537337
- Combined Prediction Score: 0.4366503232155644
- Mean Citation Score: 114.61606880000002
- Max Citation Score: 116.07027
- Similarity Product: 84.39335286619661

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test