PATENT CLAIM ANALYSIS

Application Number: 15867615
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-06
Patent Classification: ["257", "306000"]

Abstract:
A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.

Claim (Index 7):
The memory cell according to  claim 6 , wherein the capacitor comprises a storage node and a storage node pad contacting the storage node with the storage node contact.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 86.0
- Lexical Diversity: 2.88462
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13576944', '10928315', '11799572', '12076766', '10675042']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281141013565376
- 35 USC 102 Novelty (BERT): 0.5016893898996172
- Combined Prediction Score: 0.8854716302108454
- Mean Citation Score: 234.586856
- Max Citation Score: 236.03436
- Similarity Product: 158.74373237835644

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test