PATENT CLAIM ANALYSIS

Application Number: 16151161
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["710", "260000"]

Abstract:
A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Claim (Index 17):
A failure detection method of a semiconductor device having a first circuit hierarchy and a second circuit hierarchy, the first circuit hierarchy including a plurality of processors that perform a predetermined interrupt in response to an interrupt request, a plurality of circuit blocks, each outputting an interrupt signal, an interrupt control circuit that receives the interrupt signals from the circuit blocks and outputs the interrupt request to one of the processors and at least one interrupt monitoring circuit that corresponds to at least one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods, the monitoring type indicating a monitoring state of the corresponding interrupt signal, the method comprising:\n performing a predetermined operation check test on each of the first and second circuit hierarchies at startup of the semiconductor device; normally activating the semiconductor device in absence of abnormality in the operation check test; in the normal operation, monitoring, by the interrupt monitoring circuit, the interrupt signal from the second circuit hierarchy to the first circuit hierarchy; under control of the interrupt monitoring circuit,\n if the monitoring type indicates an asserted state of the interrupt signal and a first duration of the continuous asserted state exceeds the first monitoring period, detecting the state as a failure; and \n if the monitoring type indicates a negated state of the interrupt signal and a second duration of the continuous negated state exceeds the second monitoring period, detecting the state as a failure.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 97.0
- Lexical Diversity: 3.2766
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12990983', '15682934', '12019231', '15828713', '13861708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6754905153681631
- 35 USC 102 Novelty (BERT): 0.4667793963513544
- Combined Prediction Score: 0.6546194034664822
- Mean Citation Score: 154.759912
- Max Citation Score: 164.90986999999996
- Similarity Product: 122.9740373760473

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test