PATENT CLAIM ANALYSIS

Application Number: 16233985
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["713", "194000"]

Abstract:
One of the various aspects of the invention is related to suggesting various techniques for improving the tamper-resistibility of hardware. The tamper-resistant hardware may be advantageously used in a transaction system that provides the off-line transaction protocol. Amongst these techniques for improving the tamper-resistibility are trusted bootstrapping by means of secure software entity modules, a new use of hardware providing a Physical Unclonable Function, and the use of a configuration fingerprint of a FPGA used within the tamper-resistant hardware.

Claim (Index 7):
The tamper-protected hardware module according to  claim 4 , further comprising an on-chip trusted time source for providing the current date and time,\n wherein the current date and time is used by the tamper-protected hardware module to verify validity of certificates.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 1.58491
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15241360', '14004651', '14624180', '15241391', '14704914']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4539864209716031
- 35 USC 102 Novelty (BERT): 0.5555668421071326
- Combined Prediction Score: 0.464144463085156
- Mean Citation Score: 404.956198
- Max Citation Score: 476.16754
- Similarity Product: 306.33251244580504

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test