PATENT CLAIM ANALYSIS

Application Number: 15882722
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["711", "118000"]

Abstract:
A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

Claim (Index 6):
The system-on-chip of  claim 5 , wherein the cache controller further comprises:\n an entry manager configured to provide an available entry list based on the extracted cache size information; and an entry allocator configured to allocate a new entry or replace an existing entry, among the plurality of entries, with another entry according to the available entry list.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 1.90698
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14933144', '13553884', '14274815', '13326690', '15730893']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4767983512938899
- 35 USC 102 Novelty (BERT): 0.5427638865939364
- Combined Prediction Score: 0.4833949048238946
- Mean Citation Score: 215.40624
- Max Citation Score: 376.49783
- Similarity Product: 263.98484213433744

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test