PATENT CLAIM ANALYSIS

Application Number: 15881704
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["365", "066000"]

Abstract:
Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

Claim (Index 10):
The integrated circuit of  claim 1 , wherein the multiple signal lines comprise active signal lines and inactive signal lines, and wherein the inactive signal lines are chopped to create an open or break.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 1.5625
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14963111', '10935518', '14068003', '15713281', '11388464']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7800203586035347
- 35 USC 102 Novelty (BERT): 0.4775899763717308
- Combined Prediction Score: 0.7497773203803543
- Mean Citation Score: 110.62356280000002
- Max Citation Score: 120.65645
- Similarity Product: 74.75855638623834

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test