PATENT CLAIM ANALYSIS

Application Number: 15941752
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-12
Patent Classification: ["257", "077000"]

Abstract:
A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.

Claim (Index 6):
A method of manufacturing a silicon carbide semiconductor device, the method comprising:\n forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the silicon carbide semiconductor substrate; selectively forming a first semiconductor region of a second conductivity type in a surface of the first semiconductor layer; forming a second semiconductor layer of the second conductivity type on the surface of the first semiconductor layer and a surface of the first semiconductor region, an impurity concentration of the second semiconductor layer being at most 5\u00d710 16 /cm 3 ; selectively forming a second semiconductor sub-region of the first conductivity type on the first semiconductor layer, in the second semiconductor layer, to form a first sub-region of the second conductivity type and the second semiconductor sub-region of the first conductivity type in the second semiconductor layer; selectively forming third semiconductor sub-regions of the first conductivity type in the second semiconductor layer; forming a fourth semiconductor sub-region of the second conductivity type between the third semiconductor sub-regions in the second semiconductor layer, an impurity concentration of the fourth semiconductor sub-region being higher than an impurity concentration of the first sub-region of the second semiconductor layer; forming a first electrode electrically connected to the third semiconductor sub-regions and the fourth semiconductor sub-region; forming a gate insulating film on a surface of the second semiconductor layer between the third semiconductor sub-region and the second semiconductor sub-region; forming a gate electrode on the gate insulating film; and forming a second electrode on a rear surface of the silicon carbide semiconductor substrate, wherein forming the fourth semiconductor sub-region includes forming a fifth semiconductor sub-region of the second conductivity type at a corner part of an active region in which a main current flows, an impurity concentration of the fifth semiconductor sub-region being higher than the impurity concentration of the first sub-region of the second semiconductor layer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.40476
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15279450', '15716992', '15397677', '14909407', '14651985']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9154776730047078
- 35 USC 102 Novelty (BERT): 0.5139290913246202
- Combined Prediction Score: 0.875322814836699
- Mean Citation Score: 306.29833
- Max Citation Score: 313.71985
- Similarity Product: 287.2750488395214

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test