PATENT CLAIM ANALYSIS

Application Number: 15888153
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["327", "157000"]

Abstract:
A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

Claim (Index 13):
The method of  claim 12 , further comprising filtering the lock control signal to generate said first signal.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 88.0
- Lexical Diversity: 2.26087
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13275753', '11803725', '10835237', '11196492', '15251570']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7800273906767368
- 35 USC 102 Novelty (BERT): 0.4966906925874123
- Combined Prediction Score: 0.7516937208678044
- Mean Citation Score: 244.719312
- Max Citation Score: 249.41702
- Similarity Product: 171.86542577129842

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test