PATENT CLAIM ANALYSIS

Application Number: 16130691
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["708", "201000"]

Abstract:
Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.

Claim (Index 9):
The apparatus according to  claim 1 , wherein the addition unit is arranged to group bits into strings by mapping each bit to one of:\n i. a positive coefficient value in [0, . . . ,b\u22121] which is congruent to 2 i mod b; ii. a coefficient equal to (2 i mod b) or ((2 i mod b)\u2212b) which has a smaller absolute magnitude and where i is a bit index for the bit; iii. whichever of (2 i mod b) or ((2 i mod b)\u2212b) has a larger absolute magnitude provided it can be formed from fewer powers of two via addition or subtraction than the smaller magnitude value from (ii) or is less in magnitude than b and is a 2\u00d7 multiple of another bit's coefficient; iv. a coefficient according to (ii) or (iii), wherein the coefficient is selected by evaluating a plurality of combinations of coefficient choices for each bit using a cost metric; v. a coefficient selected according to any of (i)-(iv) which is a signed power of two and has an absolute magnitude which does not exceed K*b where K is a natural number; and vi. a coefficient selected according to any combination of (i)-(v) to minimise the cost metric.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 97.0
- Lexical Diversity: 1.94048
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15163848', '15797020', '10610536', '09854853', '11497496']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4069209636695908
- 35 USC 102 Novelty (BERT): 0.5518116396666455
- Combined Prediction Score: 0.4214100312692963
- Mean Citation Score: 222.492218
- Max Citation Score: 381.745
- Similarity Product: 315.9594674038887

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test