PATENT CLAIM ANALYSIS

Application Number: 16066843
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "632000"]

Abstract:
At the time of clamping, excessive stress is applied to bonding parts between substrates and input/output terminals, which may cause the bonding parts to be detached and cause the substrates to be cracked. A lower electrode of a power semiconductor element  11  is connected via a bonding material  13  to a first interconnection layer  12  arranged on a lower surface of the power semiconductor element  11,  and an upper electrode  14  of the power semiconductor element  11  is connected via the bonding material  13  to a second interconnection layer  15  arranged on an upper surface. Also, a second main terminal  16  electrically connected to the upper electrode  14  of the power semiconductor element  11  is connected via the bonding material  13  to the second interconnection layer  15  and contacts and is positioned on a third interconnection layer  24  (spacer) arranged to be parallel to the first interconnection layer  12  on the lower surface. An insulating layer  26  is laminated on a surface of each of the first interconnection layer  12  to the third interconnection layer  24  opposite the bonding material  13,  and a heat dissipating layer  27  is laminated on the insulating layer  26.

Claim (Index 1):
A power semiconductor device comprising:\n a semiconductor element including an upper electrode and a lower electrode; a first interconnection layer arranged to be opposed to the lower electrode of the semiconductor element and connected to the lower electrode of the semiconductor element via a bonding material; a second interconnection layer arranged to be opposed to the upper electrode of the semiconductor element and connected to the upper electrode of the semiconductor element via the bonding material; a first main terminal connected to the first interconnection layer via the bonding material; a second main terminal connected to the second interconnection layer via the bonding material; and a spacer, wherein the spacer is arranged to be parallel to the first interconnection layer or the second interconnection layer and is provided with the first main terminal or the second main terminal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.88732
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10260348', '12748545', '13949185', '10766944', '12382412']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.910236247694558
- 35 USC 102 Novelty (BERT): 0.4579770335787119
- Combined Prediction Score: 0.8650103262829734
- Mean Citation Score: 163.05104
- Max Citation Score: 167.68202
- Similarity Product: 139.86211500970128

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test