PATENT CLAIM ANALYSIS

Application Number: 15949634
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "368000"]

Abstract:
A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

Claim (Index 16):
The semiconductor structure of  claim 15 , wherein the low-k dielectric lower portion defines a first length and the sacrificial upper portion defines a second length, where the second length is greater than the first length.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 2.44828
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15788390', '15949544', '15815009', '15437840', '15934130']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303368158644272
- 35 USC 102 Novelty (BERT): 0.5079468434960155
- Combined Prediction Score: 0.8880978186275861
- Mean Citation Score: 261.13192200000003
- Max Citation Score: 266.95712000000003
- Similarity Product: 183.71120128047943

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test