PATENT CLAIM ANALYSIS

Application Number: 16029046
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "230030"]

Abstract:
Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

Claim (Index 6):
The memory array of  claim 4 , wherein a source of each bleeder transistor is configured to be coupled to the respective column selection line of the plurality of column selection lines.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.80357
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15488328', '10534049', '11280170', '11963831', '11495550']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7784267729664864
- 35 USC 102 Novelty (BERT): 0.5434268771124092
- Combined Prediction Score: 0.7549267833810788
- Mean Citation Score: 242.231652
- Max Citation Score: 395.32962
- Similarity Product: 306.87697575823546

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test