PATENT CLAIM ANALYSIS

Application Number: 15935277
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["257", "324000"]

Abstract:
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Claim (Index 3):
The IC according to  claim 1 , wherein the first doping type is p-type and the second doping type is n-type.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 90.0
- Lexical Diversity: 2.41667
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15167070', '14324369', '14984095', '14296496', '15582889']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916122244123616
- 35 USC 102 Novelty (BERT): 0.5134288601514403
- Combined Prediction Score: 0.8758529057263984
- Mean Citation Score: 167.50683199999995
- Max Citation Score: 169.38048
- Similarity Product: 84.62677235509871

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test