PATENT CLAIM ANALYSIS

Application Number: 16168105
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["341", "120000"]

Abstract:
Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.

Claim (Index 15):
The BER forecast circuit for successive approximation register analog-to-digital conversion of  claim 13 , wherein the test value is inversely proportional to the bit error rate of the SAR ADC.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.4
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14293736', '13607132', '15878375', '11755754', '14587825']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5796117104270594
- 35 USC 102 Novelty (BERT): 0.5064749330677611
- Combined Prediction Score: 0.5722980326911296
- Mean Citation Score: 234.307136
- Max Citation Score: 246.84084
- Similarity Product: 193.66803218550683

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test