PATENT CLAIM ANALYSIS

Application Number: 15923864
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "003000"]

Abstract:
Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Claim (Index 11):
A method of forming integrated circuitry, comprising:\n forming a structure having first conductive lines over a dielectric bonding region, having semiconductor material walls over the first conductive lines, and having insulative walls between the semiconductor material walls; the first conductive lines, the insulative walls, and the semiconductor material walls all extending along a first direction; the insulative walls and the semiconductor material walls alternating with one another along a second direction which intersects the first direction; the semiconductor material walls comprising a first semiconductor material, and the insulative walls comprising insulative material; the structure comprising a second semiconductor material under the dielectric bonding region; the structure having a planarized surface extending across the semiconductor material walls and the insulative walls; forming trenches extending downwardly into the semiconductor material walls and the insulative walls; the trenches extending along the second direction; the trenches forming semiconductor material pillars from upper regions of the semiconductor material walls; the semiconductor material pillars being over lower regions of the semiconductor material walls; said lower regions being semiconductor material rails extending along the first conductive lines; sidewall edges of the semiconductor material pillars being exposed within the trenches, and top edges of the semiconductor material rails being exposed within the trenches; forming dielectric material along the exposed sidewall edges of the semiconductor material pillars and along the exposed top edges of the semiconductor material rails; forming second conductive material within the trenches and adjacent the dielectric material; the second conductive material being configured as second conductive lines extending along the second direction; and forming memory structures over the semiconductor material pillars.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 2.86792
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14226643', '15064002', '15650274', '15391604', '13765643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8617817798440847
- 35 USC 102 Novelty (BERT): 0.4720966774171143
- Combined Prediction Score: 0.8228132696013877
- Mean Citation Score: 219.374328
- Max Citation Score: 225.80673
- Similarity Product: 202.73102481753943

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test