PATENT CLAIM ANALYSIS

Application Number: 16079771
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["327", "156000"]

Abstract:
The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area. The phase locked loop includes: a digitally controlled oscillation unit that controls an oscillation frequency by a control signal in a digital format; a multiphase clock generation unit that generates clock signals with multiple phases synchronized with the digitally controlled oscillation unit; a clock selection unit that selects a selected clock signal out of the clock signals with multiple phases; a time-to-digital conversion unit that detects a time difference between the selected clock signal and a reference clock signal; a counter unit driven by any one clock signal out of the clock signals with multiple phases; a reference phase generation unit that generates a reference phase; a phase comparison unit that compares feedback phase information obtained from an output value of the counter unit and an output value of the time-to-digital conversion unit with the reference phase; and a digital loop filter unit that smoothes output of the phase comparison unit and generates the control signal for the digitally controlled oscillation unit.

Claim (Index 15):
A control method for a phase locked loop including a digitally controlled oscillation unit, a multiphase clock generation unit, a clock selection unit, a time-to-digital conversion unit, a counter unit, a reference phase generation unit, a phase comparison unit, and a digital loop filter unit, the control method comprising:\n a step of controlling, by the digitally controlled oscillation unit, an oscillation frequency by a control signal in a digital format; a step of generating, by the multiphase clock generation unit, clock signals with multiple phases synchronized with the digitally controlled oscillation unit; a step of selecting, by the clock selection unit, any one clock signal out of the clock signals with multiple phases as a selected clock signal; detecting, by the time-to-digital conversion unit, a time difference between the selected clock signal and a reference clock signal which is a clock signal serving as a reference; a step of driving the counter unit by any one clock signal out of the clock signals with multiple phases; a step of generating, by the reference phase generation unit, a reference phase; a step of comparing, by the phase comparison unit, feedback phase information obtained from an output value of the counter unit and an output value of the time-to-digital conversion unit with the reference phase; and a step of smoothing, by the digital loop filter unit, output of the phase comparison unit and generating the control signal for the digitally controlled oscillation unit.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 96.0
- Lexical Diversity: 2.5122
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12956498', '12978221', '15710154', '13755159', '13778478']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7718552701113147
- 35 USC 102 Novelty (BERT): 0.5285502754501152
- Combined Prediction Score: 0.7475247706451947
- Mean Citation Score: 324.221052
- Max Citation Score: 353.22644
- Similarity Product: 276.0268131368661

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test