PATENT CLAIM ANALYSIS

Application Number: 16236892
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-08
Patent Classification: ["710", "313000"]

Abstract:
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Claim (Index 18):
The memory unit of  claim 17 , wherein the processor comprises a programmable controller, and wherein the programmable controller is configured to respond to the commands to access data stored in one or more of a plurality of memory devices distributed throughout the first plurality of DIMMs and the second plurality of DIMMs and to perform data operations on the data accessed from the one or more of the plurality of memory devices.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 98.0
- Lexical Diversity: 2.37778
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15071072', '14539641', '15424638', '14656488', '15090818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6497426629613038
- 35 USC 102 Novelty (BERT): 0.5235098713937701
- Combined Prediction Score: 0.6371193838045505
- Mean Citation Score: 215.749338
- Max Citation Score: 321.9290200000001
- Similarity Product: 240.6022806606317

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test