PATENT CLAIM ANALYSIS

Application Number: 16189319
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["257", "326000"]

Abstract:
A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

Claim (Index 37):
The method of  claim 36 , wherein the dielectric stack further comprises a cap layer overlying the charge-trapping layer, and wherein the second oxidation step of the two-step oxidation process consumes substantially all of the cap layer.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 1.84615
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14745217', '14942773', '15370149', '15721132', '15683274']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9341470719317014
- 35 USC 102 Novelty (BERT): 0.5282089448017289
- Combined Prediction Score: 0.8935532592187042
- Mean Citation Score: 308.65649599999995
- Max Citation Score: 326.1464
- Similarity Product: 221.44497524108888

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test