PATENT CLAIM ANALYSIS

Application Number: 15860268
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "230060"]

Abstract:
A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.

Claim (Index 6):
The memory decoding system according to  claim 5 , wherein:\n a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor; and a source of the third NMOS transistor is connected to a source of the first NMOS transistor.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 3.52632
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15249580', '15200252', '15256208', '14958149', '11772299']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8346303895558853
- 35 USC 102 Novelty (BERT): 0.5257874647937844
- Combined Prediction Score: 0.8037460970796753
- Mean Citation Score: 268.721096
- Max Citation Score: 365.52454
- Similarity Product: 309.5669981505156

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test