PATENT CLAIM ANALYSIS

Application Number: 16215857
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-08
Patent Classification: ["327", "156000"]

Abstract:
An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.

Claim (Index 12):
The electronic device of  claim 10 , wherein the direct period synthesis sub-circuit further comprises: a second K\u21921 multiplexer, an adder, and a 2\u21921 multiplexer;\n wherein, the first K\u21921 multiplexer is further configured to select one output signal from the K output signals to output to the 2\u21921 multiplexer according to the first code address; the second K\u21921 multiplexer is configured to receive K output signals from the first input and a second code address from the adder, and to select one output signal from the K output signals to output to the 2\u21921 multiplexer according to the second code address; the adder is configured to receive F/2 from a third input, and to perform adding on the F/2 to generate the second code address and to output to the second K\u21921 multiplexer; the 2\u21921 multiplexer is configured to receive output signals from the first K\u21921 multiplexer and the second K\u21921 multiplexer, respectively, and to select an output signal among the output signals to output to the DFF; and the DFF is configured to receive one output signal from the 2\u21921 multiplexer; and to invert the one output signal to generate and output the clock signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 98.0
- Lexical Diversity: 2.51923
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15690625', '15665579', '15952531', '15751615', '14726666']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7845696822391587
- 35 USC 102 Novelty (BERT): 0.4851519849885171
- Combined Prediction Score: 0.7546279125140944
- Mean Citation Score: 195.621834
- Max Citation Score: 201.84274
- Similarity Product: 142.23862561511515

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test