PATENT CLAIM ANALYSIS

Application Number: 16132790
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-12
Patent Classification: ["327", "011000"]

Abstract:
A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected. The reset FET is coupled to return the input to the first binary value responsive to detection of a short

Claim (Index 5):
A load switch circuit implemented on an integrated circuit chip, the load switch comprising:\n a first node for coupling to an input voltage; a second node for coupling to an external load; a third node for coupling to a ground plane; a first P-type field effect transistor (PFET) coupled between the first node and the second node to control an output voltage to the external load; a driver circuit coupled to control a gate of the first PFET, the driver circuit comprising a first N-type field effect transistor (NFET) coupled between the first node and the third node, the gate of the first PFET being coupled to the source of the first NFET; a slew-rate-control circuit coupled to a gate of the first NFET, the slew-rate-control circuit comprising:\n a first capacitor node for coupling to a first terminal of an external capacitor, the first capacitor node being coupled to the gate of the first NFET, \n a second PFET coupled in series with a first current sink between the first node and the third node, a point between a drain of the second PFET and the first current sink being coupled to the gate of the first NFET, a gate of the second PFET being coupled to receive a power down bar signal that is coupled to be high when the load switch is turned on, and \n a reset PFET coupled in series with a feedback NFET between the first node and the gate of the first NFET, a gate of the feedback NFET being coupled to the gate of the first PFET and a gate of the reset PFET being coupled to receive an over-current-protection signal that is coupled to be low when a short to a low potential occurs.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.47541
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13946345', '10825481', '11422926', '14087246', '13754543']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7425831813058811
- 35 USC 102 Novelty (BERT): 0.4884971101077707
- Combined Prediction Score: 0.71717457418607
- Mean Citation Score: 228.60297200000005
- Max Citation Score: 239.31808
- Similarity Product: 194.7130421847725

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test