PATENT CLAIM ANALYSIS

Application Number: 15745072
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "071000"]

Abstract:
The present disclosure discloses an array substrate and a display device. A pixel electrode of the array substrate includes a first subpixel electrode and a second subpixel electrode, and a storage capacitor includes a first storage capacitor and a second storage capacitor, wherein the first storage capacitor is configured to maintain a voltage difference between the first subpixel electrode and the common electrode line, the second storage capacitor is configured to maintain a voltage difference between the second subpixel electrode and the common electrode line, and the first storage capacitor and the second storage capacitor have different capacitances.

Claim (Index 2):
The array substrate according to  claim 1 , wherein\n a gate electrode of the first thin film transistor is formed integrally with a gate electrode of the second thin film transistor, a source electrode of the first thin film transistor is formed integrally with a source electrode of the second thin film transistor, and an active layer of the first thin film transistor is formed integrally with an active layer of the second thin film transistor.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.81081
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14771428', '13064807', '12832483', '13546654', '11622254']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9299759393009208
- 35 USC 102 Novelty (BERT): 0.5044414696321499
- Combined Prediction Score: 0.8874224923340437
- Mean Citation Score: 260.760046
- Max Citation Score: 283.37485
- Similarity Product: 227.55450673516688

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test