PATENT CLAIM ANALYSIS

Application Number: 15917509
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "668000"]

Abstract:
A semiconductor package structure includes a first patterned conductive layer including a first conductive pad, a second conductive pad and a first conductive trace disposed between the first conductive pad and the second first conductive pad. The first conductive pad defines a recess. The semiconductor package structure further includes a second patterned conductive layer including a third conductive pad. The semiconductor package structure further includes a first stud bump electrically connecting the first conductive pad of the first patterned conductive layer to the third conductive pad of the second patterned conductive layer. The semiconductor package structure further includes a first encapsulation layer disposed between the first patterned conductive layer and the second patterned conductive layer.

Claim (Index 30):
The semiconductor package structure of  claim 29 , wherein the first patterned conductive layer further comprises a plurality of fourth conductive pads, and further comprising a first die electrically connected to the plurality of fourth conductive pads of the first patterned conductive layer.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 90.0
- Lexical Diversity: 3.78125
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15685864', '15450598', '15348899', '13776567', '12874144']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9375399732792244
- 35 USC 102 Novelty (BERT): 0.5037288130462203
- Combined Prediction Score: 0.894158857255924
- Mean Citation Score: 268.841264
- Max Citation Score: 285.83398
- Similarity Product: 215.0301840980769

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test