PATENT CLAIM ANALYSIS

Application Number: 15970413
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "676000"]

Abstract:
A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.

Claim (Index 5):
The method according to  claim 2 , wherein the second auxiliary trenches are partially filled with electrically insulating material by oxidizing exposed walls of the carrier wafer.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 93.0
- Lexical Diversity: 1.83871
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15688200', '10284031', '12293101', '14141832', '14948664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9136121870943876
- 35 USC 102 Novelty (BERT): 0.4755921688764339
- Combined Prediction Score: 0.8698101852725924
- Mean Citation Score: 136.96354200000002
- Max Citation Score: 155.65617
- Similarity Product: 111.7551728762287

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test