PATENT CLAIM ANALYSIS

Application Number: 16013646
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "049170"]

Abstract:
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Claim (Index 42):
The content addressable memory array of  claim 40 , wherein said first transistor and said second transistor comprise a buried insulator region.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 94.0
- Lexical Diversity: 2.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14154138', '15375236', '14597444', '15846566', '14380779']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8569834211358397
- 35 USC 102 Novelty (BERT): 0.6185730756303254
- Combined Prediction Score: 0.8331423865852883
- Mean Citation Score: 389.131656
- Max Citation Score: 526.85046
- Similarity Product: 394.4665801469421

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test