PATENT CLAIM ANALYSIS

Application Number: 15923009
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "529000"]

Abstract:
Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.

Claim (Index 7):
The method of  claim 4 , wherein a concentration of Ge in the modified semiconductor layer is about 30 percent and a break down voltage of the modified semiconductor layer is about 2.5V.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.09615
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15810940', '15422544', '15404469', '15846447', '15468755']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9368218258700848
- 35 USC 102 Novelty (BERT): 0.5694654052190626
- Combined Prediction Score: 0.9000861838049826
- Mean Citation Score: 357.631848
- Max Citation Score: 464.48416
- Similarity Product: 391.89754657630925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test