PATENT CLAIM ANALYSIS

Application Number: 15955822
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

Claim (Index 9):
A method of forming a semiconductor structure comprising:\n forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin comprises a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion; forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile; and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin; wherein the at least one fin comprises a channel for a vertical field-effect transistor; wherein the bottom source/drain region is disposed over the top surface of the substrate; wherein forming the at least one fin comprises:\n patterning a hard mask layer over a portion of the substrate; and \n etching portions of the substrate exposed by the hard mask layer to form the at least one fin; and \n wherein forming the bottom spacer comprises:\n depositing a spacer material over the top surface of the substrate, the hard mask layer and sidewalls of the at least one fin; and \n etching the spacer material to remove portions of the spacer material disposed on the top surface of the hard mask layer and the top surface of the substrate and to leave portions of the spacer material disposed on the sidewalls of the hard mask layer and on the second portion of the sidewalls of the at least one fin, the remaining portions of the spacer material providing the bottom spacer.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.84444
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15804622', '15845594', '15705888', '15830665', '15285739']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9278242011565004
- 35 USC 102 Novelty (BERT): 0.5071194697077195
- Combined Prediction Score: 0.8857537280116223
- Mean Citation Score: 300.586056
- Max Citation Score: 309.47324
- Similarity Product: 270.9199227797198

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test