PATENT CLAIM ANALYSIS

Application Number: 15914095
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["323", "313000"]

Abstract:
A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.

Claim (Index 14):
A bandgap reference voltage generation circuit, comprising:\n an amplifier to output an operational amplified signal based on a first voltage and a second voltage; a first PMOS transistor to generate a first current based on the operational amplified signal received through a first gate terminal and a supply voltage received through a first source terminal; a second PMOS transistor to generate a second current based on the operational amplified signal received through a second gate terminal and the supply voltage received through a second source terminal; a third PMOS transistor to generate a third current the operational amplified signal received through a third gate terminal and receiving the supply voltage through a third source terminal; a first transistor connected to the first PMOS transistor in a cascode manner; a second transistor connected to the second PMOS transistor in the cascode manner; and a third transistor connected to the third PMOS transistor in the cascode manner, wherein the first transistor is to provide different voltages to a first drain terminal of the first PMOS transistor in a first mode and a second mode different from the first mode, wherein the second transistor is to provide different voltages to a second drain terminal of the second PMOS transistor in the first mode and the second mode, and wherein the third transistor is to provide different voltages to a third drain terminal of the third PMOS transistor in the first mode and the second mode.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 90.0
- Lexical Diversity: 3.34091
- Patent Class: 323.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12262057', '12344374', '10621747', '12104140', '14669352']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7199690667894945
- 35 USC 102 Novelty (BERT): 0.5079902611228475
- Combined Prediction Score: 0.6987711862228297
- Mean Citation Score: 283.416308
- Max Citation Score: 294.08002
- Similarity Product: 231.89407098474263

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test