PATENT CLAIM ANALYSIS

Application Number: 16081012
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "195000"]

Abstract:
A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Claim (Index 17):
A method of fabricating a heterostructure semiconductor device comprising:\n forming a first active layer on a substrate; forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that an electrical charge layer is formed therebetween; defining a first active area and a second active area, the first active area including a first portion of the first active layer, a first portion of the second active layer, and a first portion of the electrical charge layer, the second active area including a second portion of the first active layer, a second portion of the second active layer, and a second portion of the electrical charge layer, the second active area being electrically isolated from the first active area, wherein the first active area comprises a power transistor and the second active area comprises an integrated gate resistor of the heterostructure semiconductor device; forming first and second contacts directly on the second portion of the second active layer, the first and second contacts being laterally separated by a distance, the first and second contacts comprising first and second terminals of the integrated gate resistor, respectively; and forming an array of gates that laterally extends over the first active area of the power transistor, the array of gates being electrically connected to the second contact and functioning as a gate of the power transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 2.38596
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14539086', '13780192', '15448724', '15700087', '15587276']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8970530844884504
- 35 USC 102 Novelty (BERT): 0.4651425981379828
- Combined Prediction Score: 0.8538620358534037
- Mean Citation Score: 178.48176999999995
- Max Citation Score: 189.03392
- Similarity Product: 167.61192146724702

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test