PATENT CLAIM ANALYSIS

Application Number: 15905083
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["708", "620000"]

Abstract:
Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

Claim (Index 34):
The method of  claim 31 , wherein performing the plurality of multiplication operations on the respective plurality of element pairs comprises copying the respective results from the sensing circuitry to the array without transferring data from the sensing circuitry via activation of column decode lines coupled thereto.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 88.0
- Lexical Diversity: 2.29825
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14834065', '15692959', '14836726', '15410199', '15898894']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5310575306457228
- 35 USC 102 Novelty (BERT): 0.564998630872497
- Combined Prediction Score: 0.5344516406684002
- Mean Citation Score: 415.1248000000001
- Max Citation Score: 441.8559
- Similarity Product: 327.04711287295817

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test