PATENT CLAIM ANALYSIS

Application Number: 15927688
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "314000"]

Abstract:
A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

Claim (Index 10):
The three-dimensional memory device of  claim 1 , wherein:\n the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; the substrate comprises a silicon substrate; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and the array of monolithic three-dimensional NAND strings comprises:\n a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and \n a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 90.0
- Lexical Diversity: 2.22222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15354067', '15888714', '15818146', '15876884', '15906109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9238745325585052
- 35 USC 102 Novelty (BERT): 0.5833618350447906
- Combined Prediction Score: 0.8898232628071339
- Mean Citation Score: 412.425296
- Max Citation Score: 473.56152
- Similarity Product: 441.5030852255916

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test