PATENT CLAIM ANALYSIS

Application Number: 16447829
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["326", "081000"]

Abstract:
Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

Claim (Index 1):
A depletion mode buried channel conductor insulator semiconductor field effect transistor comprising:\n a source of first conductivity type semiconductor material, a drain of first conductivity type semiconductor material, an external gate located in between said source and said drain, a channel of first conductivity type semiconductor material located in between said source and said drain, a layer of insulating material located in between said external gate and said channel, and a back-gate doping of second conductivity type semiconductor material located next to said channel on the opposite side to said external gate; said back-gate doping corresponds to a gate, said external gate corresponds to an auxiliary gate, said source is biasable at a source potential, said gate is biasable either at a first logic potential or at a second logic potential, the depletion mode buried channel conductor insulator semiconductor field effect transistor is configured to: when said back-gate doping is being biased at said first logic potential said channel is conductive, when said back-gate doping is being biased at said second logic potential said channel is nonconductive, and said external gate is configured to be biased so that a layer of mobile second conductivity type charge carriers is being established at an insulator semiconductor interface beneath said external gate irrespective of whether said back-gate doping is being biased at said first logic potential or at said second logic potential, and said layer of mobile second conductivity type charge carriers arranged to act as a part of said gate and arranged to control said channel from an opposite side than said second conductivity type back-gate doping.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 100.0
- Lexical Diversity: 2.46809
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16173271', '15543801', '15954202', '10324485', '12996067']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7174808315824044
- 35 USC 102 Novelty (BERT): 0.6107833139705549
- Combined Prediction Score: 0.7068110798212195
- Mean Citation Score: 411.499936
- Max Citation Score: 555.81885
- Similarity Product: 531.7447197194158

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test