PATENT CLAIM ANALYSIS

Application Number: 15997557
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["327", "292000"]

Abstract:
The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Claim (Index 6):
The apparatus of  claim 4 , wherein the timing alignment circuit is coupled between an output of the VCO circuit and a second input to the error detector circuit.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.08108
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10997236', '15959332', '11778353', '10639248', '11229472']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7717853899190056
- 35 USC 102 Novelty (BERT): 0.5058595271572701
- Combined Prediction Score: 0.745192803642832
- Mean Citation Score: 252.374858
- Max Citation Score: 263.2761
- Similarity Product: 192.8981432473361

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test