PATENT CLAIM ANALYSIS

Application Number: 16017430
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["710", "308000"]

Abstract:
A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

Claim (Index 10):
The apparatus of  claim 9  wherein the memory controller comprises control register space to disable DDR5 operation in favor of simultaneously transferring data between the first and second ranks over the first and second group of I/Os.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 94.0
- Lexical Diversity: 1.25926
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15196014', '15716485', '15197424', '15907390', '15857519']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5362079967669938
- 35 USC 102 Novelty (BERT): 0.5054519516576286
- Combined Prediction Score: 0.5331323922560574
- Mean Citation Score: 183.717458
- Max Citation Score: 204.82341
- Similarity Product: 127.34453513106824

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test