PATENT CLAIM ANALYSIS

Application Number: 16051280
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "192000"]

Abstract:
A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Claim (Index 7):
The semiconductor structure of  claim 1 , wherein the buffer layer has a thickness between about 10 nm and about 20 nm.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 95.0
- Lexical Diversity: 2.70588
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14074932', '14073236', '15262136', '14072011', '14489817']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9322811550649474
- 35 USC 102 Novelty (BERT): 0.5498969575119279
- Combined Prediction Score: 0.8940427353096455
- Mean Citation Score: 310.835786
- Max Citation Score: 421.22208
- Similarity Product: 311.568540576725

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test