PATENT CLAIM ANALYSIS

Application Number: 16109272
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["257", "664000"]

Abstract:
The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Claim (Index 3):
The semiconductor substrate of  claim 1 , wherein the first conductive via comprises a tapered shape.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 96.0
- Lexical Diversity: 2.56452
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15404093', '15824913', '15348899', '15349954', '14536253']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9183517708050084
- 35 USC 102 Novelty (BERT): 0.47316483632861
- Combined Prediction Score: 0.8738330773573685
- Mean Citation Score: 166.70013799999995
- Max Citation Score: 169.52257
- Similarity Product: 128.19027221241475

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test