PATENT CLAIM ANALYSIS

Application Number: 15907711
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "148000"]

Abstract:
A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresponding one of the fifth wirings.

Claim (Index 2):
The semiconductor integrated circuit according to  claim 1 , wherein the first array further comprises first inverters disposed to correspond to the fifth wirings and second inverters disposed to correspond to the fourth wirings, at least one of the first inverters including an input terminal to receive an input signal and an output terminal connected to corresponding one of the fifth wirings, at least one of the second inverters including an input terminal connected to corresponding one of the fourth wirings and an output terminal to output an output signal, and\n the second array further comprises third inverters disposed to correspond to the seventh wirings and fourth inverters disposed to correspond to the sixth wirings, at least one of the third inverters including an input terminal to receive an input signal and an output terminal connected to corresponding one of the seventh wirings, the fourth inverter including an input terminal connected to corresponding one of the sixth wirings and an output terminal to output an output signal.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 3.86047
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15700319', '14884215', '14854361', '12282163', '14988034']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8018457600997496
- 35 USC 102 Novelty (BERT): 0.4767922127437923
- Combined Prediction Score: 0.7693404053641539
- Mean Citation Score: 173.96563600000005
- Max Citation Score: 201.73521
- Similarity Product: 150.74559368994713

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test