PATENT CLAIM ANALYSIS

Application Number: 15972827
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["341", "144000"]

Abstract:
Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Claim (Index 7):
The Analog-Digital Converter according to  claim 5 , wherein the gate electrode of the PMOS transistor is specifically configured to receive the control signal, and the gate electrode of the NMOS transistor is specifically configured to receive an inverting signal of the control signal, so as to control on-state of the at least one CMOS transmission gate, thereby implementing gating control on the first clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.37143
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15633474', '15121381', '13551950', '12857674', '14597146']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5910208048462584
- 35 USC 102 Novelty (BERT): 0.567683961125744
- Combined Prediction Score: 0.588687120474207
- Mean Citation Score: 270.70587
- Max Citation Score: 432.83826
- Similarity Product: 383.4025082224846

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test