PATENT CLAIM ANALYSIS

Application Number: 15870503
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "347000"]

Abstract:
There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claim (Index 1):
A semiconductor device, comprising:\n an SDI substrate that includes a first surface; a first semiconductor layer that includes a second surface opposite to the first surface, and the third surface opposite to the second surface, the third surface having a semiconductor element disposed thereon; an oxide film layer that is formed in contact with the first surface and the second surface; a first diffusion layer that is formed on a surface including the semiconductor layer in planar view and opposing the second surface, and is connected to a first reference potential, the oxide film layer being sandwiched between said surface opposing the second surface and the second surface; a second diffusion layer that is connected to a second reference potential and that is formed in a part of a region of the first surface corresponding to a region that is adjacent to the first diffusion layer in planar view; a second semiconductor layer that is formed co-planar with the first semiconductor layer in cross-section view, and a region corresponding to the first surface of the second semiconductor layer is disposed in a region that is sandwiched between the first diffusion layer and the second diffusion layer in planar view.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.09211
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15064686', '13583409', '14598364', '15369054', '11770238']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918757920989554
- 35 USC 102 Novelty (BERT): 0.503724279355501
- Combined Prediction Score: 0.8772545568261486
- Mean Citation Score: 249.631132
- Max Citation Score: 287.56653
- Similarity Product: 232.0827247525656

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test