PATENT CLAIM ANALYSIS

Application Number: 15989548
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["703", "013000"]

Abstract:
A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Claim (Index 6):
The method of  claim 2 , wherein the running simulations comprises simulating the loading network with the Pi model in order to define a delay in the network represented by\n (\u2202delay[slew])/(\u2202 R wire [C far ][C near ]).

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.12727
- Patent Class: 703.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14495383', '15022786', '12851044', '09267968', '11219205']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2453792317885109
- 35 USC 102 Novelty (BERT): 0.4955437565223677
- Combined Prediction Score: 0.2703956842618966
- Mean Citation Score: 143.83011000000005
- Max Citation Score: 225.15562000000003
- Similarity Product: 165.54478300493005

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test