PATENT CLAIM ANALYSIS

Application Number: 15988838
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["341", "166000"]

Abstract:
A phase locked loop comprising a time to digital converter and a fractional-n feedback loop, the PLL being configurable by a phase compensator module to reduce the dynamic range of the TDC required to maintain PLL performance.

Claim (Index 7):
The PLL of  claim 1  wherein the second output of the phase compensation module to be added to the output of the TDC is amplified by the phase compensation module or by a gain module.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 93.0
- Lexical Diversity: 1.3
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15370796', '12235623', '11463630', '12464895', '12235615']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5828716993651297
- 35 USC 102 Novelty (BERT): 0.5130462542512335
- Combined Prediction Score: 0.5758891548537401
- Mean Citation Score: 239.4356
- Max Citation Score: 243.35927
- Similarity Product: 171.6209791990459

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test