PATENT CLAIM ANALYSIS

Application Number: 15894947
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["438", "586000"]

Abstract:
A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.

Claim (Index 10):
The manufacturing method of the semiconductor memory device according to  claim 9 , wherein the spacer layer on the memory cell region is not covered by the patterned mask layer during the second etching process.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 88.0
- Lexical Diversity: 2.94444
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15479294', '15048236', '14738421', '15744163', '14729111']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8509788173232503
- 35 USC 102 Novelty (BERT): 0.4957619035878908
- Combined Prediction Score: 0.8154571259497144
- Mean Citation Score: 213.140044
- Max Citation Score: 227.93875
- Similarity Product: 177.3597151260078

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test