PATENT CLAIM ANALYSIS

Application Number: 15950291
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "229000"]

Abstract:
A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

Claim (Index 15):
An integrated circuit product, comprising\n a first fin of a PMOS FinFET device formed in a semiconductor substrate, said semiconductor substrate comprising a first semiconductor material; a first gate structure of said PMOS FinFET device positioned above a portion of said first fin; first source and drain regions of said PMOS FinFET device positioned on opposite sides of said first gate structure; a second fin of an NMOS FinFET device formed in said semiconductor substrate; a second gate structure of said NMOS FinFET device positioned above a portion of said second fin; second source and drain regions of said NMOS FinFET device positioned on opposite sides of said second gate structure; a second semiconductor material positioned on said first fin in said first source and drain regions of said PMOS FinFET device, wherein said second semiconductor material is different from said first semiconductor material; a third semiconductor material positioned on said second fin in said second source and drain regions of said NMOS FinFET device, wherein said third semiconductor material is different from said first and second semiconductor materials; a silicon-carbide (SiC) semiconductor material positioned on and in direct physical contact with said second semiconductor material in said first source and drain regions of said PMOS FinFET device and on and in direct physical contact with said third semiconductor material in said second source and drain regions of said NMOS FinFET device, said silicon-carbide (SiC) semiconductor material being different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon-carbide (SiC) semiconductor material in each of said first source and drain regions of said PMOS FinFET device and in said second source and drain regions of said NMOS FinFET device; and a plurality of contact structures, wherein each of said plurality of contact structures is conductively coupled to a respective one of said graphene contacts.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.70588
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15052098', '14223373', '15799247', '15799286', '15489920']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8430927003058614
- 35 USC 102 Novelty (BERT): 0.5517468491131831
- Combined Prediction Score: 0.8139581151865936
- Mean Citation Score: 291.132624
- Max Citation Score: 397.86185
- Similarity Product: 362.84694823027854

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test