PATENT CLAIM ANALYSIS

Application Number: 15942119
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["331", "034000"]

Abstract:
Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.

Claim (Index 5):
The phase-locked loop of  claim 4 , wherein the oscillator gain estimation circuit comprises a correction loop configured to generate the indication of gain of the oscillator based on an output signal at the output of the phase detector.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 2.2
- Patent Class: 331.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15284190', '15284195', '15284374', '15377917', '15156584']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.764893870545787
- 35 USC 102 Novelty (BERT): 0.5550155629491565
- Combined Prediction Score: 0.7439060397861239
- Mean Citation Score: 300.659222
- Max Citation Score: 411.46494
- Similarity Product: 326.04128784434084

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test