PATENT CLAIM ANALYSIS

Application Number: 15992052
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["327", "203000"]

Abstract:
An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Claim (Index 3):
The apparatus of  claim 1 , wherein the clock is to gate a data input to the switch.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 93.0
- Lexical Diversity: 1.4375
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15246445', '15178294', '15846047', '15860562', '15247713']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7790385833468743
- 35 USC 102 Novelty (BERT): 0.5053814286060282
- Combined Prediction Score: 0.7516728678727898
- Mean Citation Score: 210.28966
- Max Citation Score: 289.6303
- Similarity Product: 231.438181301254

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test