PATENT CLAIM ANALYSIS

Application Number: 16103538
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["438", "627000"]

Abstract:
A method of forming interconnects in a semiconductor device is provided. A mask including first and second openings is formed over a non-conductive structure. An etch is performed through the mask openings to define (a) a via trench having a via trench width and (b) an interconnect trench having a smaller width than the via trench width. A fill layer is deposited over the structure and (a) fills only a partial width of the via trench to thereby define via trench cavity and (b) fills the full width of the interconnect trench. A further etch is performed through the via trench cavity to form a via opening extending downwardly from the via trench. The remaining fill layer material is removed. The interconnect trench, via trench, and via opening are metallized to form a trench interconnect, a via interconnect, and a via extending downwardly from the via interconnect.

Claim (Index 11):
The method of  claim 1 , wherein the fill layer includes multiple sublayers.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 96.0
- Lexical Diversity: 2.67742
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11857805', '14501338', '11857760', '14740374', '15082588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8568504569410009
- 35 USC 102 Novelty (BERT): 0.505968717801915
- Combined Prediction Score: 0.8217622830270923
- Mean Citation Score: 159.91800600000005
- Max Citation Score: 167.8109
- Similarity Product: 92.10596313017606

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test