PATENT CLAIM ANALYSIS

Application Number: 15995881
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["710", "100000"]

Abstract:
A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.

Claim (Index 15):
Apparatus comprising:\n a common integrated circuit (IC) package; a first processor on a first semiconductor die, the first semiconductor die contained in the common IC package; a second processor on a second semiconductor die, the second semiconductor die contained in the common IC package; first connectivity circuitry on the first semiconductor die, the first connectivity circuitry connected to the first processor via a first processor bus, the first connectivity circuitry further connected to a first set of discrete signal lines, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert first processor bus transactions on the first processor bus and first discrete signaling events on the first set of discrete signal lines into die-to-die message packets for communication via a die-to-die interconnect, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis; a second connectivity circuitry on the second semiconductor die, the second connectivity circuitry connected to the die-to-die interconnect for receiving the die-to-die message packets, the second connectivity circuitry connected to the second processor via a second processor bus, the second connectivity circuitry further connected to a second set of discrete signal lines, the second connectivity circuitry configured to convert the die-to-die message packets into second processor bus transactions on the second processor bus and second discrete signaling events on the second set of discrete signal lines; and destination synchronizers, the destination synchronizers selectively enabled for scalar or Gray-coded vector signaling events of the first discrete signaling events.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 94.0
- Lexical Diversity: 2.41935
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15995983', '15840473', '15865638', '14879024', '13791642']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6455687355081943
- 35 USC 102 Novelty (BERT): 0.4826873114316302
- Combined Prediction Score: 0.6292805931005379
- Mean Citation Score: 135.51554800000002
- Max Citation Score: 242.2879
- Similarity Product: 199.52031099262243

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test