PATENT CLAIM ANALYSIS

Application Number: 16397038
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["365", "193000"]

Abstract:
Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.

Claim (Index 13):
The apparatus of  claim 12 , further comprising a timing component configured to provide a delay to respective signals asserted on the PDL signal line or the LDPL signal line so that the respective signals are received to the plurality of partitioned memory banks concurrently.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.36842
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15174019', '16199460', '16004864', '15066831', '15693378']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8142109701574408
- 35 USC 102 Novelty (BERT): 0.505852140074739
- Combined Prediction Score: 0.7833750871491707
- Mean Citation Score: 220.366954
- Max Citation Score: 296.92215
- Similarity Product: 212.2271395685971

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test