PATENT CLAIM ANALYSIS

Application Number: 16448814
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Claim (Index 11):
A semiconductor device, comprising:\n a field effect transistor (FET) device disposed on a semiconductor substrate, wherein the FET device comprises a source/drain layer, and a gate structure comprising a gate electrode layer, a gate capping layer, and a gate sidewall spacer; a first interlevel dielectric (ILD) layer which encapsulates the FET device; a vertical source/drain contact disposed within the first ILD layer and in contact with the source/drain layer of the FET device; a source/drain contact capping layer disposed on an upper surface of the vertical source/drain contact; a second ILD layer disposed over the first ILD layer and the source/drain contact capping layer, wherein the second ILD layer is formed of a material which comprises etch selectivity with respect to the source/drain contact capping layer; and a vertical gate contact disposed in contact with a portion of the gate electrode layer of the gate structure of the FET device, which is exposed through an etched opening in the second ILD layer and the gate capping layer; wherein a portion of the vertical gate contact overlaps a portion of the vertical source/drain contact; and wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate contact and the vertical source/drain contact.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.05882
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16240570', '15635944', '15198644', '16411459', '15431807']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9343249918495456
- 35 USC 102 Novelty (BERT): 0.6193966316878456
- Combined Prediction Score: 0.9028321558333756
- Mean Citation Score: 437.918966
- Max Citation Score: 570.62854
- Similarity Product: 531.6108661361244

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test