PATENT CLAIM ANALYSIS

Application Number: 15995850
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-09
Patent Classification: ["718", "104000"]

Abstract:
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.

Claim (Index 5):
The method of  claim 1 , further comprising:\n determining that the rejection condition is expected to resolve within a quantity of cycles; and responsive to determining that the rejection condition is expected to resolve within the quantity of cycles, scheduling the instruction to be issued coincident with a lapse of the quantity of cycles.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 94.0
- Lexical Diversity: 2.17778
- Patent Class: 718.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15152257', '15221035', '15060690', '15079452', '15219638']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5021889889887948
- 35 USC 102 Novelty (BERT): 0.5565737347093346
- Combined Prediction Score: 0.5076274635608488
- Mean Citation Score: 288.3183
- Max Citation Score: 313.45486
- Similarity Product: 269.76825622418164

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test