PATENT CLAIM ANALYSIS

Application Number: 15968968
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "384000"]

Abstract:
Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.

Claim (Index 19):
The method of  claim 18 , further comprising,\n before the growing of the S/D epitaxy structure:\n forming a shallow trench isolation (STI) between adjacent nanosheet stacks and adjacent gate structures; \n forming a multi-layer stack spacer on edges of the nanosheet stacks; \n forming a multi-layer gate spacer on sidewalls of the gate structure, the multi-layer gate spacer including at least a gate-side layer in contact with the gate and a spacer-side layer in contact with a layer of the multi-layer gate spacer; \n forming an organic planarization layer (OPL) on the STI and on the multi-layer stack spacer, the multi-layer stack spacer including at least an inner layer in contact with the edges of the nanosheet stacks and an outer layer in contact with the OPL; \n recessing a top surface of the OPL to a level below a top surface of the multi-layer spacer; \n removing the nanosheet stacks and recessing the substrate between adjacent inner layers of the multi-layer spacers; \n removing the inner layers of the multi-layer stack spacers; \n removing the outer layers of the multi-layer stack spacers and the spacer-side layers of the multi-layer gate spacers; \n removing the OPL; \n removing the first sacrificial SiGe layer; \n partially indenting the SiGe layers of the nanosheet stacks; \n depositing inner spacer material on the substrate and edges of the nanosheet stacks; \n recessing the inner spacer material to form inner spacers on edges of the indented SiGe layers of each nanosheet stack and beneath a bottom-most SiGe layer of each nanosheet stack; \n epitaxially growing SiGe between adjacent STIs and adjacent nanosheet stacks and recessing to a level above a top surface of the STIs and below the bottom-most SiGe layer of each nanosheet stack, thereby forming a second sacrificial SiGe layer; \n epitaxially growing Si on the second sacrificial SiGe layer; \n selectively removing the second sacrificial SiGe layer, thereby forming the isolation area; \n depositing a dielectric material in the isolation area and isotropically etching the dielectric material such that the isolation area becomes encapsulated by the dielectric material; \n thinning the Si on the second sacrificial SiGe layer; \n epitaxially growing SiGe 100+  on the thinned Si.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 1.62791
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15888401', '15434205', '15657659', '15241772', '15868742']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9137549942675676
- 35 USC 102 Novelty (BERT): 0.5304901601572561
- Combined Prediction Score: 0.8754285108565364
- Mean Citation Score: 305.3313100000001
- Max Citation Score: 339.0741
- Similarity Product: 239.8923929837644

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test