PATENT CLAIM ANALYSIS

Application Number: 16019119
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "774000"]

Abstract:
A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Claim (Index 4):
The device of  claim 1 , wherein each of the first and second stair-step structures has a thickness decreasing in a stepwise manner in the first direction.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 94.0
- Lexical Diversity: 2.76471
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15403779', '15726002', '15373922', '15383213', '15964190']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9374494562202632
- 35 USC 102 Novelty (BERT): 0.5684052739410431
- Combined Prediction Score: 0.9005450379923413
- Mean Citation Score: 357.590164
- Max Citation Score: 490.24966
- Similarity Product: 355.0567213905561

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test