PATENT CLAIM ANALYSIS

Application Number: 16275038
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-09
Patent Classification: ["365", "185170"]

Abstract:
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

Claim (Index 9):
A method of operating a memory array having multiple vertical strings of memory cells, comprising:\n accessing selected memory cells from the multiple strings of memory cells,\n wherein the multiple strings of memory cells are arranged in rows and columns, each string having multiple vertically arranged memory cells and extending between a source and a respective bit line of multiple bit lines, \n wherein the bit lines extend in a first direction, and wherein first and second bit lines are vertically stacked relative to one another, \n wherein strings of memory cells that are adjacent to one another along the first direction are coupled to different bit lines, \n wherein the vertically arranged memory cells of the multiple strings are associated with respective access lines, and \n wherein the access lines are coupled to respective memory cells in each of a plurality of strings of the multiple strings; \n applying a pass voltage to access lines not associated with the selected memory cells; applying an operational voltage to a selected access line associated with the selected memory cells to enable the selected memory cells; coupling a first bit line of the multiple stacked bit lines to a shield voltage line during at least a portion of a memory operation; and\n wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second bit line during the memory operation, and \n wherein strings of memory cells that do not contain the enabled memory cells are operably coupled to the first bit line during at least a portion of the memory operation.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 2.52
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15676659', '14867948', '13919599', '12502771', '11432135']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.792955569495018
- 35 USC 102 Novelty (BERT): 0.4808124846044398
- Combined Prediction Score: 0.7617412610059603
- Mean Citation Score: 212.896042
- Max Citation Score: 257.62024
- Similarity Product: 222.63869642377853

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test