PATENT CLAIM ANALYSIS

Application Number: 16120295
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-09
Patent Classification: ["327", "175000"]

Abstract:
A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.

Claim (Index 12):
The semiconductor device according to  claim 9 , wherein the delay unit is configured to delay the first delay clock and the second delay clock by the same amount when the first period and the second period are substantially equal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 3.31707
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14955051', '14699290', '12407727', '12630400', '13610062']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7357349614232751
- 35 USC 102 Novelty (BERT): 0.4701089032209085
- Combined Prediction Score: 0.7091723556030385
- Mean Citation Score: 146.26651399999997
- Max Citation Score: 153.25722
- Similarity Product: 116.57892869101524

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test