PATENT CLAIM ANALYSIS

Application Number: 16055492
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["257", "737000"]

Abstract:
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.

Claim (Index 22):
The method of  claim 21  wherein depositing an insulative layer includes depositing an insulative layer in the passage between the die and the first conductive material and between the die and the second conductive material.

Metadata:
- Claim Count in Document: 53.0
- Percentile: 96.0
- Lexical Diversity: 2.09259
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14300004', '10733226', '13337943', '11430735', '11494982']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9621746399211684
- 35 USC 102 Novelty (BERT): 0.5770122227108642
- Combined Prediction Score: 0.923658398200138
- Mean Citation Score: 457.334032
- Max Citation Score: 500.8122
- Similarity Product: 418.6659073848009

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test