PATENT CLAIM ANALYSIS

Application Number: 15911403
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["385", "014000"]

Abstract:
A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Claim (Index 10):
The device of  claim 8 , further comprising a passivation layer disposed over the conductive layer in the circuitry region of the semiconductor substrate, and\n wherein the reflecting layer is further disposed over the passivation layer in the first circuitry region of the semiconductor substrate.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 90.0
- Lexical Diversity: 2.4717
- Patent Class: 385.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14715039', '13399098', '13905404', '13628927', '15342669']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7635857471222105
- 35 USC 102 Novelty (BERT): 0.4948429919182338
- Combined Prediction Score: 0.7367114716018128
- Mean Citation Score: 165.94493799999995
- Max Citation Score: 211.4566
- Similarity Product: 150.94701284005643

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test