PATENT CLAIM ANALYSIS

Application Number: 15944229
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["341", "166000"]

Abstract:
Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

Claim (Index 15):
The apparatus of  claim 14 , wherein:\n the first circuit includes a first logic gate including a first input node coupled to an output node of the first DTC circuit, a second input node coupled to an output node of the second DTC circuit, and an output node to provide the first output clock signal; and the second circuit includes a second logic gate including a first input node coupled to an output node of the third DTC circuit, a second input node coupled to an output node of the fourth DTC circuit, and an output node to provide the second output clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.8
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15391575', '15187382', '15642109', '14573343', '12684908']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6022362494545803
- 35 USC 102 Novelty (BERT): 0.5147668387426272
- Combined Prediction Score: 0.5934893083833851
- Mean Citation Score: 199.249764
- Max Citation Score: 293.2422200000001
- Similarity Product: 233.2258169953681

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test