PATENT CLAIM ANALYSIS

Application Number: 15868343
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["438", "125000"]

Abstract:
Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.

Claim (Index 16):
A method for forming a semiconductor structure, comprising:\n providing a substrate, wherein the substrate includes a device region and a seal ring region surrounding the device region; and forming a first seal ring structure on the seal ring region, the first seal ring structure surrounding the device region, wherein the forming of the first seal ring structure includes:\n forming a first dielectric layer on the substrate; \n forming a lower first connection layer in the first dielectric layer, wherein a topmost surface of the lower first connection layer is leveled with a topmost surface of the first dielectric layer, the lower first connection layer includes a plurality of T-shaped discrete sub-connection layers, and the plurality of T-shaped discrete sub-connection layers are insulated by the first dielectric layer; and \n performing a seal-ring-unit forming process including:\n forming a second dielectric layer on the first dielectric layer and the lower first connection layer; \n forming, in the second dielectric layer, a plurality of via holes and an opening connecting the plurality of via holes, wherein a bottom of a via hole of the plurality of via holes extends into the first dielectric layer between two of the plurality of T-shaped discrete sub-connection layers; and \n filling a conductive material in the plurality of via holes to form a plurality of first conductive plugs and in the opening to form an upper first connection layer simultaneously, wherein the upper first connection layer connects more than one of the plurality of first conductive plugs.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 2.30435
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15220679', '14288494', '15180508', '12756982', '13660392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8647174929063411
- 35 USC 102 Novelty (BERT): 0.5236484338003079
- Combined Prediction Score: 0.8306105869957379
- Mean Citation Score: 257.384892
- Max Citation Score: 351.29297
- Similarity Product: 342.99454731351847

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test