PATENT CLAIM ANALYSIS

Application Number: 15927290
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["385", "014000"]

Abstract:
A method for fabricating a photonic integrated circuit (PIC) comprises providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned on the same or opposite sides of the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide

Claim (Index 26):
The apparatus of  claim 24 , wherein the at least two outer slots each comprise two silicon layers and a cladding layer disposed between the two silicon layers.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.46296
- Patent Class: 385.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15057638', '15689296', '10146351', '15838667', '11710624']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8241930488662074
- 35 USC 102 Novelty (BERT): 0.5015431555558181
- Combined Prediction Score: 0.7919280595351684
- Mean Citation Score: 209.22589
- Max Citation Score: 220.75955
- Similarity Product: 139.5936889958918

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test