PATENT CLAIM ANALYSIS

Application Number: 15941169
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["377", "064000"]

Abstract:
A shift register unit includes an input circuit configured to output a pre-output signal in response to an input signal and a first clock signal, a first output circuit configured to output a first output signal in response to the pre-output signal and a second clock signal; and a second output circuit configured to output a second output signal in response to the pre-output signal and a third clock signal.

Claim (Index 13):
A method of driving a shift register unit, wherein the shift register unit comprises:\n an input terminal for receiving an input signal; a first clock terminal for receiving a first clock signal; a second clock terminal for receiving a second clock signal; a third clock terminal for receiving a third clock signal; a pre-output terminal for outputting a pre-output signal; a first output terminal for outputting a first output signal; a second output terminal for outputting a second output signal; an input circuit configured to output the pre-output signal via the pre-output terminal in response to the input signal and the first clock signal; a first output circuit, connected to the input circuit, configured to output the first output signal via the first output terminal in response to the pre-output signal and the second clock signal; and a second output circuit, coupled to the input circuit, configured to output the second output signal via the second output terminal in response to the pre-output signal and the third clock signal the method comprising: supplying a pulse signal to the input terminal as the input signal, the pulse signal having an active interval 1H defined by a leading edge and a trailing edge; supplying the first clock signal to the first clock terminal, the first clock signal having a period of 2H and a duty cycle of 50%, the first clock signal comprising leading edges where the first clock signal transitions from inactive to active and trailing edges where the first clock signal transitions from active to inactive, one of the leading edges being delayed by 1/2H with respect to the leading edge of the input pulse; supplying the second clock signal to the second clock terminal, the second clock signal having a period of 2H and a duty cycle of 25%, the second clock signal comprising leading edges where the second clock signal transitions from inactive to active and trailing edges where the second clock signal transitions from active to inactive, the leading edges being synchronized with the leading edges of the first clock signal; and supplying the third clock signal to the third clock terminal, the third clock signal being a delayed version of the second clock signal delayed by 1/2H.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.92
- Patent Class: 377.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12012964', '12012845', '15773873', '15103983', '12012846']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6886543375712179
- 35 USC 102 Novelty (BERT): 0.4676281884080905
- Combined Prediction Score: 0.6665517226549051
- Mean Citation Score: 249.769604
- Max Citation Score: 251.78151
- Similarity Product: 214.7318207999146

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test