PATENT CLAIM ANALYSIS

Application Number: 15915733
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["326", "119000"]

Abstract:
Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition process—in lieu of a lithography process—thereby providing for high speed operation and low cost manufacturing.

Claim (Index 1):
An electronic logic gate comprising:\n complementary first and second clock input terminals configured to receive complementary first and second clock signals, respectively; one or more logic input terminals configured to receive one or more logic input signals, respectively; a logic output terminal configured to transmit a logic output signal; a logic network including one or more switching devices, each of the same unipolar type, the logic network configured to perform a logic function, each of the one or more switching devices of the logic network having a control terminal coupled to a corresponding one of the one or more logic input terminals, the logic network configured to modulate conductivity, based on the one or more logic input signals received on the one or more logic input terminals and on the logic function that the logic network is configured to perform, between a first supply net and a pre-evaluation net; a pre-charge network including a switching device of the unipolar type and a charge-storage capacitor, the switching device of the pre-charge network having a control terminal coupled to the first clock input terminal and configured to modulate conductivity, based on the first clock signal received on the first clock input terminal, between a second supply net and a first terminal of the charge-storage capacitor; and a logic clocking network including two switching devices, each of the unipolar type and having a control terminal coupled to the second clock input terminal, the logic clocking network configured to modulate conductivity, based on the second clock signal received on the second clock input terminal, between the logic output terminal and both the first terminal of the charge-storage capacitor and the pre-evaluation net.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 90.0
- Lexical Diversity: 1.44872
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15729470', '15316007', '13851937', '13475332', '10411853']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6750419603569418
- 35 USC 102 Novelty (BERT): 0.5183422954374632
- Combined Prediction Score: 0.6593719938649939
- Mean Citation Score: 251.805512
- Max Citation Score: 353.01053
- Similarity Product: 340.294087478047

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test