PATENT CLAIM ANALYSIS

Application Number: 15885098
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["716", "106000"]

Abstract:
This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.

Claim (Index 19):
The apparatus of  claim 18 , wherein the simstates include a normal state corresponding to a normal power mode and at least one of a corrupt state, a corrupt on activity state, a corrupt state on activity, or a corrupt state on change.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.33333
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14630345', '15885142', '14169418', '14168722', '14168884']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3695788627248038
- 35 USC 102 Novelty (BERT): 0.480753279463788
- Combined Prediction Score: 0.3806963043987022
- Mean Citation Score: 207.71002600000003
- Max Citation Score: 216.38547000000003
- Similarity Product: 142.65237069145024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test