PATENT CLAIM ANALYSIS

Application Number: 16119676
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "369000"]

Abstract:
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

Claim (Index 29):
A semiconductor chip, comprising:\n gate electrode features formed within a region of the semiconductor chip, the gate electrode features positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature in the region having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature positioned thereon, wherein at least one gate electrode feature within the region forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature within the region forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type; and a number of contact structures formed within the region of the semiconductor chip, wherein each gate electrode feature that forms any transistor gate electrode within the region has a respective top surface in physical and electrical contact with a corresponding contact structure having a substantially rectangular shape, wherein each contact structure that contacts a given gate electrode feature that forms any transistor gate electrode does not contact another gate electrode feature, wherein any contact structure that has a corresponding length greater than or equal to a corresponding width is oriented to have its corresponding length extend in an x-direction, wherein each transistor within the region is formed in part by a corresponding diffusion region, wherein each diffusion region that forms part of any transistor within the region has a substantially rectangular shape, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form a portion of a multiplexer or a portion of a latch.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 2.93478
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16119727', '16119794', '15688187', '15696728', '15696651']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9353731660031954
- 35 USC 102 Novelty (BERT): 0.5833266130092181
- Combined Prediction Score: 0.9001685107037978
- Mean Citation Score: 451.083808
- Max Citation Score: 471.4597
- Similarity Product: 461.9833611990094

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test