PATENT CLAIM ANALYSIS

Application Number: 16027263
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["710", "316000"]

Abstract:
A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.

Claim (Index 14):
The reconfigurable pin-to-pin interface of  claim 13 , wherein the fourth switch circuit is further coupled to the output port and the clock input port of the sixth lane circuit, and is arranged to:\n selectively redirect the first received signal at the output port of the first lane circuit to the clock input ports of four lane circuits selected from the second lane circuit, the third lane circuit, the fourth lane circuit, the fifth lane circuit and the sixth lane circuit; selectively redirect the second received signal at the output port of the second lane circuit to the clock input ports of four lane circuits selected from the first lane circuit, the third lane circuit, the fourth lane circuit, the fifth lane circuit and the sixth lane circuit; selectively redirect the third received signal at the output port of the third lane circuit to the clock input ports of four lane circuits selected from the first lane circuit, the second lane circuit, the fourth lane circuit, the fifth lane circuit and the sixth lane circuit; selectively redirect the fourth received signal at the output port of the fourth lane circuit to the clock input ports of four lane circuits selected from the first lane circuit, the second lane circuit, the third lane circuit, the fifth lane circuit and the sixth lane circuit; selectively redirect the fifth received signal at the output port of the fifth lane circuit to the clock input ports of four lane circuits selected from the first lane circuit, the second lane circuit, the third lane circuit, the fourth lane circuit and the sixth lane circuit; and selectively redirect the sixth received signal at the output port of the sixth lane circuit to the clock input ports of four lane circuits selected from the first lane circuit, the second lane circuit, the third lane circuit, the fourth lane circuit and the fifth lane.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 3.58537
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15262280', '14491884', '14250119', '14939692', '14462327']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6948921939293808
- 35 USC 102 Novelty (BERT): 0.4797012702404295
- Combined Prediction Score: 0.6733731015604857
- Mean Citation Score: 173.56991999999997
- Max Citation Score: 181.8552
- Similarity Product: 127.83653294205664

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test