PATENT CLAIM ANALYSIS

Application Number: 16282607
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-06
Patent Classification: ["257", "347000"]

Abstract:
A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.

Claim (Index 9):
The structure according to  claim 4 , wherein the layer of TiN is continuous between the nanosheets.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 99.0
- Lexical Diversity: 1.97727
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15146325', '14744659', '16128869', '15941525', '14706114']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239919708543828
- 35 USC 102 Novelty (BERT): 0.5335890193297234
- Combined Prediction Score: 0.8849516757019169
- Mean Citation Score: 219.338686
- Max Citation Score: 361.2728
- Similarity Product: 247.8485765560627

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test