PATENT CLAIM ANALYSIS

Application Number: 15910939
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "350000"]

Abstract:
Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Claim (Index 8):
The invention of  claim 6 , wherein the bypass module includes a bypass FET having a gate, a drain, a source, and a gate resistor series connected to the gate of the bypass FET, wherein the source and drain of the bypass FET are coupled across the selectable resistor, and the gate resistor of the bypass FET is coupled to the control signal input.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 90.0
- Lexical Diversity: 1.37838
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15495819', '14521378', '11881816', '13053211', '14845154']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9026516414148263
- 35 USC 102 Novelty (BERT): 0.5620026547264179
- Combined Prediction Score: 0.8685867427459856
- Mean Citation Score: 251.848228
- Max Citation Score: 444.33496
- Similarity Product: 361.6992823566675

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test