PATENT CLAIM ANALYSIS

Application Number: 16191429
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["365", "096000"]

Abstract:
Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.

Claim (Index 12):
The PRD memory as recited in  claim 11 , wherein the OTP element has at least one of the electrical fuse constructed from at least one of silicided polysilicon, silicide, metal, metal gate, thermally isolated silicon, FinFET, or interconnect between FinFET.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.83673
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14940012', '14101125', '14485698', '15805109', '15708116']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7931714291732478
- 35 USC 102 Novelty (BERT): 0.510397979034775
- Combined Prediction Score: 0.7648940841594005
- Mean Citation Score: 286.3937
- Max Citation Score: 316.13547
- Similarity Product: 240.10369194561488

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test