PATENT CLAIM ANALYSIS

Application Number: 15966775
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-12
Patent Classification: ["714", "011000"]

Abstract:
A redundant computer system utilizing comparison diagnostics and voting techniques includes a plurality of redundant channels. Each pair of the processors receives/obtains process information from I/O modules via dual redundant sensors (DRS). The processors execute an application program, whereby output module is utilized for comparing output data of the two processors. Output module receives output data from neighboring modules, if there is a deviation or other disparity in the output data. Each pair of processors, a voter and an improper sequence detector component disables the output module, if a majority of signals vote that output module fails. In addition, the system uses 2-of-3 voting, the system remains operational in the presence of up two transient or hard failures.

Claim (Index 4):
A redundant computer system comprising:\n a first channel, a second channel each channel comprising:\n a first central processor and a second central processor that operate in parallel redundancy; \n said first central processor is in operative communication with said secondary central processor; \n a first input module and a second input module is in operative communication with said first central processor and with said second central processor via the associated interfaces; \n said first input module and said second input module is coupled with a single sensor for each controlled point for delivering an input data of the process to the first processor and to the second processor respectively; \n said first and second control processor use said input data for synchronously execute an application program and for transfer an output data as a result of said application program execution to said output module in normal system operation; \n said output module includes an output controller, a voter and an improper sequence components, a logic circuit, and a voting network; \n said first output controller is in operative communication with said first central processor via said first interface and is in operative communication with said second central processor via said second interface; \n said second output controller is in operative communication with said second central processor via said first interface and is in operative communication with said first central processor via said second interface; \n a first voter component and a second voter component that is in operative communication with said primary central processor and with secondary central processor; \n an improper sequence detector that verify absence or presence a fault in timetable and verify a consistency of program operations of said output controller; \n said output controller is in operative communication with the associated logic circuit in said first and second channel; \n a comparing diagnostic in said first central processor (FCP) and said second central processor (SCP) in each channel for monitoring condition of said output module, said comparing diagnostic includes a voter component and includes an improper sequence detector (ISD) component; \n said comparison diagnostic allows the system for disabling said output module if at least two elements among the FCP, the SCP, and the ISD vote that said output controller fails; \n said comparison diagnostic having no single point of failure allows the system to operate with one working output controller in the event that neighboring output controller fails; \n said output controller connected via a read only bus with a neighboring output controller for receiving/sending said output data from/to said neighboring output controller; \n said output controller activates a disparity signal on inputs of said logic circuit for some controlled points if said output controller receive different data from said first and second control processor due to occurrence of some transient faults; \n said disparity signal is activated as a result of an Exclusive NOR (XNOR) operation between output data that said output controller receives from said first and second central processors; \n said output data is substitutes by the output data produced by neighboring output controller for some controlled points if said disparity signal is activated for said controlled points; \n the system continues operate if said disparity occurs in only one output controller, the system performs a safe shutdown for the process, if said disparity occurs in output controllers in said first a second channels concurrently; \n said logic circuit is in operative communication with said output controller and in operative communication with a voting network, which contains multiple switches in series; said switches in said first a second channels connected in parallel for each controlled point; \n each logic circuit and each voting network receives said output data from said first and second central processor via said output controller, said logic circuit and voting network perform a certain logic operation with said output data to provide said 2-of-2 voting among output data that produced by said first and second central processor; \n means in said first and second central processor to use an additional separate buses that provide operative communication with both first and second output controllers; \n said means provide the system continues to be operational in the presence of two faults: in first control processor and in second output controller, or in second central processor and in first output controller; \n the system continues to be operational in the presence of any single fault and may operate in the presence of some kind of two faults; \n the system energizes controlled process in the fault free operation when both first and second central processor and associating components operating properly and de-energizes said process in the presence of two dangerous failures in the system.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 1.67089
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12316966', '10899667', '11923534', '10758977', '11389349']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2472024893052581
- 35 USC 102 Novelty (BERT): 0.5035538001723332
- Combined Prediction Score: 0.2728376203919657
- Mean Citation Score: 185.776398
- Max Citation Score: 281.1801
- Similarity Product: 229.2043838344395

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test