PATENT CLAIM ANALYSIS

Application Number: 15938176
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "330000"]

Abstract:
A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.

Claim (Index 18):
A method for manufacturing a semiconductor device, comprising the steps of:\n forming a first insulating layer on a substrate; forming an opening in the first insulating layer and etching the substrate exposed inside the opening to form a first trench and a second trench; forming a gate insulating film so as to cover bottom and side surfaces inside the first trench and the second trench; embedding the first trench and the second trench and depositing a gate layer until an upper surface thereof becomes flat; etching back the gate layer until the upper surface thereof reaches a prescribed height between the bottom surfaces inside the first trench and the second trench and a surface of the substrate to form a gate electrode; embedding the first trench and the second trench and depositing a second insulating layer until an upper surface thereof becomes flat; etching back the second insulating layer until an upper surface of the first insulating layer is exposed; selectively etching the second insulating layer on the gate electrode inside the second trench to expose the gage electrode; selectively etching the first insulating layer around the first trench to expose the surface of the substrate around the first trench; depositing a third insulating layer with a film thickness at which the second trench is not completely embedded therewith; anisotropically etching the third insulating layer to expose the surface of the substrate and leaving a sidewall insulation region on the side surface on the gate electrode in the second trench; and embedding and forming a gate metal in contact with the gate electrode in a region surrounded by the sidewall insulation region in the second trench.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.78723
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12412962', '15872747', '11455888', '11772341', '13811057']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9197564091467266
- 35 USC 102 Novelty (BERT): 0.48145862658496
- Combined Prediction Score: 0.8759266308905499
- Mean Citation Score: 232.305004
- Max Citation Score: 234.76169
- Similarity Product: 197.10597714197337

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test