PATENT CLAIM ANALYSIS

Application Number: 16149621
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-01
Patent Classification: ["257", "027000"]

Abstract:
In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.

Claim (Index 17):
The method of  claim 16 , wherein the work function-controlling region is formed to overlap at least one of the second gates.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 97.0
- Lexical Diversity: 2.17949
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15371358', '15252568', '11003421', '11422663', '15367368']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9193818267242788
- 35 USC 102 Novelty (BERT): 0.5323735700265159
- Combined Prediction Score: 0.8806810010545025
- Mean Citation Score: 213.802214
- Max Citation Score: 349.2327
- Similarity Product: 207.11274522324803

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test