PATENT CLAIM ANALYSIS

Application Number: 15961157
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "427000"]

Abstract:
The present disclosure provides a method for manufacturing the semiconductor structure. The method includes forming an N th  metal layer, forming a plurality of magnetic tunneling junctions (MTJs) over the N th  metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, forming a top electrode via concaving upward over each of the plurality of MTJs, and forming an (N+M) th  metal layer over the plurality of MTJs. A semiconductor structure manufactured according to present disclosure is also provided.

Claim (Index 4):
The semiconductor structure of  claim 3 , wherein the planarization etch stop layer having a discrete pattern staggering from the plurality of MTJs from a top view perspective.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 1.88235
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15933777', '15151207', '15867427', '14948046', '15130216']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9088746904340108
- 35 USC 102 Novelty (BERT): 0.5092822532556064
- Combined Prediction Score: 0.8689154467161704
- Mean Citation Score: 208.27046
- Max Citation Score: 213.8969
- Similarity Product: 134.2691211134672

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test