PATENT CLAIM ANALYSIS

Application Number: 16039995
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["365", "154000"]

Abstract:
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Claim (Index 17):
The method of  claim 14 , wherein:\n sending the clock enabling signal comprises sending the clock enabling signal to activate clocking a plurality of flip-flops; and latching the command/address signals comprises latching the command/address signals from an input of each of the plurality of flip-flops to an output of each of the plurality of flip-flops.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 95.0
- Lexical Diversity: 2.06061
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15693194', '15649145', '16013813', '15714743', '12801182']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8097912414663024
- 35 USC 102 Novelty (BERT): 0.5359487640185226
- Combined Prediction Score: 0.7824069937215244
- Mean Citation Score: 246.97540400000003
- Max Citation Score: 387.8294
- Similarity Product: 367.4342560617805

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test