PATENT CLAIM ANALYSIS

Application Number: 16204750
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "194000"]

Abstract:
One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.

Claim (Index 1):
A controller for controlling operation of a memory device, the controller comprising:\n a data processing circuit configured to process read data and write data through a data terminal based on a chip select signal, an address signal, a command signal, and a clock signal supplied by an output circuit; wherein the controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 98.0
- Lexical Diversity: 2.55814
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15875574', '15229417', '14733924', '13615430', '14268827']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7769151159159645
- 35 USC 102 Novelty (BERT): 0.4680216113170619
- Combined Prediction Score: 0.7460257654560742
- Mean Citation Score: 239.554308
- Max Citation Score: 240.04129
- Similarity Product: 236.345185322783

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test