PATENT CLAIM ANALYSIS

Application Number: 15957428
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-06
Patent Classification: ["257", "329000"]

Abstract:
The present disclosure provides a semiconductor device including a substrate, an n− type layer, an n+ type region, a p type region, a p+ type region, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode, wherein the n+ type region is disposed at a left side and a right side of the n− type layer in a plan view and configured to form in a striped pattern in a plan view, wherein the p+ type region is disposed at an outer surface of the n+ type region in a plan view and configured to form in a striped pattern in a plan view, wherein the p type region is disposed at an inner surface the n+ type region in a plan view and is separated by a predetermined interval along a longitudinal direction of the n+ type region in a plan view.

Claim (Index 2):
The semiconductor device of  claim 1 , wherein:\n the n\u2212 type layer is disposed between the p type regions.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 3.05769
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15828898', '14939904', '12820252', '12238556', '15203981']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907742087588904
- 35 USC 102 Novelty (BERT): 0.5035335710446844
- Combined Prediction Score: 0.867321235934482
- Mean Citation Score: 202.470234
- Max Citation Score: 228.41286
- Similarity Product: 161.91686057925224

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test