PATENT CLAIM ANALYSIS

Application Number: 15896404
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["438", "300000"]

Abstract:
A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Claim (Index 2):
The method of  claim 1 , further comprising:\n performing a chemical mechanical planarization (CMP) process on an upper surface of the first dielectric layer, an upper surface of the metal buffer layer and an upper surface of the metal gate.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 88.0
- Lexical Diversity: 1.78261
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15299864', '14492595', '11583500', '15274087', '15354212']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8389027375356989
- 35 USC 102 Novelty (BERT): 0.5269341361657458
- Combined Prediction Score: 0.8077058773987036
- Mean Citation Score: 252.74455200000003
- Max Citation Score: 320.2966
- Similarity Product: 224.59934779775145

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test