PATENT CLAIM ANALYSIS

Application Number: 15960492
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "369000"]

Abstract:
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Claim (Index 1):
A semiconductor integrated circuit device comprising:\n (a) a semiconductor substrate having a first main surface; (b) an embedded SRAM region which is provided on the first main surface side of the semiconductor substrate; (c) a memory cell arrangement region which is provided within the SRAM region; and (d) a large number of memory cell regions which are provided in a matrix within the memory cell arrangement region, wherein each memory cell region has a rectangular shape including a long side and a short side when seen in a plan view, each memory cell region including (d1) a first well region having a first conductivity type which is provided at a central portion, with respect to the long side, (d2) a second well region and a third well region having a second conductivity type which are provided on both sides of the first well region, with respect to the long side, (d3) a first bit line and a second bit line that extend in a direction perpendicular to the long side and form a mutually complementary pair, (d4) a third bit line and a fourth bit line that extend in a direction perpendicular to the long side and form a mutually complementary pair, and (d5) a fifth bit line and a sixth bit line that extend in a direction perpendicular to the long side and form a mutually complementary pair.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.94737
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14909135', '15338390', '15635970', '15795502', '14490235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9187627469245856
- 35 USC 102 Novelty (BERT): 0.5939274055822593
- Combined Prediction Score: 0.8862792127903532
- Mean Citation Score: 377.603038
- Max Citation Score: 496.8272
- Similarity Product: 462.55278332910535

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test