PATENT CLAIM ANALYSIS

Application Number: 15948737
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "185170"]

Abstract:
A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.

Claim (Index 14):
The memory device of  claim 1 , wherein:\n the memory device comprises a vertical NAND device located over the substrate; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device; the substrate comprises a silicon substrate; the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and the array of monolithic three-dimensional NAND strings comprises:\n a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; \n a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and \n a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprising at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.09589
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15078555', '15850073', '15704286', '15496359', '15628495']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8314755505744797
- 35 USC 102 Novelty (BERT): 0.5733341841820503
- Combined Prediction Score: 0.8056614139352368
- Mean Citation Score: 380.482124
- Max Citation Score: 493.9241
- Similarity Product: 433.2091947206318

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test