PATENT CLAIM ANALYSIS

Application Number: 15871818
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "324000"]

Abstract:
In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

Claim (Index 11):
A semiconductor device having:\n a semiconductor substrate; a first gate electrode formed over the semiconductor substrate in a first region via a first insulation film including a charge accumulation film; a first offset spacer formed of a second insulation film covering the side surface of the first gate electrode; first source/drain regions formed at the top surface of the semiconductor substrate in the first region; a second gate electrode formed over the semiconductor substrate in a second region via a third insulation film; a second offset spacer formed of a fourth insulation film covering the side surface of the second gate electrode; and second source/drain regions formed at the top surface of the semiconductor substrate in the second region, wherein a first transistor including the first gate electrode and the first source/drain regions forms a nonvolatile storage element, wherein a second transistor including the second gate electrode and the second source/drain regions forms a selection transistor, wherein the first transistor and the second transistor form one memory cell, and are coupled in series with each other, wherein in the gate length direction of the first gate electrode, the ends of the first insulation film protrude outwardly from the side surfaces of the first gate electrode, respectively, and wherein in the gate length direction of the second gate electrode, the ends of the third insulation film protrude outwardly from the side surfaces of the second gate electrode, respectively.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.26984
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13964576', '15011510', '15661649', '14921445', '15468673']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.937833880437324
- 35 USC 102 Novelty (BERT): 0.5160778501325962
- Combined Prediction Score: 0.8956582774068511
- Mean Citation Score: 295.1903220000001
- Max Citation Score: 312.2362
- Similarity Product: 250.8730572264672

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test