PATENT CLAIM ANALYSIS

Application Number: 15870503
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "347000"]

Abstract:
There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claim (Index 5):
The semiconductor device according to  claim 4 , wherein\n the fourth diffusion layer is connected to the second reference potential.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.09211
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15064686', '13583409', '14598364', '15369054', '11770238']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9269326605315962
- 35 USC 102 Novelty (BERT): 0.5117093622524937
- Combined Prediction Score: 0.8854103307036859
- Mean Citation Score: 249.631132
- Max Citation Score: 287.56653
- Similarity Product: 207.1157168575859

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test