PATENT CLAIM ANALYSIS

Application Number: 16043674
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["257", "331000"]

Abstract:
Trench gate power MOSFET with an on-region. Cells in the on-region include a first epitaxial layer and a channel region. First trenches corresponding to polysilicon gates penetrate through the channel region, and each polysilicon gate is etched to form a groove in the top, the grooves filled with an interlayer film. A source region formed on side faces of the grooves in a self-aligned mode through angled ion implantation. Through the source region of a side structure, the surface of a portion, between the first trenches, of the channel region is directly exposed and formed with a well contact region. A front metal layer is formed on the surfaces of the cells in the on-region and leads out a source. The front metal layer of the source directly makes contact with well contact region and source region to form a connection structure without contact holes.

Claim (Index 10):
The manufacturing method of the trench gate power MOSFET according to  claim 8 , wherein a gate lead-out region is located outside the on-region and comprise a second trench wider than the first trench, and the second trench and the first trench are connected and formed at the same time in Step 2;\n a gate dielectric layer is formed on a bottom surface and side faces of the second trench, the second trench is filled with a polysilicon gate made of polysilicon, the gate dielectric layer in the second trench and the gate dielectric layers in the first trench are formed at the same time in Step 3, and the polysilicon gate in the second trench and the polysilicon gate in the first trench are formed at the same time in Step 3 and are connected with each other; in Step 4, the polysilicon gate in the second trench is etched back until a top surface of the polysilicon gate is higher than or as high as a top surface of the second trench; in Step 5, the source region obtained through angled ions implantation is not formed in the channel region located on the side face of the second trench; in Step 7, before the interlayer film is etched back, a formation area of a contact hole is opened at a top of the second trench by a photolithograph process, and after the interlayer film is etched back, an opening of the contact hole is formed in a top of the polysilicon gate in the second trench; and in Step 9, after the front metal layer is patterned, a gate is also formed, and the gate is connected to the polysilicon gate in the second trench through the corresponding contact hole and also connected to the polysilicon gate in the first trench through the polysilicon gate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 2.24286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12137527', '14771089', '12458293', '13377029', '14019159']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9156385566555076
- 35 USC 102 Novelty (BERT): 0.5034876533408102
- Combined Prediction Score: 0.874423466324038
- Mean Citation Score: 249.28664
- Max Citation Score: 260.66483
- Similarity Product: 209.804194029398

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test