PATENT CLAIM ANALYSIS

Application Number: 16007619
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["717", "106000"]

Abstract:
An accelerator image generator includes a synthesis block and a simulation block. The accelerator image generator receives a hardware description language representation for a desired function, inputs the hardware description language representation for the desired function to the synthesis block and to the simulation block so the synthesis block and simulation block work in parallel, monitors progress of the synthesis block and the simulation block, and when a defined threshold is reached in the synthesis block, halts the simulation block while the synthesis block continues until the synthesis block outputs an accelerator image for deployment to a programmable device. When an error is detected in the synthesis block following halting of the simulation block, the simulation block may be resumed, and the defined threshold may be adjusted. The accelerator image can be deployed to a programmable device to provide a hardware accelerator corresponding to the accelerator image.

Claim (Index 10):
An apparatus comprising:\n at least one processor; a memory coupled to the at least one processor; an accelerator image generator residing in the memory and executed by the at least one processor, the accelerator image generator comprising:\n a synthesis block that comprises circuit synthesis, place and route, timing analysis, hardware test, and a synthesis debug feedback path; \n a first simulation block that comprises first computer simulation, first simulation test, and a first simulation debug feedback path; \n a second simulation block in parallel with the first simulation block that comprises second computer simulation, second simulation test, and a second simulation debug feedback path; and \n a synthesis and simulation controller that receives a hardware description language representation for a desired function, inputs the hardware description language representation for the desired function to the synthesis block and to the first and second simulation blocks so the synthesis block and first and second simulation blocks work in parallel, monitors progress of the synthesis block and the simulation blocks, feeds results from the simulation blocks into the synthesis block, and when a confidence threshold for the synthesis block is reached, halts the simulation blocks while the synthesis block continues, detects an error in the synthesis block after halting the simulation blocks, and in response, resumes the simulation blocks and adjusts the confidence threshold to a higher specified completion percentage for the synthesis block, and when the adjusted confidence threshold for the synthesis block is reached, halts the simulation blocks while the synthesis block continues until the synthesis block outputs an accelerator image; \n an accelerator deployment tool residing in the memory and executed by the at least one processor, wherein the accelerator deployment tool receives the accelerator image from the accelerator image generator and deploys the accelerator image to a programmable device to provide a hardware accelerator corresponding to the accelerator image.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 94.0
- Lexical Diversity: 2.7069
- Patent Class: 717.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15849582', '15964166', '15964115', '11607452', '15334182']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.387170647952534
- 35 USC 102 Novelty (BERT): 0.5228186063376453
- Combined Prediction Score: 0.4007354437910452
- Mean Citation Score: 222.493754
- Max Citation Score: 286.16226
- Similarity Product: 196.2752068371105

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test