PATENT CLAIM ANALYSIS

Application Number: 16080101
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["257", "043000"]

Abstract:
Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.

Claim (Index 15):
The transistor of  claim 14 , wherein the multilayer gate oxide wraps entirely around the wire.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 96.0
- Lexical Diversity: 2.02564
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14135534', '14138750', '15777744', '14133521', '15197606']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9176927151886964
- 35 USC 102 Novelty (BERT): 0.4999489502756745
- Combined Prediction Score: 0.8759183386973942
- Mean Citation Score: 174.36705600000005
- Max Citation Score: 175.63074
- Similarity Product: 104.00150709508542

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test