PATENT CLAIM ANALYSIS

Application Number: 15934804
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["714", "700000"]

Abstract:
A byte lane of an integrated circuit including two data strobe loopback paths that allow external test signals to flow in and out of the integrated circuit through data strobe pins in two opposite directions. The integrated circuit includes a Feed Forward Equalization (FFE) path configured to send FFE signals output from the FFE logic via a transmitter set to a first data strobe interface during a normal operation. In a loopback test mode operation, a test signal can be supplied from a second data strobe interface and output to the first data strobe interface by reusing the FFE path. The second loopback path conversely allows a test signal to be routed from the first data strobe interface to the second.

Claim (Index 13):
The memory controller of  claim 11 , wherein said interface circuitry further comprising: a first receiver and a third transmitter set both coupled to said first data strobe interface; and a second receiver coupled to said second data strobe interface, and wherein said first external loopback path comprises said first receiver and said second external loopback path comprises said second receiver.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 90.0
- Lexical Diversity: 1.96923
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13559741', '12972977', '11802846', '14036709', '13079391']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3054733977389064
- 35 USC 102 Novelty (BERT): 0.4961847629066852
- Combined Prediction Score: 0.3245445342556843
- Mean Citation Score: 231.00518
- Max Citation Score: 260.0033
- Similarity Product: 187.8964656867921

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test