PATENT CLAIM ANALYSIS

Application Number: 15741742
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["377", "064000"]

Abstract:
The present application discloses a shift, register circuit having a plurality of shift register units cascaded in series. The shift register circuit includes a first shift register unit and a second shift register unit. The first shift register unit includes a first pull-up node and a first output terminal and the second shift register unit includes a second pull-up node and a second output terminal. The shift register circuit includes a stabilizer circuit coupled to both the first shift register unit and the second shift register unit such that the first pull-up node is directly connected to the second pull-up node as a common pull-up node and configured to maintain a potential level of the common pull-up node stable during a stabilizing period when none of the first output terminal and the second output terminal output a turn-on signal.

Claim (Index 6):
The shift register circuit of  claim 4 , wherein the first clock signal comprises a waveform characterized by a high-voltage signal with 50% duty cycle in a first period of 4t, where t is a line of image time corresponding to displaying one line of image; the second clock signal comprises a waveform characterized by a high-voltage pulse signal with 50% duty cycle in a second period of 4t and provided with a time delay oft relative to the first clock signal; the common control signal comprises a high voltage during one frame of image time with an odd serial number to make the potential level of the shared pull-down node of the first shift register unit at high shared with the second shift register unit to maintain potential levels of the common pull-up node, the first output terminal, and the second output terminal at low in the stabilizing period within the one frame of image time with the odd serial number, and the common control signal comprises a high voltage during one frame of image time with an even serial number to make the potential level of the shared pull-down node of the second shift register unit at high shared with the first shift register unit to maintain potential levels of the common pull-up node, the first output terminal, and the second output terminal at low in the stabilizing period within the one frame of image time with the even serial number.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 86.0
- Lexical Diversity: 2.88
- Patent Class: 377.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15752518', '15520557', '15529731', '15506398', '15327852']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7719841901346831
- 35 USC 102 Novelty (BERT): 0.5025318364852197
- Combined Prediction Score: 0.7450389547697368
- Mean Citation Score: 333.4888660000001
- Max Citation Score: 342.74957
- Similarity Product: 236.9172323113221

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test