PATENT CLAIM ANALYSIS

Application Number: 15917443
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["345", "690000"]

Abstract:
Provided are a display panel and a display device. A pixel circuit in the disclosed display panel includes a driving module, a data writing module, a storage module, and at least one control module. The data writing module is configured to write a data signal into a control terminal of the driving module. The storage module is electrically connected to the control terminal of the driving module for maintaining a voltage on the control terminal of the driving module in an emit-lighting phase. The control module is electrically connected to the control terminal of the driving module for writing a signal into the control terminal of the driving module prior to the light-emitting stage. At least one hollowed structure is provided on the continuous gate structure of the control transistor of the control module. At least one channel's width-to-length ratio is different from others among the overlapping portions' channels.

Claim (Index 11):
The display panel according to  claim 9 ,\n wherein the data writing module comprises a data writing transistor, the driving module comprises a driving transistor, the first light-emitting control module comprises a first light-emitting control transistor, the second light-emitting module comprises a second light-emitting control transistor, the bypass module comprises a bypass transistor, and the storage module comprises a storage capacitor; wherein a gate electrode of the initialization transistor is electrically connected to the second scan signal input terminal, a first electrode thereof is electrically connected to the reference voltage signal input terminal, and a second electrode thereof is electrically connected to a gate electrode of the driving transistor; wherein a gate electrode of the data writing transistor is electrically connected to the first scan signal input terminal, a first electrode thereof is electrically connected to the data signal input terminal, and a second electrode thereof is electrically connected to a first electrode of the driving transistor; wherein a gate electrode of the threshold voltage compensation transistor is electrically connected to the first scan signal input terminal, a first electrode thereof is electrically connected to a second electrode of the driving transistor, and a second electrode thereof is electrically connected to the gate electrode of the driving transistor; wherein a gate electrode of the first light-emitting control transistor is electrically connected to the enable signal input terminal, a first electrode thereof is electrically connected to the first power signal input terminal, and a second electrode thereof is electrically connected to the first electrode of the driving transistor; wherein a gate electrode of the second light-emitting control transistor is electrically connected to the enable signal input terminal, a first electrode thereof is electrically connected to a second electrode of the driving transistor, a second electrode thereof is electrically connected to a first electrode of the organic light-emitting device; wherein a gate electrode of the bypass transistor is electrically connected to the second scan signal input terminal, a first electrode thereof is electrically connected to the first electrode of the organic light-emitting device, and a second electrode thereof is electrically connected to the reference voltage signal input terminal; and wherein a first electrode of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second electrode thereof is electrically connected to the first power signal input terminal.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.47692
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15593929', '15593734', '15668699', '15116624', '14348296']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6849440126853925
- 35 USC 102 Novelty (BERT): 0.4748074777266454
- Combined Prediction Score: 0.6639303591895178
- Mean Citation Score: 226.116042
- Max Citation Score: 227.53497
- Similarity Product: 202.22786559694111

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test