PATENT CLAIM ANALYSIS

Application Number: 16046273
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "383000"]

Abstract:
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.

Claim (Index 17):
The vertical finFET of  claim 15 , wherein the first doped layer region is silicon germanium (SiGe) doped with boron to form a p-type FET.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.4
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15177358', '15177362', '15353352', '15695688', '15789620']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.941407151305282
- 35 USC 102 Novelty (BERT): 0.5653866504688091
- Combined Prediction Score: 0.9038051012216348
- Mean Citation Score: 383.768
- Max Citation Score: 449.61224
- Similarity Product: 395.60024008845335

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test