PATENT CLAIM ANALYSIS

Application Number: 16126590
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["716", "115000"]

Abstract:
A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Claim (Index 10):
A computer system for performing a coupled noise analysis in designing an integrated circuit (IC), comprising:\n a memory device storing machine executable instructions; and at least one processing device coupled to the memory device, the at least one processing device configured to run the machine executable instructions to perform: copying one or more victim circuit sections of a victim circuit in the IC; generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, wherein the one or more victim circuit sections are directly connected to the blockage circuit section through at least one coupling capacitor; determining a first subcircuit from the blockage circuit section, wherein circuit elements constituting the first subcircuit are all connected one to another within the blockage circuit section, selecting, for a first victim pin on the victim circuit, a first power-driven virtual node on the first subcircuit; applying a first power source to the selected first power-driven virtual node on the first subcircuit; calculating a first coupled noise at the first victim pin contributed by the first subcircuit in response to the first power source being applied; pre-determining, using computer-based simulation, a threshold noise level for said victim circuit; comparing the first coupled noise at the first victim pin to the threshold noise level; and altering the IC design when the first coupled noise exceeds the threshold noise level.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.48485
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15288260', '12203115', '10313866', '12203128', '14067720']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.286925575853046
- 35 USC 102 Novelty (BERT): 0.5621284536758511
- Combined Prediction Score: 0.3144458636353265
- Mean Citation Score: 242.930608
- Max Citation Score: 460.21472
- Similarity Product: 425.74829890930175

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test