PATENT CLAIM ANALYSIS

Application Number: 16229250
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "777000"]

Abstract:
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

Claim (Index 4):
The package of  claim 1 , wherein the first dielectric layer has a first hardness that is harder than a hardness of the second dielectric layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 3.12195
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15919897', '14132709', '14323960', '13789866', '15272491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9096168946493842
- 35 USC 102 Novelty (BERT): 0.5163095604908241
- Combined Prediction Score: 0.8702861612335282
- Mean Citation Score: 214.150304
- Max Citation Score: 257.70383
- Similarity Product: 168.47472429590226

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test