PATENT CLAIM ANALYSIS

Application Number: 16184827
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["365", "145000"]

Abstract:
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

Claim (Index 11):
The method of  claim 2 , further comprising:\n updating a value of a counter based at least in part on the first voltage being applied across the memory cell, wherein the second voltage is applied based at least in part on the value of the counter.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.89706
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15197416', '15438462', '15858831', '15641020', '15291711']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8034867380439422
- 35 USC 102 Novelty (BERT): 0.5033397247769054
- Combined Prediction Score: 0.7734720367172385
- Mean Citation Score: 265.85141600000003
- Max Citation Score: 298.3122600000001
- Similarity Product: 236.39005015573392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test