PATENT CLAIM ANALYSIS

Application Number: 16130034
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-08
Patent Classification: ["365", "203000"]

Abstract:
A memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including the plurality of memory cells, and a driving determination unit determining whether to perform at least one of a pre-charging operation, a development operation and a latching operation of page buffers connected to the memory cells provided with the read voltage.

Claim (Index 4):
The memory device of  claim 2 , wherein the processing circuitry is configured to select some of the plurality of the page buffers such that bit lines connected to the selected page buffers are spaced apart from each other by an interval.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 1.72973
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13948557', '15341253', '16047384', '13289463', '14639331']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8169369825836899
- 35 USC 102 Novelty (BERT): 0.4878685650608501
- Combined Prediction Score: 0.784030140831406
- Mean Citation Score: 223.702248
- Max Citation Score: 245.9541
- Similarity Product: 188.1886889571905

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test