PATENT CLAIM ANALYSIS

Application Number: 16166010
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["712", "205000"]

Abstract:
Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Claim (Index 5):
The processor of  claim 1 , wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.01818
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14216493', '15862496', '15257593', '14215633', '13359767']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5833499782287279
- 35 USC 102 Novelty (BERT): 0.60006590829383
- Combined Prediction Score: 0.5850215712352381
- Mean Citation Score: 312.69396400000005
- Max Citation Score: 528.21454
- Similarity Product: 482.53488156091095

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test