PATENT CLAIM ANALYSIS

Application Number: 16017286
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-09
Patent Classification: ["327", "261000"]

Abstract:
A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.

Claim (Index 20):
The system of  claim 19 , further comprising:\n a comparator circuit configured to:\n compare a sampled bit sequence bit with a reference bit sequence for a read training process; and \n generate a comparison result signal based on the comparison, \n wherein the write training controller is configured to adjust the clock delay and the data delays in response to receipt of the comparison result signal.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 94.0
- Lexical Diversity: 1.94643
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16008678', '16008640', '13584091', '12318306', '10931358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.761278463714864
- 35 USC 102 Novelty (BERT): 0.4785731694531404
- Combined Prediction Score: 0.7330079342886916
- Mean Citation Score: 181.421728
- Max Citation Score: 195.55617
- Similarity Product: 141.585798083151

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test