PATENT CLAIM ANALYSIS

Application Number: 16003337
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["327", "115000"]

Abstract:
Aspects of the disclosure are directed to multi-module frequency division. As may be implemented in accordance with one or more embodiments herein, an apparatus includes latching circuitry having three or fewer vertically-stacked transistors between power rails, which operate to provide output signals from input signals, the output signals having a frequency that is a divided representation of the frequency of the input signals. A pulse widening circuit modifies the output signals by widening a pulse thereof, providing a modified output signal. A further latching circuit may be utilized to perform a further frequency division of the modified output signal. The respective latching circuitry can be used to selectively provide frequency-divided output signals from input signals at respective divided frequencies.

Claim (Index 2):
The multi-module frequency divider circuit of  claim 1 , wherein the first latching circuit has multiple latches, each having no more than three vertically-stacked transistors.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.82857
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13099074', '12212538', '10771488', '10815162', '10880990']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7780502526972453
- 35 USC 102 Novelty (BERT): 0.4778058587654105
- Combined Prediction Score: 0.7480258133040618
- Mean Citation Score: 177.78888
- Max Citation Score: 188.12112
- Similarity Product: 137.7002070658207

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test