PATENT CLAIM ANALYSIS

Application Number: 15873438
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "389000"]

Abstract:
A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Claim (Index 1):
A semiconductor device comprising:\n a substrate; a nitride semiconductor layer formed on the substrate, the nitride semiconductor layer including an element region and a high resistance region; a first source electrode, a first drain electrode and a first gate electrode, each of which is formed on the element region of the nitride semiconductor layer; and a first gate wire layer formed on the nitride semiconductor layer and connected to the first gate electrode, wherein: a resistance of the high resistance region is higher than a resistance of the element region, the first gate electrode includes a first extending portion and a second extending portion, arranged in parallel with each other, the first gate wire layer includes (i) a first portion from which the first and second extending portions of the first gate electrode protrude, and (ii) a second portion is not in direct contact with the first gate electrode and is disposed adjacent to the first portion, at least one of the first source electrode and the first drain electrode is disposed between the first extending portion and the second extending portion of the first gate electrode in plan view, an interface between the high resistance region and the element region is located closer to the second portion than a point where the first extending portion or the second extending portion protrude from the first portion in plan view.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 1.97403
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14636149', '14887249', '13231514', '11109858', '13150574']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9038806410146004
- 35 USC 102 Novelty (BERT): 0.5453242642381718
- Combined Prediction Score: 0.8680250033369574
- Mean Citation Score: 271.804574
- Max Citation Score: 383.62396
- Similarity Product: 345.7190989086532

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test