PATENT CLAIM ANALYSIS

Application Number: 16042910
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["712", "222000"]

Abstract:
The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

Claim (Index 35):
An integrated circuit that generates a double-precision floating-point sum of first and second double-precision floating-point numbers, comprising:\n a cascade chain that interconnects a plurality of processing circuitries; and the plurality of processing circuitries, wherein a first processing circuitry of the plurality of processing circuitries receives a first portion of the first double-precision floating-point number and a first portion of the second double-precision floating-point number, wherein the first processing circuitry is selectively operated in a first mode or second mode, wherein the first mode comprises the first processing circuitry:\n receiving a first carry signal over the cascade chain; \n generating a first control signal indicating whether the first double-precision floating-point number or the second double-precision floating-point number is larger; \n generating a first data signal indicating shifted values of the first or second two double-precision floating-point numbers; and \n generating most significant bits (MSBs) of the double-precision floating-point sum based at least in part on the first carry signal, and \n transmitting the first control signal and the first data signal; and \n the second mode comprises the first processing circuitry:\n receiving a second control signal from a second processing circuitry of the plurality of processing circuitries; \n generating a second carry signal; and \n generating least significant bits (LSBs) of the double-precision floating-point sum based at least in part on the second control signal.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 2.26923
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15367205', '15367208', '16039029', '15242923', '15270153']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6830199648170244
- 35 USC 102 Novelty (BERT): 0.6165650926693004
- Combined Prediction Score: 0.676374477602252
- Mean Citation Score: 498.582776
- Max Citation Score: 607.45935
- Similarity Product: 520.9246807415127

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test