PATENT CLAIM ANALYSIS

Application Number: 15925928
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "706000"]

Abstract:
The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

Claim (Index 13):
A semiconductor structure, comprising:\n a fin disposed over a semiconductor substrate; a functional gate disposed over the fin, wherein the functional gate comprises a gate dielectric formed over the fin and a gate conductor formed over the gate dielectric; and an isolation layer laterally spaced from the fin and contacting the functional gate, wherein the isolation layer has a first width in an upper portion thereof and a second width greater than the first width in a lower portion thereof.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 2.16667
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15486387', '15467536', '15643940', '15897204', '15451869']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.886376708624555
- 35 USC 102 Novelty (BERT): 0.5311524996227663
- Combined Prediction Score: 0.8508542877243762
- Mean Citation Score: 351.619714
- Max Citation Score: 369.63498
- Similarity Product: 337.70564423920155

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test