PATENT CLAIM ANALYSIS

Application Number: 15909682
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "751000"]

Abstract:
A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.

Claim (Index 11):
The semiconductor device of  claim 8 , wherein the conductive layer is formed over the conductive blocking layer, and the conductive barrier layer is arranged over the conductive layer, and the total thickness of three layers along the side portions of the contact region are less than 20 \u212b.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.07317
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15909777', '14321366', '15484934', '15860317', '15802729']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9196146441645084
- 35 USC 102 Novelty (BERT): 0.499188812720887
- Combined Prediction Score: 0.8775720610201463
- Mean Citation Score: 185.665774
- Max Citation Score: 203.29196
- Similarity Product: 129.38811091541766

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test