PATENT CLAIM ANALYSIS

Application Number: 16203635
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["174", "260000"]

Abstract:
A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.

Claim (Index 9):
A stacked structure, comprising:\n the chip module of  claim 1 ; and a circuit board, comprising:\n a circuit layer; \n a dielectric layer over the circuit layer and having an opening to expose a part of the circuit layer, wherein the first bonding layer of the chip module is in the opening; and \n a patterned seed layer between the exposed part of the circuit layer and the first bonding layer of the chip module and on a sidewall of the opening, wherein the bump and the first bonding layer of the chip module and the circuit layer and the patterned seed layer of the circuit board are bonded with each other to form an integral solid structure.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 98.0
- Lexical Diversity: 2.15385
- Patent Class: 174.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15590020', '14181739', '14532393', '11302863', '11934793']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8300273128962937
- 35 USC 102 Novelty (BERT): 0.5049251194455988
- Combined Prediction Score: 0.7975170935512242
- Mean Citation Score: 208.042256
- Max Citation Score: 288.4514
- Similarity Product: 219.2078454058528

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test