PATENT CLAIM ANALYSIS

Application Number: 16003754
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["327", "143000"]

Abstract:
A power on reset circuit includes a bias current generation module for generating a bias current, a power on reset module for generating a power on reset voltage signal, and a feedback latch module, which are electrically connected in sequence. The power on reset module includes two series switches capable of being turned on or off to adjust the bias current to further adjust the power on reset time. The feedback latch module is used for latching the power on reset voltage signal to restrain the jitter of the power voltage within the input voltage range V IL -V IH  of inverters in the power on stage and to avoid jump of the signal. The feedback latch module comprises a feedback branch, which is formed by two NMOS transistors in series connection and achieves rapider and stable output of the power on reset voltage signal through feedback of the signal.

Claim (Index 4):
The power on reset circuit according to  claim 3 , wherein the power on reset module comprises a 3rd PMOS transistor P 2 , a 4 th  PMOS transistor P 3 , a 5 th  PMOS transistor P 4 , a 6 th  PMOS transistor P 5 , a 1 st  switch K 0 , a 2 nd  switch K 1 , a 3 rd  NMOS transistor N 2 , a 1 st  capacitor C 0  and a 2 nd  capacitor C 1 , wherein a source of the 3 rd  PMOS transistor P 2  is connected to the power voltage, a gate of the 3 rd  PMOS transistor P 2  is connected to the gate of the 1 st  PMOS transistor P 0 , the gate of the 2 nd  PMOS transistor P 1 , a gate of the 4 th  PMOS transistor P 3  and a gate of the 5 th  PMOS transistor P 4 , the drain of the 3 rd  PMOS transistor P 2  is connected to the source of the 4 th  PMOS transistor P 3 , a drain and a source of the 4 th  PMOS transistor P 3  are connected through the 1 st  switch, the drain of the 4 th  PMOS transistor P 3  is connected to a source of the 5 th  PMOS transistor P 4 , a drain of the 5 th  PMOS transistor and the source of the 5 th  PMOS transistor P 4  are connected through the 2 nd  switch K 1 , the drain of the 5 th  PMOS transistor P 4  is connected to an upper plate electrode of the 1 st  capacitor C 0  and a gate of the 3 rd  NMOS transistor N 2 , a lower plate electrode of the 1 st  capacitor C 0  is grounded, a source of the 6 th  PMOS transistor P 5  is connected to the power voltage, a gate of the 6 th  PMOS transistor P 5  is connected to the gate of the 3 rd  PMOS transistor P 2 , the gate of the 1 st  PMOS transistor P 0  is connected to the gate of the 2 nd  PMOS transistor P 1 , a drain of the 6 th  PMOS transistor P 5  is connected to a drain of the 3 rd  NMOS transistor N 2  and a lower plate electrode of the 2 nd  capacitor, the gate of the 3 rd  NMOS transistor N 2  is connected to the drain of the 5 th  PMOS transistor P 4  and an upper plate electrode of the 1 st  capacitor C 0 , the source of the 3 rd  NMOS transistor N 2  is grounded, an upper plate electrode of the 2 nd  capacitor C 1  is connected to the power voltage, and a lower plate electrode of the 2 nd  capacitor C 1  is connected to the drain of the 6 th  PMOS transistor P 5  and the drain of the 3 rd  NMOS transistor N 2 .

Metadata:
- Claim Count in Document: 3.0
- Percentile: 94.0
- Lexical Diversity: 2.28986
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15682560', '15687546', '15742037', '15687548', '15684953']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7998887763769996
- 35 USC 102 Novelty (BERT): 0.5025960603173445
- Combined Prediction Score: 0.7701595047710341
- Mean Citation Score: 252.796608
- Max Citation Score: 280.58063
- Similarity Product: 211.54413386097667

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test