PATENT CLAIM ANALYSIS

Application Number: 16101667
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["257", "192000"]

Abstract:
A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

Claim (Index 9):
The method of  claim 1 , wherein the forming metal layer includes forming an n-type work functional metal layer in a first region and a second region, the method further comprising:\n forming a p-type work function metal layer over the barrier layer in the first region and the second region, after the forming of the barrier layer and before the treating of the barrier layer; forming a patterned mask covering the p-type work function metal layer in the second region; removing the p-type work function metal layer from the first region, thereby exposing the barrier layer in the first region; and removing the patterned mask after the removing of the p-type work function metal layer from the first region.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 96.0
- Lexical Diversity: 1.96667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15800164', '13329877', '12424153', '15219967', '12702012']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.89581348521368
- 35 USC 102 Novelty (BERT): 0.4981665028599902
- Combined Prediction Score: 0.856048786978311
- Mean Citation Score: 198.64231
- Max Citation Score: 252.42685
- Similarity Product: 205.9695028547346

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test