PATENT CLAIM ANALYSIS

Application Number: 15919805
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["710", "316000"]

Abstract:
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Claim (Index 2):
The slave device according to  claim 1 , wherein the medium voltage output clock signal is the medium voltage clock bus signal or the medium voltage clock signal.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14848472', '14028806', '11715478', '10764406', '14217510']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6459718122814009
- 35 USC 102 Novelty (BERT): 0.5730748327288977
- Combined Prediction Score: 0.6386821143261506
- Mean Citation Score: 245.13131600000008
- Max Citation Score: 441.9628
- Similarity Product: 437.0583589859008

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test