PATENT CLAIM ANALYSIS

Application Number: 16140053
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-06
Patent Classification: ["365", "222000"]

Abstract:
A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.

Claim (Index 11):
The memory system of  claim 1 , wherein the refresh control circuit includes:\n a refresh clock generator including an oscillator configured to be enabled in response to a self-refresh entry signal corresponding to the self-refresh entry command, to generate a refresh clock signal in response to a refresh control signal and a mode signal, and configured to be disabled in in response to a self-refresh exit signal corresponding to the self-refresh exit command; a refresh address counter configured to generate counting address for sequentially refreshing the memory cell rows in response to the refresh clock signal, the refresh address counter outputting a done signal upon generating a maximum counting address; a weak page address generator configured to store a weak page address of a weak page, and output the weak page address in response to the refresh clock signal; an address comparing circuit configured to compare the counting address with the weak page address to output a first match signal and a second match signal; a control signal generator configured to generate a plurality of control signals based on the refresh control signal, the mode signal, the done signal, the first match signal and the second match signal; an address converter configured to generate a changed refresh row address by do-not-care processing at least one bit of the counting address, in response to a third control signal of the plurality of the control signals; and a refresh address output circuit configured to output one of the counting address, the weak page address and the changed refresh row address as a refresh row address according to a refresh mode, based on a first control signal and a second control signal of the plurality of the control signals.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.85185
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14793749', '15065211', '15194784', '14858140', '13720998']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8462661319403483
- 35 USC 102 Novelty (BERT): 0.5338353375105321
- Combined Prediction Score: 0.8150230524973666
- Mean Citation Score: 346.570112
- Max Citation Score: 392.89798
- Similarity Product: 311.4334581829512

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test