PATENT CLAIM ANALYSIS

Application Number: 15754871
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "351000"]

Abstract:
Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

Claim (Index 8):
The integrated circuit of  claim 1 , further comprising a layer between the body and the sub-body region, the layer including carbon.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 1.89412
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15117590', '15790907', '15576150', '15753739', '15122796']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9134965785127016
- 35 USC 102 Novelty (BERT): 0.4923939136134496
- Combined Prediction Score: 0.8713863120227764
- Mean Citation Score: 202.407964
- Max Citation Score: 206.25311
- Similarity Product: 138.9557638770568

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test