PATENT CLAIM ANALYSIS

Application Number: 16022540
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["257", "066000"]

Abstract:
A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Claim (Index 10):
A system, comprising:\n a processor; and a memory coupled with the processor, wherein the memory includes a 3D-stacked memory array including a plurality of memory cells, wherein the plurality of memory cells comprises:\n a plurality of floating gates adjacent to a channel region, wherein a length of one or more of the floating gates along a direction of the channel region is substantially longer than along an orthogonal direction of the channel region; \n a plurality of control gates, each adjacent to a corresponding floating gate of the plurality of floating gates, wherein one or more of the corresponding floating gates extends at least as long as an adjacent control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the adjacent control gate; and \n a dielectric layer disposed between one or more of the plurality of control gates and one or more of the corresponding floating gates and following the tapered edge along the one or more corresponding floating gates and forming a discrete region proximate to the one or more corresponding floating gates to assist in insulating the one or more corresponding floating gates from an adjacent memory cell.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 2.61667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14808475', '15252090', '13153964', '14140215', '14144442']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90992572866648
- 35 USC 102 Novelty (BERT): 0.490680427757644
- Combined Prediction Score: 0.8680011985755964
- Mean Citation Score: 182.97255
- Max Citation Score: 187.5822
- Similarity Product: 123.0106234752059

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test