PATENT CLAIM ANALYSIS

Application Number: 16169157
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "043000"]

Abstract:
A gate insulating film is formed over an oxide semiconductor film. A gate electrode is formed over the gate insulating film. An interlayer insulating film is formed over the oxide semiconductor film and the gate electrode. Planarization treatment is performed on the interlayer insulating film. An opening is formed in the interlayer insulating film subjected to the planarization treatment. A conductive film is formed in the opening and over the interlayer insulating film subjected to the planarization treatment. A pair of conductive films is formed by performing planarization treatment on the conductive film. A first region and a second region are formed in the oxide semiconductor film by adding an impurity to the pair of conductive films. The second region and the opening overlap with each other. The second region is formed by an impact caused by addition of the impurity to the pair of conductive films.

Claim (Index 18):
The method for manufacturing a semiconductor device, according to  claim 13 , further comprising forming a gate electrode after forming the oxide semiconductor film.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 3.41304
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14808246', '14645781', '14489074', '14454071', '14921141']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9243237768234426
- 35 USC 102 Novelty (BERT): 0.55545903219888
- Combined Prediction Score: 0.8874373023609863
- Mean Citation Score: 325.719844
- Max Citation Score: 441.79553
- Similarity Product: 343.737566199466

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test