PATENT CLAIM ANALYSIS

Application Number: 16222557
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["363", "074000"]

Abstract:
A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.

Claim (Index 5):
The DC-DC converter circuit of  claim 2 , wherein said adjustable differential delay circuit comprises two voltage controlled delay circuits configured to receive the high side command signal and the delay control signal, each of the two voltage controlled delay controls circuits configured to apply a respective delay to the high side command signal to generate a corresponding delayed command signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 98.0
- Lexical Diversity: 2.13793
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11757181', '15159053', '14678932', '15627196', '14847989']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8087785270037293
- 35 USC 102 Novelty (BERT): 0.4695628454791052
- Combined Prediction Score: 0.7748569588512669
- Mean Citation Score: 139.41826799999998
- Max Citation Score: 143.42218
- Similarity Product: 102.03592908344032

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test