PATENT CLAIM ANALYSIS

Application Number: 15996099
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["438", "702000"]

Abstract:
Patterning techniques are disclosed that can relax overlay requirements and/or increase integrated circuit design flexibility. An exemplary method includes forming a first set of fins and a second set of fins having different etch sensitivities on a material layer. The fins of the second set of fins are interspersed between the fins of the first set of fins. A first patterning process removes a subset of the first set of fins and a portion of the material layer underlying the subset of the first set of fins. The first patterning process avoids substantial removal of an exposed portion of the second set of fins. A second patterning process removes a subset of the second set of fins and a portion of the material layer underlying the subset of the second set of fins. The second patterning process avoids substantial removal of an exposed portion of the first set of fins.

Claim (Index 20):
The method of  claim 19 , wherein the depositing of the second spacer material and the third spacer material includes:\n depositing a directed self-assembly material on the material layer; and curing the directed self-assembly material.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 3.07843
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14689288', '14835495', '15477588', '15990147', '15684282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8503473816653239
- 35 USC 102 Novelty (BERT): 0.5336953837894829
- Combined Prediction Score: 0.8186821818777398
- Mean Citation Score: 240.767746
- Max Citation Score: 334.17044
- Similarity Product: 228.80281949681049

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test