PATENT CLAIM ANALYSIS

Application Number: 16053123
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "401000"]

Abstract:
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

Claim (Index 17):
The semiconductor device structure of  claim 16 , wherein the collinear vertical fin segments of the third set are separated from each other by the fin trench, and the collinear vertical fin segments of the fourth set are separated from each other by the fin trench.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.43333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15443573', '15789620', '15178193', '15177362', '15628102']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9481006759037088
- 35 USC 102 Novelty (BERT): 0.5817499579598958
- Combined Prediction Score: 0.9114656041093276
- Mean Citation Score: 449.994254
- Max Citation Score: 513.18616
- Similarity Product: 412.21657648794167

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test