PATENT CLAIM ANALYSIS

Application Number: 16212540
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["711", "104000"]

Abstract:
A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.

Claim (Index 11):
The memory system of  claim 10 , wherein the host is configured to issue the responsive operation command in response to the determination that a threshold value has been reached.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 98.0
- Lexical Diversity: 2.36842
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15482288', '15482263', '15229301', '13485455', '14524823']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5158793591628591
- 35 USC 102 Novelty (BERT): 0.5225565960831351
- Combined Prediction Score: 0.5165470828548867
- Mean Citation Score: 188.713176
- Max Citation Score: 295.47037
- Similarity Product: 186.16496455910683

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test