PATENT CLAIM ANALYSIS

Application Number: 15896499
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "368000"]

Abstract:
An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Claim (Index 1):
An integrated circuit structure comprising:\n a substrate; a semiconductor active area overlying the substrate; a first gate overlying a first channel region in the active area; a first transistor that includes the first channel region, a first source region adjacent to a first side of the first channel region in the active area, a first drain region adjacent to a second side of the first channel region and the first gate; a conductive contact that is directly connected to the first drain region of the first transistor, the conductive contact having an upper surface and being a first material; a second gate spaced from the first gate, the second gate overlying a second channel region; a second transistor that includes the second channel region, a second source region adjacent to a first side of the second channel region in the active area, a second drain region adjacent to a second side of the second channel region and the second gate; a conductive via that is directly connected to the second gate, the conductive via having an upper surface and being a second material that is different than the first material; an expanded conductive via that overlays the conductive contact and the conductive via to electrically connect them to each other, the expanded conductive via extending in a plane from the conductive contact to the conductive via, wherein the upper surface of the conductive via and the upper surface of the conductive contact are at a same level as the plane; and a first electrical insulation layer that surrounds the expanded conductive via.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.97826
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14662326', '14277150', '13312828', '13591663', '14713948']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912310457381308
- 35 USC 102 Novelty (BERT): 0.4556034591729794
- Combined Prediction Score: 0.8666397575604751
- Mean Citation Score: 177.43833999999995
- Max Citation Score: 180.73862
- Similarity Product: 159.43690282254934

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test