PATENT CLAIM ANALYSIS

Application Number: 15919746
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["257", "676000"]

Abstract:
A power semiconductor device package includes a power semiconductor die having a first load terminal at a die frontside and a second load terminal at a die backside. The package has a package top side, a package footprint side, and a first terminal interface and a second terminal interface arranged at the package footprint side. The first terminal interface is electrically connected with the first load terminal. The die is disposed in a main cavity of an insulating core layer. A conductive material is provided at a cavity sidewall of the main cavity, and an insulation structure is provided in the main cavity. The insulation structure embeds the die, with the die backside facing the package top side. An electrical connection provided between the second load terminal and the second terminal interface is formed by at least the conductive material at the cavity sidewall.

Claim (Index 1):
A method of embedding a power semiconductor die in a package, the power semiconductor die comprising a first load terminal arranged at a die frontside and a second load terminal arranged at a die backside, and the package having a package top side and a package footprint side, and comprising a first terminal interface and a second terminal interface, both arranged at the package footprint side, the first terminal interface being for electrical connection with the first load terminal, the method comprising:\n providing an insulating core layer having a main cavity configured to house the power semiconductor die, the main cavity having a cavity sidewall, providing a conductive material at the cavity sidewall; arranging the power semiconductor die in the main cavity, wherein the die backside faces the package top side; providing an insulation structure in the main cavity and that embeds the power semiconductor die; and providing an electrical connection between the second load terminal and the second terminal interface by at least the conductive material provided at the cavity sidewall.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 90.0
- Lexical Diversity: 2.81818
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13432333', '14930514', '14964972', '13964153', '14642531']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9122507319657314
- 35 USC 102 Novelty (BERT): 0.4682124885576154
- Combined Prediction Score: 0.8678469076249198
- Mean Citation Score: 184.22596
- Max Citation Score: 185.7608
- Similarity Product: 150.04356695985794

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test