PATENT CLAIM ANALYSIS

Application Number: 15905256
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "148000"]

Abstract:
A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Claim (Index 1):
A semiconductor memory device, comprising:\n a plurality of memory cell arrays that include a plurality of memory cells between a plurality of first wiring extending in a first direction and a plurality of second wirings extending in a second direction intersecting the first direction; a first control circuit including a plurality of control transistors of a first conductivity type disposed in a first region directly below the plurality of memory cell arrays in the second direction and electrically connected to a first wiring of the plurality of first wirings and configured to supply a voltage to the first wiring; and a second control circuit including a first transistor of a first conductivity type connected in parallel to a second transitory of a second conductivity type, an end of the first and second transistors being connected to an end of at least one control transistor in the plurality, the second control circuit being configured to deliver a voltage to the plurality of control transistors for application to the first wirings, wherein the first transistor is disposed in the first region, the second transistor is disposed in a second region adjacent to the first region, the second region being below a gap between adjacent memory cell arrays in the plurality of memory cell arrays.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 88.0
- Lexical Diversity: 3.09091
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10372626', '13620184', '11134476', '15629489', '15214253']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7761510666857168
- 35 USC 102 Novelty (BERT): 0.4522053097945102
- Combined Prediction Score: 0.7437564909965961
- Mean Citation Score: 146.79899799999995
- Max Citation Score: 156.89511000000005
- Similarity Product: 125.68490634892883

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test