PATENT CLAIM ANALYSIS

Application Number: 15944032
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "171000"]

Abstract:
The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.

Claim (Index 20):
A method, comprising:\n configuring a first row which is connected to a gate of a first NMOS transistor which has a source connected to a reference data magnetic tunnel junction (reference data MTJ1); turning on a power supply on a second row which is connected to a gate of a second NMOS transistor which has a source connected to a first data magnetic tunnel junction (data MTJ1) in a memory array circuit to provide a current flow through a third row which is connected to a gate of a third NMOS transistor which has a source connected to a second data magnetic tunnel junction (data MTJ2) in the memory array circuit; and configuring an inverter switching threshold of an inverter between the first data MTJ1 and the second data MTJ2 to create a voltage divider to mimic a logic operation in the memory array circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.24138
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13613205', '15636970', '12784848', '14970564', '13764139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7563726149573622
- 35 USC 102 Novelty (BERT): 0.4693105443478482
- Combined Prediction Score: 0.7276664078964108
- Mean Citation Score: 180.946558
- Max Citation Score: 188.29303
- Similarity Product: 151.0630491525483

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test