PATENT CLAIM ANALYSIS

Application Number: 15983395
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["708", "501000"]

Abstract:
An arithmetic unit includes a multiplier multiplying first and second inputs to output a multiplication result, an adder adding the third input to the multiplication result to output a multiplication addition result, a normalization shift circuit shifting the multiplication addition result left with a left shift amount, and a left shift amount prediction circuit. The adder includes a carry-save adder adding a first addition value and a first carry value to the third input and a full adder outputting the multiplication addition result. The left shift amount prediction circuit includes a leading zero count circuit generating a leading zero count, a leading one count circuit generating a leading one count, and a correction circuit correcting the leading one count to zero when NOR of respective least significant bits of the M upper order bits of the second addition value and the second carry value of the full adder is true.

Claim (Index 2):
An arithmetic unit comprising:\n a multiplier that converts a floating point format of a first input and a second input in a first operand and a second operand into an internal format in which M (where M is a plurality) most significant bits are set at 0 and N (where N is a plurality) lower order bits following the most significant bits constitute a fraction, and then multiplies the first input and the second input to output a multiplication result; an adder that converts a floating point format of a third input in a third operand into the internal format, and adds the third input to the multiplication result to output a multiplication addition result; a normalization shift circuit for shifting the multiplication addition result left on the basis of a left shift amount; and a left shift amount prediction circuit for predicting the left shift amount, wherein the adder includes: a carry-save adder that adds a first addition value and a first carry value, which together serve as the multiplication result, to the third input; and a full adder that adds together a second addition value and a second carry value output by the carry-save adder to output the multiplication addition result, and the left shift amount prediction circuit includes: a leading zero count circuit that generates a zero count determination value for each bit from the N lower order bits of the second addition value and the second carry value, and generates a leading zero count, which is a number of true zero count determination values occurring consecutively in descending order from an upper order bit side; a leading one count circuit that generates a one count determination value for each bit from the N lower order bits of the second addition value and the second carry value, and generates a leading one count, which is a number of true one count determination values occurring consecutively in descending order from the upper order bit side; and a correction circuit that corrects the leading one count to zero in a correction enabled state where an AND of an EOR of respective most significant bits of the N lower order bits of the first addition value and the first carry value and a NOT of a most significant bit of the N lower order bits of the third input is true.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.77193
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12479531', '14610029', '13916850', '12929827', '14113636']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4042673958340824
- 35 USC 102 Novelty (BERT): 0.5061126828224702
- Combined Prediction Score: 0.4144519245329212
- Mean Citation Score: 239.41739
- Max Citation Score: 248.8799
- Similarity Product: 189.33818655815125

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test