PATENT CLAIM ANALYSIS

Application Number: 15754150
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "029000"]

Abstract:
Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.

Claim (Index 21):
A method of forming a transistor, the method comprising:\n forming a fin from a substrate; forming a gate stack on the fin; removing at least a portion of the fin adjacent the gate stack to define a recess, and depositing sacrificial material into the recess thereby forming a sacrificial source region or drain region; depositing an insulator layer over the sacrificial source region or drain region; etching a contact trench in the insulator layer over the source region or drain region; and removing at least some of the sacrificial material in the source region or drain region through the contact trench, and depositing doped semiconductor material into the source region or drain region through the contact trench.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 88.0
- Lexical Diversity: 1.95062
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14020299', '15138651', '16474446', '15576150', '15173132']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914336037934225
- 35 USC 102 Novelty (BERT): 0.4825887540848998
- Combined Prediction Score: 0.8711613095492925
- Mean Citation Score: 202.933806
- Max Citation Score: 209.03609
- Similarity Product: 158.34699217714433

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test