PATENT CLAIM ANALYSIS

Application Number: 16015168
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["365", "001000"]

Abstract:
Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is performed on at least one memory cell in a first group of memory cells out of a plurality of groups of memory cells coupled to a line. A first voltage is applied across the first group of memory cells for the operation and a lower second voltage is applied across the other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells. These steps may repeated until the operations covers all the groups.

Claim (Index 8):
The method of  claim 5  wherein each group of memory cells in the row comprises an equal number of memory cells.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 94.0
- Lexical Diversity: 2.17544
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14841615', '15426909', '16015156', '16015164', '14841521']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8402532659210956
- 35 USC 102 Novelty (BERT): 0.5732560691564383
- Combined Prediction Score: 0.8135535462446298
- Mean Citation Score: 431.216638
- Max Citation Score: 480.605
- Similarity Product: 404.1762391328812

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test