PATENT CLAIM ANALYSIS

Application Number: 16120794
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["257", "529000"]

Abstract:
A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

Claim (Index 3):
The device as recited in  claim 1 , wherein the defective semiconductor layer includes Si and forms a conductive path by activating a gate of the gate structure in the anti-fuse region above a threshold voltage.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 97.0
- Lexical Diversity: 2.22727
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15694170', '15174200', '15926369', '14969717', '15366296']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9268894357181858
- 35 USC 102 Novelty (BERT): 0.5115227347344323
- Combined Prediction Score: 0.8853527656198105
- Mean Citation Score: 250.68911
- Max Citation Score: 321.8264200000001
- Similarity Product: 314.3308785902787

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test