PATENT CLAIM ANALYSIS

Application Number: 16458852
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["716", "052000"]

Abstract:
A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

Claim (Index 5):
The method of  claim 4 , wherein the design rules further include at least one or more of:\n satisfying a second set of spacing requirements for the third set of vias; or determining if two or more vias of the third set of vias are aligned in the first direction or the second direction.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.48889
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15258932', '15465167', '15966693', '14554958', '14484588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3574108242978003
- 35 USC 102 Novelty (BERT): 0.5154697939899678
- Combined Prediction Score: 0.3732167212670171
- Mean Citation Score: 222.11727
- Max Citation Score: 357.15204
- Similarity Product: 248.580196934352

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test