PATENT CLAIM ANALYSIS

Application Number: 15995149
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "072000"]

Abstract:
A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.

Claim (Index 1):
A thin-film transistor (TFT) substrate, comprising, stacked in sequence from bottom to top, a backing plate, a light shielding layer, a buffer layer, an active layer and the source electrode and the drain electrode, a first gate insulation layer, a second gate insulation layer, a gate electrode, a first passivation layer, a planarization layer, a common electrode, a second passivation layer, and a pixel electrode;\n wherein the source electrode and the drain electrode are respectively located at two opposite sides of the active layer and in connection therewith, the source electrode and the drain electrode being both formed by subjecting a semiconductor to heavy ion doping, the active layer comprising two lightly-ion-doped semiconductor layers respectively located at two ends thereof and connected with the source electrode and the drain electrode and a channel-zone semiconductor layer located between the two lightly-ion-doped semiconductor layers; the first gate insulation layer covers the active layer, the source electrode, the drain electrode, and the buffer layer; the second gate insulation layer and the active layer overlap each other so as to correspond, in position, to each other; and the gate electrode and the channel-zone semiconductor layer correspond to each other; and the first gate insulation layer, the first passivation layer, and the planarization layer comprise a first via formed therein to correspond, in position, to and be located above the drain electrode; the second passivation layer comprises a second via formed therein to correspond, in position, to and be located above the drain electrode and located inside the first via, the pixel electrode being connected through the second via to the drain electrode.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 94.0
- Lexical Diversity: 1.86905
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15441245', '15441246', '15735614', '15544023', '14778090']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9307798750658558
- 35 USC 102 Novelty (BERT): 0.5441130872998098
- Combined Prediction Score: 0.8921131962892512
- Mean Citation Score: 347.37581600000016
- Max Citation Score: 400.1556
- Similarity Product: 361.98157639160166

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test