PATENT CLAIM ANALYSIS

Application Number: 15954874
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "306000"]

Abstract:
An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Claim (Index 8):
The method of  claim 7 , wherein the third sidewall spacers comprise a multilayer of a silicon oxide layer and a silicon nitride layer.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 2.86538
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15133394', '11738003', '15296205', '14305137', '15370149']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917600060186852
- 35 USC 102 Novelty (BERT): 0.5725348797277293
- Combined Prediction Score: 0.8830935421409398
- Mean Citation Score: 310.011526
- Max Citation Score: 476.95374
- Similarity Product: 346.53681543338297

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test