PATENT CLAIM ANALYSIS

Application Number: 15875553
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["717", "149000"]

Abstract:
A compiler system, computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors (P1 to Pn) of a multi-processor system. The compiler further includes a static analysis component configured to determine data dependencies) within the program code, and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system at runtime by using a predefined execution evaluation function.

Claim (Index 15):
A computer program product that when loaded into a memory of a computing device and executed by at least one processor of the computing device executes the steps of:\n loading a program code of the program wherein the program is to be executed by at least one processor (P1 to Pn); as a result of a static analysis of the program code, generating a control flow graph representing traversable paths through the execution of the program, and determining data dependencies between pairs of statements of the program code wherein sets of statements are represented by basic blocks of the control flow graph; receiving a mapping which includes for each statement an assignment of the statement to a particular processor (P1 to Pn) of a multi-processor system; identifying at least one data dependency between a first statement in a first basic block and a second statement in a second basic block where a data flow is indicated from a first processor (P1) to a second processor (P2) of the multi-processor system; identifying all paths between the first basic block and the second basic block in the control flow graph; determining all basic blocks providing potential insertion positions along the identified paths where communication statements are adapted to be inserted to enable the data flow at runtime; evaluating, by using a predefined execution evaluation function, each potential insertion position with respect to an impact on the execution of the program on the multi-processor system; and obtaining optimized program code by inserting coupled send and receive communication statements in each identified path at one or more insertion positions wherein each insertion position has an evaluation value which indicates optimal runtime execution of the program when executed on the multi-processor system.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 1.67857
- Patent Class: 717.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12972198', '14982257', '09956901', '15443038', '11861512']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4172186259298915
- 35 USC 102 Novelty (BERT): 0.497679152032728
- Combined Prediction Score: 0.4252646785401752
- Mean Citation Score: 208.643118
- Max Citation Score: 228.19614
- Similarity Product: 181.77305740165832

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test