PATENT CLAIM ANALYSIS

Application Number: 15903097
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "043000"]

Abstract:
A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

Claim (Index 2):
A method for manufacturing a semiconductor device, comprising the steps of:\n forming an oxide semiconductor layer; forming a first insulating layer over the oxide semiconductor layer; forming a second insulating layer by etching the first insulating layer so that a first part of the oxide semiconductor layer is exposed; forming a first conductive layer over the first part of the oxide semiconductor layer and the second insulating layer; forming a second conductive layer by etching the first conductive layer so that part of the first part of the oxide semiconductor layer is exposed, wherein the second conductive layer is along and in contact with a side surface of the second insulating layer; removing the second insulating layer; etching the oxide semiconductor layer with the second conductive layer as a mask; forming a third insulating layer over the oxide semiconductor layer and the second conductive layer after etching the oxide semiconductor layer; forming a groove in the third insulating layer so that a region of the second conductive layer is exposed; forming a source electrode layer and a drain electrode layer by removing the region of the second conductive layer; and forming an oxide layer, a gate insulating layer over the oxide layer and a gate electrode layer over the gate insulating layer in the groove.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 88.0
- Lexical Diversity: 3.975
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15408719', '15224958', '15041502', '15182812', '15864033']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9424775356869878
- 35 USC 102 Novelty (BERT): 0.5678586525323953
- Combined Prediction Score: 0.9050156473715284
- Mean Citation Score: 392.370052
- Max Citation Score: 440.32275
- Similarity Product: 379.83438455392417

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test