PATENT CLAIM ANALYSIS

Application Number: 16023816
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["341", "120000"]

Abstract:
Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Claim (Index 2):
The DAC circuit of  claim 1 , further comprising:\n a calibration memory to store:\n a first set of K\u00d7M bits of calibration data for calibration of the first subword, \n a second set of K\u00d7M bits of calibration data for calibration of the second subword, and \n a third set of K\u00d7M bits of calibration data for calibration of the third subword \n the calibration memory configured to provide a calibration code from the calibration data based on the digital input signal; and \n a calibration circuit configured to provide the modulator code based on:\n the calibration code, \n and the second and third subwords.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 94.0
- Lexical Diversity: 1.90244
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15790986', '15962690', '11454595', '11467174', '13669958']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5826328980051545
- 35 USC 102 Novelty (BERT): 0.7106499574065317
- Combined Prediction Score: 0.5954346039452922
- Mean Citation Score: 446.622674
- Max Citation Score: 734.4248
- Similarity Product: 728.0337186697958

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test