PATENT CLAIM ANALYSIS

Application Number: 16125784
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-08
Patent Classification: ["326", "041000"]

Abstract:
A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Claim (Index 5):
The chip package of  claim 4  further comprising multiple through package vias in the polymer layer and on the interposer, wherein each of the through package vias has a top surface coplanar with the top surface of the polymer layer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.65455
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16029701', '15841326', '14580240', '11307127', '13646477']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6916377971557687
- 35 USC 102 Novelty (BERT): 0.5474560578439384
- Combined Prediction Score: 0.6772196232245856
- Mean Citation Score: 276.192732
- Max Citation Score: 472.83008
- Similarity Product: 294.51988639266966

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test