PATENT CLAIM ANALYSIS

Application Number: 15747139
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["330", "051000"]

Abstract:
An analog multiplexer core circuit ( 120 A) includes a differential pair ( 121 ) that includes two transistors (Q 1,  Q 2 ), a differential pair ( 122 ) that includes two transistors (Q 3,  Q 4 ), a differential pair ( 123 ) that includes two transistors (Q 5,  Q 6 ), and a constant current source ( 124 ) that causes a current (I EE ) to flow. This analog multiplexer core circuit ( 120 A) time-multiplexes two analog signals (Ain 1,  Ain 2 ) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (R EA 1,  R EA 2,  R EA 3,  R EA 4 ) is connected to a corresponding one of the transistors (Q 1,  Q 2,  Q 3,  Q 4 ). At this time, a relation of “R EA ·I EE ≥the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs ( 121, 122 ).

Claim (Index 15):
An analog multiplexer circuit comprising:\n a first analog multiplexer core circuit that is formed from an analog multiplexer core circuit according to  claim 1 , to which two analog signals as the first analog signal and the second analog signal are input, and a first clock signal is input as the clock signal; a second multiplexer core circuit that is formed from the analog multiplexer core circuit according to  claims 1 , to which two analog signals different from the two analog signals are input as the first analog signal and the second analog signal, and the first clock signal as the clock signal is input in a different phase from that of the first analog multiplexer core circuit; and a third multiplexer core circuit that is formed from the analog multiplexer core circuit according to  claims 1 , to which two time-multiplexed analog signals output from the first analog multiplexer core circuit and the second analog multiplexer core circuit are input as the first analog signal and the second analog signal, and a second clock signal whose cycle is \u00bd that of the cycle of the first clock signal is input as the clock signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.54321
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11943074', '14889127', '13527510', '11038415', '13981313']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7470026362912099
- 35 USC 102 Novelty (BERT): 0.5092895386487865
- Combined Prediction Score: 0.7232313265269675
- Mean Citation Score: 223.83871800000003
- Max Citation Score: 254.24689
- Similarity Product: 183.9765427054977

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test