PATENT CLAIM ANALYSIS

Application Number: 15747692
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["257", "300000"]

Abstract:
Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

Claim (Index 44):
The system of  claim 42 , wherein the second doped region is disposed on the first side, and wherein the second doped region surrounds the capacitor at the first side.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 2.35
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11222273', '10924296', '13108917', '10998483', '11461666']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9139076016389628
- 35 USC 102 Novelty (BERT): 0.481618840841413
- Combined Prediction Score: 0.8706787255592078
- Mean Citation Score: 137.673036
- Max Citation Score: 138.80235
- Similarity Product: 91.24866655789016

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test