PATENT CLAIM ANALYSIS

Application Number: 15755757
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["257", "401000"]

Abstract:
A TFT device is manufactured starting from a substrate with mutually insulated elongated strips of semi-conductor material. A stack of layers over the strips on the substrate, the stack comprising a gate electrode layer. A multi-level resist layer is provided over the gate electrode layer. The multi-level resist layer defines gate and source drain regions, the channel running in parallel with the direction of the strips. Gate portions in the resist layer cross source drain regions in the resist layer, overreaching the source drain regions on either side at least by a distance corresponding to a pitch of the strips.

Claim (Index 1):
A method of manufacturing a semi-conductor device comprising a thin film transistor, the method comprising\n providing a substrate with mutually insulated elongated strips of semi-conductor material on the substrate, the strips extending in a first direction; depositing an stack of layers over the strips on the substrate, the stack comprising a gate electrode layer and a gate insulation layer between the gate electrode layer and the strips; providing a multi-level resist layer comprising first and second parts with a first and second non-zero resist height level on top of the stack respectively, the first resist height level being smaller than the second resist height level, the second part comprising a portion that crosses the first part in a second direction transverse to the first direction, overreaching the first part on either side at least by a distance corresponding to a pitch of the strip; etching the stack and the strips over an area of the substrate not covered by the first and second parts, using the multi-level resist layer as a mask; etching the multi-level resist layer at least down from the first resist height level, leaving the substrate underneath the second part covered by resist from the multi-level resist layer; etching the stack to expose parts of the strips where the first part of the multi-level resist layer has been removed, leaving a part of the gate electrode layer underneath the second part of the multi-level resist layer for use as a gate electrode of the transistor; forming source and drain contacts of the transistor from the exposed parts of the strips.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 88.0
- Lexical Diversity: 1.96364
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11144204', '13172543', '10482101', '12807215', '10849000']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8985665969364574
- 35 USC 102 Novelty (BERT): 0.4793649125760635
- Combined Prediction Score: 0.856646428500418
- Mean Citation Score: 175.62777
- Max Citation Score: 179.41284
- Similarity Product: 135.99189857856274

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test