PATENT CLAIM ANALYSIS

Application Number: 15995983
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["710", "100000"]

Abstract:
A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.

Claim (Index 8):
A method comprising:\n on a first semiconductor die, receiving first processor bus transactions via a first processor bus; on the first semiconductor die, converting the first bus transactions into die-to-die message packets to be communicated to a second semiconductor die via a die-to-die interconnect; on the first semiconductor die, utilizing a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions; on the second semiconductor die, transmitting to the first semiconductor die process bus flow control information and elasticity buffer status information pertaining to an elasticity buffer on the second semiconductor die for flow control, the first semiconductor die and the second semiconductor die contained in a common integrated circuit (IC) package; classifying processor bus interface messages communicating processor bus interface protocol information and elasticity buffer flow control information according to a first message classification; and classifying non-processor-bus-interface messages communicating elasticity buffer flow control information according to a second message classification.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 2.2
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15995881', '13434605', '15043622', '13028250', '11855706']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5944624468038471
- 35 USC 102 Novelty (BERT): 0.4863501761858114
- Combined Prediction Score: 0.5836512197420435
- Mean Citation Score: 145.331639
- Max Citation Score: 235.63698
- Similarity Product: 196.7692188501906

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test