PATENT CLAIM ANALYSIS

Application Number: 16033154
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["323", "271000"]

Abstract:
A current balance method used in multi-phase switching converters, including: generating an error amplifying signal based on a reference voltage signal and a feedback voltage signal indicative of an output voltage of the multi-phase converter; generating a first and second voltage signals respectively indicative of output currents of a first and second switching circuits; generating an average voltage signal indicative of the average value of the first and second voltage signals; generating a first adjusting voltage signal based on the average voltage signal and the first voltage signal; comparing a sum of the error amplifying signal and the first adjusting voltage signal with a first current sensing signal indicative of the current flowing through a transistor in the first switching circuit, to provide a first comparison signal; and generating a first control signal based on the first comparison signal to control the transistor.

Claim (Index 1):
A controller used in multi-phase switching converters, wherein the multi-phase converter includes a first switching circuit and a second switching circuit coupled in parallel, and the controller comprises:\n an error amplifying circuit configured to generate an error amplifying signal based on a reference voltage signal and a feedback voltage signal indicative of an output voltage of the multi-phase converter; a first current sensing circuit configured to generate a first voltage signal indicative of an output current of the first switching circuit; a first current averaging circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the first current sensing circuit to receive the first voltage signal, wherein the first current averaging circuit includes a first resistor; a second current sensing circuit configured to generate a second voltage signal indicative of an output current of the second switching circuit; a second current averaging circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the second current sensing circuit to receive the second voltage signal, the output terminals of the first and second current averaging circuits are coupled together to generate an average voltage signal indicative of an average value of the first and second voltage signals, wherein the second current averaging circuit includes a second resistor; a first amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the average voltage signal, the second input terminal is configured to receive the first voltage signal, and the output terminal is coupled to the error amplifying signal through a third resistor; a first comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first amplifier, the second input terminal is configured to receive a first current sensing signal indicative of the current flowing through a transistor in the first switching circuit, and the output terminal is configured to provide a first comparison signal; and a first logic circuit configured to generate a first control signal based on the first comparison signal, to control the transistor in the first switching circuit wherein the error amplifying circuit includes an error amplifier for comparing the reference voltage signal with the feedback voltage signal, an impedance network coupled to an output terminal of the error amplifier, and a buffer coupled between the error amplifying signal and the output terminal of the error amplifier.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 95.0
- Lexical Diversity: 2.92308
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15846142', '15387621', '14585645', '15389390', '14548180']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.752188864975153
- 35 USC 102 Novelty (BERT): 0.4750700678932354
- Combined Prediction Score: 0.7244769852669612
- Mean Citation Score: 206.970012
- Max Citation Score: 223.28291
- Similarity Product: 186.3273292168063

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test