PATENT CLAIM ANALYSIS

Application Number: 15964864
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "226000"]

Abstract:
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Claim (Index 26):
The semiconductor device according to  claim 25 ,\n wherein the first N channel type drive MOS transistor has a source coupled to a third power line for supplying a second voltage, wherein the second N channel type drive MOS transistor has a source coupled to the third voltage line, and wherein the second voltage is lower than the first voltage.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 91.0
- Lexical Diversity: 1.88333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14942822', '15274852', '11438668', '15680269', '12367871']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8684296123359625
- 35 USC 102 Novelty (BERT): 0.5668954397355389
- Combined Prediction Score: 0.8382761950759201
- Mean Citation Score: 469.29611399999993
- Max Citation Score: 492.4683
- Similarity Product: 356.76519238286016

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test