PATENT CLAIM ANALYSIS

Application Number: 16106119
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-04
Patent Classification: ["326", "093000"]

Abstract:
An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Claim (Index 3):
The apparatus according to  claim 1 , wherein said apparatus is configured to reduce jitter on said strobe signal and said data signal received from a DRAM memory module.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 96.0
- Lexical Diversity: 3.01818
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15729802', '15439190', '16059287', '14369501', '15360404']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.636496711407276
- 35 USC 102 Novelty (BERT): 0.5513228726470942
- Combined Prediction Score: 0.6279793275312578
- Mean Citation Score: 234.768892
- Max Citation Score: 404.19992
- Similarity Product: 367.931870475626

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test