PATENT CLAIM ANALYSIS

Application Number: 16052581
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["711", "103000"]

Abstract:
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Claim (Index 11):
The system as in  claim 10  wherein the PCM memory comprises a phase change memory and switch (PCMS).

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 2.45333
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13994731', '15192871', '13997189', '15457847', '13994729']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6374245197379974
- 35 USC 102 Novelty (BERT): 0.5546835570569589
- Combined Prediction Score: 0.6291504234698936
- Mean Citation Score: 403.159092
- Max Citation Score: 423.2226
- Similarity Product: 405.0546850948692

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test