PATENT CLAIM ANALYSIS

Application Number: 15923864
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["438", "003000"]

Abstract:
Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Claim (Index 21):
The method of  claim 11  wherein the trenches are second trenches, wherein the structure is a third assembly, and wherein the forming of the structure comprises:\n forming the first conductive lines over a mass of the first semiconductor material; the first conductive lines being spaced from one another by gaps; \n extending the gaps into the mass of the first semiconductor material to form first trenches within the mass of the first semiconductor material; the first trenches extending along the first direction; a base of the first semiconductor material remaining under the first trenches; \n forming an insulative mass which fills the first trenches and covers the first conductive lines; the insulative mass having an upper surface comprising a first dielectric bonding material, and comprising the insulative material within the trenches; a first assembly comprising the insulative mass, the first semiconductor material and the first conductive lines; the first trenches having sidewalls of the first semiconductor material, with such sidewalls being along the semiconductor material walls; \n forming a second assembly comprising a second dielectric bonding material over the second semiconductor material; \n inverting the first assembly and bonding the first dielectric bonding material with the second dielectric bonding material to form the dielectric bonding region, and to form the third assembly to comprise the first assembly bonded to the second assembly through the dielectric bonding region; an upper surface of the third assembly comprising the base of the first semiconductor material; and \n polishing said upper surface of the third assembly to remove the base of the first semiconductor material and form the planarized surface extending across the semiconductor material walls and the insulative walls.

Metadata:
- Claim Count in Document: 62.0
- Percentile: 90.0
- Lexical Diversity: 2.86792
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14226643', '15064002', '15650274', '15391604', '13765643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8588283008034256
- 35 USC 102 Novelty (BERT): 0.4978844098247044
- Combined Prediction Score: 0.8227339117055535
- Mean Citation Score: 219.374328
- Max Citation Score: 225.80673
- Similarity Product: 151.37301733502449

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test