PATENT CLAIM ANALYSIS

Application Number: 15862930
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

Claim (Index 12):
A method of forming a semiconductor structure, comprising:\n forming a plurality of fins disposed over a top surface of a substrate; and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process; wherein a gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin; wherein forming the one or more VTFETs comprises:\n forming bottom source/drain regions disposed over the top surface of the substrate surrounding the plurality of fins; \n forming bottom spacers disposed over the bottom source/drain regions; \n forming an oxide layer disposed over the bottom spacers and sidewalls of the plurality of fins; \n forming a dummy gate disposed over the oxide layer; \n recessing the dummy gate below top surfaces of the plurality of fins; \n removing exposed portions of the oxide layer; \n forming top spacers disposed over the dummy gate and the plurality of fins; \n wherein the dummy gate comprises a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:\n a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and \n a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device; and \n wherein forming the one or more VTFETs further comprises:\n patterning a gate opening in an interlevel dielectric layer disposed over a top spacer disposed over the shared dummy gate; \n removing portions of the interlevel dielectric layer to expose a portion of the top surface of the top spacer; \n forming a liner on exposed sidewalls of the interlevel dielectric layer in the gate opening; and \n removing the shared dummy gate.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 86.0
- Lexical Diversity: 1.94
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15852109', '15426479', '15819109', '15245634', '15831354']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919578755853882
- 35 USC 102 Novelty (BERT): 0.5066727047643141
- Combined Prediction Score: 0.8782881507449252
- Mean Citation Score: 264.368154
- Max Citation Score: 295.12448
- Similarity Product: 238.3352889471436

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test