PATENT CLAIM ANALYSIS

Application Number: 15868513
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["711", "207000"]

Abstract:
A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

Claim (Index 12):
The method of  claim 9 , further comprising:\n executing a page size assignment instruction to assign the first page size to the first way.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 86.0
- Lexical Diversity: 2.66
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13667440', '10750523', '10643765', '13517763', '13517738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4934535813171387
- 35 USC 102 Novelty (BERT): 0.4953311083156522
- Combined Prediction Score: 0.49364133401699
- Mean Citation Score: 161.504086
- Max Citation Score: 164.86417
- Similarity Product: 95.6215990886736

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test