PATENT CLAIM ANALYSIS

Application Number: 15960698
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["257", "686000"]

Abstract:
Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.

Claim (Index 3):
The semiconductor package of  claim 2 ,\n wherein the first lower supporter is positioned between the lower semiconductor chip and the lower conductive connection, and wherein the lower conductive connection is positioned between the first lower supporter and the second lower supporter.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 2.65909
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14493379', '10844877', '15051171', '14448794', '15956414']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239351842013662
- 35 USC 102 Novelty (BERT): 0.4812725040254584
- Combined Prediction Score: 0.8796689161837754
- Mean Citation Score: 201.072614
- Max Citation Score: 204.14877
- Similarity Product: 157.78319857100487

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test