PATENT CLAIM ANALYSIS

Application Number: 16022568
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "185170"]

Abstract:
According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.

Claim (Index 9):
The semiconductor storage device of  claim 8 , wherein\n the third contact plugs do not overlap with each other when viewed in the second direction, and the fourth contact plugs do not overlap with each other when viewed in the second direction.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.74074
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14788629', '15583609', '13784735', '15905827', '15919480']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8591915973719922
- 35 USC 102 Novelty (BERT): 0.5477321524258527
- Combined Prediction Score: 0.8280456528773783
- Mean Citation Score: 298.93750200000005
- Max Citation Score: 358.5903
- Similarity Product: 263.24677619608644

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test