PATENT CLAIM ANALYSIS

Application Number: 16159049
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "145000"]

Abstract:
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

Claim (Index 17):
The method of  claim 10 , further comprising:\n identifying a first voltage level of a digit line during an access operation, the first voltage level based at least in part on the first state associated with the ferroelectric capacitor, the second state associated with the middle electrode, and a voltage applied to the digit line.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 2.48276
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16032398', '15619158', '16159023', '15619163', '15246249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8233979641689722
- 35 USC 102 Novelty (BERT): 0.5038368230277058
- Combined Prediction Score: 0.7914418500548456
- Mean Citation Score: 279.192646
- Max Citation Score: 301.81067
- Similarity Product: 223.3879481460673

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test