PATENT CLAIM ANALYSIS

Application Number: 15983678
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["330", "288000"]

Abstract:
A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Claim (Index 3):
The multiplexing amplifier of  claim 1  further comprising:\n a gate voltage bias circuit, said gate voltage bias circuit coupled to an external temperature compensation current source at its drain terminus and said gate voltage bias circuit further coupled at its gate terminus to each pHEMPT stage amplifier to provide a gate bias voltage.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.17544
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15451096', '14881998', '13528222', '13224430', '13271566']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.802261697303525
- 35 USC 102 Novelty (BERT): 0.5501169640174456
- Combined Prediction Score: 0.7770472239749171
- Mean Citation Score: 316.5974
- Max Citation Score: 417.6103
- Similarity Product: 324.2484554171442

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test