PATENT CLAIM ANALYSIS

Application Number: 16112066
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "700000"]

Abstract:
An apparatus comprising a printed circuit board (PCB) that includes: a multilayer lamination of layers; vias on a surface of the PCB; and bonding pads that couple a ball grid array of an integrated circuit (IC) package to layers through the vias, wherein the bonding pads includes: first bonding pads in a first area of the PCB, each first bonding pad being coupled to a via of the vias in the first area, second bonding pads arranged in a second area of the PCB, each second bonding pad being coupled to a via of the vias in the second area, and third bonding pads arranged in a third area of the PCB, each third bonding pad being coupled to two or more vias of the vias in the third area, wherein the third area is located between the first area and the second area is disclosed.

Claim (Index 5):
The apparatus of  claim 1 , wherein the plurality of vias include:\n second vias that are coupled to the third bonding pads and that are conductive vias.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.89286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15630636', '14088094', '10459140', '15085080', '13275588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9151699616003578
- 35 USC 102 Novelty (BERT): 0.5832451202234589
- Combined Prediction Score: 0.881977477462668
- Mean Citation Score: 304.5805220000001
- Max Citation Score: 465.93042
- Similarity Product: 428.63308259188415

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test