PATENT CLAIM ANALYSIS

Application Number: 15771047
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-08
Patent Classification: ["257", "040000"]

Abstract:
The present disclosure relates to a thin film transistor (TFT) substrate, a manufacturing method thereof, and an organic light-emitting (OLED) substrate. The interlayer dielectric layer manufactured by the manufacturing method may be configured in the structure of two silicon oxide layers sandwiching one silicon nitride layer. As such, the bonding force between the interlayer dielectric layer and the gate, and the bonding force between the interlayer dielectric layer, and the source and the drain may be improved. The source and the drain may be prevented from falling off from the interlayer dielectric layer during the annealing process. Production yield of the TFT substrate may be improved. The OLED substrate adopting the manufactured of the OLED substrate of the present disclosure may have a better production yield and quality.

Claim (Index 7):
A thin film transistor (TFT) substrate, comprising:\n a base substrate, a buffer layer configured on the base substrate, an active layer configured on the buffer layer, a gate insulation layer configured on the active layer and the buffer layer, a gate configured on the gate insulation layer, an interlayer dielectric layer configured on the gate and the gate insulation layer, and a source and a drain configured on the interlayer dielectric layer; wherein a source-contacting hole and a drain-contacting hole are configured in the interlayer dielectric layer and the gate insulation layer, the source-contacting hole and the drain-contacting hole respectively correspond to two ends of the active layer, and the source and the drain respectively contact with the two ends of the active layer via the source-contacting hole and the drain-contacting hole; wherein the interlayer dielectric layer comprises a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer configured on the gate and the gate insulation layer in sequence from bottom to up, such that the gate is in direct contact with the first silicon oxide layer and the source and the drain are in direct contact with the second silicon oxide layer; and wherein each of the source and the drain comprises a source-drain metal layer that comprises an aluminum thin film and at least one titanium thin film configured on two ends of the aluminum thin film, the at least one titanium thin film being in contact with the second silicon oxide layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.2
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15569775', '15544023', '15773690', '14422343', '15569776']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9267611267326326
- 35 USC 102 Novelty (BERT): 0.5203553046778905
- Combined Prediction Score: 0.8861205445271584
- Mean Citation Score: 296.644552
- Max Citation Score: 331.61557
- Similarity Product: 261.4905819522375

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test