PATENT CLAIM ANALYSIS

Application Number: 16012362
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["438", "218000"]

Abstract:
A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

Claim (Index 1):
A method of manufacturing a semiconductor device, comprising the steps of:\n (a) providing a semiconductor substrate including a first region for a first transistor, a second region for a nonvolatile memory cell and a third region for a second transistor; (b) forming a first gate insulating film for the first transistor over a main surface of the semiconductor substrate in the first region; (c) after the step (b), forming a second gate insulating film including a charge trapping layer for the nonvolatile memory cell over the main surface of the semiconductor substrate in the second region; (d) after the step (c), forming a third gate insulating film for the second transistor over the main surface of the semiconductor substrate in the third region; (e) after the step (d), forming a first film over the main surface of the semiconductor substrate covering the first, second and third gate insulating films; and (f) after the step (e), patterning the first film for forming a first gate electrode for the first transistor in the first region, a second gate electrode for the nonvolatile memory cell in the second region and a third gate electrode for the second transistor in the third region, wherein a thickness of the first gate insulating film for the first transistor is larger than that of the third gate insulating film for the third transistor.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 3.62791
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15592279', '15062504', '14085825', '15043576', '15404463']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8652016902864212
- 35 USC 102 Novelty (BERT): 0.5330833785282495
- Combined Prediction Score: 0.8319898591106041
- Mean Citation Score: 345.86198199999984
- Max Citation Score: 356.17978
- Similarity Product: 306.18948645635606

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test