PATENT CLAIM ANALYSIS

Application Number: 15992239
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["345", "520000"]

Abstract:
Techniques for improving memory utilization for communication between stages of a graphics processing pipeline are disclosed. The techniques include analyzing output instructions of a first shader program to determine whether any such output instructions output some data that is not used by a second shader program. The compiler performs data packing if gaps exist between used output data to reduce memory footprint. The compiler generates optimized output instructions in the first shader program and optimized input instructions in the second shader program to output the used data from the first shader program and input that data in the second shader program in a packed format based on information about usage of output data and data packing. If needed, the compiler inserts instructions to perform runtime checking to identify unused output data of the first shader program based on information not known at compile-time.

Claim (Index 17):
The computer system of  claim 10 , wherein:\n the graphics pipeline state is pre-defined at application startup; and the identifying, determining, and modifying steps occur at application startup.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 2.06944
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15221431', '13829900', '13631866', '12505402', '13631865']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6636936475598219
- 35 USC 102 Novelty (BERT): 0.4909701153731552
- Combined Prediction Score: 0.6464212943411551
- Mean Citation Score: 194.700052
- Max Citation Score: 201.24304
- Similarity Product: 138.3007443556118

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test