PATENT CLAIM ANALYSIS

Application Number: 15900479
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "401000"]

Abstract:
High-mobility semiconductor fins are formed on an insulator layer using techniques allowing precise control of fin heights. Lattice-matched fins are grown epitaxially on sidewalls of an essentially defect-free portion of a semiconductor template. The fins are formed within laterally extending trenches in a top dielectric layer, the thickness of which determines fin height. The trenches extend orthogonally to the template. Epitaxial overgrowth above the top dielectric layer is removed by planarization. The fin template and top dielectric layer are removed, leaving sets of parallel fins on the insulator layer. The fin template can be replaced by an isolation region for electrically isolating sets of fins.

Claim (Index 1):
A method of fabricating a monolithic structure including parallel semiconductor fins, comprising:\n obtaining a first structure including:\n a semiconductor substrate, \n a bottom dielectric layer on the substrate, \n a top dielectric layer on the bottom dielectric layer, \n a first trench extending vertically through the top dielectric layer and the bottom dielectric layer and exposing a top surface portion of the semiconductor substrate, and \n an epitaxial semiconductor pillar within the first trench and directly on the exposed top surface portion of the semiconductor substrate; \n forming a plurality of parallel second trenches extending vertically through the top dielectric layer and orthogonally with respect to the first trench, the second trenches including bottom ends adjoining the bottom dielectric layer and inner ends adjoining the semiconductor pillar; epitaxially growing a plurality of semiconductor fins directly on the semiconductor pillar such that the semiconductor fins extend laterally from the semiconductor pillar within the plurality of second trenches, the semiconductor fins adjoining the bottom dielectric layer; removing the semiconductor pillar from at least a top portion of the first trench adjoining the top dielectric layer, and filling at least the top portion of the first trench with electrically insulating material.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 88.0
- Lexical Diversity: 1.80952
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14961372', '14962401', '15344272', '15344256', '15818674']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9108567418130908
- 35 USC 102 Novelty (BERT): 0.5090404070182107
- Combined Prediction Score: 0.8706751083336028
- Mean Citation Score: 278.293254
- Max Citation Score: 284.78265
- Similarity Product: 230.0133217238724

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test