PATENT CLAIM ANALYSIS

Application Number: 15944032
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "171000"]

Abstract:
The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.

Claim (Index 6):
The structure of  claim 1 , wherein the memory array circuit comprises the first reference data magnetic tunnel junction (reference data MTJ1), the first data magnetic tunnel junction (data MTJ1), the second data magnetic tunnel junction (data MTJ1), and the inverter connected to a first column.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.24138
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13613205', '15636970', '12784848', '14970564', '13764139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7789232722529086
- 35 USC 102 Novelty (BERT): 0.4641743532020257
- Combined Prediction Score: 0.7474483803478204
- Mean Citation Score: 180.946558
- Max Citation Score: 188.29303
- Similarity Product: 160.90576464813827

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test