PATENT CLAIM ANALYSIS

Application Number: 16114958
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["708", "603000"]

Abstract:
A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

Claim (Index 7):
The circuit of  claim 6 , wherein the second input of the third selection unit is configured to receive the second number.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 96.0
- Lexical Diversity: 4.15
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15275037', '10435976', '11749224', '15283606', '11019735']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4189506233069895
- 35 USC 102 Novelty (BERT): 0.5332702756205869
- Combined Prediction Score: 0.4303825885383493
- Mean Citation Score: 234.556014
- Max Citation Score: 320.34332
- Similarity Product: 227.7569865725613

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test