PATENT CLAIM ANALYSIS

Application Number: 16058550
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "043000"]

Abstract:
A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , group IIIA-nitrides, semiconductor oxides, and any combination thereof.

Claim (Index 26):
A method of preparing a multilayer structure in the manufacture of a semiconductor on insulator device, the multilayer structure comprising a single crystal silicon handle wafer comprising two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon handle wafer and the other of which is a back surface of the single crystal silicon handle wafer, a circumferential edge joining the front and back surfaces of the single crystal silicon handle wafer, a bulk single crystal silicon region, and the central plane of the single crystal silicon handle wafer between the front and back surfaces of the single crystal silicon handle wafer, wherein the single crystal silicon handle wafer comprises a p-type dopant and has a bulk resistivity between about 750 ohm cm and about 100,000 Ohm-cm, the method comprising:\n forming an intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon handle wafer, wherein the intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprising a material selected from the group consisting of Si 1-x C x  wherein x is a molar ratio with a value between 0.1 and 0.9, a group IIIA-nitride, a metal oxide, and any combination thereof; forming a charge trapping layer in interfacial contact with the intermediate semiconductor layer; and forming a semiconductor oxide layer in interfacial contact with the charge trapping layer.

Metadata:
- Claim Count in Document: 152.0
- Percentile: 96.0
- Lexical Diversity: 1.89091
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15112083', '15675001', '14524693', '15526640', '15984586']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9304435193234076
- 35 USC 102 Novelty (BERT): 0.5662770896185386
- Combined Prediction Score: 0.8940268763529208
- Mean Citation Score: 361.94157600000005
- Max Citation Score: 447.93643
- Similarity Product: 420.9151068690544

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test