PATENT CLAIM ANALYSIS

Application Number: 16403774
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-11
Patent Classification: ["327", "156000"]

Abstract:
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Claim (Index 4):
The time-to-digital converter circuit of  claim 1 , further comprising:\n a first trigger circuit to receive the first clock and the third clock and to generate the first trigger signal, wherein the first trigger circuit is to assert the first trigger signal responsive to an asserted edge of the third clock coincident with the first clock asserted high; and a second trigger circuit to receive the second clock and the third clock and to generate the second trigger signal, wherein the second trigger circuit is to assert the second trigger signal responsive to an asserted edge of the third clock coincident with the second clock asserted high.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 100.0
- Lexical Diversity: 2.625
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15991020', '16214179', '16218970', '16226938', '16101009']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7719500256119457
- 35 USC 102 Novelty (BERT): 0.5374419065823719
- Combined Prediction Score: 0.7484992137089883
- Mean Citation Score: 258.738598
- Max Citation Score: 383.09784
- Similarity Product: 352.39656383826247

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test