PATENT CLAIM ANALYSIS

Application Number: 15863993
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "072000"]

Abstract:
An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on the substrate and the gate. The insulating layer has an upper surface that is a plane. A source and a drain are disposed on the polycrystalline silicon layer and a pixel electrode is disposed on the insulating layer and a part of the drain. A plain passivation layer is disposed on the source and drain and includes a contact via formed therein at a location outside the polycrystalline silicon layer to expose a surface of one of the gate, the source, and the drain. A transparent electrode layer is disposed on the plain passivation layer to be electrically connected to the surface of the one of the gate, the source, and the drain that is exposed through the contact via.

Claim (Index 9):
The LTPS array substrate as claimed in  claim 8 , wherein the first impurity ions comprise N+ type impurity ions and the second impurity ions comprise N\u2212 type impurity ions.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.85455
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14762458', '14760750', '15863991', '14779089', '15853832']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9377790448710654
- 35 USC 102 Novelty (BERT): 0.5371506680171017
- Combined Prediction Score: 0.897716207185669
- Mean Citation Score: 336.925846
- Max Citation Score: 380.52533
- Similarity Product: 287.8659173712933

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test