PATENT CLAIM ANALYSIS

Application Number: 15892463
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["327", "536000"]

Abstract:
A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Claim (Index 1):
A bias regulator circuit comprising:\n a voltage divider including a first resistive element and a second resistive element; a first node of the voltage divider coupled to a first terminal of the first resistive element; a second node of the voltage divider coupled between a second terminal of the first resistive element and a first terminal of the second resistive element; a first amplifier with a first input coupled to an input voltage, and a second input coupled to the first node; a first power supply coupled to the first amplifier; a second power supply coupled to the first amplifier; an N-polarity metal-oxide semiconductor (NMOS) bias voltage node coupled to an output of the first amplifier, a plurality of NMOS devices, and the first node; a second amplifier with a first input coupled to a symmetry voltage, and a second input coupled to the second node; a third power supply coupled to the second amplifier; a fourth power supply coupled to the second amplifier; a P-polarity metal-oxide semiconductor (PMOS) bias voltage node coupled to the output of the second amplifier, the second terminal of the second resistive element, and a plurality of PMOS devices, wherein a voltage at the NMOS bias voltage node is configured to control a voltage at the PMOS bias voltage node such that the voltage at the PMOS bias voltage node symmetrically tracks the voltage at the NMOS bias voltage node about the symmetry voltage.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 88.0
- Lexical Diversity: 3.16667
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14840257', '10672793', '13754267', '11119130', '13196633']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7669831328458508
- 35 USC 102 Novelty (BERT): 0.4683687695048006
- Combined Prediction Score: 0.7371216965117459
- Mean Citation Score: 195.39971
- Max Citation Score: 199.53568
- Similarity Product: 161.2404627884865

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test