PATENT CLAIM ANALYSIS

Application Number: 15914079
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-12
Patent Classification: ["365", "145000"]

Abstract:
A ferroelectric field effect transistor is provided. Within the ferroelectric field effect transistor, a semiconductor substrate, a dielectric layer, a polarity retention layer and a conductive layer are sequentially fabricated. The polarity retention layer includes a ferroelectric layer and an anti-ferroelectric layer. By switching directions of electric dipoles in the ferroelectric layer, the operation speed of the memory including the ferroelectric field effect transistor is increased. A ferroelectric memory and a data writing method, a data reading method and a manufacturing method thereof are also provided.

Claim (Index 12):
A manufacturing method of a ferroelectric memory including a non-ferroelectric field effect transistor and a ferroelectric field effect transistor, comprising steps of:\n providing a semiconductor substrate made of a semiconductor material and doped with a material of a first conductivity type; forming a first dielectric layer and a word line on a first area of the semiconductor substrate; forming a second dielectric layer, a polarity retention layer and a control electrode on a second area of the semiconductor substrate; doping a material of a second conductivity type into the semiconductor substrate by using the word line and the control electrode as a mask to form a first doped region, a second doped region, a third doped region and a fourth region, the first doped region and the second doped region being adjacent to the first area, the third doped region and the fourth doped region being adjacent to the second area, wherein the non-ferroelectric field effect transistor comprises the first dielectric layer, the word line, the first doped region, the second doped region and the first area of the semiconductor substrate, and the ferroelectric field effect transistor comprises the second dielectric layer, the polarity retention layer, the control electrode, the third doped region, the fourth doped region and the second area of the semiconductor substrate; forming a first interconnect, a second interconnect, a third interconnect, a fourth interconnect and an electrode interconnect respectively on the first doped region, the second doped region, the third doped region, the fourth doped region and the control electrode; forming a plate electrically connected to the electrode interconnect and the second interconnect; forming a plate line electrically connected to the fourth interconnect; forming a bit-write line electrically connected to the first interconnect; and forming a bit-read line electrically connected to the third interconnect.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.08696
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15385593', '15360238', '14338996', '15903216', '15797774']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.80632238355949
- 35 USC 102 Novelty (BERT): 0.498225922171279
- Combined Prediction Score: 0.775512737420669
- Mean Citation Score: 261.059708
- Max Citation Score: 284.8116
- Similarity Product: 215.57675558202263

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test