PATENT CLAIM ANALYSIS

Application Number: 15989105
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["711", "122000"]

Abstract:
Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.

Claim (Index 14):
The cache controller of  claim 12 , wherein the converter is further configured to drop any pending speculative loads that are executing at stages of the instruction pipeline internal to the processor, in response to the flush request.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 2.43636
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15244873', '13649505', '11210557', '09753053', '11016200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5844291347594617
- 35 USC 102 Novelty (BERT): 0.569462214606381
- Combined Prediction Score: 0.5829324427441537
- Mean Citation Score: 330.64841
- Max Citation Score: 476.12300000000016
- Similarity Product: 386.362355456412

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test