PATENT CLAIM ANALYSIS

Application Number: 15897811
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "063000"]

Abstract:
According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Claim (Index 2):
A semiconductor memory device, comprising:\n a substrate; a first semiconductor layer extending in a first direction crossing a surface of the substrate: a second semiconductor layer extending in the first direction, the first semiconductor layer and the second semiconductor layer being arranged in a second direction crossing the first direction; a third semiconductor layer extending in the second direction, the third semiconductor layer being connected with the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer extending in the first direction; a fifth semiconductor layer extending in the first direction, the fourth semiconductor layer and the fifth semiconductor layer being arranged in the second direction; a sixth semiconductor layer extending in the second direction, the sixth semiconductor layer being connected with the fourth semiconductor layer and the fifth semiconductor layer; a seventh semiconductor layer extending in the first direction; an eighth semiconductor layer extending in the first direction, the seventh semiconductor layer and the eighth semiconductor layer being arranged in the second direction; a ninth semiconductor layer extending in the second direction, the ninth semiconductor layer being connected with the seventh semiconductor layer and the eighth semiconductor layer; a first bit line electrically connected with the first semiconductor layer; a second bit line electrically connected with the fifth semiconductor layer; a third bit line electrically connected with the seventh semiconductor layer; and a source line electrically connected with the second semiconductor layer, the fourth semiconductor layer, and the eighth semiconductor layer, the first semiconductor layer being adjacent to the seventh semiconductor layer in a third direction crossing the first and second directions, and the fourth semiconductor layer and the fifth semiconductor layer being disposed between the first semiconductor layer and the seventh semiconductor layer in the third direction.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 2.6
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15331026', '15007880', '15388691', '13524750', '14307196']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8179288568387071
- 35 USC 102 Novelty (BERT): 0.4961723120230426
- Combined Prediction Score: 0.7857532023571407
- Mean Citation Score: 284.076744
- Max Citation Score: 295.45004
- Similarity Product: 247.61934242519385

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test