PATENT CLAIM ANALYSIS

Application Number: 15869349
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["257", "329000"]

Abstract:
Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

Claim (Index 14):
The method of  claim 1  wherein the support structure includes a first section and a second section that is spaced from the first section, the semiconductor fin has a first end surface, a second end surface, and opposite sidewalls connected by the first end surface and the second end surface, and the first end surface and the second end surface of the semiconductor fin are arranged horizontally between the first section and the second section of the support structure.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 86.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15676300', '15586621', '15800563', '15427403', '15694109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.930083994231529
- 35 USC 102 Novelty (BERT): 0.5158599877788196
- Combined Prediction Score: 0.8886615935862581
- Mean Citation Score: 264.099646
- Max Citation Score: 318.81198
- Similarity Product: 274.5187972880316

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test