PATENT CLAIM ANALYSIS

Application Number: 15779410
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "040000"]

Abstract:
Provided are an OLED (Organic Light-Emitting Diode) display panel and a manufacturing method thereof. The OLED display panel comprises a plurality of scan lines (Sn), data lines (D 1  and D 2 ), and power lines (VDD), wherein the scan lines (Sn) and the data lines (D 1  and D 2 ) define a plurality of pixel groups arranged in a matrix; wherein each pixel group has two sub-pixels, two sub-pixels in a same pixel group connected to a same power line (VDD) and arranged in mirror symmetry with respect to the power line (VDD), and wherein the data lines (D 1  and D 2 ) connected to the two sub-pixels in the same pixel group are located on different structural layers. On one hand, the probability of occurrence of a short circuit between the data lines (D 1  and D 2 ) is effectively reduced, and crosstalk between the data lines (D 1  and D 2 ) is significantly eliminated. On the other hand, the pixel area can be reduced based on existing apparatuses and process conditions, improving the PPI of the OLED display panel, and enhancing the resolution of the OLED display panel.

Claim (Index 26):
The method for manufacturing an OLED display panel of  claim 12 , further comprising: forming a gate insulative layer and a plurality of first through holes, wherein the gate insulative layer is formed on the substrate and the silicon island, and wherein a drain of the first switch transistor, a lower plate of the first storage capacitor, a drain of the second switch transistor and a lower plate of the second storage capacitor are electrically connected via the first through holes;\n forming a patterned first metal layer on the gate insulative layer for forming the scan line, the lower plate of the first storage capacitor, the lower plate of the second storage capacitor, a gate of the first switch transistor, a gate of the first drive transistor, a gate of the second switch transistor and a gate of the second drive transistor, forming a first interlayer insulative layer and a second through hole, wherein the first interlayer insulative layer is formed on the gate insulative layer and the patterned first metal layer, and wherein the first data line and the source of the first switch transistor are electrically connected via the second through hole; forming a patterned second metal layer on the first interlayer insulative layer for forming the first data line, the source of the first switch transistor, and the upper plate of the second storage capacitor; forming a second interlayer insulative layer and a third through hole, wherein the second interlayer insulative layer is formed on the first interlayer insulative layer and the patterned second metal layer, and wherein the second data line and the source of the second switch transistor are electrically connected via the third through hole; forming a patterned third metal layer on the second interlayer insulative layer for forming the second data line, the source of the second switch transistor and the upper plate of the first storage capacitor; forming a third interlayer insulative layer and fourth through holes, wherein the third interlayer insulative layer is formed on the second interlayer insulative layer and the patterned third metal layer, and wherein the source and the drain of the first drive transistor, the source and the drain of the second drive transistor, the power line, the upper plate of the first storage capacitor and the upper plate of the second storage capacitor are electrically connected via the fourth through holes; forming a patterned fourth metal layer on the third interlayer insulative layer for forming the source and the drain of the first drive transistor, the source and the drain of the second drive transistor and the power line; and forming a passivated insulative layer and a plurality of contact holes, wherein the passivated insulative layer is formed on the third interlayer insulative layer and the patterned fourth metal layer; and wherein the drain of the first drive transistor, an anode of a first OLED, the drain of the second drive transistor and an anode of a second OLED are electrically connected via the contact holes.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.67059
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14630662', '15509198', '15005758', '13397563', '15736305']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9249223257051796
- 35 USC 102 Novelty (BERT): 0.4974924522496573
- Combined Prediction Score: 0.8821793383596273
- Mean Citation Score: 247.45031
- Max Citation Score: 262.13794
- Similarity Product: 201.5505750094593

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test