PATENT CLAIM ANALYSIS

Application Number: 15983982
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["713", "192000"]

Abstract:
A system includes programmable systolic cryptographic modules for security processing of packets from a data source. A first programmable input/output interface routes each incoming packet to one of the systolic cryptographic modules for encryption processing. A second programmable input/output interface routes the encrypted packets from the one systolic cryptographic module to a common data storage. In one embodiment, the first programmable input/output interface is coupled to an interchangeable physical interface that receives the incoming packets from the data source. In another embodiment, each cryptographic module includes a programmable systolic packet input engine, a programmable cryptographic engine, and a programmable systolic packet output engine, each configured as a systolic array (e.g., using FPGAs) for data processing.

Claim (Index 29):
The system of  claim 28 , further comprising at least one memory, wherein the at least one memory is configured to store the at least one key, and the cryptographic engine is further configured to load the at least one key from the at least one memory.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 2.28571
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14177392', '15072730', '14217912', '14198097', '15355303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4720204264662425
- 35 USC 102 Novelty (BERT): 0.5449183121982004
- Combined Prediction Score: 0.4793102150394383
- Mean Citation Score: 350.09630400000015
- Max Citation Score: 412.4897
- Similarity Product: 315.8423726783872

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test