PATENT CLAIM ANALYSIS

Application Number: 16390210
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["438", "268000"]

Abstract:
A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.

Claim (Index 11):
The device of  claim 10 , wherein the tip of the gate electrode is in contact with the metal gate.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 100.0
- Lexical Diversity: 1.68627
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15615901', '15347255', '13225431', '12164067', '14285065']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8542014834860877
- 35 USC 102 Novelty (BERT): 0.4832166316694994
- Combined Prediction Score: 0.8171029983044289
- Mean Citation Score: 152.668974
- Max Citation Score: 183.36166
- Similarity Product: 132.62539760710715

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test