PATENT CLAIM ANALYSIS

Application Number: 15994370
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["370", "503000"]

Abstract:
A communication system controller having an input for receiving output signals of a sending device. The communication system controller further has a clock signal. The communication system controller further has an output for transmitting input signals to a target device. The communication system controller further has a signal processing element capable of determining if the received output signals of the sending device are synchronous with the clock signal. The signal processing element is further capable of determining if the received output signals of the sending device are asynchronous with the clock signal. The communication system controller is capable of transmitting the received output signals of the sending device as input signals to the target device if the received output signals of the sending device are determined to be synchronous with the clock signal.

Claim (Index 8):
A system for controlling synchronization of signals in a system of devices, the system for controlling synchronization of signals comprising:\n a processor; and a computer-readable storage medium storing computer-readable instructions, which when executed by the processor, cause the processor to perform steps of:\n receiving a first signal from a first transmitting device to a first destination device; \n initializing an estimator by setting a first initial sampling time estimate and a first initial covariance of estimation error; \n determining a first time interval of the received first signal between a first current time step and a first previous time step; \n estimating a first probability of synchronicity, wherein the first probability is estimated by applying a first Mahalanobis distance as a metric; \n based on the estimated first probability of synchronicity, determining the first signal is synchronous with an internal clock of a computing device; \n based on the determination that the first signal is synchronous with the internal clock of the computing device:\n flagging the first transmitting device as a synchronous device; and \n transmitting the first signal to the first destination device; \n \n receiving a second signal from a second transmitting device to a second destination device; \n initializing the estimator by setting a second initial sampling time estimate and a second initial covariance of estimation error; \n determining a second time interval of the received second signal between a second current time step and a second previous time step; \n estimating a second probability of synchronicity, wherein the second probability is estimated by applying a second Mahalanobis distance as a second metric; \n based on the estimated second probability of synchronicity, determining that the second signal is asynchronous with the internal clock of the computing device; and \n based on the determination that the second signal is asynchronous with the internal clock of the computing device:\n flagging the second transmitting device as an asynchronous device; and \n transmitting the second signal to a synchronization device.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 93.0
- Lexical Diversity: 3.5641
- Patent Class: 370.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11746275', '12165257', '13099133', '11773344', '13071287']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5272104080725326
- 35 USC 102 Novelty (BERT): 0.4662171699281307
- Combined Prediction Score: 0.5211110842580924
- Mean Citation Score: 112.0721448
- Max Citation Score: 124.18919
- Similarity Product: 86.04909111316384

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test