PATENT CLAIM ANALYSIS

Application Number: 15975266
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-03
Patent Classification: ["365", "194000"]

Abstract:
A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Claim (Index 3):
The non-volatile memory device of  claim 2 , wherein a phase of the plurality of serial pipeline driving clock signals is delayed from the serializer to the FIFO memory.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 93.0
- Lexical Diversity: 2.28302
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15403923', '14600366', '11984145', '10463781', '14995834']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8130128395801107
- 35 USC 102 Novelty (BERT): 0.5002766112827023
- Combined Prediction Score: 0.7817392167503698
- Mean Citation Score: 220.013178
- Max Citation Score: 260.94525
- Similarity Product: 177.16414559085666

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test