PATENT CLAIM ANALYSIS

Application Number: 15909494
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.

Claim (Index 8):
A semiconductor memory device, comprising:\n a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate; a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region; a plurality of electrode layers stacked on a substrate in a first direction, spaced from each in the first direction, and extending in a second direction from the memory cell region into the contact region; a first semiconductor pillar in the memory cell region and extending through the plurality of electrode layers in a third direction to the first semiconductor well, a charge trap film coating an outer surface of the first semiconductor pillar between the first semiconductor pillar and each electrode layer of the plurality; a second semiconductor pillar in the contact region extending in the third direction through at least one electrode layer in the plurality to the substrate, an insulating film coating an outer surface of the second semiconductor pillar between the second semiconductor pillar and the at least one electrode layer; and a third semiconductor well of the first conductivity type in the second semiconductor well, the second semiconductor well being between the first and third semiconductor wells, wherein a lower end portion of the second semiconductor pillar along the first direction directly contacts the third semiconductor well.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 3.51111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15909451', '13051595', '14819706', '15008671', '15266850']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.915017129801024
- 35 USC 102 Novelty (BERT): 0.4676494279732115
- Combined Prediction Score: 0.8702803596182428
- Mean Citation Score: 200.834398
- Max Citation Score: 213.02965
- Similarity Product: 189.52075880538823

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test