PATENT CLAIM ANALYSIS

Application Number: 15863000
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "334000"]

Abstract:
Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg 1 , wherein the gates formed alongside the second fin(s) have a second gate length Lg 2 , and wherein Lg 1 <Lg 2 ; forming top spacers over the gates; and forming top source/drains over the top spacers. A VFET is also provided.

Claim (Index 12):
The method of  claim 1 , further comprising the steps of:\n forming a trench in the wafer between the at least one first fin and the at least one second fin; and filling the trench with a dielectric to isolate the at least one first fin from the at least one second fin.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 86.0
- Lexical Diversity: 2.52941
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15853769', '15853822', '15812843', '15843318', '15833543']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9269605205065904
- 35 USC 102 Novelty (BERT): 0.5667988434960938
- Combined Prediction Score: 0.8909443528055409
- Mean Citation Score: 410.113332
- Max Citation Score: 464.81003
- Similarity Product: 350.1627612144613

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test