PATENT CLAIM ANALYSIS

Application Number: 16412210
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "382000"]

Abstract:
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Claim (Index 12):
A computing device, comprising:\n a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a fin comprising silicon, the fin having a length along a first direction; a first gate structure over the fin and along a second direction orthogonal to the first direction, the first gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers; a second gate structure over the fin and along the second direction, the second gate structure adjacent the first gate structure, and the second gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers; a third gate structure over the fin and along the second direction, the third gate structure adjacent the second gate structure, and the third gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers; a fourth gate structure over the fin and along the second direction, the fourth gate structure adjacent the third gate structure, and the fourth gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers; a first conductive contact structure over the fin and along the second direction, the first conductive contact structure between the first gate structure and the second gate structure, and the first conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the first gate structure and with the dielectric cap of the second gate structure; a second conductive contact structure over the fin and along the second direction, the second conductive contact structure between the second gate structure and the third gate structure, and the second conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the second gate structure and with the dielectric cap of the third gate structure; and a third conductive contact structure over the fin and along the second direction, the third conductive contact structure between the third gate structure and the fourth gate structure, and the third conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the third gate structure and with the dielectric cap of the fourth gate structure.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 100.0
- Lexical Diversity: 2.79167
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15624036', '13995678', '14827510', '14951726', '14854590']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9252998135229332
- 35 USC 102 Novelty (BERT): 0.5600330503182409
- Combined Prediction Score: 0.8887731372024639
- Mean Citation Score: 332.48802
- Max Citation Score: 452.26398
- Similarity Product: 361.3642687268329

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test