PATENT CLAIM ANALYSIS

Application Number: 16255361
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "185050"]

Abstract:
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Claim (Index 19):
The memory bank of  claim 17 , wherein the shift register based multiplexing signal generator comprises one column select output, with a plurality of lines connecting the one column select with each of two different memory matrices of the memory bank, there being no more than 12 lines between the multiplexing signal generator and each of the memory matrices.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.93939
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15986531', '15327927', '12867822', '16095001', '15114823']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7710905667431878
- 35 USC 102 Novelty (BERT): 0.4848600658347819
- Combined Prediction Score: 0.7424675166523472
- Mean Citation Score: 186.692888
- Max Citation Score: 266.06506
- Similarity Product: 259.8355670764589

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test