PATENT CLAIM ANALYSIS

Application Number: 15980436
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "192000"]

Abstract:
A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.

Claim (Index 8):
The method according to  claim 7 , wherein the epi S/D comprises epitaxially grown silicon germanium (SiGe).

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 2.75
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15592172', '13948374', '15423326', '14744080', '15638087']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92889455762214
- 35 USC 102 Novelty (BERT): 0.5099346176809028
- Combined Prediction Score: 0.8869985636280163
- Mean Citation Score: 255.311454
- Max Citation Score: 282.75342
- Similarity Product: 204.1970471997285

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test