PATENT CLAIM ANALYSIS

Application Number: 15864371
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["708", "603000"]

Abstract:
An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

Claim (Index 13):
The arithmetic logic unit of  claim 1 , further comprising a backend circuit used for additional logic function with the adder output, the backend circuit including a Rotator, two operand circuits and a fusing circuit wherein the output of the first operand circuit forms a first input to the fusing circuit, the output of the adder forms a second input to the fusing circuit, the output of the second operand circuit forms a third input to the fusing circuit, and the output of the Rotator forms a fourth input to the fusing circuit; further wherein:\n each operand circuit comprises an inverter, and two AND gates whose outputs are the two inputs to an OR gate, and the first input to the first AND gate is a first control signal, the second input to the first AND gate is the third operand, and the input to the inverter is the third operand with the output of the inverter forming the first input to the second AND gate, and the second input to the second AND gate is a second control signal; and the fusing circuit comprises two AND gates whose outputs are the two inputs to an OR gate, wherein the first and second inputs to the first AND gate of the fusing circuit are the output from the first operand circuit, and the output of the adder; and the first and second inputs of the second AND gate of the fusing circuit are the output of the second operand circuit and the output of the Rotator.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 2.73913
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10893163', '10406046', '10035033', '11506283', '11760553']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4576781137183733
- 35 USC 102 Novelty (BERT): 0.5047816426670514
- Combined Prediction Score: 0.4623884666132411
- Mean Citation Score: 248.514394
- Max Citation Score: 261.6972
- Similarity Product: 193.42184577748776

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test