PATENT CLAIM ANALYSIS

Application Number: 16137579
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["361", "301400"]

Abstract:
A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.

Claim (Index 1):
A multilayer capacitor comprising:\n a laminate including conductor layers and dielectric layers alternately laminated, the laminate including external dimensions including a length of about 0.45 mm or less and a width of 0.25 mm or less when viewed from a lamination direction; and a first outer electrode and a second outer electrode disposed on surfaces of the laminate, which are spaced from each other in a lengthwise direction of the laminate; wherein in the laminate, the dielectric layers and the conductor layers are alternately laminated such that the conductor layers are in a first arrangement and a second arrangement, the second arrangement being different from the first arrangement when viewed from the lamination direction, and such that the conductor layers are included in the first arrangement or the second arrangement; the first outer electrode is connected to ones of the conductor layers included in the first arrangement; the second outer electrode is connected to others of the conductor layers included in the second arrangement; a width of each of the conductor layers has a difference of less than about 0.12 mm between a width of the conductor layer and a width of the laminate, and is about 70% or less of the width of the laminate; at least one of the dielectric layers is an ineffective dielectric layer that is sandwiched between the conductor layers both included in one of the first arrangement and the second arrangement; at least one of the dielectric layers is an effective dielectric layer that is sandwiched between the conductor layer included in the first arrangement and the conductor layer included in the second arrangement; at least one of the conductor layers adjacent to the effective dielectric layer is curved in the lamination direction; and each of a plurality of the conductor layers has an arc shape in which a thickness of a central portion of the conductor layer in a widthwise direction of the laminate is greater than a thickness of an end portion of the conductor layer in the widthwise direction.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.29231
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15802642', '15802648', '14943771', '15014164', '15728568']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8459198343835295
- 35 USC 102 Novelty (BERT): 0.5748474956094558
- Combined Prediction Score: 0.8188126005061221
- Mean Citation Score: 382.63301999999993
- Max Citation Score: 457.0873
- Similarity Product: 446.02109112474335

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test