PATENT CLAIM ANALYSIS

Application Number: 16038052
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-04
Patent Classification: ["257", "296000"]

Abstract:
Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Claim (Index 6):
The semiconductor memory device of  claim 1 ,\n wherein the first electrode comprises a first end portion that is adjacent and connected to the drain region, wherein the first electrode further comprises a second end portion that is opposite the first end portion, and wherein an axis that extends through the first end portion and the second end portion is parallel to the first direction.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 2.75
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15708266', '15259941', '14735811', '15245218', '13366818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9147608924685552
- 35 USC 102 Novelty (BERT): 0.5015586111478945
- Combined Prediction Score: 0.873440664336489
- Mean Citation Score: 236.367428
- Max Citation Score: 247.97386
- Similarity Product: 193.20930826187129

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test