PATENT CLAIM ANALYSIS

Application Number: 16040149
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.

Claim (Index 7):
The strained vertical p-type field effect transistor of  claim 6 , further comprising a gate fill layer on the work function layer, wherein the gate fill layer extends below the bottom spacer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.35417
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15450715', '15273252', '15627875', '15426739', '15087495']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9232861822515472
- 35 USC 102 Novelty (BERT): 0.5562276013827376
- Combined Prediction Score: 0.8865803241646661
- Mean Citation Score: 381.547884
- Max Citation Score: 466.21127
- Similarity Product: 276.3784428102803

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test