PATENT CLAIM ANALYSIS

Application Number: 16104709
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["365", "145000"]

Abstract:
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

Claim (Index 16):
A method of accessing a memory cell, comprising:\n activating first and second transistors of the memory cell; applying a voltage to a plate line coupled to first and second ferroelectric capacitors, the first ferroelectric capacitor coupled to the first transistor and vertically displaced relative to the first transistor and the second ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor; and comparing a first voltage developed at a first digit line coupled to the first ferroelectric capacitor to a second voltage developed at a second digit line coupled to the second ferroelectric capacitor.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 96.0
- Lexical Diversity: 2.2381
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15678978', '15679016', '16058202', '15679032', '15919994']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.812371708892052
- 35 USC 102 Novelty (BERT): 0.513594692598267
- Combined Prediction Score: 0.7824940072626735
- Mean Citation Score: 249.98536600000003
- Max Citation Score: 334.1724
- Similarity Product: 285.4698248097897

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test