PATENT CLAIM ANALYSIS

Application Number: 15954874
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "306000"]

Abstract:
An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Claim (Index 1):
A method of manufacturing an integrated circuit comprising at least one high-voltage MOS (HV) transistor and at least one capacitor, the method comprising the successive steps of:\n a) forming, on a semiconductor layer, a first insulating layer at a location of the HV transistor; b) depositing a first polysilicon layer; c) forming a gate stack of the HV transistor and a first electrode of the capacitor by etching the first polysilicon layer; d) successively forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer; e) depositing a second polysilicon layer; f) forming a second electrode of the capacitor at least partly resting over the first electrode by etching the second polysilicon layer, and removing the exposed portions of the second oxide layer by leaving the silicon nitride layer and the first silicon oxide layer; g) forming, on the silicon nitride layer, first silicon oxide spacers laterally bordering the gate stack of the HV transistor and the first and second electrodes; and h) forming second silicon nitride spacers laterally bordering the gate stack of the HV transistor and the first and second electrodes.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 91.0
- Lexical Diversity: 2.86538
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15133394', '11738003', '15296205', '14305137', '15370149']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.906684620787254
- 35 USC 102 Novelty (BERT): 0.5798856335640932
- Combined Prediction Score: 0.8740047220649381
- Mean Citation Score: 310.011526
- Max Citation Score: 476.95374
- Similarity Product: 403.9509924851132

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test