PATENT CLAIM ANALYSIS

Application Number: 15909073
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "296000"]

Abstract:
A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

Claim (Index 15):
A method of forming a three-dimensional memory device, comprising:\n forming a first alternating stack of first insulating layers and first spacer material layers over a substrate, wherein the first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers; forming first stepped surfaces by patterning the first alternating stack; forming a first retro-stepped dielectric material portion on the first stepped surfaces of the first alternating stack; forming a second alternating stack of second insulating layers and second spacer material layers over the first alternating stack, wherein the second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers; forming second stepped surfaces by patterning the second alternating stack; forming a second retro-stepped dielectric material portion on the second stepped surfaces of the second alternating stack; forming memory stack structures through the first alternating stack and the second alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; forming contact via cavities through the first and second retro-stepped dielectric material portions using a reactive ion etch process that provides a higher average etch rate through the first retro-stepped dielectric material portion than through the second retro-stepped dielectric material portion; and forming contact via structures in the contact via cavities through the first and second retro-stepped dielectric material portions and on a respective one of the first and second electrically conductive layers.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.95745
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15632983', '15877219', '15489050', '15269294', '15269041']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9339814888027382
- 35 USC 102 Novelty (BERT): 0.571289418381822
- Combined Prediction Score: 0.8977122817606467
- Mean Citation Score: 466.246204
- Max Citation Score: 493.9883400000001
- Similarity Product: 352.9943054999578

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test