PATENT CLAIM ANALYSIS

Application Number: 16126316
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185050"]

Abstract:
A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

Claim (Index 11):
The method of  claim 9 , further comprising applying a third voltage to the first substrate region and the second substrate region, wherein the third voltage is different from the second voltage.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 2.61538
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15895732', '13786197', '10511712', '14864354', '13786202']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7732892783689838
- 35 USC 102 Novelty (BERT): 0.5359674841363704
- Combined Prediction Score: 0.7495570989457224
- Mean Citation Score: 273.135776
- Max Citation Score: 385.00443
- Similarity Product: 255.1386483410168

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test