PATENT CLAIM ANALYSIS

Application Number: 16111263
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "329000"]

Abstract:
Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Claim (Index 1):
A method comprising:\n forming a first source/drain region for a vertical field effect transistor of a memory cell of a memory array,\n the first source/drain region comprising a first semiconductor material and being above and immediately adjacent to a semiconductor region, \n the semiconductor region comprising a second semiconductor material that is different from the first semiconductor material and being above a top surface of a substrate, and \n the first source/drain region and the semiconductor region having essentially equal widths; \n etching back sidewalls of the semiconductor region such that the semiconductor region is narrower than the first source/drain region and such that cavities are created below the first source/drain region and positioned laterally adjacent to the semiconductor region; depositing a conductor to fill the cavities; and performing an etch process to remove any portion of the conductor that extends laterally beyond the cavities in order to create a bitline for the memory array, the bitline comprising:\n a pair of essentially parallel, elongated, bitline sections extending a length of the bitline and comprising a first bitline section and a second bitline section; and \n the semiconductor region positioned laterally between the first bitline section and the second bitline section.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 1.85542
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15661058', '16009331', '15994392', '15873156', '15920748']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.932983538720501
- 35 USC 102 Novelty (BERT): 0.5667156062176599
- Combined Prediction Score: 0.8963567454702169
- Mean Citation Score: 352.76871199999994
- Max Citation Score: 460.6132
- Similarity Product: 396.5787685390473

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test