PATENT CLAIM ANALYSIS

Application Number: 16105207
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["455", "078000"]

Abstract:
An apparatus includes an impedance matching network, a first switch circuit, and a second switch circuit. The impedance matching network generally comprises a first port, a second port, and a third port. The first switch circuit may be coupled between the first port and a circuit ground potential. The second switch circuit may be coupled between the second port and the circuit ground potential. The impedance matching network generally provides a first impedance value for the first port and for the third port when the second port is connected to the circuit ground potential. The impedance matching network generally provides a second impedance value for the second port and for the third port when the first port is connected to the circuit ground potential. The first impedance value and the second impedance value are asymmetrical.

Claim (Index 7):
The apparatus according to  claim 5 , wherein said transistor comprises at least one of a bipolar junction transistor, a metal-oxide-semiconductor (MOS) transistor, a field-effect transistor, or a pseudomorphic high electron mobility transistor (pHEMT).

Metadata:
- Claim Count in Document: 35.0
- Percentile: 96.0
- Lexical Diversity: 4.05556
- Patent Class: 455.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15825736', '12130869', '11765041', '14034081', '12621856']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7113994330679695
- 35 USC 102 Novelty (BERT): 0.5351449594425051
- Combined Prediction Score: 0.693773985705423
- Mean Citation Score: 238.65388
- Max Citation Score: 371.19785
- Similarity Product: 353.99955483815666

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test