PATENT CLAIM ANALYSIS

Application Number: 15938176
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "330000"]

Abstract:
A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.

Claim (Index 2):
The semiconductor device according to  claim 1 , wherein the width of the first trench and the width of the second trench are substantially the same size.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.78723
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12412962', '15872747', '11455888', '11772341', '13811057']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9272639196945134
- 35 USC 102 Novelty (BERT): 0.4972243736828936
- Combined Prediction Score: 0.8842599650933515
- Mean Citation Score: 232.305004
- Max Citation Score: 234.76169
- Similarity Product: 167.41413409175811

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test