PATENT CLAIM ANALYSIS

Application Number: 16394472
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["257", "066000"]

Abstract:
A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Claim (Index 3):
The semiconductor devices of  claim 2 , wherein a first set of spacers are disposed adjacent the first and second amorphous hydrogenated silicon layers of the HJFET.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 100.0
- Lexical Diversity: 2.52542
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15830639', '15660305', '15606317', '15266414', '14226285']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9436343092601588
- 35 USC 102 Novelty (BERT): 0.5878072706166259
- Combined Prediction Score: 0.9080516053958056
- Mean Citation Score: 427.3729
- Max Citation Score: 524.74994
- Similarity Product: 421.086371941917

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test