PATENT CLAIM ANALYSIS

Application Number: 15986628
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "296000"]

Abstract:
Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

Claim (Index 19):
The apparatus of  claim 18  wherein each capacitor is within a memory cell, with the memory cells being in one-to-one correspondence with the capacitors, and comprising:\n bitline pairs coupled with each of the memory cells, one of the bitlines within each bitline pair corresponding to a first comparative bitline and the other of the bitlines within each bitline pair corresponding to a second comparative bitline; \n the bitline pairs extending to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another; \n the memory cells being subdivided amongst a first memory cell set and a second memory cell set; the memory cells of the first memory cell set comprising the capacitors of the first capacitor set, and the memory cells of the second memory cell set comprising the capacitors of the second capacitor set; \n the memory cells of the first memory cell set using a first set of bitline pairs and a first set of sense amplifiers; \n the memory cells of the second memory cell set using a second set of bitline pairs and a second set of sense amplifiers; and \n the bitline pairs of the second set of bitline pairs comprising the same bitlines as the bitline pairs of the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.78571
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15797462', '15664161', '15900403', '15664140', '15664143']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9140875577470182
- 35 USC 102 Novelty (BERT): 0.5227763206474824
- Combined Prediction Score: 0.8749564340370647
- Mean Citation Score: 298.757582
- Max Citation Score: 325.2625700000001
- Similarity Product: 264.5667230727936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test