PATENT CLAIM ANALYSIS

Application Number: 15965505
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["327", "175000"]

Abstract:
A duty cycle correction circuit includes a first inverter suitable for driving a second clock in response to a first clock; a second inverter suitable for driving the first clock in response to the second clock; and a duty cycle detector suitable for detecting a duty cycle of the first clock or the second clock, wherein driving forces of one or more inverters among the first inverter and the second inverter are controlled based on a duty detection result of the duty cycle detector.

Claim (Index 15):
The clock correction circuit of  claim 14 , wherein the second duty cycle correction circuit includes:\n a third inverter suitable for driving the fourth clock in response to the third clock; a fourth inverter suitable for driving the third clock in response to the fourth clock; and a second duty cycle detector suitable for detecting a duty cycle of the third clock and a duty cycle of the fourth clock, and driving forces of one or more inverters of the third inverter and the fourth inverter are controlled based on the duty detection result of the second duty cycle detector.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 91.0
- Lexical Diversity: 2.31579
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13522745', '12071635', '14710326', '11323511', '14800392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7994871024566197
- 35 USC 102 Novelty (BERT): 0.485950006552022
- Combined Prediction Score: 0.7681333928661599
- Mean Citation Score: 235.270278
- Max Citation Score: 241.35959
- Similarity Product: 192.51860183784007

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test