PATENT CLAIM ANALYSIS

Application Number: 16176547
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "737000"]

Abstract:
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate and a conductive bond pad is separated from the substrate by the dielectric layer. A back-side through-substrate-via (BTSV) extends through the substrate and the dielectric layer. A conductive bump is arranged over the conductive bond pad. The conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump. A BTSV liner separates sidewalls of the BTSV from the substrate. The sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer.

Claim (Index 12):
The integrated chip of  claim 8 , further comprising:\n a BTSV liner arranged along sidewalls of the BTSV and separating the BTSV from the substrate, wherein the BTSV liner has an uppermost surface facing away from the substrate and directly contacting the bottommost surface of the conductive bond pad.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 97.0
- Lexical Diversity: 2.2381
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15143950', '16046183', '14750003', '15380186', '16167844']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9234850967264764
- 35 USC 102 Novelty (BERT): 0.5133384370039035
- Combined Prediction Score: 0.882470430754219
- Mean Citation Score: 252.56769
- Max Citation Score: 323.2159
- Similarity Product: 283.4490851188064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test