PATENT CLAIM ANALYSIS

Application Number: 15863566
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["716", "108000"]

Abstract:
An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.

Claim (Index 2):
The method of  claim 1 , further comprising selecting the clock signal by identifying the clock signal associated with a lowest jitter clock value of the jitter clock values associated with the plurality of clock signals, the lowest jitter clock value being the first jitter clock value.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.59259
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14952656', '14703727', '14507687', '15179893', '12630629']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2855213156344044
- 35 USC 102 Novelty (BERT): 0.5044825128313106
- Combined Prediction Score: 0.307417435354095
- Mean Citation Score: 193.302972
- Max Citation Score: 310.6329
- Similarity Product: 232.11510852708216

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test