PATENT CLAIM ANALYSIS

Application Number: 15970083
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["711", "154000"]

Abstract:
According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.

Claim (Index 10):
The semiconductor device according to  claim 1 , wherein\n the first master is formed by using a first processor, and the second master is formed by using a second processor.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 93.0
- Lexical Diversity: 1.97368
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11498230', '11657473', '09132085', '10500252', '10847627']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.553555284821639
- 35 USC 102 Novelty (BERT): 0.4824446365422609
- Combined Prediction Score: 0.5464442199937012
- Mean Citation Score: 193.742492
- Max Citation Score: 203.1443
- Similarity Product: 150.63811367414

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test