PATENT CLAIM ANALYSIS

Application Number: 15965872
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "421000"]

Abstract:
Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Claim (Index 16):
The memory device of  claim 15 , wherein:\n the first neighbor memory cell is arranged about 1050 Angstroms away from the memory cell along the first direction and is isolated by a dielectric material from the memory cell; and the second neighbor memory cell is arranged about 1700 Angstroms away from the memory cell along the second direction and is isolated by the dielectric material from the memory cell.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 2.54348
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14688073', '15601095', '15249559', '14801988', '15428509']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9036473431386328
- 35 USC 102 Novelty (BERT): 0.4972180907035707
- Combined Prediction Score: 0.8630044178951265
- Mean Citation Score: 175.88931399999996
- Max Citation Score: 181.69939
- Similarity Product: 120.99155379105984

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test