PATENT CLAIM ANALYSIS

Application Number: 16211589
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["365", "156000"]

Abstract:
In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Claim (Index 5):
The semiconductor memory device of  claim 1 , wherein the switch comprises a transistor, further comprising\n a memory controller configured to apply a pulse to a gate of the transistor in accordance with a programmable duration, and wherein a time measured between an edge of the pulse and a neighboring edge of a wordline signal has different values for different programmable durations.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 3.25532
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15911824', '15871484', '15627837', '16108672', '15388991']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7478376091611609
- 35 USC 102 Novelty (BERT): 0.4973071860270694
- Combined Prediction Score: 0.7227845668477518
- Mean Citation Score: 192.322156
- Max Citation Score: 286.12042
- Similarity Product: 257.9250029878664

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test