PATENT CLAIM ANALYSIS

Application Number: 16237657
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["716", "108000"]

Abstract:
The present invention provides theoretical bases and practical schematic diagrams for a state machine which is coded in HDL and synthesized to generate a circuit that comprises one or more state groups each of which has an independent clock gating device. A state group will receive a clock pulse on the next cycle when either a synchronous initialization input signal for a state machine is asserted on the current cycle or the state group will change states on the next cycle, reducing power consumption and simplifying the final logic, compared with a traditionally generated state machine circuit. In addition the invention also provides a code designer with a proposed method for HDL standard on how to divide all states in a state machine into state groups at his discretion.

Claim (Index 1):
A method for generating a circuit for a state machine, comprising:\n dividing a plurality of states into a plurality of state groups, and each state group of the plurality of state groups comprising at least one state in the plurality of states; defining a plurality of jumping signals, a currently asserted jumping signal in the plurality of jumping signals making the state machine jump from a current state of the currently asserted jumping signal to a target state of the currently asserted jumping signal on a next cycle; classifying a jumping signal of the plurality of jumping signals for each state group of the plurality of state groups into one of three categories, the three categories comprising:\n a true jumping signal when the current state and the target state of the jumping signal of the plurality of jumping signals are different, and the target state of the jumping signal of the plurality of jumping signals belongs to the each state group of the plurality of state groups; \n a holding jumping signal when the current state and the target state of the jumping signal of the plurality of jumping signals are the same and both belong to the each state group of the plurality of state groups; and \n a leaving jumping signal when the current state of the jumping signal of the plurality of jumping signals belongs to the each state group of the plurality of state groups, and the target state of the jumping signal of the plurality of jumping signals does not belong to the each state group of the plurality of state groups; \n feeding each state of the plurality of states with the at least one true jumping signal, and the each state of the plurality of states being a common target state of the at least one true jumping signal; feeding an initial state in the plurality of states with a synchronous initialization input signal SINI for the state machine; remembering each state group of the plurality of state groups by one independent memory group of a plurality of memory groups; attaching each memory group of the plurality of memory groups with one independent clock gating device of a plurality of clock gating devices; generating a clock pulse for a memory group of the plurality of memory groups on the next cycle when one of two first conditions is satisfied, the two first conditions comprising:\n the synchronous initialization input signal SINI for the state machine is asserted on a current cycle; or \n one state group of the plurality of state groups will make a state change on the next cycle, and the one state group of the plurality of state groups is remembered by the memory group of the plurality of memory groups; and \n generating a plurality of state outputs from the plurality of memory groups.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.61446
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15861093', '12121827', '11608558', '10262769', '10428170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3228799147548428
- 35 USC 102 Novelty (BERT): 0.463894724624409
- Combined Prediction Score: 0.3369813957417994
- Mean Citation Score: 164.27026999999995
- Max Citation Score: 197.74767
- Similarity Product: 146.25317541113375

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test