PATENT CLAIM ANALYSIS

Application Number: 16173289
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["341", "118000"]

Abstract:
Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced digital-to-analog converter (DAC) topology to enable offset correction without the need for a dedicated compensation DAC. This eliminates addition analog circuitry and die area. To perform the offset correction, the differential SAR ADC couples together inputs thereof to create an offset voltage, converts the offset voltage into a digital representation thereof, stores the digital representation of the offset voltage in an offset register, and corrects for the offset voltage by generating an offset compensation voltage with the capacitor-reduced array DAC controlled by the digital representation stored in the offset register. The digital representation controls scaling of reference voltages to the reduced capacitor array DAC associated with a least-significant-bit (LSB) of the differential SAR ADC.

Claim (Index 18):
An apparatus for offset correction in a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced capacitor array digital-to-analog converter (DAC), said apparatus comprising:\n a SAR ADC comprising:\n inputs for a positive voltage Vinp and a negative voltage Vinn, \n a positive reference voltage Vrefp and a negative reference voltage Vrefn, and \n a common mode voltage Vcm; \n a first plurality of binary weighted capacitors having top plates coupled together to form a node Vx; \n a second plurality of binary weighted capacitors having top plates coupled together to form a node Vy; \n a plurality of first switches adapted for selectably coupling the bottom plates of the first plurality of binary weighted capacitors to voltages Vrefp, Vrefn, Vcm, and Vinp; \n a plurality of second switches adapted for selectably coupling the bottom plates of the second plurality of binary weighted capacitors to the voltages Vrefp, Vrefn, Vcm, and Vinn; \n a reduced capacitor array DAC comprising:\n N positive offset correction capacitors having top plates coupled to the node Vx, \n N negative offset correction capacitors having top plates coupled to the node Vy, \n a plurality of third switches adapted for selectably coupling bottom plates of the N positive offset correction capacitors to Vcm and a plurality of scaled voltage references Vrefp/2 m  and Vrefn/2 m , where m is a positive integer; and \n a plurality of fourth switches adapted for selectably coupling bottom plates of the N negative offset correction capacitors to Vcm and the plurality of scaled voltage references Vrefn/2 m  and Vrefp/2 m , where m is a positive integer.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 97.0
- Lexical Diversity: 2.07042
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16166733', '14255269', '15206433', '14871475', '15017995']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.650243391715489
- 35 USC 102 Novelty (BERT): 0.5317323050426535
- Combined Prediction Score: 0.6383922830482054
- Mean Citation Score: 333.71620599999994
- Max Citation Score: 357.2428
- Similarity Product: 308.6666665249824

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test