PATENT CLAIM ANALYSIS

Application Number: 16154717
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["257", "040000"]

Abstract:
A display device includes a gate insulating layer disposed on a channel region of a semiconductor layer. A gate electrode is disposed on the gate insulating layer over the channel region of the semiconductor layer. A source electrode is disposed in direct contact with the source region of the semiconductor layer and a drain electrode is disposed in direct contact with a drain region of the semiconductor layer. A passivation layer is disposed on the gate electrode, the source electrode, and the drain electrode. The passivation layer is in direct contact with semiconductor layer in a region between the source electrode and the gate electrode, and is in direct contact with the semiconductor layer in a region between the gate electrode and the drain electrode. The first gate electrode, the first source electrode, and the first drain electrode comprise a same layer and a same material.

Claim (Index 14):
A manufacturing method for manufacturing a display device, the method comprising:\n forming a buffer layer on a substrate; forming a first semiconductor layer of a first thin film transistor on the buffer layer; forming a gate insulating layer on a channel region of the first semiconductor layer; forming a first gate electrode on the gate insulating layer over the channel region of the first semiconductor layer; concurrently with forming the first gate electrode, forming a first source electrode in direct contact with a source region of the first semiconductor layer, the first source electrode having a same material as the first gate electrode; concurrently with forming the first gate electrode and the first source electrode, forming a first drain electrode over a drain region of the first semiconductor layer, the first drain electrode having the same material as the first gate electrode and the first source electrode; and forming a passivation layer on the first gate electrode, the first source electrode, and the first drain electrode, in direct contact with first semiconductor layer in a region between the first source electrode and the first gate electrode, and in direct contact with the first semiconductor layer in a region between the first gate electrode and the first drain electrode.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 97.0
- Lexical Diversity: 4.61765
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14983240', '15684785', '15607979', '15298749', '16016306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9247000627076424
- 35 USC 102 Novelty (BERT): 0.5143111906993436
- Combined Prediction Score: 0.8836611755068124
- Mean Citation Score: 283.689256
- Max Citation Score: 301.39432
- Similarity Product: 207.88569502154823

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test