PATENT CLAIM ANALYSIS

Application Number: 16105368
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["365", "194000"]

Abstract:
A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

Claim (Index 6):
The method of  claim 5 , wherein performing the locking operation includes:\n aligning the divided clock signal and the feedback clock signal in same phases or in opposite phases.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 96.0
- Lexical Diversity: 2.21818
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12697547', '15226310', '15399195', '14219181', '15258672']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8083288449998022
- 35 USC 102 Novelty (BERT): 0.5091404820414239
- Combined Prediction Score: 0.7784100087039644
- Mean Citation Score: 288.38359
- Max Citation Score: 302.08463
- Similarity Product: 246.8145497915727

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test