PATENT CLAIM ANALYSIS

Application Number: 16011884
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-04
Patent Classification: ["257", "324000"]

Abstract:
A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pillar extending in a first direction and a first conductive pattern surrounding the channel pillar. The semiconductor device also has second conductive patterns surrounding the channel pillar above the first conductive pattern, wherein the second conductive patterns are stacked in the first direction and spaced apart from each other. The semiconductor device further has an etch stop pattern disposed above the first conductive pattern and below the second conductive patterns.

Claim (Index 19):
The semiconductor device of  claim 12  further comprising:\n dummy insulating layers and nitride layers, disposed in the same layer as the interlayer insulating layers and the gate electrodes, wherein the dummy insulating layers and the nitride layers are alternately stacked; and \n a resistor pattern within the stacked nitride layers, wherein the resistor pattern is disposed in the same layer as the etch stop pattern, and wherein the etch stop pattern and the resistor pattern comprise a poly-silicon layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 94.0
- Lexical Diversity: 2.16279
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16011975', '15934477', '15259380', '15280132', '15965139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.93136323711529
- 35 USC 102 Novelty (BERT): 0.5306061538138958
- Combined Prediction Score: 0.8912875287851506
- Mean Citation Score: 312.514078
- Max Citation Score: 365.6654
- Similarity Product: 256.8426028238177

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test