PATENT CLAIM ANALYSIS

Application Number: 16464880
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-10
Patent Classification: ["257", "774000"]

Abstract:
An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.

Claim (Index 8):
The integrated circuit packaging method according to  claim 7 , wherein a protective layer is provided on an inner wall of the connection through hole, and the protective layer is configured to protect the substrate when the additional through holes are formed.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 100.0
- Lexical Diversity: 2.91837
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16465229', '13438066', '15914852', '15109124', '15316985']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9194849170760928
- 35 USC 102 Novelty (BERT): 0.511812249954075
- Combined Prediction Score: 0.8787176503638912
- Mean Citation Score: 192.324256
- Max Citation Score: 271.07666
- Similarity Product: 186.02319947096944

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test