PATENT CLAIM ANALYSIS

Application Number: 16129663
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["712", "007000"]

Abstract:
A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.

Claim (Index 9):
The method of  claim 1 , wherein the temporary reduction element received by a designated first cell of the plurality of cells is a null value.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 3.0
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15477791', '15966275', '15496418', '13914731', '14175268']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5910470499798879
- 35 USC 102 Novelty (BERT): 0.5143589539302689
- Combined Prediction Score: 0.5833782403749259
- Mean Citation Score: 204.308168
- Max Citation Score: 316.50174
- Similarity Product: 245.7588617758261

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test