PATENT CLAIM ANALYSIS

Application Number: 15886717
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "392000"]

Abstract:
A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

Claim (Index 7):
The semiconductor device structure of  claim 6 , further comprising:\n a first source/drain extension region connected to the first source/drain region, in the substrate of the first MOS device; and a second source/drain extension region connected to the second source/drain region, in the substrate of the second MOS device.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 88.0
- Lexical Diversity: 2.53846
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11714569', '14922209', '15842899', '12494028', '15419144']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9153409185533472
- 35 USC 102 Novelty (BERT): 0.4891199927485427
- Combined Prediction Score: 0.8727188259728667
- Mean Citation Score: 208.00789
- Max Citation Score: 209.16226
- Similarity Product: 147.44034016873482

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test