PATENT CLAIM ANALYSIS

Application Number: 15904982
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

Claim (Index 7):
The semiconductor structure of  claim 6 , wherein the transistor gate comprises polysilicon.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 1.89286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14309096', '14490274', '14613610', '12607104', '14802110']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9297859624189933
- 35 USC 102 Novelty (BERT): 0.5263677198765829
- Combined Prediction Score: 0.8894441381647522
- Mean Citation Score: 231.565742
- Max Citation Score: 317.33588
- Similarity Product: 201.85169592889787

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test