PATENT CLAIM ANALYSIS

Application Number: 15908838
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "686000"]

Abstract:
A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability.

Claim (Index 22):
The semiconductor assembly of  claim 16 , wherein the first device is electrically connected to the first conductive pads by first conductive bumps or additional bonding wires, and the second device is electrically connected to the second conductive pads by second conductive bumps.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 90.0
- Lexical Diversity: 1.60714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15872828', '15166185', '15438937', '15353537', '15473629']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9204603430106711
- 35 USC 102 Novelty (BERT): 0.5186821349027184
- Combined Prediction Score: 0.880282522199876
- Mean Citation Score: 276.43282600000003
- Max Citation Score: 287.8713
- Similarity Product: 204.405964032662

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test