PATENT CLAIM ANALYSIS

Application Number: 16115114
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

Claim (Index 10):
The semiconductor device of  claim 9 , wherein the second spacer has a vertical cross-section having a horseshoe shape convex toward a central portion of the lower portion of the gate structure in the second direction.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 96.0
- Lexical Diversity: 2.88889
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15444550', '16040807', '15001568', '15296077', '14921006']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9111404783593507
- 35 USC 102 Novelty (BERT): 0.4876624077929957
- Combined Prediction Score: 0.8687926713027154
- Mean Citation Score: 212.342636
- Max Citation Score: 224.17645
- Similarity Product: 187.19830110694167

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test