PATENT CLAIM ANALYSIS

Application Number: 16416792
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["438", "275000"]

Abstract:
A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Claim (Index 16):
The method of  claim 15 , wherein a ratio of the second channel length to the first channel length is greater than about 2.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 100.0
- Lexical Diversity: 3.5641
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15598825', '13748419', '13741086', '15610981', '12898421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8528201871038875
- 35 USC 102 Novelty (BERT): 0.5082569339828596
- Combined Prediction Score: 0.8183638617917848
- Mean Citation Score: 230.089188
- Max Citation Score: 283.9682
- Similarity Product: 218.73204715845583

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test