PATENT CLAIM ANALYSIS

Application Number: 16035032
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["714", "033000"]

Abstract:
A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

Claim (Index 3):
The method of  claim 1 , wherein each of the plurality of ranks is specified in a binary format.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.09333
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15156136', '13172179', '15166612', '15454931', '14197336']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2580905307029402
- 35 USC 102 Novelty (BERT): 0.5638501163012369
- Combined Prediction Score: 0.2886664892627699
- Mean Citation Score: 208.978336
- Max Citation Score: 432.54004
- Similarity Product: 383.8025291295099

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test