PATENT CLAIM ANALYSIS

Application Number: 15938887
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["257", "341000"]

Abstract:
A split gate power transistor includes a laterally configured power PMOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.

Claim (Index 40):
The integrated circuit transistor of  claim 39  wherein a merged contact is electrically coupled to a surface of said a doped N+ type region, said doped P+ type bridge region, said first channel region, said doped P+ type bridge region, and said second channel region.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 90.0
- Lexical Diversity: 2.51724
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13312827', '13446987', '13460603', '13460717', '12234515']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9238513357861088
- 35 USC 102 Novelty (BERT): 0.600777336222781
- Combined Prediction Score: 0.8915439358297759
- Mean Citation Score: 251.376636
- Max Citation Score: 258.79886
- Similarity Product: 162.8900425152969

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test