PATENT CLAIM ANALYSIS

Application Number: 16237657
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["716", "108000"]

Abstract:
The present invention provides theoretical bases and practical schematic diagrams for a state machine which is coded in HDL and synthesized to generate a circuit that comprises one or more state groups each of which has an independent clock gating device. A state group will receive a clock pulse on the next cycle when either a synchronous initialization input signal for a state machine is asserted on the current cycle or the state group will change states on the next cycle, reducing power consumption and simplifying the final logic, compared with a traditionally generated state machine circuit. In addition the invention also provides a code designer with a proposed method for HDL standard on how to divide all states in a state machine into state groups at his discretion.

Claim (Index 4):
The method of  claim 1  further comprising:\n determining the state change for one state group of the plurality of state groups, the state change happening on the next cycle when one true jumping signal of the at least one true jumping signal for the one state group of the plurality of state groups is asserted on the current cycle.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.61446
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15861093', '12121827', '11608558', '10262769', '10428170']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3216733488887763
- 35 USC 102 Novelty (BERT): 0.4693521981246913
- Combined Prediction Score: 0.3364412338123678
- Mean Citation Score: 164.27026999999995
- Max Citation Score: 197.74767
- Similarity Product: 138.2415335360813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test