PATENT CLAIM ANALYSIS

Application Number: 15862926
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "004000"]

Abstract:
Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Claim (Index 1):
A method of manufacturing a semiconductor device, the method comprising:\n forming a first electrode line layer over a substrate, the first electrode line layer including a plurality of first electrode lines that extend in a first direction and are spaced apart from each other in a second direction different from the first direction, and a first insulation layer being disposed between adjacent first electrode lines; forming a first stacked structure over the first electrode line layer and the first insulation layer, the first stacked structure including a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer in an up or down direction; patterning the first stacked structure to form a first memory cell layer over the plurality of first electrode lines, the first memory cell layer including a plurality of first memory cells which are spaced apart from each other in the first direction and the second direction; forming a second insulation layer which fills gaps between adjacent first memory cells and covers tops of the plurality of first memory cells; forming a third insulation layer over the second insulation layer and patterning the third insulation layer to form a plurality of trenches which extend in the second direction, are spaced apart from each other in the first direction, and respectively expose the tops of the plurality of first memory cells; and filling the plurality of trenches with a conductive material to form a second electrode line layer including a plurality of second electrode lines which extend in the second direction and are spaced apart from each other in the first direction, wherein the plurality of first memory cells are respectively disposed in portions located where the plurality of first electrode lines intersect the plurality of second electrode lines.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 86.0
- Lexical Diversity: 1.59524
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15288233', '14736525', '15285922', '15179068', '15595307']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9033010324339102
- 35 USC 102 Novelty (BERT): 0.4918563874537486
- Combined Prediction Score: 0.8621565679358941
- Mean Citation Score: 217.348484
- Max Citation Score: 227.6333
- Similarity Product: 165.84862151839138

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test