PATENT CLAIM ANALYSIS

Application Number: 15903507
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["327", "211000"]

Abstract:
In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Claim (Index 11):
A sequential circuit, comprising:\n a first stage comprising: a first PMOS transistor having one end connected to a first node in response to a clock, a second PMOS transistor configured to connect the first node to a power supply terminal in response to a voltage of a second node, a third PMOS transistor configured to connect other end of the first PMOS transistor to the power supply terminal in response to a scan input, a fourth PMOS transistor configured to connect the one end of the first PMOS transistor to the power supply terminal in response to a scan enable signal, a first NMOS transistor configured to connect a first connection node to the first node in response to the clock, a second NMOS transistor having one end connected to the first node in response to the scan input, and a third NMOS transistor configured to connect a second connection node to other end of the second NMOS transistor in response to the scan enable signal; a second stage comprising: a first PMOS transistor configured to connect the second node to the power supply terminal in response to the clock, a second PMOS transistor configured to connect the second node to the power supply terminal in response to a logic signal, a first NMOS transistor connected to the second node in response to the logic signal, and a second NMOS transistor configured to connect a ground terminal to other end of the first NMOS transistor of the second stage in response to the clock; a combinational logic configured to receive data, the voltage of the first node, and a voltage of the second node and to generate the logic signal, wherein an output terminal of the combinational logic outputting the logic signal is connected to the first connection node; and a latch circuit configured to latch the voltage of the second node in response to the clock.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 88.0
- Lexical Diversity: 4.41935
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15254272', '15663852', '13440007', '14873634', '13049427']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7486703470069271
- 35 USC 102 Novelty (BERT): 0.5684566716094711
- Combined Prediction Score: 0.7306489794671815
- Mean Citation Score: 301.87892
- Max Citation Score: 444.85358
- Similarity Product: 417.3011193934179

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test