PATENT CLAIM ANALYSIS

Application Number: 15916585
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["365", "149000"]

Abstract:
Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET; a control circuit configured to supply a first electric potential on a second terminal of the capacitor, a second electric potential on the gate of the TFET and a third electric potential on a second electrode of the TFET, such that:          when the stored potential is low, the TFET is reverse biased with a conduction current obtained by band-to-band tunneling with a value higher than a capacitor leakage current; when the stored potential is high, the TFET is reverse biased with an OFF state current value less than the capacitor leakage current.

Claim (Index 15):
Flip-flop comprising at least:\n first and second memory latches according  claim 1 ; a first inverter having an input forming the input of the flip-flop and an output connected to the storage node of the first latch; a second inverter having an input connected to the storage node of the first latch and an output connected to the storage node of the second latch.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 2.38182
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15452783', '15454405', '14882611', '15694841', '13006109']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7660620110272413
- 35 USC 102 Novelty (BERT): 0.5125638074608947
- Combined Prediction Score: 0.7407121906706067
- Mean Citation Score: 240.292258
- Max Citation Score: 288.76407
- Similarity Product: 193.29182870167315

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test