PATENT CLAIM ANALYSIS

Application Number: 15963725
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "668000"]

Abstract:
The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.

Claim (Index 18):
The system of  claim 16 , wherein the dielectric material has a dielectric constant between 3.9 and 1000.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 91.0
- Lexical Diversity: 2.33824
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15621084', '15600224', '14447426', '15618210', '14289739']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9274862875833322
- 35 USC 102 Novelty (BERT): 0.5006855644040956
- Combined Prediction Score: 0.8848062152654085
- Mean Citation Score: 195.839792
- Max Citation Score: 216.15562000000003
- Similarity Product: 139.9774825866759

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test