PATENT CLAIM ANALYSIS

Application Number: 16023103
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["365", "185290"]

Abstract:
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Claim (Index 5):
The device according to  claim 4 , wherein\n the third voltage is higher than the first voltage.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 94.0
- Lexical Diversity: 2.38333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15422640', '14597787', '12332681', '13660044', '13162051']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8458693395083026
- 35 USC 102 Novelty (BERT): 0.5273842753499115
- Combined Prediction Score: 0.8140208330924634
- Mean Citation Score: 362.632374
- Max Citation Score: 364.65244
- Similarity Product: 204.79527633858208

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test