PATENT CLAIM ANALYSIS

Application Number: 15958871
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["326", "046000"]

Abstract:
An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Claim (Index 19):
The non-transitory computer readable storage medium of  claim 18 , including instructions that cause the processing circuitry to configure the hierarchical linked lists to include a rules list, wherein the actions list includes a rules list pointer and entries of the rules list identify one or more logic conditions associated with a state action of the actions lists.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 91.0
- Lexical Diversity: 1.94643
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15428406', '12497847', '11465789', '15661906', '12813265']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6493439870320452
- 35 USC 102 Novelty (BERT): 0.4627233916367267
- Combined Prediction Score: 0.6306819274925134
- Mean Citation Score: 113.0253622
- Max Citation Score: 137.09468
- Similarity Product: 99.91599993706228

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test