PATENT CLAIM ANALYSIS

Application Number: 15981167
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "369000"]

Abstract:
Present disclosure provides a hybrid semiconductor transistor structure, including a substrate, a first transistor on the substrate, a channel of the first transistor including a fin and having a first channel height, a second transistor adjacent to the first transistor, a channel of the second transistor including a nanowire, and a separation laterally spacing the fin from the nanowire. The first channel height is greater than the separation. Present disclosure also provides a method for manufacturing the hybrid semiconductor transistor structure.

Claim (Index 19):
The method of  claim 17 , further comprising:\n depositing a first dummy oxide layer over the channel region of the silicon germanium fin after obtaining the silicon germanium fin; removing the dummy gate over the silicon germanium fin to expose the first dummy oxide layer; annealing the silicon germanium fin so as to transform the first dummy oxide layer to a second dummy oxide layer; and removing the second dummy oxide layer.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 93.0
- Lexical Diversity: 2.43243
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15879888', '15926664', '15941798', '15868683', '15794286']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9136072112338957
- 35 USC 102 Novelty (BERT): 0.4897491575652093
- Combined Prediction Score: 0.871221405867027
- Mean Citation Score: 200.966716
- Max Citation Score: 211.93062
- Similarity Product: 149.92163310047866

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test