PATENT CLAIM ANALYSIS

Application Number: 15963766
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "390000"]

Abstract:
A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space. A conductive fill material is provided in the electrode space, and a dielectric layer electrically separates the conductive fill material into a first electrode electrically connected to the first contact of the first semiconductor device and a second electrode electrically connected to the second semiconductor device and electrically insulated from the first electrode. A first circuit terminal extends vertically from the top or bottom surface of the electrode structure and is electrically connected to the first electrode.

Claim (Index 1):
A method of forming a semiconductor device, the method comprising:\n providing a substrate defining an initial connection area, the substrate having at least three nanowires positioned within the initial connection area, the nanowires being uncovered, the nanowires having a longitudinal axis that extends in a horizontal direction, the nanowires being positioned in a vertical stack and spaced apart from each other, the nanowires including a first nanowire, a second nanowire, and a third nanowire, the second nanowire being positioned above the first nanowire, and the third nanowire being positioned above the second nanowire; forming a first electrode that covers the first nanowire and extends vertically to a top of the initial connection area, the first electrode having a step-shaped cross-section; forming a second electrode that covers the second nanowire and extends vertically a top of the initial connection area; and forming a third electrode that covers the third nanowire and extends vertically to a top of the initial connection area.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 3.22222
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15654327', '15671771', '13989509', '14754751', '15628821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9156361621229976
- 35 USC 102 Novelty (BERT): 0.5150349508128982
- Combined Prediction Score: 0.8755760409919876
- Mean Citation Score: 238.120606
- Max Citation Score: 322.00632
- Similarity Product: 269.250974681139

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test