PATENT CLAIM ANALYSIS

Application Number: 16059686
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["706", "025000"]

Abstract:
One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

Claim (Index 7):
The accelerator of  claim 1 , wherein the second memory bank comprises 3D SRAM.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 96.0
- Lexical Diversity: 2.0125
- Patent Class: 706.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15462180', '15335769', '15336216', '15455685', '15465774']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4102142354258355
- 35 USC 102 Novelty (BERT): 0.5516507626166712
- Combined Prediction Score: 0.4243578881449191
- Mean Citation Score: 335.491964
- Max Citation Score: 439.18576
- Similarity Product: 268.1962724106121

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test