PATENT CLAIM ANALYSIS

Application Number: 16100443
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["365", "222000"]

Abstract:
A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.

Claim (Index 3):
The system of  claim 1 , wherein the command address input circuit is configured to refresh the plurality of memory banks of the semiconductor device by outputting a first row address of the first set of memory banks to be refreshed or a second row address of the second set of memory banks to be refreshed to the address path.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 96.0
- Lexical Diversity: 2.81579
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15676424', '15692804', '15800267', '12482626', '12240331']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.853900199896836
- 35 USC 102 Novelty (BERT): 0.570102969725316
- Combined Prediction Score: 0.825520476879684
- Mean Citation Score: 379.732192
- Max Citation Score: 462.4485
- Similarity Product: 454.6792061221898

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test