PATENT CLAIM ANALYSIS

Application Number: 16019254
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["365", "189011"]

Abstract:
Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

Claim (Index 11):
The memory device of  claim 1 , wherein a first semiconductor die comprises the first impedance adjustment circuitry and a second semiconductor die comprises the second impedance adjustment circuitry.

Metadata:
- Claim Count in Document: 65.0
- Percentile: 94.0
- Lexical Diversity: 2.28814
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15722769', '15976716', '15853514', '15977125', '15976698']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7847090513279793
- 35 USC 102 Novelty (BERT): 0.4693915893816208
- Combined Prediction Score: 0.7531773051333435
- Mean Citation Score: 123.638765
- Max Citation Score: 126.69416
- Similarity Product: 84.7259099727249

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test