PATENT CLAIM ANALYSIS

Application Number: 16106269
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "798000"]

Abstract:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

Claim (Index 1):
A semiconductor on insulator structure comprising:\n a single crystal silicon handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of 100 Ohm-cm; a multilayer in interfacial contact with the front surface layer, the multilayer comprising one or more passivated semiconductor layers, wherein the one or more passivated semiconductor layers comprise a polycrystalline or an amorphous structure and comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; a semiconductor layer in interfacial contact with the multilayer, the semiconductor layer comprising a polycrystalline or an amorphous structure and comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; a dielectric layer in interfacial contact with the semiconductor layer; and a semiconductor device layer in interfacial contact with the dielectric layer.

Metadata:
- Claim Count in Document: 101.0
- Percentile: 96.0
- Lexical Diversity: 2.02174
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15675001', '14524693', '15984586', '15526798', '16077176']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9339478023224494
- 35 USC 102 Novelty (BERT): 0.6008035490702491
- Combined Prediction Score: 0.9006333769972295
- Mean Citation Score: 478.520996
- Max Citation Score: 506.38916
- Similarity Product: 494.1361609656073

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test