PATENT CLAIM ANALYSIS

Application Number: 15986628
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "296000"]

Abstract:
Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

Claim (Index 2):
The apparatus of  claim 1  wherein the memory cells include capacitors, and comprising wordlines gatedly coupling the capacitors with the bitlines; wherein the wordlines are recessed into a semiconductor material of a semiconductor substrate.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.78571
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15797462', '15664161', '15900403', '15664140', '15664143']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9140094720841044
- 35 USC 102 Novelty (BERT): 0.5274135731665028
- Combined Prediction Score: 0.8753498821923444
- Mean Citation Score: 298.757582
- Max Citation Score: 325.2625700000001
- Similarity Product: 222.8429569947756

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test