PATENT CLAIM ANALYSIS

Application Number: 16048392
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-03
Patent Classification: ["365", "185220"]

Abstract:
To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.

Claim (Index 10):
The semiconductor storage device according to  claim 1 ,\n wherein the verify control circuit is configured to supply a selection signal to each verify circuit in time division, and wherein each verify circuit transmits a result of the verify processing in the verify circuit to the verify control circuit at a timing when the selection signal is activated.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 95.0
- Lexical Diversity: 2.18
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11082992', '12320575', '11819015', '12211495', '11692501']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7724728506975219
- 35 USC 102 Novelty (BERT): 0.4802985371944411
- Combined Prediction Score: 0.7432554193472138
- Mean Citation Score: 174.102816
- Max Citation Score: 178.71489
- Similarity Product: 129.1968346835911

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test