PATENT CLAIM ANALYSIS

Application Number: 16044723
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "329000"]

Abstract:
Method and structures for forming vertical transistors with uniform fin thickness. A structure includes: a substrate, a plurality of fins over the substrate, a top and a bottom source/drain region in contact with the plurality of fins, respectively, where the bottom source/drain region has an alternating topography, and a bottom spacer in contact with the bottom source/drain region, where the bottom spacer conforms to the alternating topography of the bottom-source drain region.

Claim (Index 16):
The method of  claim 12  further comprising:\n removing each of the sidewall spacers of the plurality of tapered fins; and \n etching the plurality of fins to form a plurality of straightened fins, wherein the etching removes a portion of the sacrificial plug to form an opening in the sacrificial plug.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 1.97561
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14955738', '14951726', '14795524', '15986886', '14500304']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907424529487334
- 35 USC 102 Novelty (BERT): 0.5146963045204219
- Combined Prediction Score: 0.8681517069906427
- Mean Citation Score: 258.55822
- Max Citation Score: 264.0215
- Similarity Product: 172.99352898365262

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test