PATENT CLAIM ANALYSIS

Application Number: 15954353
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

Claim (Index 9):
The semiconductor device of  claim 7 , wherein the identifiable pattern includes rows of the interconnect pads.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 3.06122
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15231277', '15954326', '14971291', '13715424', '13234902']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9241227675988432
- 35 USC 102 Novelty (BERT): 0.4905292741660969
- Combined Prediction Score: 0.8807634182555687
- Mean Citation Score: 200.729056
- Max Citation Score: 252.46751
- Similarity Product: 212.76809582416536

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test