PATENT CLAIM ANALYSIS

Application Number: 16237143
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["438", "003000"]

Abstract:
A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

Claim (Index 2):
The magnetic memory array as in  claim 1 , wherein the semiconductor channel structure has a cylindrical configuration.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 98.0
- Lexical Diversity: 2.90196
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15857387', '15881035', '16007644', '16150874', '15933512']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8680991591128517
- 35 USC 102 Novelty (BERT): 0.5206318201028857
- Combined Prediction Score: 0.8333524252118552
- Mean Citation Score: 235.345278
- Max Citation Score: 302.4507
- Similarity Product: 200.96579823668003

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test