PATENT CLAIM ANALYSIS

Application Number: 16004404
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "497000"]

Abstract:
A  3 D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Claim (Index 13):
The 3D semiconductor device according to  claim 8 ,\n wherein at least one of said plurality of second transistors at least partially overlays at least one of said plurality of first transistors.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 94.0
- Lexical Diversity: 3.51111
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15917629', '15913917', '15904377', '13251269', '13869963']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927286158920254
- 35 USC 102 Novelty (BERT): 0.4979868033229241
- Combined Prediction Score: 0.884356223360521
- Mean Citation Score: 268.31646
- Max Citation Score: 290.28104
- Similarity Product: 272.1938417144776

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test