PATENT CLAIM ANALYSIS

Application Number: 15903629
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "185030"]

Abstract:
A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Claim (Index 2):
A nonvolatile semiconductor memory device, comprising:\n a cell unit including:\n a first selection gate transistor, \n a second selection gate transistor, and \n a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor; and \n a data write circuit configured to execute a writing operation to write data to the memory cells; wherein the memory cells include:\n a first memory cell connected with a first word line and capable of being programmable in D 1  stages to thereby store data of D 1  bits, D 1  being an integer of 2 or more, \n a second memory cell connected with a second word line and capable of being programmable in D 2  stages to thereby store data of D 2  bits, D 2  being an integer of 3 or more, the second memory cell being closer to the first selection gate transistor than the first memory cell, and \n a third memory cell connected with a third word line and capable of being programmable in D 3  stages to thereby store data of D 3  bits, D 3  being an integer of 3 or more, the third memory cell being closer to the first selection gate transistor than the second memory cell; and \n the data write circuit executes:\n a first program on the third memory cell as first one of the D 3  stages, \n a second program on the second memory cell as first one of the D 2  stages, after the first program, \n a third program on the third memory cell as second one of the D 3  stages, after the second program, \n a fourth program on the first memory cell as first one of the D 1  stages, after the third program, and \n a fifth program on the first memory cell as second one of the D 1  stages, after the fourth program.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 88.0
- Lexical Diversity: 2.33333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15462300', '15166895', '13711894', '14707908', '14075400']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8596798358016872
- 35 USC 102 Novelty (BERT): 0.5678553693815994
- Combined Prediction Score: 0.8304973891596784
- Mean Citation Score: 470.358446
- Max Citation Score: 473.174
- Similarity Product: 441.8282971397638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test