PATENT CLAIM ANALYSIS

Application Number: 15934883
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["370", "474000"]

Abstract:
An integrated circuit device may include a configurable packet parser that is programmable to simultaneously process multiple protocols to separate packet headers from payload data of network packets. The separated packet headers and payload data can be stored in respective memories. Replacement packet headers can be generated by a programmable header builder from the separated packet headers according to configurable commands, and new packets can be generated from the replacement packet headers and the payload data.

Claim (Index 7):
The integrated circuit device of  claim 1 , wherein the commands include both arithmetic and logic operations.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 90.0
- Lexical Diversity: 1.70213
- Patent Class: 370.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14594137', '15263089', '14980664', '14027257', '13770505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5660754866166177
- 35 USC 102 Novelty (BERT): 0.5049342385803073
- Combined Prediction Score: 0.5599613618129866
- Mean Citation Score: 205.497592
- Max Citation Score: 238.99863
- Similarity Product: 151.06229824763238

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test