PATENT CLAIM ANALYSIS

Application Number: 15950183
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "072000"]

Abstract:
A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Claim (Index 9):
A memory device, comprising:\n a plurality of word lines elongated along a first direction; at least one memory unit comprising:\n a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; \n at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; \n at least one column word line elongated along the second direction; and \n a plurality of switches arranged along the second direction, each of the switches comprising:\n a control terminal coupled to one of the at least one column word line; \n a first terminal coupled to one of the memory cell groups; and \n a second terminal coupled to one of the at least one bit line; \n wherein each of the switches is configured to control conduction between the coupled bit line and the coupled memory cell group thereto; and \n \n a control circuit, coupled to the plurality of column word lines, configured to generate a plurality of column word line signals; \n wherein a plurality of the memory units are arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the switches of corresponding memory blocks respectively; \n wherein when a first memory block among the plurality of memory blocks is selected over a plurality of consecutive cycles, the control circuit generates the first column word line signal retaining at a first voltage level during the plurality of consecutive cycles such that the plurality of switches within the first memory block remain conducted during the plurality of consecutive cycles.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 3.17778
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15497229', '13620184', '11509991', '10389753', '12382243']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8224322151990624
- 35 USC 102 Novelty (BERT): 0.4895504633441995
- Combined Prediction Score: 0.7891440400135761
- Mean Citation Score: 260.984684
- Max Citation Score: 291.00253
- Similarity Product: 270.1326946157289

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test