PATENT CLAIM ANALYSIS

Application Number: 16021949
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-04
Patent Classification: ["257", "076000"]

Abstract:
A method of forming a nanowire heterostructure, including, forming a dummy nanowire on a substrate, forming a sacrificial cover layer on the dummy nanowire, forming a spacer layer on a portion of the sacrificial cover layer, wherein a portion of the sacrificial cover layer extends above the top surface of the spacer layer, removing the portion of the sacrificial cover layer that extends above the top surface of the spacer layer, forming a gate structure on the spacer layer and a remaining portion of the sacrificial cover layer, forming an interlayer dielectric (ILD) layer on the gate structure, removing the dummy nanowire to form a nanowire trench, and forming a replacement nanowire in the nanowire trench

Claim (Index 7):
The method of  claim 6 , wherein the gate fill layer is made of a material selected from the group consisting of doped polycrystalline silicon (p-Si), doped amorphous silicon (a-Si), germanium (Ge), and silicon-germanium (SiGe).

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 3.2
- Patent Class: 257.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15793566', '15399064', '15173006', '15822724', '15417312']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9364152252297234
- 35 USC 102 Novelty (BERT): 0.5873235869304569
- Combined Prediction Score: 0.9015060613997968
- Mean Citation Score: 379.6021
- Max Citation Score: 526.41626
- Similarity Product: 403.05429843319536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test