PATENT CLAIM ANALYSIS

Application Number: 16050527
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "029000"]

Abstract:
A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

Claim (Index 6):
The method of  claim 5 , wherein the gate stack comprises one or more high-k dielectric materials.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 95.0
- Lexical Diversity: 2.6
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14988083', '15177483', '15396842', '15207802', '15628821']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9406239925719044
- 35 USC 102 Novelty (BERT): 0.534996339480143
- Combined Prediction Score: 0.9000612272627282
- Mean Citation Score: 356.537508
- Max Citation Score: 375.6915
- Similarity Product: 248.8636953485012

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test