PATENT CLAIM ANALYSIS

Application Number: 15948958
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["257", "666000"]

Abstract:
Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Claim (Index 35):
A semiconductor package, comprising:\n a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall; a plurality of conductive contacts at the second side of the die; a reinforcement layer having a first portion laterally adjacent to the first lateral sidewall of the die, and the reinforcement layer having a second portion laterally adjacent to the second lateral sidewall of the die, the reinforcement layer comprising glass fibers suspended in an epoxy matrix, and the reinforcement layer having a surface co-planar with the second side of the die; a dielectric material on the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts; a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts; a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via; a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump electrically coupled to the first conductive trace, the first solder bump outside of a periphery of the die; and a second solder bump electrically coupled to the second conductive trace, the second solder bump outside of the periphery of the die.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.13208
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14491892', '15899222', '14930514', '14586580', '12591812']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9177005439804404
- 35 USC 102 Novelty (BERT): 0.5068925483842787
- Combined Prediction Score: 0.8766197444208242
- Mean Citation Score: 212.89848
- Max Citation Score: 287.4933
- Similarity Product: 218.2105686718404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test