PATENT CLAIM ANALYSIS

Application Number: 16122762
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["257", "774000"]

Abstract:
An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.

Claim (Index 13):
A method of generating an integrated circuit layout, the method comprising:\n generating first and second cells; generating a first conductive via such that a first end of the first conductive via is in contact with the first cell; and generating a first conductive feature that is configured to receive a supply voltage, that is in contact with a second end of the first conductive via, and that extends from the first cell into the second cell.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 97.0
- Lexical Diversity: 2.35135
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15468281', '15171862', '11870330', '15865941', '15574813']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8892216009725266
- 35 USC 102 Novelty (BERT): 0.4670571725485284
- Combined Prediction Score: 0.8470051581301268
- Mean Citation Score: 138.823406
- Max Citation Score: 150.79898
- Similarity Product: 118.58388067655684

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test