PATENT CLAIM ANALYSIS

Application Number: 16143225
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["375", "230000"]

Abstract:
A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Claim (Index 1):
An apparatus comprising:\n a plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and wherein each driver slice circuit comprises:\n a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, \n for each resistive element, a voltage switching circuit connected to the second end of the resistive element, the voltage switching circuit configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit being controlled by the digital driver input; and, \n a common output node connected to (i) the plurality of driver slice outputs and (ii) a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.86364
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14315306', '15918851', '15402148', '14829388', '14952491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5197723831990606
- 35 USC 102 Novelty (BERT): 0.5970573401036414
- Combined Prediction Score: 0.5275008788895187
- Mean Citation Score: 403.421006
- Max Citation Score: 496.3756
- Similarity Product: 489.2491500113964

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test