PATENT CLAIM ANALYSIS

Application Number: 16037767
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["708", "835000"]

Abstract:
Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R on  or R off  to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Claim (Index 1):
A memory device comprising:\n a control bus; and multiple memory units connected by the control bus, each of the multiple memory units comprising a control circuit and a computation circuit, wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar array and a format conversion circuit, the first RRAM crossbar array having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds, and outputs of the comparator circuits are connected to the format conversion circuit; wherein the control circuit is connected to the control bus and configured to: receive a computation instruction; parse the computation instruction into an instruction to perform a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array in the computation circuit such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; setting the word lines of the first RRAM crossbar array according to elements of vector A; wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B; the format conversion circuit being set up to convert the outputs of the comparator circuits into an output corresponding to a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 1.72
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13965459', '14287701', '14308273', '14731933', '14025299']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3821726421514389
- 35 USC 102 Novelty (BERT): 0.4981417691738282
- Combined Prediction Score: 0.3937695548536778
- Mean Citation Score: 191.697904
- Max Citation Score: 210.35286
- Similarity Product: 154.05943810026884

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test