PATENT CLAIM ANALYSIS

Application Number: 16042436
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-05
Patent Classification: ["330", "009000"]

Abstract:
A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.

Claim (Index 5):
The circuit of  claim 4 , further comprising a seventh NMOS coupled between the seventh node and a ground voltage potential and an eighth NMOS coupled between the eighth node and the ground voltage potential.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 95.0
- Lexical Diversity: 1.96875
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15057273', '14221263', '15912477', '14970392', '14718204']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7593872873398412
- 35 USC 102 Novelty (BERT): 0.5229219822946931
- Combined Prediction Score: 0.7357407568353264
- Mean Citation Score: 257.151066
- Max Citation Score: 262.8033
- Similarity Product: 153.77374407881496

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test