PATENT CLAIM ANALYSIS

Application Number: 15862269
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "185220"]

Abstract:
A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

Claim (Index 7):
The method of  claim 4 , one of the first group of memory strings and one of the second group of memory strings, which are adjacent to each other, share a source-line.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.51163
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14997731', '15431442', '14617246', '15092108', '15250841']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8248924046054459
- 35 USC 102 Novelty (BERT): 0.5311998321699236
- Combined Prediction Score: 0.7955231473618937
- Mean Citation Score: 283.8590200000001
- Max Citation Score: 379.61005
- Similarity Product: 346.60856597329683

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test