PATENT CLAIM ANALYSIS

Application Number: 15741742
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["377", "064000"]

Abstract:
The present application discloses a shift, register circuit having a plurality of shift register units cascaded in series. The shift register circuit includes a first shift register unit and a second shift register unit. The first shift register unit includes a first pull-up node and a first output terminal and the second shift register unit includes a second pull-up node and a second output terminal. The shift register circuit includes a stabilizer circuit coupled to both the first shift register unit and the second shift register unit such that the first pull-up node is directly connected to the second pull-up node as a common pull-up node and configured to maintain a potential level of the common pull-up node stable during a stabilizing period when none of the first output terminal and the second output terminal output a turn-on signal.

Claim (Index 21):
A method for driving the shift register circuit of  claim 10 , the method comprising:\n providing a high voltage to the first common control signal and a low voltage to the second common control signal in a frame of image time with an odd serial number; providing the first clock signal with a clock period; providing the second clock signal with the same clock period and a time-delay of \u00bc of the clock period relative to the first clock signal; receiving the input signal with a pulse width of \u00bd of the clock period and a phase ahead of that of the first clock signal by \u00bd of the clock period; outputting the turn-on signal at the first output terminal with a pulse width of \u00bd of the clock period and a phase delayed by \u00bd of the clock period relative to the input signal; outputting the turn-on signal at the second output terminal with a pulse width of \u00bd of the clock period and a phase delayed by \u00bc of the clock signal relative to the turn-on signal at the first output terminal; receiving the reset signal with a pulse width of \u00bd of the clock period and a phase delayed by \u00bd of the clock period relative to the turn-on signal at the second output terminal; pulling up the first pull-down node to the high voltage of the first common control signal in a stabilizing period started as the reset signal is provided and lasted to an end of the frame of image time; maintaining the common pull-up node, the first output terminal, and the second output terminal at a fixed low voltage during the stabilizing period.

Metadata:
- Claim Count in Document: 51.0
- Percentile: 86.0
- Lexical Diversity: 2.88
- Patent Class: 377.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15752518', '15520557', '15529731', '15506398', '15327852']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7503672963411052
- 35 USC 102 Novelty (BERT): 0.5000186556495122
- Combined Prediction Score: 0.725332432271946
- Mean Citation Score: 333.4888660000001
- Max Citation Score: 342.74957
- Similarity Product: 240.1742817047096

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test