PATENT CLAIM ANALYSIS

Application Number: 16154522
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["375", "326000"]

Abstract:
Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

Claim (Index 19):
A method for correcting clock duty cycles, the method comprising:\n processing an input clock signal using a first pair of transistors, the input clock signal being characterized by a first duty cycle; providing an output clock signal using the first pair of transistors; generating a first correction signal by at least inverting a portion of the output clock signal; providing a control signal by a second pair of transistors; determining a rise time based on a control voltage; generating a second correction signal by a third pair of transistors using the control signal and the first correction signal, the second correction signal being associated with the rise time; and applying the second correction signal to the output clock signal, the output clock signal being characterized by a second duty cycle, the second duty cycle being closer to 50% than the first duty cycle.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 2.25926
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15389830', '15840984', '11819414', '13957004', '15206622']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4733226292196721
- 35 USC 102 Novelty (BERT): 0.5337192105534415
- Combined Prediction Score: 0.4793622873530491
- Mean Citation Score: 305.343444
- Max Citation Score: 359.87744
- Similarity Product: 335.4202892859268

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test