PATENT CLAIM ANALYSIS

Application Number: 16048960
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "737000"]

Abstract:
A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Claim (Index 19):
The method of  claim 16  further comprising:\n disposing a dielectric layer extending into the semiconductor substrate; and \n etching the dielectric layer to reveal a conductive feature in the interconnect structure of the wafer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.35135
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15229302', '14724694', '16028763', '14981204', '14599872']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9170095429339294
- 35 USC 102 Novelty (BERT): 0.4827405108433079
- Combined Prediction Score: 0.8735826397248673
- Mean Citation Score: 175.78573999999998
- Max Citation Score: 203.50955
- Similarity Product: 155.48914409291746

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test