PATENT CLAIM ANALYSIS

Application Number: 16285437
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-08
Patent Classification: ["361", "752000"]

Abstract:
Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

Claim (Index 20):
A fabrication method comprising:\n fabricating a tamper-respondent assembly, the fabricating comprising:\n providing a circuit board; \n providing an enclosure mounted to the circuit board along an enclosure-to-board interface, the enclosure facilitating enclosing at least one electronic component coupled to the circuit board within a secure volume; \n providing a tamper-respondent electronic circuit structure facilitating defining the secure volume, the tamper-respondent electronic circuit structure comprising one or more tamper-detect circuits comprising at least one conductive trace disposed, at least in part, within the enclosure-to-board interface, the at least one conductive trace comprising stress rise regions to facilitate detecting a tamper event at the enclosure-to-board interface; and \n securing the enclosure to the circuit board using an adhesive, the adhesive contacting, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface, including at the stress rise regions of the at least one conductive trace.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 99.0
- Lexical Diversity: 2.47692
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15901985', '15827275', '15193525', '15423833', '14974036']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8709441121243514
- 35 USC 102 Novelty (BERT): 0.6139250447006294
- Combined Prediction Score: 0.8452422053819793
- Mean Citation Score: 437.888306
- Max Citation Score: 554.35767
- Similarity Product: 544.0262043915475

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test