PATENT CLAIM ANALYSIS

Application Number: 15969359
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-06
Patent Classification: ["257", "668000"]

Abstract:
A fan-out semiconductor package includes first and second structures. The first structure includes a first semiconductor chip, a first encapsulant, and a connection member. The second structure includes a second semiconductor chip, a second encapsulant, and conductive bumps. The first and second structures are disposed so that active surfaces of the first and second semiconductor chips face each other. The conductive bumps are electrically connected to a redistribution layer, and connection pads of the first and second semiconductor chips are connected to each other through the redistribution layer in a signal manner. Signal transmission times between one point of the redistribution layer and connection pads of each of the first and second semiconductor chips are substantially the same as each other.

Claim (Index 1):
A fan-out semiconductor package comprising:\n a first structure including a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface, a first encapsulant encapsulating at least portions of the first semiconductor chip, a connection member disposed on the first encapsulant, and the first active surface and including a redistribution layer that includes first conductors extending in a direction parallel with the first active surface to be electrically connected to the first connection pads, and a first wiring member disposed between the first active surface and the connection member and including a first wiring layer that includes second conductors extending in the direction parallel with the first active surface to redistribute the first connection pads to electrically connect the first connection pads to the redistribution layer; and a second structure including a second semiconductor chip having a second active surface having second connection pads disposed thereon and a second inactive surface opposing the second active surface, a second encapsulant encapsulating at least portions of the second semiconductor chip, and conductive bumps disposed on the second active surface and electrically connected to the second connection pads, wherein the first and second structures are disposed so that the first and second active surfaces face each other, the conductive bumps are electrically connected to the redistribution layer, and the first and second connection pads are electrically connected to each other through the redistribution layer in a signal manner.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 2.58824
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15946109', '15928845', '15962577', '15278248', '15297831']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.925774140279252
- 35 USC 102 Novelty (BERT): 0.5484721149704539
- Combined Prediction Score: 0.8880439377483723
- Mean Citation Score: 388.698354
- Max Citation Score: 399.72922
- Similarity Product: 331.82451751396303

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test