PATENT CLAIM ANALYSIS

Application Number: 15913533
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-08
Patent Classification: ["257", "506000"]

Abstract:
A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Claim (Index 11):
The semiconductor device according to  claim 1 , wherein\n a material of the channel layer comprises polycrystalline silicon, amorphous silicon, GaN, indium gallium zinc oxide, or ZnO.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 90.0
- Lexical Diversity: 3.67442
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15264885', '15648889', '14887814', '11095969', '14495639']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9119325885775916
- 35 USC 102 Novelty (BERT): 0.4995150823388071
- Combined Prediction Score: 0.8706908379537132
- Mean Citation Score: 221.13792200000003
- Max Citation Score: 223.13496
- Similarity Product: 162.36694366091248

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test