PATENT CLAIM ANALYSIS

Application Number: 16108761
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["714", "726000"]

Abstract:
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Claim (Index 4):
The test architecture of  claim 1  in which the serial to parallel register includes a header section and the header section includes the command output.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 96.0
- Lexical Diversity: 2.64444
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15233280', '13217851', '13595297', '13870319', '15622840']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3755087180573355
- 35 USC 102 Novelty (BERT): 0.5547963089679471
- Combined Prediction Score: 0.3934374771483966
- Mean Citation Score: 429.42660400000005
- Max Citation Score: 436.74344
- Similarity Product: 328.60757820306304

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test