PATENT CLAIM ANALYSIS

Application Number: 16186840
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "185120"]

Abstract:
A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Claim (Index 14):
The method of  claim 13 , wherein the precharging comprises:\n outputting a bit line voltage control signal (BLSHF) having a level of the precharge voltage to the first node; and connecting the first decoupling capacitor charged to the supply voltage to the first node.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 1.875
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15495072', '15717992', '14283209', '15274071', '15341253']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8201970549798002
- 35 USC 102 Novelty (BERT): 0.5735742682595362
- Combined Prediction Score: 0.7955347763077738
- Mean Citation Score: 301.631836
- Max Citation Score: 538.4229
- Similarity Product: 380.2060125262141

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test