PATENT CLAIM ANALYSIS

Application Number: 15916538
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185110"]

Abstract:
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

Claim (Index 8):
A memory system comprising:\n a semiconductor memory capable of storing data; and a controller capable of reading data from the semiconductor memory, and wherein the semiconductor memory includes: a first block including a plurality of first memory cells three-dimensionally stacked above a semiconductor substrate, a second block including a plurality of second memory cells three-dimensionally stacked above the semiconductor substrate, a plurality of first word lines coupled to the first memory cells, a plurality of second word lines coupled to the second memory cells, a first row decoder capable of transferring voltages to the first word lines, and a second row decoder capable of transferring voltages to the second word lines, wherein when the controller issues a data read command for data held in the first block to the semiconductor memory, the semiconductor memory outputs a busy signal notifying the controller that the semiconductor memory is in a busy state, in the busy state, the first row decoder transfers a first voltage to a selected first word line, and transfers a second voltage larger than the first voltage to unselected other first word lines, after data is read from the first block and the semiconductor memory outputs a ready signal notifying the controller that the semiconductor memory is in a ready state, the first row decoder transfers a third voltage smaller than the first voltage to the first word lines during the first period, and when the controller issues another access command for the second block to the semiconductor memory during the first period, the first row decoder stops transferring a voltage to the first word lines, and the second row decoder initiates transferring voltages to the second word lines.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.82692
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14843878', '15455419', '14847086', '15286751', '15916472']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7602024360690154
- 35 USC 102 Novelty (BERT): 0.4672595207600588
- Combined Prediction Score: 0.7309081445381198
- Mean Citation Score: 194.88964400000003
- Max Citation Score: 205.99907
- Similarity Product: 178.3072921409428

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test