PATENT CLAIM ANALYSIS

Application Number: 16040963
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-07
Patent Classification: ["327", "107000"]

Abstract:
A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

Claim (Index 19):
The electronic circuit of  claim 18 , wherein the flip-flop is further configured to output an output value representing a difference between the sampled voltage and the delayed reference voltage.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 1.65957
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16019070', '15869854', '15605261', '12753471', '13874229']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7806628518607553
- 35 USC 102 Novelty (BERT): 0.513615081013995
- Combined Prediction Score: 0.7539580747760793
- Mean Citation Score: 210.52297400000003
- Max Citation Score: 308.15906
- Similarity Product: 222.93359588267208

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test