PATENT CLAIM ANALYSIS

Application Number: 15897706
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["438", "268000"]

Abstract:
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

Claim (Index 14):
A method of forming a spacer for a vertical transistor, the method comprising:\n forming multiple fins on a semiconductor substrate; depositing a first spacer and an oxide on each of the multiple fins and on exposed surfaces of the semiconductor substrate between and around the multiple fins such that uppermost portions of the first spacer are exposed through openings in the oxide; etching portions of the first spacer to re-expose surfaces of the substrate adjacent to each of the multiple fins via the openings to define gaps between remainders of the first spacer and corresponding ones of each of the multiple fins; and depositing a second spacer on the re-exposed surfaces of the semiconductor substrate in at least the gaps.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 1.90909
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15235829', '15240056', '15276349', '15188476', '15422724']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8569261749223122
- 35 USC 102 Novelty (BERT): 0.5482571125300585
- Combined Prediction Score: 0.8260592686830868
- Mean Citation Score: 260.09920800000003
- Max Citation Score: 401.85196
- Similarity Product: 387.1278214111638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test