PATENT CLAIM ANALYSIS

Application Number: 15956926
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "288000"]

Abstract:
The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

Claim (Index 8):
The method of  claim 1 , further comprising forming a spacer layer and etching said spacer layer so as to form additional sidewall spacers that substantially cover sidewalls of said first and second electrode structures.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 91.0
- Lexical Diversity: 1.36364
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11559462', '14722818', '12905655', '11466802', '13198107']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9159661959226216
- 35 USC 102 Novelty (BERT): 0.4739640734820124
- Combined Prediction Score: 0.8717659836785606
- Mean Citation Score: 209.26946
- Max Citation Score: 221.54156
- Similarity Product: 191.5711507663393

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test