PATENT CLAIM ANALYSIS

Application Number: 15871643
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["327", "109000"]

Abstract:
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Claim (Index 18):
A method of digitally tuning a capacitor in an integrated circuit, the method comprising the steps of:\n providing a first node; providing a second node; providing a series arrangement of two or more capacitors and a plurality of FET switches; the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor; providing a non-negative second supply voltage independent of a number of FET switches of the plurality of FET switches providing a resistive network, the resistive network comprising:\n a plurality of resistors coupled across drain and source terminals of corresponding FET switches, and \n a series resistor, connecting a resistor of the plurality of resistors to the second supply voltage; \n providing a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches connecting each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor; coupling the series arrangement of two or more capacitors and the plurality of FET switches between the first node and the second node; coupling a first capacitor of the two or more capacitors to the first node and coupling a second capacitor of the two or more capacitors to the second node; and enabling or disabling the FET switches using the first supply voltage and the second supply voltage and thereby adjusting a capacitance between the first node and the second node.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 1.35211
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15256453', '15279302', '12735954', '15376471', '14638917']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7012622041964415
- 35 USC 102 Novelty (BERT): 0.5321826731921785
- Combined Prediction Score: 0.6843542510960152
- Mean Citation Score: 253.206168
- Max Citation Score: 376.70914
- Similarity Product: 362.26499925267217

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test