PATENT CLAIM ANALYSIS

Application Number: 16066355
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["711", "133000"]

Abstract:
Data memory node ( 400 ) for ESM (Emulated Share Memory) architectures ( 100, 200 ), comprising a data memory module ( 402 ) containing data memory for storing input data therein and retrieving stored data therefrom responsive to predetermined control signals, a multi-port cache ( 404 ) for the data memory, said cache being provided with at least one read port ( 404 A,  404 B) and at least one write port ( 404 C,  404 D,  404 E), said cache ( 404 ) being configured to hold recently and/or frequently used data stored in the data memory ( 402 ), and an active memory unit ( 406 ) at least functionally connected to a plurality of processors via an interconnection network ( 108 ), said active memory unit ( 406 ) being configured to operate the cache ( 404 ) upon receiving a multioperation reference ( 410 ) incorporating a memory reference to the data memory of the data memory module from a number of processors of said plurality, wherein responsive to the receipt of the multioperation reference the active memory unit ( 406 ) is configured to process the multioperation reference according to the type of the multioperation indicated in the reference, utilizing cached data in accordance with the memory reference and data provided in the multioperation reference. A method to be performed by the memory node is also presented.

Claim (Index 1):
A data memory node for use in ESM (Emulated Shared Memory) architectures, comprising\n a data memory module containing data memory for storing input data therein and retrieving stored data therefrom responsive to predetermined control signals, a multi-port cache for the data memory, said cache being provided with at least one read port and at least one write port, said cache being configured to hold recently and/or frequently used data stored in the data memory, and an active memory unit at least functionally connected to a plurality of processors via an interconnection network, said active memory unit being configured to operate the cache upon receiving a multioperation reference incorporating a memory reference to the data memory of the data memory module from a number of processors of said plurality, wherein responsive to the receipt of the multioperation reference the active memory unit is configured to process the multioperation reference according to the type of the multioperation indicated in the reference, utilizing cached data in accordance with the memory reference and data provided in the multioperation reference.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 94.0
- Lexical Diversity: 2.56122
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14892446', '15105583', '10263836', '10263743', '10263741']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4987751659567102
- 35 USC 102 Novelty (BERT): 0.4989731727684585
- Combined Prediction Score: 0.498794966637885
- Mean Citation Score: 182.715498
- Max Citation Score: 280.02106000000003
- Similarity Product: 228.63634654156925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test