PATENT CLAIM ANALYSIS

Application Number: 15869261
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "343000"]

Abstract:
An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Claim (Index 11):
The integrated circuit device of  claim 10 , further comprising a second doped region having the second conductivity type, the second doped region having a higher concentration of P-type dopants that the first doped region, the source region being interposed between the first doped region and the second doped region.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.38889
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15269552', '13351295', '15850854', '14808991', '15646968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9161468577215336
- 35 USC 102 Novelty (BERT): 0.498329098768945
- Combined Prediction Score: 0.8743650818262748
- Mean Citation Score: 225.129614
- Max Citation Score: 264.05927
- Similarity Product: 204.5879291534656

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test