PATENT CLAIM ANALYSIS

Application Number: 16256296
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-07
Patent Classification: ["375", "286000"]

Abstract:
Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

Claim (Index 6):
The apparatus of  claim 2 , further comprising:\n a metal layer coupled with the second portion of the access line and the memory die, the second portion of the access line coupled with the memory die via the metal layer.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 99.0
- Lexical Diversity: 1.88462
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15872456', '16020834', '15892118', '15977815', '15662002']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4588425825223011
- 35 USC 102 Novelty (BERT): 0.4948975015707923
- Combined Prediction Score: 0.4624480744271502
- Mean Citation Score: 167.32568
- Max Citation Score: 235.63994
- Similarity Product: 173.0938403128648

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test