PATENT CLAIM ANALYSIS

Application Number: 15938819
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["327", "153000"]

Abstract:
Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

Claim (Index 9):
The apparatus of  claim 7 , wherein the stacked semiconductor device further comprises a third die stacked on the second die, wherein the first path is further configured to provide read data from the third die, wherein the first path further includes a third align circuit on the third die, wherein the second path further includes a third replica align circuit on the third die, wherein, during the read data align operation, the first control circuit of the first die is configured to adjust the first delay provided by the first align circuit and the first replica align circuit based on a propagation delay of the clock signal through the third replica align circuit, and after the first align circuit and the first replica align circuit are set to provide the first delay value, a third control circuit of the third die is configured to set the third align circuit and the third replica align circuit to provide a third delay based on the propagation delay of the clock signal through the third replica align circuit compared with the propagation delay of the clock signal through the first replica align circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15176442', '13566882', '15138042', '15449688', '13291733']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.768901727336472
- 35 USC 102 Novelty (BERT): 0.4640683732268767
- Combined Prediction Score: 0.7384183919255125
- Mean Citation Score: 140.914518
- Max Citation Score: 154.5303
- Similarity Product: 117.05617613346575

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test