PATENT CLAIM ANALYSIS

Application Number: 16006140
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "327000"]

Abstract:
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure on a base substrate and forming a first dielectric layer on the base substrate. The first dielectric layer has a top lower than the gate structure and exposes a sidewall portion of the gate structure. The method also includes forming an isolation sidewall spacer on the exposed sidewall portion of the gate structure.

Claim (Index 9):
The method according to  claim 1 , wherein:\n a source and drain doped region is formed in the base substrate on both sides of the gate structure, wherein after forming the isolation sidewall spacer, further including:\n forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a material density higher than the first dielectric layer, \n forming a contact hole to penetrate through the first dielectric layer and the second dielectric layer, wherein a bottom of the contact hole exposes the source and drain doped region, and \n forming a plug in the contact hole.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.2
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15785071', '15473726', '15392215', '15187070', '15829453']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9236394461225718
- 35 USC 102 Novelty (BERT): 0.4811551922718766
- Combined Prediction Score: 0.8793910207375023
- Mean Citation Score: 203.013522
- Max Citation Score: 203.77246
- Similarity Product: 157.56864248919368

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test