PATENT CLAIM ANALYSIS

Application Number: 16075120
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-02
Patent Classification: ["257", "707000"]

Abstract:
In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

Claim (Index 17):
A three-dimensional (3D) semiconductor package to implement a thermal solution for 3D packaging, the 3D semiconductor package comprising:\n a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die partially covering a first portion of the first silicon functional die and wherein a second portion of the first silicon functional die remains uncovered by the second layer functional silicon die; a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to electrically join the second layer functional silicon die to the first layer functional silicon die; a thermal pad integrated upon a top surface of the first functional silicon die within the second portion of the first silicon functional die which remains uncovered by the second layer functional silicon die; encapsulation material fully encasing the first layer functional silicon die, the second layer functional silicon die, and the conductivity layer; a drill hole from which the a portion of the encapsulation material is evacuated from a surface of the 3D semiconductor package down to the thermal pad integrated upon the top surface of the first functional silicon die; and solder material partially filling the drill hole to bond a copper slug to the thermal pad within the drill hole.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 96.0
- Lexical Diversity: 2.92308
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16075513', '15283055', '15475879', '14588715', '15475902']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9156514503997428
- 35 USC 102 Novelty (BERT): 0.5033873392276398
- Combined Prediction Score: 0.8744250392825325
- Mean Citation Score: 221.117068
- Max Citation Score: 258.28192
- Similarity Product: 179.70079995752334

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test