PATENT CLAIM ANALYSIS

Application Number: 16059136
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "158000"]

Abstract:
Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

Claim (Index 34):
The method of  claim 28 , wherein determining the number of cycles of the clock signal in the delay further comprises:\n starting a counter when the omitted cycle of the plurality of cycles is provided to the first end of the delay locked loop; and determining the number of cycles of the clock signal in the delay based on the counter when the omitted cycle is detected at the location within the delay locked loop.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.04839
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15583539', '12659057', '11588954', '11250600', '12615833']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7875485429167915
- 35 USC 102 Novelty (BERT): 0.5150024421535715
- Combined Prediction Score: 0.7602939328404695
- Mean Citation Score: 220.804588
- Max Citation Score: 312.15414
- Similarity Product: 245.7216654079986

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test