PATENT CLAIM ANALYSIS

Application Number: 16236062
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["326", "038000"]

Abstract:
Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

Claim (Index 3):
The programmable logic device of  claim 1 , wherein the third die comprises programmable logic layer that comprises programmable logic.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 98.0
- Lexical Diversity: 1.29167
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16235956', '16146849', '11794335', '15392225', '12057326']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6684931735880533
- 35 USC 102 Novelty (BERT): 0.4624188932317131
- Combined Prediction Score: 0.6478857455524193
- Mean Citation Score: 148.893374
- Max Citation Score: 167.6283
- Similarity Product: 131.33538687962294

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test