PATENT CLAIM ANALYSIS

Application Number: 16011356
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["714", "724000"]

Abstract:
Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.

Claim (Index 4):
The apparatus of  claim 2 , wherein the second multiplexer is to provide a regular clock on the regular clock node to the clock input during a normal mode or a non-test mode.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.70968
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15072280', '15462732', '15663852', '15254272', '15903507']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2863421332393817
- 35 USC 102 Novelty (BERT): 0.480655460808179
- Combined Prediction Score: 0.3057734659962614
- Mean Citation Score: 128.1874268
- Max Citation Score: 193.94409
- Similarity Product: 140.7280635917598

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test