PATENT CLAIM ANALYSIS

Application Number: 15882461
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["361", "056000"]

Abstract:
An overvoltage protection circuit for a transistor device is presented. The overvoltage protection circuit comprises a first pin coupled to a gate terminal of the transistor device, an electrostatic discharge protection circuit coupled between a second pin and a source terminal of the transistor device, a first diode coupled between the first pin and the second pin, and a second diode coupled in parallel to the first diode between the first pin and the second pin. The forward direction of the first diode is opposite to the forward direction of the second diode. In addition, A method of measuring a gate leakage current of a transistor device and a method of bonding a transistor device coupled to such an overvoltage protection circuit are presented.

Claim (Index 1):
An overvoltage protection circuit for a transistor device, the overvoltage protection circuit comprising:\n a first pin coupled to a gate terminal of the transistor device; an electrostatic discharge protection circuit coupled between a second pin and a source terminal of the transistor device; a first diode coupled between the first pin and the second pin; and a second diode coupled in parallel to the first diode between the first pin and the second pin, wherein the forward direction of the first diode is opposite to the forward direction of the second diode, wherein the electrostatic discharge protection circuit comprises: a first circuit branch including one or more diodes and a first resistance coupled in series between the second pin and a first intermediate node of the electrostatic discharge protection circuit, wherein the forward directions of the one or more diodes of the first circuit branch are aligned with each other; a second circuit branch including one or more diodes and a second resistance coupled in series between the source terminal of the transistor device and the first intermediate node, wherein the forward directions of the one or more diodes of the second circuit branch are aligned with each other and opposite to the forward directions of the one or more diodes of the first circuit branch; a second transistor device coupled in parallel to the first circuit branch between the second pin and the first intermediate node, wherein a gate terminal of the second transistor device is coupled to a second intermediate node between the one or more diodes of the first circuit branch and the first resistance of the first circuit branch; and a third transistor device coupled in parallel to the second circuit branch between the source terminal of the transistor device and the first intermediate node, wherein a gate terminal of the third transistor device is coupled to a third intermediate node between the one or more diodes of the second circuit branch and the second resistance of the second circuit branch.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.93333
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11775897', '14658779', '14827165', '10445617', '15420979']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8533456599787591
- 35 USC 102 Novelty (BERT): 0.4855195764572584
- Combined Prediction Score: 0.816563051626609
- Mean Citation Score: 255.58
- Max Citation Score: 262.4193
- Similarity Product: 223.2647235437393

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test