PATENT CLAIM ANALYSIS

Application Number: 15894019
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["711", "119000"]

Abstract:
A cache memory control device for controlling a first cache memory of a multi-cache memory system that includes logic circuitry operable for storing state information assigned to an invalid copy of a cache line stored in the first cache memory, where the state information includes a cache memory identifier identifying an individual second cache memory of the multi-cache memory system that is likely to contain a valid copy of the cache line.

Claim (Index 8):
The device of  claim 7 , wherein the third chip comprises the cache coherence directory, copies the speculative request, when forwarding the respective request to the second cache memory, and provides the resulting copy of the forwarded request to the cache coherence directory.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 1.85
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12402025', '12105464', '09749660', '12107350', '11184315']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5526493060953094
- 35 USC 102 Novelty (BERT): 0.488871665232615
- Combined Prediction Score: 0.5462715420090399
- Mean Citation Score: 205.48853
- Max Citation Score: 210.05435
- Similarity Product: 148.0293555523038

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test