PATENT CLAIM ANALYSIS

Application Number: 15997706
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "296000"]

Abstract:
A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas.

Claim (Index 10):
A method of manufacturing a DRAM, comprising:\n forming a plurality of isolation structures in a substrate to divide the substrate into a plurality of active areas, wherein the active areas are configured in a shape of band and arranged in an array; forming a plurality of word line sets in the substrate, wherein the word line sets extend in a Y direction and pass through the isolation structures and the active areas to divide the substrate into a plurality of a plurality of first areas and a plurality of second areas, the first areas and the second areas are alternately arranged in an X direction, and the word line sets are located in the first areas; forming a plurality of bit-line structures on the substrate, wherein the bit-line structures extend in the X direction and cross the word line sets; forming a plurality of spacers respectively on sidewalls of the bit-line structures; forming a plurality of conductive layers on the substrate in the second areas; forming a plurality of first dielectric layers on the substrate in the first areas, wherein top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers; forming a plurality of second dielectric layers respectively in the conductive layers, wherein each of the second dielectric layers divides the corresponding conductive layer into two conductive posts and a material of the first dielectric layers is the same as a material of the second dielectric layers; and forming a plurality of capacitors respectively on the conductive posts.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 94.0
- Lexical Diversity: 2.54098
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15590023', '12191315', '15680217', '10447065', '12892684']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9151666614292896
- 35 USC 102 Novelty (BERT): 0.5107292918165753
- Combined Prediction Score: 0.8747229244680182
- Mean Citation Score: 225.040582
- Max Citation Score: 276.7055
- Similarity Product: 183.7038132752478

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test