PATENT CLAIM ANALYSIS

Application Number: 15901054
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["714", "718000"]

Abstract:
An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.

Claim (Index 4):
The system of  claim 3  wherein the second logical address range forms an NVMe namespace that is configured as a debug namespace.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 88.0
- Lexical Diversity: 2.17778
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14843884', '15873395', '15609758', '15242299', '14191335']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2730205432319754
- 35 USC 102 Novelty (BERT): 0.4826012668182123
- Combined Prediction Score: 0.293978615590599
- Mean Citation Score: 177.75363199999995
- Max Citation Score: 183.3289
- Similarity Product: 134.21729681359528

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test