PATENT CLAIM ANALYSIS

Application Number: 15880455
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "737000"]

Abstract:
An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

Claim (Index 7):
The IC package of  claim 1 , wherein at least one output pad on the first die is coupled to a buffer included in the first die that is used to drive a signal coupled to at least one corresponding input pad on the second die, and wherein the at least one corresponding input pad on the second die is coupled to protection circuitry in the second die.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 2.15686
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14040223', '09961767', '12512313', '14435677', '15346512']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9179022831813486
- 35 USC 102 Novelty (BERT): 0.4774463271456762
- Combined Prediction Score: 0.8738566875777813
- Mean Citation Score: 163.316214
- Max Citation Score: 168.52696
- Similarity Product: 122.53380546331404

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test