PATENT CLAIM ANALYSIS

Application Number: 16022704
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Claim (Index 10):
A semiconductor package, comprising:\n at least one die; a first redistribution layer, disposed over the at least one die and electrically connected with the at least one die, wherein the first redistribution layer includes a first dual damascene redistribution pattern and a first seed metallic pattern, the first dual damascene redistribution pattern includes a first via portion and a first routing portion located directly on the first via portion, and the first seed metallic pattern covers sidewalls of the first routing portion and covers sidewalls and a bottom surface of the first via portion; a second redistribution layer, disposed on the first redistribution layer and over the at least one die and electrically connected with the first redistribution layer and the at least one die, wherein the second redistribution layer includes a second dual damascene redistribution pattern and a second seed metallic pattern, the second dual damascene redistribution pattern includes a second via portion and a second routing portion located directly on the second via portion, and the second seed metallic pattern covers sidewalls of the second routing portion and covers sidewalls and a bottom surface of the second via portion; and a third redistribution layer, disposed on the second redistribution layer and over the at least one die and electrically connected with the first and second redistribution layers and the at least one die, wherein the third redistribution layer includes a third dual damascene redistribution pattern and a third seed metallic pattern, the third dual damascene redistribution pattern includes a third via portion and a third routing portion, and the third seed metallic pattern covers a bottom surface of the third routing portion and covers sidewalls and a bottom surface of the third via portion, wherein the first via portion, the second via portion and the third via portion are vertically stacked over one another and vertically aligned with one another.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 3.02778
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15688817', '15693950', '15157220', '14447426', '15859123']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9134211770657236
- 35 USC 102 Novelty (BERT): 0.4996576578128123
- Combined Prediction Score: 0.8720448251404326
- Mean Citation Score: 217.664304
- Max Citation Score: 267.35162
- Similarity Product: 212.4976763553929

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test