PATENT CLAIM ANALYSIS

Application Number: 15917883
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["375", "355000"]

Abstract:
Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.

Claim (Index 3):
The I/O interface of  claim 2 , wherein the clock edge tracking module is configured to be powered down when the multiplexer selects the master data sample clock control signals.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.30303
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14594472', '09951939', '14801310', '14853912', '15422263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5138026862933909
- 35 USC 102 Novelty (BERT): 0.5050929920818014
- Combined Prediction Score: 0.5129317168722319
- Mean Citation Score: 218.468078
- Max Citation Score: 258.25092
- Similarity Product: 179.72111579778672

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test