PATENT CLAIM ANALYSIS

Application Number: 15974136
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "506000"]

Abstract:
The present disclosure generally relates to the field of semiconductor technologies, and particularly discloses a resistance device and a manufacturing method thereof. In one implementation, a resistance device is disclosed. The resistance device includes a substrate, a fin on the substrate, a trench isolation structure formed around the fin. The resistance device further includes at least one first dummy gate structure on the fins, an inter-layer dielectric layer on the trench isolation structure, where the inter-layer dielectric layer covers the fin and the at least one first dummy gate structure. The resistance device further includes a resistance material layer on the inter-layer dielectric layer. The resistance device of the present disclosure provides relatively desirable uniformity and performance.

Claim (Index 22):
The method according to  claim 12 , further comprising:\n forming an insulator covering layer that covers the resistance material layer; and forming a first contact element and a second contact element that pass through the insulator covering layer and are in contact with two ends of the resistance material layer.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 2.34545
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15612805', '15925390', '15918719', '15963049', '15823029']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920997876245648
- 35 USC 102 Novelty (BERT): 0.5152727346792677
- Combined Prediction Score: 0.8804253620890099
- Mean Citation Score: 257.63339
- Max Citation Score: 279.34888
- Similarity Product: 167.73900868224143

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test