PATENT CLAIM ANALYSIS

Application Number: 15989491
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["438", "268000"]

Abstract:
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Claim (Index 1):
A method, comprising:\n forming a plurality of vertical fin structures with a space formed between at least two adjacent vertical fin structures; forming gate material contacting at least one of the plurality of vertical fin structures; and forming source and drain contacts at ends of the at least one vertical fin structure by deposition of metal material in electrical contact with silicide regions.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 93.0
- Lexical Diversity: 1.68571
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15296577', '14965988', '14560672', '14965985', '15452818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8557064874754214
- 35 USC 102 Novelty (BERT): 0.4842475725894304
- Combined Prediction Score: 0.8185605959868223
- Mean Citation Score: 253.057292
- Max Citation Score: 257.8275
- Similarity Product: 237.70021722078323

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test