PATENT CLAIM ANALYSIS

Application Number: 16049624
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["719", "312000"]

Abstract:
Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

Claim (Index 14):
A system configured to enable verification of a data transaction over an inter-processor communication (IPC) link between two or more independently operable processors, the system comprising:\n a shared memory structure comprising a transfer descriptor ring and a completion descriptor ring, the shared memory structure being accessible to a first processor apparatus and second processor apparatus via the IPC link; wherein the first processor apparatus is configured to:\n write one or more transfer descriptors to the transfer descriptor ring of the shared memory structure, the transfer descriptor being descriptive of data to be transmitted by the second processor apparatus; and \n in response to transmission of the data described by the transfer descriptor, via the second processor apparatus, read one or more completion descriptors, and acknowledge the processing of the data by the second processor apparatus, wherein the read of the one or more completion descriptors occurs according to a dynamically set time interval, the time interval being increased or decreased based at least on a quantity of data transmissions respectively exceeding or falling below a threshold over a given time period; and \n wherein the second processor apparatus is configured to:\n retrieve the data to be transmitted, the data to be transmitted being described by the transfer descriptor, based on information read from the one or more transfer descriptors from the transfer descriptor ring of the shared memory structure; and \n in response to the transaction of the data described by the transfer descriptor, write the one or more completion descriptors to be read by the first processor apparatus to the completion descriptor ring of the shared memory structure, the writing of the one or more completion descriptors enabling verification of completion of the data transaction between the first and second processor apparatus.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 1.93902
- Patent Class: 719.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15984153', '15865638', '14879030', '15011291', '15721200']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5399399097591095
- 35 USC 102 Novelty (BERT): 0.5100564532760621
- Combined Prediction Score: 0.5369515641108048
- Mean Citation Score: 260.273578
- Max Citation Score: 303.18237
- Similarity Product: 246.5410714914787

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test