PATENT CLAIM ANALYSIS

Application Number: 16131670
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185180"]

Abstract:
A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

Claim (Index 1):
A semiconductor memory device comprising:\n a first memory string including first and second select transistors and first and second memory cell transistors connected between the first and second select transistors; a second memory string including third and fourth select transistors and third and fourth memory cell transistors connected between the third and fourth select transistors; a first word line connected to gates of the first and third memory cell transistors; a second word line connected to gates of the second and fourth memory cell transistors; first and second selection gate lines respectively connected to gates of the first and third select transistors; a bit line connected to the first and third select transistors; and a source line connected to the second and fourth select transistors, wherein, during a read operation performed on the first memory cell transistor, the second word line is boosted from a first voltage to a second voltage over a first time interval starting at a first point in time, the first selection gate line is boosted from the first voltage to a third voltage, which is lower than the second voltage, over a second time interval, which is shorter than the first time interval, starting at the first point in time, the first word line is boosted from the first voltage to a fourth voltage, which is lower than the third voltage, over a third time interval, which is shorter than the second time interval, starting at the first point in time, and then a fifth voltage lower than the fourth voltage is applied to the first word line, the second selection gate line is boosted from the first voltage to the fourth voltage over the third time interval starting at the first point in time, and then the first voltage is applied to the second selection gate line, and the bit line and the source line are maintained at a sixth voltage, which is lower than the fifth voltage, during the third time interval, and then, after the end of the third time interval, the bit line and the source line are boosted from the sixth voltage to a seventh voltage.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 97.0
- Lexical Diversity: 3.56522
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15693407', '15916551', '14474307', '15688846', '15885076']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8139322450825304
- 35 USC 102 Novelty (BERT): 0.5217289653212707
- Combined Prediction Score: 0.7847119171064044
- Mean Citation Score: 271.261202
- Max Citation Score: 359.03253
- Similarity Product: 343.17882744873583

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test