PATENT CLAIM ANALYSIS

Application Number: 16023866
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-10
Patent Classification: ["257", "314000"]

Abstract:
A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

Claim (Index 12):
A method of forming a three-dimensional memory device, comprising:\n forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; forming a sacrificial matrix layer over the alternating stack; forming sacrificial pillar structures through the sacrificial matrix layer and the alternating stack; replacing at least the sacrificial matrix layer with a combination of a patterned template structure, doped semiconductor spacers contacting sidewalls of the patterned template structure, and an insulating cap layer; replacing the sacrificial pillar structures with memory opening fill structures comprising a memory film and a vertical semiconductor channel; forming drain-select-level cavities by removing an entirety of each of the patterned template structure selective to materials of the doped semiconductor spacers and the insulating cap layer; and depositing at least one electrically conductive material within volumes of the drain-select-level cavities to form drain-select-level electrically conductive strips comprising a combination of a respective portion of the at least one deposited electrically conductive material and a respective pair of doped semiconductor spacers.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 94.0
- Lexical Diversity: 2.12
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16023289', '16024048', '15198175', '16020817', '16002294']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9388331014805286
- 35 USC 102 Novelty (BERT): 0.5672253898066839
- Combined Prediction Score: 0.901672330313144
- Mean Citation Score: 423.77172600000006
- Max Citation Score: 493.10068
- Similarity Product: 364.5880176069832

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test