PATENT CLAIM ANALYSIS

Application Number: 15903974
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["323", "364000"]

Abstract:
Circuits comprising: a first capacitor(C1); a first switch(S1) having a first side coupled to a VIN and a second side coupled to a first side of C1; a second switch(S2) having a first side coupled to the second side of S1; a third switch(S3) having a first side coupled to a second side of S2 and a second side coupled to a second side of C1; a fourth switch(S4) having a first side coupled to a second side of S3 and a second side coupled to a V SUPPLY , wherein: in a first state, S1 and S3 are off, and S2 and S4 are on; in a second state, S1 and S3 are on, and S2 and S4 are off; and at least one of a control of S1, a control of S2, a control of S3, and a control of S4 is coupled to a time-varying-slew-rate signal.

Claim (Index 3):
The circuit of  claim 1 , wherein the second switch is an NMOS FET, and the control of the second switch is a gate of the NMOS FET.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 4.18605
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15695955', '15668119', '15868496', '15379475', '15487682']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7358577826192984
- 35 USC 102 Novelty (BERT): 0.476692472380654
- Combined Prediction Score: 0.709941251595434
- Mean Citation Score: 161.84054999999995
- Max Citation Score: 178.81423999999996
- Similarity Product: 128.11852431021686

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test