PATENT CLAIM ANALYSIS

Application Number: 16015168
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["365", "001000"]

Abstract:
Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is performed on at least one memory cell in a first group of memory cells out of a plurality of groups of memory cells coupled to a line. A first voltage is applied across the first group of memory cells for the operation and a lower second voltage is applied across the other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells. These steps may repeated until the operations covers all the groups.

Claim (Index 5):
In a cross-point array of memory cells, each memory cell having only one thyristor, the thyristor connected between an anode line and a cathode line, a method of performing a write or read operation on a row of memory cells of the cross-point array, comprising:\n performing the write or read operation on a first group of memory cells in the row of memory cells, the first group of memory cells forming a portion of memory cells in the row, while holding the balance of the memory cells of the row in a standby state; performing the write or read operation on a second group of memory cells in the row of memory cells, the second group of memory cells forming a portion of memory cells and excluding the first group of memory cells in the row, while holding the balance of memory cells of the row in a Standby state; and continuing the write or read operation on remaining groups of the row of memory cells one group of memory cells at a time and excluding groups upon which the write or read operation has been performed, while holding the balance of the memory cells in the row in a standby state until the write or read operation has been performed on all groups of memory cells in the row of memory cells; whereby the amount of current used for the write or read operation on the row of memory cells is controlled.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 94.0
- Lexical Diversity: 2.17544
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14841615', '15426909', '16015156', '16015164', '14841521']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8205835287876115
- 35 USC 102 Novelty (BERT): 0.5825898720641564
- Combined Prediction Score: 0.796784163115266
- Mean Citation Score: 431.216638
- Max Citation Score: 480.605
- Similarity Product: 471.7013605722785

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test