PATENT CLAIM ANALYSIS

Application Number: 16003950
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["712", "215000"]

Abstract:
Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where each load/store slice includes a load miss queue and a load reorder queue, includes: receiving, at a load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; and if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction.

Claim (Index 14):
The multi-slice processor of  claim 8  wherein merging the entry comprises modifying an entry in the load reorder queue for the previous load instruction indicating a merge with the load instruction.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 94.0
- Lexical Diversity: 2.50943
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15077015', '15135685', '15180838', '15219638', '15997863']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6080964702150318
- 35 USC 102 Novelty (BERT): 0.562502364965736
- Combined Prediction Score: 0.6035370596901022
- Mean Citation Score: 325.77904
- Max Citation Score: 430.5251
- Similarity Product: 392.0656437217117

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test