PATENT CLAIM ANALYSIS

Application Number: 16290102
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-06
Patent Classification: ["365", "097000"]

Abstract:
A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Claim (Index 1):
A semiconductor device, comprising:\n a plurality of word lines;\n a plurality of bit lines crossing the plurality of word lines, the plurality of bit lines including first bit lines and second bit lines, the second bit lines spaced apart from the first bit lines in a direction of extension of the plurality of word lines; \n a plurality of first memory cells connected between the plurality of word lines and the first bit lines, each of the plurality of first memory cells including a first memory element and a first selection element, the first memory element and the first selection element connected to each other; and \n a plurality of second memory cells connected between the plurality of word lines and the second bit lines, each of the plurality of second memory cells including a second memory element and a second selection element, the second memory element and the second selection element connected to each other, \n wherein the first memory element includes a first magnetic tunnel junction, and the second memory element includes a second magnetic tunnel junction, each of the first and second magnetic tunnel junctions including a pinned layer, a free layer, and a tunnel barrier layer between the pinned layer and the free layer, \n wherein the tunnel barrier layers of a first portion of the second magnetic tunnel junctions have an irreversible resistance state, \n wherein the first magnetic tunnel junction has a rewritable structure, and is configured to have one of (i) a first resistance corresponding to first data, and (ii) a second resistance corresponding to second data; \n wherein at least one second magnetic tunnel junction among the first portion of the second magnetic tunnel junctions has a third resistance corresponding to the first data, the at least one second magnetic tunnel junction having been programmed through a first one-time programming operation, \n wherein at least one other second magnetic tunnel junction from among the first portion of the second magnetic tunnel junctions has a fourth resistance corresponding to the second data, the at least one other second magnetic tunnel junction having been programmed through a second one-time programming operation, \n wherein the first to fourth resistances are different from each other,\n wherein one or more of the plurality of first memory cells are configured as one or more first reference cells for a reading operation on the plurality of first memory cells, and one or more of the plurality of second memory cells are configured as one or more second reference cells for a reading operation on the plurality of second memory cells, and \n wherein the one or more of the plurality of first memory cells includes one or more pairs of first memory cells, and a pair of first memory cells among the one or more pairs of first memory cells are connected in parallel to one of the first bit lines.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 99.0
- Lexical Diversity: 2.14706
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15293782', '14526489', '15078182', '15227334', '14639183']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7947946787794771
- 35 USC 102 Novelty (BERT): 0.5440282850989243
- Combined Prediction Score: 0.7697180394114218
- Mean Citation Score: 276.65533400000004
- Max Citation Score: 405.81754
- Similarity Product: 395.97413016384127

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test