PATENT CLAIM ANALYSIS

Application Number: 15986886
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "329000"]

Abstract:
Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.

Claim (Index 9):
The method of  claim 1  further comprising:\n removing the spacer and first dielectric liner layers; \n depositing a bottom spacer layer onto the substrate; \n forming a gate dielectric and gate conductor structure about each of the fins in both the PFET and NFET regions; \n forming a top spacer layer on the substrate; \n depositing an interlayer dielectric on the substrate; \n removing the hardmask to expose the top surface of the fins in both the PFET and NFET regions; \n epitaxially growing the first in-situ doped semiconductor on the fins in both the PFET and NFET regions; \n conformally depositing a second dielectric liner layer onto the semiconductor substrate; \n applying a mask material onto the PFET region if the first in situ doped semiconductor is the p-type doped semiconductor or onto the NFET region if the first in situ doped semiconductor is an p-type doped semiconductor; \n removing the second dielectric liner layer from horizontal surfaces so as to expose a surface of the first in-situ doped semiconductor in the NFET region or the PFET region that is free of the mask material; \n removing the mask material; \n selectively removing the first epitaxial grown in-situ doped semiconductor from the NFET region or the PFET region that is free of the mask material to form a second recess; and \n epitaxially growing the second in-situ doped semiconductor in the second recess of the NFET region or the PFET region that is free of the mask such that the PFET region includes the p-type dopant semiconductor to define a PFET top S/D and the NFET region includes the n-type dopant semiconductor to define an NFET top S/D.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 93.0
- Lexical Diversity: 1.51282
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15918077', '13848203', '14750455', '15404466', '14729105']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9303196950948748
- 35 USC 102 Novelty (BERT): 0.5206952535275929
- Combined Prediction Score: 0.8893572509381465
- Mean Citation Score: 323.995334
- Max Citation Score: 332.1764
- Similarity Product: 240.4531771945

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test