PATENT CLAIM ANALYSIS

Application Number: 15907992
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["257", "324000"]

Abstract:
According to one embodiment, a memory device includes a plurality of first electrode layers stacked over each other in a stacking direction, a pair of second electrode layers located over the plurality of first electrode layers in the stacking direction, a channel layer extending through the first and second electrode layers, and a charge storage layer between each first electrode layer and the channel layer. A thickness in the stacking direction of at least one of the second electrode layers being greater than a thickness in the stacking direction of any of the first electrode layers.

Claim (Index 16):
The memory device according to  claim 9 , further comprising:\n two or more third electrode layers located over the first electrode layers, each third electrode layer extending in a direction crossing over the first and second portions of second electrode layers; and an insulator between the second electrode layers and the third electrode layer, wherein a thickness of the third electrode layers in the first direction is larger than the thicknesses of the first electrode layers in the first direction.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 88.0
- Lexical Diversity: 2.42857
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15456869', '15463582', '15854433', '15046611', '15268140']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9096699682471556
- 35 USC 102 Novelty (BERT): 0.4862362058573407
- Combined Prediction Score: 0.8673265920081742
- Mean Citation Score: 177.533812
- Max Citation Score: 185.20526
- Similarity Product: 126.5313287442398

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test