PATENT CLAIM ANALYSIS

Application Number: 16017126
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["716", "104000"]

Abstract:
Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

Claim (Index 6):
The method of  claim 1 , wherein the feedback input is received from a user.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.76471
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10780140', '14794871', '14557920', '10420951', '14108786']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3344726451755396
- 35 USC 102 Novelty (BERT): 0.508230275544887
- Combined Prediction Score: 0.3518484082124743
- Mean Citation Score: 158.0857
- Max Citation Score: 174.17136000000005
- Similarity Product: 73.14224152363302

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test