PATENT CLAIM ANALYSIS

Application Number: 16049497
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["326", "093000"]

Abstract:
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

Claim (Index 3):
A data processing system comprising:\n a system processor; and a programmable logic device communicatively coupled to the processor, wherein the programmable logic device comprises:\n a first stage of combinational logic circuitry in programmable logic fabric of the programmable logic device, wherein the first stage of combinational logic circuitry is disposed between a first latch and a second latch; and \n a second stage of combinational logic circuitry in programmable logic fabric of the programmable logic device, wherein the second stage of combinational logic circuitry is disposed between the second latch and a third latch; \n wherein:\n the first stage of combinational logic circuitry has a first delay and wherein the second stage of combinational logic circuitry has a second delay that is different from the first delay by a first time difference; \n the first latch is clocked to a first clock, the second latch is clocked to a second clock, and the third latch is clocked to the first clock, wherein the first clock and the second clock have the same frequency, and wherein at least one clock edge of the first clock is out of phase with at least one clock edge of the second clock by a second time difference; and \n the second time difference between the at least one clock edge of the first clock and the at least one clock edge of the second clock accommodates at least part of the first time difference between the first delay and the second delay between the first stage of combinational logic circuitry and the second stage of combinational logic circuitry.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 1.83333
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15464067', '14639735', '12060795', '13347626', '11731125']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6905494738235184
- 35 USC 102 Novelty (BERT): 0.541456209384322
- Combined Prediction Score: 0.6756401473795988
- Mean Citation Score: 304.804712
- Max Citation Score: 404.64197
- Similarity Product: 377.3644308691538

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test