PATENT CLAIM ANALYSIS

Application Number: 15951666
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "185220"]

Abstract:
Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.

Claim (Index 6):
The memory device according to  claim 1 , wherein the memory cells are formed in a single-stack structure or in a multi-stack structure in which a plurality of stacks are piled up.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 1.89796
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15398814', '15724329', '15651217', '15628808', '15648639']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8238042858360103
- 35 USC 102 Novelty (BERT): 0.5327017158868713
- Combined Prediction Score: 0.7946940288410964
- Mean Citation Score: 281.136236
- Max Citation Score: 385.60147
- Similarity Product: 308.2110998590195

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test