PATENT CLAIM ANALYSIS

Application Number: 15867180
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "124000"]

Abstract:
The present disclosure illustrates to a serially-connected transistor device including a lead line frame including a carrier board and an electrode pin set, and the carrier board including a first board and a second board, and the electrode pin set including a first pin electrically connected to the first board, and a second pin, a third pin and a fourth pin; and a die unit including a first die and a second die electrically connected to the first board and the second board, respectively, so that two transistors can be electrically connected in series in the serially-connected transistor device to increase reverse voltage. As a result, the serially-connected transistor device of the present disclosure can be produced by automation die bonding and wire bonding manner, so as to achieve the effect of automated production, high yield, low cost, and better product consistency and reliability.

Claim (Index 1):
A serially-connected transistor device, comprising:\n a lead line frame made by conductive material and comprising a carrier board and an electrode pin set, said carrier board comprising a first board and a second board insulated from said first board, said electrode pin set comprising a first pin, a second pin, a third pin and a fourth pin, wherein said second pin, said third pin and said fourth pin are disposed independently, and said first pin is electrically connected to said first board; a die unit comprising a first die and a second die, and said first die and said second die respectively comprising first electrodes formed at a back surface thereof and served as a collector of the serially-connected transistor device, said first die and said second die respectively comprising second electrodes formed at a front surface thereof and served as gates of the serially-connected transistor device, and said first die and said second die comprising third electrodes formed at a front surface thereof and served as an emitter of the serially-connected transistor device, wherein said first die and said second die are disposed on said carrier board and connected to said first board and said second board through said first electrodes thereof, respectively, and said second electrodes of said first die and said second die are electrically connected to said second pin and said third pin, respectively, and said third electrode of said first die is electrically connected to said second board, and said third electrode of said second die is electrically connected to said fourth pin; and an outer insulative protective layer disposed on said lead line frame and configured to cover said die unit, wherein said electrode pin set is exposed out of said outer insulative protective layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.39394
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15823085', '10301200', '15552409', '14457965', '15291284']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9085696249020144
- 35 USC 102 Novelty (BERT): 0.4614245233687635
- Combined Prediction Score: 0.8638551147486893
- Mean Citation Score: 165.15748
- Max Citation Score: 178.3012
- Similarity Product: 149.46125390126704

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test