PATENT CLAIM ANALYSIS

Application Number: 15745073
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["257", "072000"]

Abstract:
The disclosure provides a manufacturing method of a LTPS-TFT, including: providing a substrate and sequentially forming a buffer layer, a low temperature poly-silicon layer, a source contact region, a drain contact region, a gate insulator layer, a gate layer, and a dielectric layer on the substrate, respectively forming a first and a second contact holes through the dielectric layer and the gate insulator layer by dry etching to expose the source and the drain contact regions; and on the dielectric layer, forming a source electrode to contact the source contact region through the first contact hole and a drain electrode to contact the drain contact region through the second contact hole. When the contact holes are manufactured by dry etching, H 2  is added into the etching gas to increase the selectivity ratio to the poly-silicon, thereby reducing the loss of poly-silicon. A LTPS-TFT and an array substrate are also provided.

Claim (Index 3):
The manufacturing method of the low temperature poly-silicon thin film transistor according to  claim 1 , wherein a flow ratio of the fluorine-containing gas to the hydrogen gas is 5-15:1.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 2.56923
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13994244', '14375911', '15740606', '15085217', '14778090']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9140772944067233
- 35 USC 102 Novelty (BERT): 0.5002266672696377
- Combined Prediction Score: 0.8726922316930147
- Mean Citation Score: 237.47079
- Max Citation Score: 245.28601
- Similarity Product: 192.3850179556984

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test