PATENT CLAIM ANALYSIS

Application Number: 15919639
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "427000"]

Abstract:
A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

Claim (Index 2):
The semiconductor memory device of  claim 1 , wherein the top surface of the capping metal pattern is in direct contact with the bottom electrode of the magnetic tunnel junction pattern.

Metadata:
- Claim Count in Document: 49.0
- Percentile: 90.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15656007', '15210151', '15648772', '14716913', '15158981']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9358738606123536
- 35 USC 102 Novelty (BERT): 0.5173805742503369
- Combined Prediction Score: 0.894024531976152
- Mean Citation Score: 308.847028
- Max Citation Score: 327.6744700000001
- Similarity Product: 280.6997158946968

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test