PATENT CLAIM ANALYSIS

Application Number: 15919805
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["710", "316000"]

Abstract:
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Claim (Index 8):
The slave device according to  claim 7 , wherein the selection control module comprises an address delay flip-flop comprising an address delay flip-flop data output, an address delay flip-flop clock input and an address delay flip-flop data input, the address delay flip-flop providing the selection control signal at the address delay flip-flop data output depending on the medium voltage data signal and a timing control signal being provided at an address delay flip-flop clock input by an AND gate depending on the low voltage address signal and the medium voltage clock signal.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.56757
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14848472', '14028806', '11715478', '10764406', '14217510']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6225624433914635
- 35 USC 102 Novelty (BERT): 0.5621011138798162
- Combined Prediction Score: 0.6165163104402988
- Mean Citation Score: 245.13131600000008
- Max Citation Score: 441.9628
- Similarity Product: 364.93997850494384

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test