PATENT CLAIM ANALYSIS

Application Number: 16176327
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-06
Patent Classification: ["385", "131000"]

Abstract:
In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.

Claim (Index 1):
A semiconductor device comprising:\n a substrate; an optical waveguide section to be arranged over a first surface of the substrate and propagate light along the first surface; and a first insulating film formed over the first surface so as to cover the optical waveguide section, wherein the optical waveguide section includes: a first semiconductor layer formed over the first surface; a dielectric layer formed over the first semiconductor layer; and a second semiconductor layer formed over the dielectric layer, wherein the first semiconductor layer has: a first part to propagate the light; and a second part formed integrally with the first part so as not to overlap with the first part in a plan view, wherein the second semiconductor layer has: a third part formed so as to cover the first part; and a fourth part formed integrally with the third part so as not to overlap with the first part and the second part in a plan view, wherein a first coupling hole reaching the second part and a second coupling hole reaching the fourth part are formed in the first insulating film, wherein a first electrode electrically coupled to the second part is formed in the first coupling hole, wherein a second electrode electrically coupled to the fourth part is formed in the second coupling hole; and wherein the first semiconductor layer is arranged but the second semiconductor layer is not arranged between the first electrode and the substrate, and the second semiconductor layer is arranged but the first semiconductor layer is not arranged between the second electrode and the substrate.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 97.0
- Lexical Diversity: 2.40984
- Patent Class: 385.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15271350', '15807978', '15005195', '15411268', '15145712']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7825376518188437
- 35 USC 102 Novelty (BERT): 0.4826688411845432
- Combined Prediction Score: 0.7525507707554138
- Mean Citation Score: 207.72455
- Max Citation Score: 215.99309
- Similarity Product: 176.87503965948224

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test