PATENT CLAIM ANALYSIS

Application Number: 16215870
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "192000"]

Abstract:
A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

Claim (Index 17):
A semiconductor device structure comprising:\n a semiconductor substrate having a first major surface and an opposing second major surface; a heterostructure adjacent the first major surface, the heterostructure comprising:\n a channel layer; and \n a barrier layer over the channel layer; \n a first electrode disposed proximate to a first portion of the channel layer; a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode; a third electrode disposed on the second major surface of the semiconductor substrate; a first control electrode disposed between the first electrode and the second electrode and configured to control a first current path between the first electrode and the second electrode; a fourth electrode disposed at least in part proximate to the first major surface, wherein the fourth electrode is electrically coupled to the first electrode; and a clamping device disposed in the semiconductor substrate and electrically coupled to the fourth electrode, wherein the clamping device comprises a plurality of n-type regions and a plurality of p-type regions disposed in the semiconductor substrate in a back-to-back p-n diode configuration.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 3.64103
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15648211', '14853720', '15648264', '14989370', '14853729']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91048372844971
- 35 USC 102 Novelty (BERT): 0.5634015932334115
- Combined Prediction Score: 0.8757755149280801
- Mean Citation Score: 318.612908
- Max Citation Score: 421.7774
- Similarity Product: 409.2256049514531

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test