PATENT CLAIM ANALYSIS

Application Number: 16013813
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["326", "080000"]

Abstract:
A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.

Claim (Index 2):
The semiconductor device of  claim 1 , comprising command splitting circuitry configured to transmit the command and the even clock signal to the even command path when the clock signal and the even clock signal are in phase, and transmit the command and the odd clock signal to the odd command path when the clock signal and the odd clock signal are in phase.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 94.0
- Lexical Diversity: 3.16279
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15649145', '12071198', '11647761', '11600079', '15693194']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6579067649085273
- 35 USC 102 Novelty (BERT): 0.5520167173713911
- Combined Prediction Score: 0.6473177601548137
- Mean Citation Score: 258.226084
- Max Citation Score: 417.29547
- Similarity Product: 415.467919949162

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test