PATENT CLAIM ANALYSIS

Application Number: 16229155
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["375", "362000"]

Abstract:
A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

Claim (Index 6):
The transceiver according to  claim 1 , wherein the multi-phase signal generator comprises:\n a first phase-generation-path, configured to receive the system-clock signal and generate the first shifted system-clock signal according to a first phase-configuration signal from the calibration circuit; a second phase-generation-path, comprising:\n a first sub-circuit, electrically connected to a symmetric terminal and configured to receive the system-clock signal and selectively receive a first-second phase-configuration signal from the calibration circuit; and \n a second sub-circuit, electrically connected to the symmetric terminal, configured to selectively receive a second-second phase-configuration signal from the calibration circuit and generate the second shifted system-clock signal, wherein the first sub-circuit and the second sub-circuit are symmetric; and \n a third phase-generation-path, electrically connected to the symmetric terminal, configured to selectively receive a third phase-configuration signal from the calibration circuit and generate the third system-clock signal, wherein the first set of phase control signals further comprises the first-second phase-configuration signal and the second-second phase-configuration signal, and the second set of phase control signals further comprises the first phase-configuration signal and the third phase-configuration signal.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 98.0
- Lexical Diversity: 2.6
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12079388', '15722209', '10852864', '13249954', '10923421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4588524830211
- 35 USC 102 Novelty (BERT): 0.5133426288586791
- Combined Prediction Score: 0.4643014976048579
- Mean Citation Score: 278.11861600000003
- Max Citation Score: 291.84943
- Similarity Product: 224.576280067696

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test