PATENT CLAIM ANALYSIS

Application Number: 15989556
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "774000"]

Abstract:
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure is in the first and second IC dies and extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure. The plurality of TSV coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

Claim (Index 19):
A three-dimensional (3D) integrated circuit (IC) comprising:\n a first IC die and a second IC die over the first IC die, wherein the first and second IC dies comprise respective semiconductor substrates, respective interconnect structures between the semiconductor substrates, and respective bonding structures between the interconnect structures, wherein the interconnect structures comprise alternating stacks of wiring layers and via layers, wherein the bonding structures comprise respective bonding dielectric layers, respective redistribution layers, and respective bonding contacts, wherein the bonding dielectric layers contact at a bonding interface between the first and second IC dies, wherein the redistribution layers are in the bonding dielectric layers and contact at the bonding interface, and wherein the bonding contacts extend respectively from the redistribution layers respectively to the interconnect structures; a seal-ring structure arranged at a peripheral region of the 3D IC in the first and second IC dies, wherein the seal-ring structure extends respectively from and to the semiconductor substrates to define a barrier around an interior of the first and second IC dies; and a plurality of through silicon via (TSV) coupling structures arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure, wherein the plurality of TSV coupling structures respectively comprises a through silicon via (TSV) disposed in the semiconductor substrate of the second IC die and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias, a pair of TSV redistribution layers and a pair of TSV bonding contacts; wherein the seal-ring structure comprises a first conductive ring having a bonding contact and a redistribution layer electrically coupled to the first and second interconnect structures, and wherein the seal-ring structure further comprises a second conductive ring without bonding contacts or redistribution layers.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 2.72414
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15383419', '15954772', '15665495', '12618412', '15216815']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9176058850338698
- 35 USC 102 Novelty (BERT): 0.4960525806393944
- Combined Prediction Score: 0.8754505545944222
- Mean Citation Score: 237.237586
- Max Citation Score: 275.49405
- Similarity Product: 234.68900818516013

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test