PATENT CLAIM ANALYSIS

Application Number: 15937906
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["330", "311000"]

Abstract:
A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.

Claim (Index 15):
A method for operating a cascode circuit for digital power amplifier (DPA), the method comprising:\n applying a first voltage to a first power supply terminal; applying a second voltage to a common ground terminal; and applying a third voltage to a second power supply terminal, wherein the first, second and third voltages differ from each other, wherein the cascode circuit for DPA comprises: a first cascode circuit and a second cascode circuit stacked between the first and second power supply terminals, wherein the first cascode circuit is coupled to the first power supply terminal and the second cascode circuit is coupled to the second power supply terminal; an output signal terminal coupled to a first node connecting the first cascode circuit and the second cascode circuit; a first signal path between the first cascode circuit and the common ground terminal; and a second signal path between the second cascode circuit and the common ground terminal, wherein each cascode circuit comprises at least two transistors, wherein the first signal path is coupled to a second node between a first transistor and a second transistor of the first cascode circuit and the second signal path is coupled to a third node between a first transistor and a second transistor of the second cascode circuit, wherein the first transistor of the first cascode circuit and the first transistor of the second cascode circuit are input transistors, wherein the cascode circuit for DPA operates either in a switching state where an input signal drives the first and second cascode circuits or in an off state where the input transistors are turned off, wherein a low impedance path is formed between the common ground terminal and the output signal terminal in the off state such that a potential at the common ground terminal and a potential at the output signal terminal are substantially same in the off state.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 90.0
- Lexical Diversity: 2.66667
- Patent Class: 330.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14983512', '11635685', '12547973', '14136469', '15728264']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7705149645693373
- 35 USC 102 Novelty (BERT): 0.4759313542447928
- Combined Prediction Score: 0.7410566035368829
- Mean Citation Score: 182.492038
- Max Citation Score: 190.18234
- Similarity Product: 148.84469958536033

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test