PATENT CLAIM ANALYSIS

Application Number: 15945121
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "190000"]

Abstract:
A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.

Claim (Index 5):
The method of  claim 1 , further comprising forming the first and second fin structures on a silicon (Si) substrate having a (110) orientation.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 2.19298
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15338653', '15674697', '14840960', '15804303', '14800381']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9189060647897758
- 35 USC 102 Novelty (BERT): 0.4995416409346119
- Combined Prediction Score: 0.8769696224042595
- Mean Citation Score: 239.92921600000005
- Max Citation Score: 250.67361
- Similarity Product: 178.41512672745108

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test