PATENT CLAIM ANALYSIS

Application Number: 16052516
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-11
Patent Classification: ["708", "190000"]

Abstract:
A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

Claim (Index 11):
The circuit of  claim 10 , wherein the access transistor of each of the plurality of memory cells is coupled between the capacitor and a column line to program the memory array a row at a time.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.86957
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15581110', '15685788', '15709709', '15535765', '16027347']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4518539183640164
- 35 USC 102 Novelty (BERT): 0.4789666648945943
- Combined Prediction Score: 0.4545651930170742
- Mean Citation Score: 148.352228
- Max Citation Score: 229.89586
- Similarity Product: 217.5420730074929

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test