PATENT CLAIM ANALYSIS

Application Number: 15905256
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "148000"]

Abstract:
A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Claim (Index 16):
The semiconductor device according to  claim 13 , further comprising:\n a guard layer in the substrate between the first and second regions, wherein the guard layer is between the first transistor and the second transistor.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 88.0
- Lexical Diversity: 3.09091
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10372626', '13620184', '11134476', '15629489', '15214253']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7738147170488546
- 35 USC 102 Novelty (BERT): 0.4647224267416179
- Combined Prediction Score: 0.742905488018131
- Mean Citation Score: 146.79899799999995
- Max Citation Score: 156.89511000000005
- Similarity Product: 113.84610371444823

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test