PATENT CLAIM ANALYSIS

Application Number: 15965872
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "421000"]

Abstract:
Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Claim (Index 14):
The memory device of  claim 10 , wherein a total thickness of the first electrode, the second electrode and the magnetic tunnel junction in each memory cell along a third direction that is in parallel with the backend layer and perpendicular to the first direction is less than a maximum value of lengths of the first electrode, the second electrode and the magnetic tunnel junction in each memory cell along the first direction.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 2.54348
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14688073', '15601095', '15249559', '14801988', '15428509']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9052442603951624
- 35 USC 102 Novelty (BERT): 0.4793279127779976
- Combined Prediction Score: 0.8626526256334459
- Mean Citation Score: 175.88931399999996
- Max Citation Score: 181.69939
- Similarity Product: 143.00307334324657

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test