PATENT CLAIM ANALYSIS

Application Number: 15994402
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["257", "192000"]

Abstract:
Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A semiconductor fin having a channel region, a nanowire arranged over the channel region of the semiconductor fin, a source/drain region connected with the channel region of the semiconductor fin and the nanowire, and a gate structure that overlaps with the channel region of the semiconductor fin and the nanowire. The nanowire has a first gate length, and the channel region of the semiconductor fin has a second gate length that is greater than the first gate length.

Claim (Index 4):
The structure of  claim 1  wherein the gate structure surrounds the nanowire in a gate-all-around arrangement, the section of the gate structure is positioned in the vertical direction between the nanowire and the channel region of the semiconductor fin, and the section of the gate structure has a height and a variable length dimension that tapers in the vertical direction.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 2.67568
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15867036', '15590409', '15812263', '15339665', '15479801']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.933200561723606
- 35 USC 102 Novelty (BERT): 0.5090866187216047
- Combined Prediction Score: 0.8907891674234057
- Mean Citation Score: 274.026838
- Max Citation Score: 280.33884
- Similarity Product: 200.66478361903668

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test