PATENT CLAIM ANALYSIS

Application Number: 16204409
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "104000"]

Abstract:
Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

Claim (Index 26):
A memory cell, comprising:\n two pulldown devices and two pullup devices supported by a base; the two pulldown devices being first and second pulldown devices, and the two pullup devices being first and second pullup devices; the first pullup device and first pulldown device being together comprised by a first inverter; the second pullup device and second pulldown device being together comprised by a second inverter; the first and second inverters having first and second inverter outputs, respectively; the first and second pullup devices being one atop another; the first and second pulldown devices being one atop another; a first access transistor gatedly coupling the first inverter output to a first comparative bitline; the first access transistor having a first access transistor gate; a second access transistor gatedly coupling the second inverter output to a second comparative bitline; the second access transistor having a second access transistor gate; and a wordline coupling the first and second access transistor gates to one another; the wordline having a first side and an opposing second side; the first and second inverters being adjacent the first side of the wordline, and the first and second comparative bitlines being adjacent the second side of the wordline.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.71698
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15796611', '10801334', '15797462', '13746395', '16043653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7751047200541701
- 35 USC 102 Novelty (BERT): 0.5847373288344191
- Combined Prediction Score: 0.7560679809321951
- Mean Citation Score: 313.302702
- Max Citation Score: 485.1104
- Similarity Product: 463.3725465620044

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test