PATENT CLAIM ANALYSIS

Application Number: 15959298
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "401000"]

Abstract:
A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

Claim (Index 14):
A semiconductor device, comprising:\n a semiconductor fin comprising a first channel portion and a second channel portion; a first gate overlapped with the first channel portion of the semiconductor fin; a first dielectric layer covering the first channel portion of the semiconductor fin, the first dielectric layer being between the first gate and the first channel portion of the semiconductor fin; a pair of first spacers disposed on the first dielectric layer and covering sidewalls of the first gate; a second dielectric layer covering the second channel portion of the semiconductor fin, the second channel portion being uncovered by the first dielectric layer, and the first dielectric layer being thinner than the second dielectric layer; a second gate disposed on the second dielectric layer and overlapped with the second channel portion of the semiconductor fin, a width of the first gate being smaller than that of the second gate; and a pair of second spacers disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the pair of second spacers to space apart the second gate from the pair of second spacers.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 4.10256
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14953427', '14968916', '14941673', '15062224', '15715153']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.914793607452371
- 35 USC 102 Novelty (BERT): 0.477264116771541
- Combined Prediction Score: 0.871040658384288
- Mean Citation Score: 200.10886800000003
- Max Citation Score: 219.74133
- Similarity Product: 182.665484175666

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test