PATENT CLAIM ANALYSIS

Application Number: 16031698
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "957000"]

Abstract:
An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.

Claim (Index 1):
A method of forming a semiconductor structure comprising:\n providing a metallization structure comprising a first dielectric material layer and a first lower interconnect structure embedded in a portion of the first dielectric material layer and a second lower interconnect structure embedded in another portion of the first dielectric material layer; forming a second dielectric material layer on the metallization structure; forming a plurality of trenches in an upper portion of the second dielectric material layer, wherein the plurality of trenches extend across the first lower interconnect structure and the second lower interconnect structure; forming a first metal layer along sidewall surfaces and a bottom surface of each trench of the plurality of trenches and a topmost surface of the second dielectric material layer; patterning the first metal layer to remove the first metal layer completely from an area where the second lower interconnect structure is located, wherein the patterning the first metal layer provides a first metal portion overlying the first lower interconnect structure; forming a first capacitor dielectric layer on the first metal portion and exposed surfaces of the plurality of trenches; forming a second metal layer over the first capacitor dielectric layer; patterning the second metal layer to remove the second metal layer completely from an area where the first lower interconnect structure is located, wherein the patterning the second metal layer provides a second metal portion overlying the second lower interconnect structure; forming a third dielectric material layer to completely fill the plurality of trenches; and forming a first upper interconnect structure extending through the third dielectric material layer, the first capacitor dielectrics layer, the first metal portion and the second dielectric material layer to contact the first lower interconnect structure and a second upper interconnect structure extending through the third dielectric material layer, the second metal portion, the first capacitor dielectric layer and the second dielectric material layer to contact the second lower interconnect structure.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 95.0
- Lexical Diversity: 1.37838
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15400351', '15450193', '15951208', '15970601', '14957843']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8767429370273508
- 35 USC 102 Novelty (BERT): 0.5450841136141934
- Combined Prediction Score: 0.8435770546860352
- Mean Citation Score: 288.164396
- Max Citation Score: 405.6303
- Similarity Product: 318.6455409881831

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test