PATENT CLAIM ANALYSIS

Application Number: 16166000
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-05
Patent Classification: ["712", "220000"]

Abstract:
A processor comprising: an execution unit for executing a respective thread in each of a repeating sequence of time slots; and a plurality of context register sets, each comprising a respective set of registers for representing a state of a respective thread. The context register sets comprise a respective worker context register set for each of the number of time slots the execution unit is operable to interleave, and at least one extra context register set. The worker context register sets represent the respective states of worker threads and the extra context register set being represents the state of a supervisor thread. The processor is configured to begin running the supervisor thread in each of the time slots, and to enable the supervisor thread to then individually relinquish each of the time slots in which it is running to a respective one of the worker threads.

Claim (Index 6):
The processor of any of  claim 4 , wherein one or more instructions of the instruction set including at least said one or more relinquish instructions are reserved for use by the supervisor thread and are not executable by the worker threads.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 2.62712
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15885955', '15886099', '15886185', '15886138', '12605201']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6599704119692228
- 35 USC 102 Novelty (BERT): 0.5435818566318656
- Combined Prediction Score: 0.648331556435487
- Mean Citation Score: 325.325886
- Max Citation Score: 439.8989
- Similarity Product: 258.2277653785527

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test