PATENT CLAIM ANALYSIS

Application Number: 15918115
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["330", "12400R"]

Abstract:
The disclosure relates to a lock-in amplifier comprising a plurality of channels (CH 1 -CH N ), wherein each channel of the plurality of channels (CH 1 -CH N ) is configured to receive an input signal (S in1 -S inN ) and generate at least one output signal (S out1 -S outN ), a synchronization unit ( 110 ) configured to synchronize the generated output signals (S out1 -S outN ) of the plurality of channels (CH 1 -CH N ), an aggregation module ( 150 ) configured to receive the generated output signals (S out1 -S outN ) and generate an aggregated signal (S agg ) based on the generated output signals (S out1 -S outN ).

Claim (Index 3):
The lock in amplifier according to  claim 2 , wherein the output module ( 123 ,  133 ,  143 ) of each channel is configured to:\n generate the output signal (S out1 -S outN ) by calculating an average based on the processed signal (S p1 -S pN ), and wherein the synchronization unit ( 110 ) is further configured to trigger the output modules ( 123 ,  133 ,  143 ) of each channel to generate the output signals (S out1 -S outN ) synchronously.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.44444
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15168399', '14806036', '13161994', '11203493', '12487687']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.731405361084684
- 35 USC 102 Novelty (BERT): 0.4788976963513994
- Combined Prediction Score: 0.7061545946113555
- Mean Citation Score: 111.69738
- Max Citation Score: 117.88697
- Similarity Product: 82.19866532201469

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test