PATENT CLAIM ANALYSIS

Application Number: 16033181
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "506000"]

Abstract:
A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.

Claim (Index 5):
The semiconductor device of  claim 1 , wherein the second doped region comprises epitaxially grown p + -doped hydrogenated crystalline silicon with 5 to 40 atomic percent hydrogen.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 2.82143
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15484172', '12727027', '11321051', '12099316', '12795108']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9249428272771846
- 35 USC 102 Novelty (BERT): 0.5269810613917223
- Combined Prediction Score: 0.8851466506886384
- Mean Citation Score: 248.906652
- Max Citation Score: 348.81088
- Similarity Product: 297.7651429761505

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test