PATENT CLAIM ANALYSIS

Application Number: 16263964
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-06
Patent Classification: ["341", "141000"]

Abstract:
A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

Claim (Index 6):
The converter of  claim 5 , wherein the shuffle control circuitry includes:\n second analog signal routing circuitry to couple the positive version of the first analog signal to the fourth capacitor in the first coupling state and to couple the inverted version of the second analog signal to the fourth capacitor in the second coupling state, and third analog signal routing circuitry to couple the positive version of the first analog signal to the second capacitor in the first coupling state and to couple the inverted version of the second analog signal to the second capacitor in the second coupling state.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 99.0
- Lexical Diversity: 1.22727
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15271697', '12113307', '12773768', '14919830', '13673103']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6163980124098438
- 35 USC 102 Novelty (BERT): 0.5527166075641232
- Combined Prediction Score: 0.6100298719252718
- Mean Citation Score: 261.224594
- Max Citation Score: 396.1421
- Similarity Product: 301.96696843920347

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test