PATENT CLAIM ANALYSIS

Application Number: 15991128
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["438", "197000"]

Abstract:
A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

Claim (Index 4):
The method of  claim 1 , further comprising employing work function metal patterning to remove the first work function metal layer prior to forming the at least one gate trench.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 93.0
- Lexical Diversity: 2.03509
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15788390', '15413588', '15481012', '15920303', '15890246']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8689456041492295
- 35 USC 102 Novelty (BERT): 0.5070456010924304
- Combined Prediction Score: 0.8327556038435496
- Mean Citation Score: 265.183236
- Max Citation Score: 273.422
- Similarity Product: 190.58804870033265

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test