PATENT CLAIM ANALYSIS

Application Number: 15891284
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["365", "185080"]

Abstract:
A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

Claim (Index 5):
The method of  claim 1 , wherein activating the first DSG signal at a first DSG further includes logically coupling a Q-terminal of the SRAM to a NAND based nonvolatile memory string with a plurality of NAND based nonvolatile memory cells.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 88.0
- Lexical Diversity: 3.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14855323', '14864741', '15687405', '14923247', '15704006']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8295204758166784
- 35 USC 102 Novelty (BERT): 0.5872422708025858
- Combined Prediction Score: 0.8052926553152692
- Mean Citation Score: 339.86800000000005
- Max Citation Score: 556.3796
- Similarity Product: 430.4744111409664

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test