PATENT CLAIM ANALYSIS

Application Number: 15874125
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "370000"]

Abstract:
An insulated gate bipolar transistor and a method for fabricating the insulated gate bipolar transistor are provided. The insulated gate bipolar transistor includes a semiconductor layer including a bulk layer and a cell region including a first region and a second region. The insulated gate bipolar transistor also includes a well region, a drift region, and a plurality of gate structures in the bulk layer associated with the cell region. Further, the insulated gate bipolar transistor includes source and drain doped regions and an ohmic contact region in a top region of the well region. A size of the source and drain doped regions in the second region is smaller than a size of the source and drain doped regions in the first region. A size of the ohmic contact region in the second region is larger than a size of the ohmic contact region in the first region.

Claim (Index 1):
An insulated gate bipolar transistor, comprising:\n a semiconductor layer, including a collector electrode layer and a bulk layer on the collector electrode layer, wherein the semiconductor layer has a cell region and an edge region around the cell region, and the cell region includes a first region and a second region around the first region; a well region, in the bulk layer associated with the cell region; a drift region, in the bulk layer associated with the cell region, wherein the drift region is formed between the well region and the collector electrode layer, and a conductivity type of the drift region is respectively opposite to conductivity types of the well region and the collector electrode layer; a plurality of gate structures, in the bulk layer associated with the cell region, wherein each gate structure penetrates through the well region and extends into the drift region; source and drain doped regions, in a top region of the well region on both sides of each gate structure, wherein a conductivity type of the source and drain doped regions is opposite to the conductivity type of the well region, and a size of the source and drain doped regions in the second region is smaller than a size of the source and drain doped regions in the first region; and an ohmic contact region, in the top region of the well region, wherein the source and drain doped regions are formed between each gate structure and the ohmic contact region, a conductivity type of the ohmic contact region is the same as the conductivity type of the well region, and a size of the ohmic contact region in the second region is larger than a size of the ohmic contact region in the first region.

Metadata:
- Claim Count in Document: 32.0
- Percentile: 86.0
- Lexical Diversity: 3.22449
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12648818', '12556870', '14834542', '14899428', '14040891']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9041223385440614
- 35 USC 102 Novelty (BERT): 0.509079063139833
- Combined Prediction Score: 0.8646180110036387
- Mean Citation Score: 268.65883599999995
- Max Citation Score: 285.03214
- Similarity Product: 230.26107457904345

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test