PATENT CLAIM ANALYSIS

Application Number: 15909929
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["714", "764000"]

Abstract:
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Claim (Index 3):
The method of  claim 2 , the error correction codeword comprises at least a bit of data, respectively, stored in memory arrays of the set of memory arrays; and\n a common physical location in the at least two memory arrays is mapped to at least two different error correction codewords to reduce uncorrectable errors in data stored in the memory arrays due to systemic errors in the set of memory arrays overloading the error correction codeword with errors in the data stored in the memory arrays.

Metadata:
- Claim Count in Document: 54.0
- Percentile: 90.0
- Lexical Diversity: 1.89744
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13792597', '14844843', '13365064', '15787644', '11391000']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2970058145008166
- 35 USC 102 Novelty (BERT): 0.5335716226153016
- Combined Prediction Score: 0.3206623953122651
- Mean Citation Score: 256.56980200000004
- Max Citation Score: 365.56512
- Similarity Product: 344.8062913549805

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test