PATENT CLAIM ANALYSIS

Application Number: 15958555
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "383000"]

Abstract:
A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.

Claim (Index 17):
The semiconductor structure according to  claim 14 , wherein:\n a top surface of the first dielectric layer levels with a top surface the protective layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 91.0
- Lexical Diversity: 3.41304
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15059501', '15059635', '15707543', '15785071', '14722818']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281986201991868
- 35 USC 102 Novelty (BERT): 0.516787308496612
- Combined Prediction Score: 0.8870574890289294
- Mean Citation Score: 256.08247800000004
- Max Citation Score: 302.74258
- Similarity Product: 212.85436393930672

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test