PATENT CLAIM ANALYSIS

Application Number: 16118655
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["341", "087000"]

Abstract:
An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer, wherein the plurality of polarization processors is configured to polarize channels with different bit-channel reliability; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern, wherein at least one permutation processor is configured to not further polarize a bit channel.

Claim (Index 20):
A method of constructing an integrated circuit, comprising:\n generating a mask layout for a set of features for a layer of the integrated circuit, wherein the mask layout includes standard cell library macros for one or more circuit features that include an apparatus comprising a plurality of polarization processors, including n inputs and n outputs, where n is an integer, wherein the plurality of polarization processors is configured to polarize channels with different bit-channel reliability, and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern, wherein at least one permutation processor is configured to not further polarize a bit channel; disregarding relative positions of the macros for compliance to layout design rules during the generation of the mask layout; checking the relative positions of the macros for compliance to layout design rules after generating the mask layout; upon detection of noncompliance with the layout design rules by any of the macros, modifying the mask layout by modifying each of the noncompliant macros to comply with the layout design rules; generating a mask according to the modified mask layout with the set of features for the layer of the integrated circuit; and manufacturing the integrated circuit layer according to the mask.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.76923
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15459962', '15467369', '14837763', '15849034', '15838559']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5037308246968938
- 35 USC 102 Novelty (BERT): 0.6078631853784164
- Combined Prediction Score: 0.514144060765046
- Mean Citation Score: 244.75773000000004
- Max Citation Score: 503.74728
- Similarity Product: 482.9917000205757

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test