PATENT CLAIM ANALYSIS

Application Number: 15896561
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "401000"]

Abstract:
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

Claim (Index 12):
The semiconductor device of  claim 8 , wherein a width of the conductive contact narrows as the conductive contact approaches the gate structure.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 88.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15410071', '15394362', '15433121', '15394003', '14996979']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918538809174668
- 35 USC 102 Novelty (BERT): 0.499374512036991
- Combined Prediction Score: 0.8766223794609002
- Mean Citation Score: 177.05320600000005
- Max Citation Score: 222.71037
- Similarity Product: 152.6360522973454

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test