PATENT CLAIM ANALYSIS

Application Number: 15903711
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["341", "118000"]

Abstract:
The present disclosure, in some embodiments, relates to an analog-to-digital converter (ADC). The ADC has a successive approximation register (SAR) configured to receive an input signal and to generate a first digital signal having a plurality of most significant bits and a residue voltage. A voltage-to-time conversion element is configured to generate a time domain representation using the residue voltage. The voltage-to-time conversion element has an amplifier with a input coupled to an output of the SAR, a zero crossing detector coupled to an output of the amplifier, and a current source selectively coupled to the output of the SAR and the input of the amplifier by way of a switching element. A time-based signal processing element is configured to convert the time domain representation to a second digital signal having a plurality of least significant bits.

Claim (Index 11):
The ADC of  claim 1 , wherein the voltage-to-time conversion element has an output coupled directly to an input of the time-based signal processing element.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 2.27273
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14959064', '15685198', '15620821', '14600702', '15099460']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6276180106023923
- 35 USC 102 Novelty (BERT): 0.5318862637015964
- Combined Prediction Score: 0.6180448359123127
- Mean Citation Score: 258.765746
- Max Citation Score: 344.98557
- Similarity Product: 271.6179109137547

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test