PATENT CLAIM ANALYSIS

Application Number: 16218149
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "773000"]

Abstract:
Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

Claim (Index 5):
A semiconductor integrated circuit device comprising:\n a core region including an internal circuit; an I/O region provided along at least a portion of a periphery of the semiconductor integrated circuit device; a core power supply interconnect provided in the core region, and supplying a power supply potential or a ground potential to the core region; a plurality of I/O cells arranged in the I/O region; a first pad row comprised of a plurality of external connection pads, which are at least partially located in the core region; a second pad row comprised of a plurality of external connection pads, each connected to an associated one of the plurality of I/O cells, and provided outwardly from the first pad row in the semiconductor integrated circuit device; and a third pad row comprised of a plurality of external connection pads, and provided between the first and second pad rows, the plurality of external connection pads of the first, second and third pad rows being connected to an outside of the semiconductor integrated circuit device, wherein the plurality of external connection pads of the first pad row include a first pad for core power supply, the first pad being connected to the core power supply interconnect, and supplied with the power supply potential or the ground potential, the plurality of I/O cells include at least one I/O cell for core power supply, the plurality of external connection pads of the second pad row include a second pad for core power supply, the second pad being supplied with the same power supply potential or ground potential as the first pad, and connected to the I/O cell for core power supply, and the second pad overlaps with the I/O cell for core power supply in a plan view, and the plurality of external connection pads of the third pad row include a third pad for core power supply, the third pad being connected to the first and second pads via an interconnect.

Metadata:
- Claim Count in Document: 47.0
- Percentile: 98.0
- Lexical Diversity: 2.45098
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15493321', '15493338', '15982766', '12268904', '12872678']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9288291444882464
- 35 USC 102 Novelty (BERT): 0.5201283510594961
- Combined Prediction Score: 0.8879590651453714
- Mean Citation Score: 289.085826
- Max Citation Score: 341.69073
- Similarity Product: 334.8187146360325

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test