PATENT CLAIM ANALYSIS

Application Number: 15923501
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185170"]

Abstract:
A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

Claim (Index 2):
The device according to  claim 1 , wherein the drive circuit applies the first potential to the gates of all of the fourth memory cell transistors when reading the value from the first memory cell transistor.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 3.04545
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13619118', '14096371', '12603099', '15868718', '14849082']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8122088123439781
- 35 USC 102 Novelty (BERT): 0.4904326526778316
- Combined Prediction Score: 0.7800311963773635
- Mean Citation Score: 206.628214
- Max Citation Score: 210.59702
- Similarity Product: 137.98938198551772

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test