PATENT CLAIM ANALYSIS

Application Number: 16050148
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "368000"]

Abstract:
In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Claim (Index 16):
The semiconductor device of  claim 14 , wherein the processed region extends from a top surface of the ILD layer 5 nm to 125 nm into the ILD layer, wherein the remaining portion of the ILD layer comprises the unprocessed region.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 95.0
- Lexical Diversity: 2.09589
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15441063', '15356439', '16050553', '15993970', '15725867']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9262380204569706
- 35 USC 102 Novelty (BERT): 0.4992489788775416
- Combined Prediction Score: 0.8835391162990276
- Mean Citation Score: 186.75862
- Max Citation Score: 204.68187
- Similarity Product: 130.9494849098629

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test