PATENT CLAIM ANALYSIS

Application Number: 16043503
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "774000"]

Abstract:
Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Claim (Index 18):
A method for constructing a package structure comprising:\n constructing an interconnect bridge wafer on a carrier substrate, wherein the interconnect bridge wafer comprises a first layer of bond pads formed on the first carrier substrate, a second layer of bond pads, and a plurality of dielectric layers and metallization layers between the first and second layers of bond pads, to provide interconnect wiring between bond pads of the second layer of bond pads and to provide interconnect wiring between bond pads of the first and second layers of bond pads; dicing the interconnect bridge wafer and the carrier substrate to form an interconnect bridge device with a portion of the carrier substrate connected thereto; direct chip attaching a first integrated circuit die and a second integrated circuit die to the second layer of bond pads of the interconnect bridge device; removing the portion of the carrier substrate connected to the interconnect bridge device to expose the first layer of bond pads of the interconnect bridge device; and direct chip attaching the first layer of bond pads of the interconnect bridge device and the first and second integrated circuit dies to a package substrate; wherein the interconnect wiring between the bond pads of the second layer of bond pads of the interconnect bridge device provides die-to-die interconnects between the first and second integrated circuit dies connected to bridge device; wherein the interconnect wiring between the bond pads of the first and second layers of bond pads provides package-to-die connections between the package substrate and the first and second integrated circuit dies, wherein the package-to-die connections comprise power connections; wherein the interconnect bridge device and the first and second integrated circuit dies are connected to a planar top-side surface of the package substrate; wherein direct chip attaching comprises forming standoff connection structures disposed between the planar top-side surface of the package substrate and the first and second integrated circuit dies, wherein the standoff connection structures provide die-to-package connections between the package substrate and the first and second integrated circuit dies, wherein the standoff connection structures are configured to offset a height of the interconnection bridge device mounted to the planar top-side surface of the package substrate; and forming an underfill layer between the planar top side surface of the package substrate and the first and second integrated circuit dies, wherein the standoff connection structures and the interconnect bridge device are encapsulated in the underfill layer.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 95.0
- Lexical Diversity: 1.52
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13280368', '12905095', '14220912', '15234425', '12370537']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9292876455345448
- 35 USC 102 Novelty (BERT): 0.5119473500649209
- Combined Prediction Score: 0.8875536159875823
- Mean Citation Score: 300.693974
- Max Citation Score: 306.84738
- Similarity Product: 231.1840188338649

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test