PATENT CLAIM ANALYSIS

Application Number: 15896091
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["257", "773000"]

Abstract:
A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

Claim (Index 12):
The semiconductor device of  claim 10 , wherein a bottom surface of the bottom portion is lower than a top surface of the conductive layer.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 88.0
- Lexical Diversity: 2.06977
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15830008', '15172161', '15706655', '15643488', '15092076']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9164609404988082
- 35 USC 102 Novelty (BERT): 0.4796972673177975
- Combined Prediction Score: 0.8727845731807072
- Mean Citation Score: 158.15595000000005
- Max Citation Score: 164.39122
- Similarity Product: 116.13420438145044

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test