PATENT CLAIM ANALYSIS

Application Number: 15746618
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["711", "157000"]

Abstract:
In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

Claim (Index 13):
A system comprising:\n a first collection of memory banks; and a plurality of processors to perform interleaved access of the first collection of memory banks, each processor of the plurality of processors to perform the interleaved access by applying an interleave transform that transforms an input memory address to an output memory address, each processor of the plurality of processors performing its interleave transform independently without using common circuitry, wherein for any given memory address of memory addresses in use by the plurality of processors, applying any of the interleave transforms selects a same memory bank of the collection of memory banks and a same address within the same memory bank.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 86.0
- Lexical Diversity: 1.84211
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10979007', '14865718', '12698719', '11719926', '15359895']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4819138927298787
- 35 USC 102 Novelty (BERT): 0.462078926872334
- Combined Prediction Score: 0.4799303961441242
- Mean Citation Score: 128.76937
- Max Citation Score: 132.21187
- Similarity Product: 96.52881301431717

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test