PATENT CLAIM ANALYSIS

Application Number: 16204909
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["398", "182000"]

Abstract:
A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Claim (Index 2):
The receiver of  claim 1  wherein the ingress signal path further comprises a plurality of different ingress path clock domains operating according to different ingress path clock signals having different clock rates, wherein the plurality of ingress path clock domains comprises:\n an ingress analog-to-digital converter clock domain including an analog-to-digital converter operating at a first sampling rate according to a first clock signal, the analog-to-digital converter to convert the analog signal vector to the digital signal vector; \n an ingress digital signal processor clock domain including an ingress digital signal processor operating at a second sampling rate according to a second clock signal, the ingress digital signal processor to demodulate the digital signal vector to generate the digital receive signal; and \n an ingress host interface clock domain including an ingress host interface operating at a third sampling rate according to a third clock signal, the ingress host interface to output the digital receive signal, wherein the first, second, and third sampling rates are different.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.44615
- Patent Class: 398.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15647765', '15148645', '14093306', '14743660', '13655302']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7545774344637163
- 35 USC 102 Novelty (BERT): 0.6026917993055886
- Combined Prediction Score: 0.7393888709479035
- Mean Citation Score: 410.025968
- Max Citation Score: 521.692
- Similarity Product: 423.6627424740792

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test