PATENT CLAIM ANALYSIS

Application Number: 15754520
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "712000"]

Abstract:
A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die disposed on the base substrate, the die including a semiconductor device, a solder bump disposed on a surface of the die, and configured to discharge heat generated in the die to an outside; and a solder ball disposed on another surface, opposite to the surface, of the die, and configured to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

Claim (Index 4):
The semiconductor package structure of  claim 3 , wherein the solder bump comprises a first portion facing the die and a second portion facing the heat dissipation plug, and\n wherein a width of the first portion is smaller than a width of the second portion.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 88.0
- Lexical Diversity: 2.29545
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15638472', '14980445', '14535643', '12370537', '13835701']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92217061910362
- 35 USC 102 Novelty (BERT): 0.4902915405775773
- Combined Prediction Score: 0.8789827112510157
- Mean Citation Score: 196.510746
- Max Citation Score: 209.85507
- Similarity Product: 150.48648788855374

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test