PATENT CLAIM ANALYSIS

Application Number: 15922932
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "678000"]

Abstract:
The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

Claim (Index 8):
The chip integration module according to  claim 1 , wherein the passive device bonding portion is formed on the passive device by means of electroplating, sputtering, or chemical vapor deposition.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 3.03922
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15482321', '13883143', '14729316', '11254659', '11765930']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9203530975603366
- 35 USC 102 Novelty (BERT): 0.4781039606682023
- Combined Prediction Score: 0.8761281838711231
- Mean Citation Score: 162.458672
- Max Citation Score: 169.3281
- Similarity Product: 122.06451939897538

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test