PATENT CLAIM ANALYSIS

Application Number: 15942132
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["365", "051000"]

Abstract:
Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

Claim (Index 8):
The integrated circuit of  claim 1 , wherein the body biasing signal comprises a digital body biasing signal provided by the one or more buffer devices.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.14286
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15490352', '15904292', '14963111', '15238551', '15789715']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7881820390941695
- 35 USC 102 Novelty (BERT): 0.4777765258338971
- Combined Prediction Score: 0.7571414877681423
- Mean Citation Score: 137.43755000000002
- Max Citation Score: 145.07747
- Similarity Product: 93.6950762557495

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test