PATENT CLAIM ANALYSIS

Application Number: 16128879
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["365", "200000"]

Abstract:
A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Claim (Index 22):
The memory device of  claim 21 , wherein the input/output circuit outputs the pass/file signal indicating the fail of the write operation when compare indicates the data read has a number of errors greater than an error correcting capability of the memory device.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15795595', '15498855', '13753165', '15398409', '12552738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8345176312391782
- 35 USC 102 Novelty (BERT): 0.5111629980770953
- Combined Prediction Score: 0.8021821679229699
- Mean Citation Score: 284.283722
- Max Citation Score: 289.2221
- Similarity Product: 174.33356932779552

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test