PATENT CLAIM ANALYSIS

Application Number: 16030584
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-01
Patent Classification: ["365", "063000"]

Abstract:
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Claim (Index 17):
A memory device comprising:\n a first access line and a second access line both extending in first direction in a first level of the memory device; a third access line and a fourth access line both extending in a second direction in a second level of the memory device; a driver region comprising a first driver coupled with the first access line and the second access line via a first interconnect and a second driver coupled with the third access line and the fourth access line via a second interconnect; and a memory controller coupled with the first driver and the second driver, the memory controller operable to:\n transmit a signal to the first level via the first interconnect; and \n transmit the signal to the second level via the second interconnect.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 95.0
- Lexical Diversity: 1.39024
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14982362', '13777811', '13651149', '14689409', '14543708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7970924323193772
- 35 USC 102 Novelty (BERT): 0.4916602963225598
- Combined Prediction Score: 0.7665492187196955
- Mean Citation Score: 222.68064
- Max Citation Score: 229.7155
- Similarity Product: 152.27812444794174

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test