PATENT CLAIM ANALYSIS

Application Number: 16392189
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["438", "275000"]

Abstract:
A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

Claim (Index 11):
A method of forming a semiconductor device, comprising:\n providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate, the first semiconductor layers having a different material composition than the second semiconductor layers and the first and second semiconductor layers being alternatingly disposed with respect to each other in a vertical direction; etching a portion of the pluralities of first and second semiconductor layers such that a sidewall of the pluralities of first and second semiconductor layers and a top surface of the substrate are exposed; depositing a dielectric material layer over the sidewall; and while the dielectric material layer is disposed on the sidewall, epitaxially growing a plurality of third semiconductor layers and a plurality of fourth semiconductor layers from the exposed top surface of the substrate, the dielectric material layer separating the plurality of third and fourth semiconductor layers from contacting the plurality of first and second semiconductor layers, the plurality of third semiconductor layers having a different material composition than the plurality of fourth semiconductor layers and the pluralities of third and fourth semiconductor layers being alternatingly disposed with respect to each other in the vertical direction, wherein a bottommost portion of the pluralities of third and fourth semiconductor layers is lower than a bottommost portion of the pluralities of first and second semiconductor layers.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 100.0
- Lexical Diversity: 2.72093
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15628345', '13996506', '12703918', '15447967', '14985203']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8520921764833894
- 35 USC 102 Novelty (BERT): 0.4775136351038911
- Combined Prediction Score: 0.8146343223454396
- Mean Citation Score: 196.086706
- Max Citation Score: 234.3729
- Similarity Product: 209.77959665445684

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test