PATENT CLAIM ANALYSIS

Application Number: 16225094
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["345", "212000"]

Abstract:
A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.

Claim (Index 5):
A shift register circuit comprising:\n a plurality of shift register basic circuits each of which outputs a high voltage and a low voltage to an output line; and a first clock signal line applying a first clock signal to the plurality of shift register basic circuits, wherein each of the shift register basic circuits comprises: a first transistor applying the high voltage to the output line when in an ON state; a second transistor applying the low voltage to the output line when in an ON state; a third transistor applying the low voltage to the output line when in an ON state in at least a part of a period until the second transistor is turned on after the first transistor is turned off; a fourth transistor applying an OFF voltage to a control electrode of the second transistor when in an ON state; and a fifth transistor applying an ON voltage to a control electrode of the second transistor when in an ON state, wherein a common ON control signal which is output from a previous stage of the shift register basic circuit is supplied to both a control electrode of the fourth transistor and a control electrode of the first transistor, wherein the fourth transistor and the first transistor are turned on by the common ON control signal, and the control electrode of the fifth transistor is electrically connected to the first clock signal line applying the ON voltage, and wherein the control electrode of the first transistor and the control electrode of the fourth transistor are electrically connected by two voltage buffer transistors which are connected in series.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 98.0
- Lexical Diversity: 3.47727
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14805134', '15361785', '16106835', '15830061', '13356700']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.71625065619844
- 35 USC 102 Novelty (BERT): 0.5358677575305132
- Combined Prediction Score: 0.6982123663316473
- Mean Citation Score: 384.496642
- Max Citation Score: 390.28928
- Similarity Product: 281.6718946416473

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test