PATENT CLAIM ANALYSIS

Application Number: 15982775
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "409000"]

Abstract:
A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring faulted on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.

Claim (Index 12):
A semiconductor device comprising:\n a substrate; a first transistor which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate; a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view; a first wiring formed on the first guard ring and electrically connected to the first guard ring; a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region; a second transistor, which includes a third impurity region of the second conductivity type formed in the substrate, and which includes a fourth impurity region of the second conductivity type formed in the substrate; a second guard ring of the first conductivity type formed in the substrate, the second guard ring surrounding the second transistor in a plan view; a second wiring formed on the second guard ring and electrically connected to the second guard ring; and a power supply wiring formed on the second wiring, the power supply wiring being electrically connected to the second wiring and the third impurity region, wherein the first transistor includes a first part and a second part, the first part of the first transistor is separated with a first distance from the first guard ring in a plan view, the second part of the first transistor is separated with a second distance from the first guard ring in a plan view, the second distance is shorter than the first distance, the first part is separated from the ground wiring in a plan view, the second part is overlapped with the ground wiring in a plan view, the second transistor includes a fourth part and a fifth part, the fourth part of the second transistor is separated with a fourth distance from the second guard ring in a plan view, the fifth part of the second transistor is separated with a fifth distance from the second guard ring in a plan view, the fifth distance is shorter than the fourth distance, the fourth part is separated from the power supply wiring in a plan view, and the fifth part is overlapped with the power supply wiring in a plan view.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 93.0
- Lexical Diversity: 3.08
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15972949', '15921643', '13940952', '13557923', '15729040']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9000979732344655
- 35 USC 102 Novelty (BERT): 0.5465551422615228
- Combined Prediction Score: 0.8647436901371712
- Mean Citation Score: 258.651806
- Max Citation Score: 388.042
- Similarity Product: 318.3905951688289

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test