PATENT CLAIM ANALYSIS

Application Number: 16203943
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-06
Patent Classification: ["375", "262000"]

Abstract:
Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively, Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.

Claim (Index 16):
A radio-frequency integrated chip configured to transmit a carrier aggregated signal, the radio-frequency integrated chip comprising:\n a first carrier transmitter configured to receive a first digital, carrier signal and generate therefrom a first transmitting signal, the first carrier transmitter comprising a first digital mixer configured to translate frequencies of the first digital carrier signal in a digital domain, and a first analog mixer configured to translate frequencies of a first analog Garner signal, derived from the first digital carrier signal, in an analog domain; a second carder transmitter configured to receive a second digital earner signal and generate therefrom a second transmitting signal, the second garner transmitter comprising a second digital mixer configured to translate, frequencies of the second digital carrier signal in the digital domain, and a second analog mixer configured to translate frequencies of a second analog carrier signal, derived from the second digital earner signal, in the analog domain; and a phase-locked loop (PLL) configured to output a first frequency signal having a first frequency to the first carrier transmitter and the second carrier transmitter, wherein the first analog mixer up-converts the frequencies of the first analog carrier signal using a second frequency signal generated by dividing the first frequency signal, and the, second analog mixer up-converts the frequencies of the second analog carrier signal using a third frequency signal generated by dividing the first frequency signal.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.63793
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12336178', '13238249', '11208430', '13635841', '14421886']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.443678784975135
- 35 USC 102 Novelty (BERT): 0.4886499675594729
- Combined Prediction Score: 0.4481759032335688
- Mean Citation Score: 213.185844
- Max Citation Score: 223.39282000000003
- Similarity Product: 178.06934785997748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test