PATENT CLAIM ANALYSIS

Application Number: 16368485
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["345", "213000"]

Abstract:
A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Claim (Index 7):
The semiconductor device according to  claim 2 , wherein:\n the amplification accelerator circuit further includes\n third and fourth output nodes for outputting currents, \n a second conductivity-type third current control transistor connected between the third output node and the third power supply terminal, and \n a first conductivity-type fourth current control transistor connected between the fourth output node and the fourth power supply terminal; \n the comparator circuit converts a first current that is a composite of currents corresponding to the voltages of the first to Nth input signals and a second current corresponding to the voltage of the output signal into voltages with respect to the voltage of the fourth power supply terminal, and outputs signals of the obtained voltages from the first output terminal and a fourth output terminal, and converts the first and second currents into voltages with respect to the voltage of the third power supply terminal and outputs signals of the obtained voltages from the second output terminal and a third output terminal; the first to fourth output terminals are connected to the control terminals of the first to fourth current control transistors, respectively; when the weighted average voltage of the first to Nth input signals is higher than the voltage of the output signal, the first and third current control transistors are activated in accordance with the signals outputted from the first and third output terminals, to add a current sent out of the first current control transistor to a current flowing through the current output portion of the second current mirror through the first output node and to add a current sent out of the third current control transistor to a current flowing through the current input portion of the second current mirror through the third output node, while the second and fourth current control transistors are inactivated in accordance with the signals outputted from the second and fourth output terminals to cut off both of current outputs from the second and fourth output nodes; when the weighted average voltage of the first to Nth input signals is lower than the voltage of the output signal, the second and fourth current control transistors are activated in accordance with the signals outputted from the second and fourth output terminals to add a current sent out of the second current control transistor to a current flowing through the current output portion of the first current mirror through the second output node and to add a current sent out of the fourth current control transistor to a current flowing through the current input portion of the first current mirror through the fourth output node, while the first and third current control transistors are inactivated in accordance with the signals outputted from the first and third output terminals to cut off both of current outputs from the first and third output nodes; and when the weighted average voltage of the first to Nth input signals is equal to the voltage of the output signal, the first to fourth current control transistors are inactivated in accordance with the signals outputted from the first to fourth output terminals, respectively, to cut off current outputs from the first to fourth output nodes.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 99.0
- Lexical Diversity: 1.85714
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15442107', '13155023', '13029888', '15818628', '16243249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6897966983898217
- 35 USC 102 Novelty (BERT): 0.6119710689539158
- Combined Prediction Score: 0.6820141354462311
- Mean Citation Score: 296.590204
- Max Citation Score: 540.95166
- Similarity Product: 513.6927484118736

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test