PATENT CLAIM ANALYSIS

Application Number: 15862554
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["714", "731000"]

Abstract:
A BIST circuit is provided with modes of operation in which the BIST procedure for a circuit-under-test occurs at a system clock rate for the circuit-under-test that is greater than a test clock rate for the BIST circuit.

Claim (Index 19):
The integrated circuit of  claim 18 , wherein the means is further configured to drive the BIST controller into a third mode of operation in which failure information from the first mode of operation is shifted out of the BIST controller responsive to the reference clock signal and to drive the BIST controller into a fourth mode of operation in which failure information from the second mode of operation is shifted out of the BIST controller responsive to the BIST clock signal.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 86.0
- Lexical Diversity: 1.5
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12160211', '11265488', '10301127', '10780878', '10861247']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.306884314653956
- 35 USC 102 Novelty (BERT): 0.4914322372648421
- Combined Prediction Score: 0.3253391069150446
- Mean Citation Score: 168.169332
- Max Citation Score: 170.32802
- Similarity Product: 103.2852688578868

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test