PATENT CLAIM ANALYSIS

Application Number: 15884725
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["257", "295000"]

Abstract:
A memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.

Claim (Index 19):
A monolithic three-dimensional memory array comprising:\n a first memory level disposed above a substrate, the first memory level comprising:\n a plurality of first bit lines disposed in parallel along a first axis; \n a plurality of first source lines disposed in parallel along the first axis and above the plurality of first bit lines; \n a plurality of first word lines disposed in parallel substantially perpendicular to the first axis; and \n a plurality of first memory elements, each first memory element comprising a first vertical ferroelectric transistor disposed between a corresponding one of the first bit lines and a corresponding one of the first source lines, and each first memory element coupled to a corresponding one of the first word lines, \n wherein each first vertical ferroelectric transistor comprises two separate and distinct first gate electrodes, and each first ferroelectric vertical transistor comprises a long axis in a first direction, and the first gate electrodes each comprise a long axis in a second direction substantially perpendicular to the first direction; and \n a second memory level disposed above the first memory level, the second memory level comprising:\n a plurality of second bit lines disposed in parallel along the first axis and above the plurality of first source lines; \n a plurality of second word lines disposed in parallel substantially perpendicular to the first axis; and \n a plurality of second memory elements, each second memory element comprising a second vertical ferroelectric transistor disposed between a corresponding one of the second bit lines and a corresponding one of the first source lines, and each second memory element coupled to a corresponding one of the second word lines \n wherein each second vertical ferroelectric transistor comprises two separate and distinct gate electrodes, and each second ferroelectric vertical transistor comprises a long axis in the first direction, and the first gate electrodes each comprise a long axis in the second direction.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 86.0
- Lexical Diversity: 1.25
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14075010', '13897037', '10453441', '14542213', '12987302']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912698866508229
- 35 USC 102 Novelty (BERT): 0.4687284499934244
- Combined Prediction Score: 0.8683018248567484
- Mean Citation Score: 158.940444
- Max Citation Score: 172.31046
- Similarity Product: 134.24359783312082

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test