PATENT CLAIM ANALYSIS

Application Number: 15925762
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "189050"]

Abstract:
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Claim (Index 33):
A semiconductor device according to  claim 32 ,\n wherein the first transistor of the logic circuit is comprised of a fin type field-effect transistor, wherein the gate electrode of the first transistor is comprised of a first gate wiring, wherein the first gate wiring is formed on a first projection semiconductor layer, wherein the first projection semiconductor layer extends along a first direction, and the first gate wiring extends along a second direction perpendicular to the first direction, wherein the second transistor of the first data buffer is comprised of a fin type field-effect transistor, wherein the drain electrode of the second transistor is comprised of a first local wiring, wherein the first local wiring is formed on a second projection semiconductor layer, wherein the second projection semiconductor layer extends along the first direction, and the first local wiring extends along the second direction,

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 1.53333
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15211298', '15607599', '15841950', '14944262', '11320751']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7836644914123952
- 35 USC 102 Novelty (BERT): 0.4966072724997459
- Combined Prediction Score: 0.7549587695211304
- Mean Citation Score: 213.51475
- Max Citation Score: 289.29242
- Similarity Product: 236.2210750557876

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test