PATENT CLAIM ANALYSIS

Application Number: 15745396
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["711", "154000"]

Abstract:
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

Claim (Index 10):
A memory system comprising:\n a memory controller; a motherboard having memory-module slots, data-link groups extending from the memory controller to the memory-module slots, and control-link groups extending from the memory controller to the memory-module slots; and a memory module installed in one of the memory-module slots, the memory module having:\n a module connector, including module data connections and module control connections, connected to ones of the data link groups; \n an address buffer coupled to the control-link groups; \n first memory components coupled to the address buffer via a first memory-component control interface; \n second memory components coupled to the address buffer via a second memory-component control interface; and \n data buffers each coupled between ones of the module data connections at least two of the memory components, including one of the first memory components and one of the second memory components, each data buffer supporting:\n a wide-data mode to steer parallel data on the ones of the module data connections to both the one of the first memory components and the one of the second memory components; and \n a narrow-data mode to steer parallel data on the ones of the module data connections to only one of the first memory components and the second memory components.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 86.0
- Lexical Diversity: 2.01852
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15262741', '15610001', '15260880', '15522182', '15552569']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5291775464902375
- 35 USC 102 Novelty (BERT): 0.4788129551488994
- Combined Prediction Score: 0.5241410873561037
- Mean Citation Score: 223.718738
- Max Citation Score: 243.826
- Similarity Product: 214.47236968410016

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test