PATENT CLAIM ANALYSIS

Application Number: 15777535
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "004000"]

Abstract:
A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfO x ), tantalum oxide (TaO x ), or titanium dioxide (TiO x ), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

Claim (Index 13):
The integrated circuit of  claim 1 , wherein the memory device is configured as cross-point memory.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 93.0
- Lexical Diversity: 2.01124
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12110644', '12272871', '11761043', '14752935', '13997392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9138010788170544
- 35 USC 102 Novelty (BERT): 0.4546207371543759
- Combined Prediction Score: 0.8678830446507866
- Mean Citation Score: 132.01034999999996
- Max Citation Score: 135.00377
- Similarity Product: 108.20320718731104

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test