PATENT CLAIM ANALYSIS

Application Number: 16261810
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-08
Patent Classification: ["327", "109000"]

Abstract:
A driver circuit (DRV 1 ) includes a pull-up circuit (PU 1 ) and a pull-down circuit (PD 1 ) that share an output node (external terminal (T 3 )). A signal (DI 1  (DI 2 )) input to the pull-up circuit (PU 1 ) and a signal (DI 3 ) input to the pull-down circuit (PD 1 ) are selected in a complementary manner, and the output node outputs an output signal in which rising time and falling time of the signals (DI 1  (DI 2 ) and DI 3 ) are adjusted in accordance with on-off operation of the signals. The rising time is adjusted by transistors (M 1  and M 2 ) and a resistor (R 1 ), while the falling time is adjusted by transistors (M 3 , M 4  and M 5 ) and a resistor (R 2 ).

Claim (Index 12):
The driver circuit according to  claim 2 , wherein\n the pull-up circuit or the pull-down circuit includes bipolar type first transistor and second transistor having main conductive paths connected in parallel, and the first response is made by the first transistor, while the second response is made by the second transistor.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 99.0
- Lexical Diversity: 2.87931
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11517629', '10895568', '10631394', '11207370', '11007602']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7517142680650603
- 35 USC 102 Novelty (BERT): 0.4807617901122668
- Combined Prediction Score: 0.7246190202697809
- Mean Citation Score: 177.736132
- Max Citation Score: 184.40057
- Similarity Product: 138.32967489818392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test