PATENT CLAIM ANALYSIS

Application Number: 16018199
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-05
Patent Classification: ["257", "324000"]

Abstract:
A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

Claim (Index 11):
The device of  claim 7 , wherein the second gate insulation regions of each of the electrode structures have different lengths from each other in the first direction.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 94.0
- Lexical Diversity: 2.34426
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15403779', '16019119', '14878453', '15726002', '15348009']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9332888188787648
- 35 USC 102 Novelty (BERT): 0.5095446538212389
- Combined Prediction Score: 0.8909144023730122
- Mean Citation Score: 275.839736
- Max Citation Score: 289.28055
- Similarity Product: 217.11397388815288

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test