PATENT CLAIM ANALYSIS

Application Number: 15989135
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["327", "319000"]

Abstract:
In examples, an apparatus comprises a pin, an input buffer coupled to the pin at an output of the input buffer, a voltage divider circuit coupled to the input buffer at an input of the input buffer, a first current mirror coupled to the input buffer, and a second current mirror coupled to the input buffer. The apparatus also comprises a first output buffer coupled between the input buffer and the first current mirror, and a second output buffer coupled between the input buffer and the second current mirror.

Claim (Index 17):
The apparatus of  claim 10 , wherein gates of transistors in the input buffer couple to gates of transistors in the multiple level shifters.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 3.46429
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11582206', '12980161', '12836454', '10922135', '13553329']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7222427952017382
- 35 USC 102 Novelty (BERT): 0.4865275035750375
- Combined Prediction Score: 0.698671266039068
- Mean Citation Score: 193.605904
- Max Citation Score: 199.2246
- Similarity Product: 137.93316965056658

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test