PATENT CLAIM ANALYSIS

Application Number: 16221027
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "076000"]

Abstract:
A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Claim (Index 9):
The method of  claim 8 , wherein an orientation of the second contact region is a mirror image of the one or more contact regions.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 98.0
- Lexical Diversity: 2.5
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15713457', '13962180', '10883522', '09943078', '15297123']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9208604824294389
- 35 USC 102 Novelty (BERT): 0.4935994576050871
- Combined Prediction Score: 0.8781343799470036
- Mean Citation Score: 170.867594
- Max Citation Score: 265.60803
- Similarity Product: 232.1824568157417

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test