PATENT CLAIM ANALYSIS

Application Number: 15974426
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "105000"]

Abstract:
A VTFET device and fabrication method is provided. The method includes: forming a first doped layer on a semiconductor substrate. Vertical nanowires are formed on the first doped layer. Dummy gate layers are formed on the first doped layer, and a first interlayer dielectric layer is formed on a top surface of the first doped layer exposed by dummy gate layers. Grooves are formed in the first interlayer dielectric layer, by removing a portion of the first interlayer dielectric layer and removing a partial thickness of the vertical nanowires. A second doped layer is formed in each groove. Openings are formed by etching the first interlayer dielectric layer between adjacent vertical nanowires, to expose the dummy gate layers. The dummy gate layers are removed through the openings to form cavities and each cavity includes the opening and a space provided by the removed dummy gate layers.

Claim (Index 17):
The device according to  claim 15 , wherein the interlayer dielectric layer covers the second doped layer.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.59016
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14722818', '14495639', '15909419', '13904341', '14266521']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.926993809923737
- 35 USC 102 Novelty (BERT): 0.4971327745183959
- Combined Prediction Score: 0.8840077063832029
- Mean Citation Score: 234.23705
- Max Citation Score: 241.38937
- Similarity Product: 176.9517410996926

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test