PATENT CLAIM ANALYSIS

Application Number: 16026209
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "369000"]

Abstract:
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

Claim (Index 11):
The semiconductor device of  claim 1 , wherein the second nitride layer includes TiN.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 95.0
- Lexical Diversity: 3.12766
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14996563', '14996575', '15397042', '15795413', '14996579']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9546407789531624
- 35 USC 102 Novelty (BERT): 0.5865654003935568
- Combined Prediction Score: 0.917833241097202
- Mean Citation Score: 512.208086
- Max Citation Score: 525.4378
- Similarity Product: 429.8438959365488

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test