PATENT CLAIM ANALYSIS

Application Number: 15872256
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "329000"]

Abstract:
A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.

Claim (Index 15):
The vertical transistor of  claim 14 , wherein the dielectric layer of the gate is a high-k dielectric layer.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 86.0
- Lexical Diversity: 2.33333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15406022', '15463314', '15405433', '15704088', '15438114']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281352545486832
- 35 USC 102 Novelty (BERT): 0.5053479328505487
- Combined Prediction Score: 0.8858565223788696
- Mean Citation Score: 248.119742
- Max Citation Score: 276.501
- Similarity Product: 210.41896880060432

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test