PATENT CLAIM ANALYSIS

Application Number: 15909378
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["341", "110000"]

Abstract:
The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

Claim (Index 14):
The ADC of  claim 13 , wherein the error correction block is configured to measure the PRBS error from the averaged code generated by the ADC, the fine gain error, the coarse gain error, the reference averaged code and a magnitude of the coarse PRBS signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 3.3125
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15485552', '13597075', '15231415', '15836039', '13232442']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5572651197603882
- 35 USC 102 Novelty (BERT): 0.5643607870236461
- Combined Prediction Score: 0.5579746864867139
- Mean Citation Score: 245.130078
- Max Citation Score: 408.87134
- Similarity Product: 365.0508983657885

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test