PATENT CLAIM ANALYSIS

Application Number: 16043558
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["438", "217000"]

Abstract:
A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.

Claim (Index 2):
The method of  claim 1 , further comprising forming separation films in the semiconductor substrate before the forming of the gate insulating film.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 95.0
- Lexical Diversity: 3.2
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15389501', '15408200', '15831897', '13075625', '11177576']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8815932084834206
- 35 USC 102 Novelty (BERT): 0.571729260619497
- Combined Prediction Score: 0.8506068136970283
- Mean Citation Score: 353.323004
- Max Citation Score: 480.69696
- Similarity Product: 394.56090998886106

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test