PATENT CLAIM ANALYSIS

Application Number: 15908215
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["257", "043000"]

Abstract:
A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

Claim (Index 9):
A semiconductor device comprising:\n a first insulating layer over a substrate; a first oxide insulating layer over the first insulating layer; an oxide semiconductor layer over the first oxide insulating layer; a second oxide insulating layer over the oxide semiconductor layer; a gate insulating layer over the second oxide insulating layer; a gate electrode layer over the gate insulating layer; and a sidewall insulating layer over the oxide semiconductor layer, wherein a bottom surface of the oxide semiconductor layer is located above a bottom surface of the gate electrode layer in a cross section in a channel width direction, wherein a top surface and a side surface of the oxide semiconductor layer each comprise a region facing the gate electrode layer, wherein the sidewall insulating layer comprises a region in contact with a side surface of the gate insulating layer, wherein the oxide semiconductor layer comprises first to third regions, wherein the first region comprises a region overlapping with the gate electrode layer, wherein the second region comprises a region which is between the first region and the third region and overlaps with the sidewall insulating layer, wherein the second region comprises a region with lower resistance than the first region, wherein the third region comprises a region with lower resistance than the second region, and wherein the second region and the third region each comprise any one of elements of cobalt, nickel, vanadium, and palladium, and any one of elements of titanium, zirconium, hafnium, and tantalum.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 4.5
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15224958', '15903097', '15408719', '15208767', '15041502']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9166624345148794
- 35 USC 102 Novelty (BERT): 0.5438625779232551
- Combined Prediction Score: 0.879382448855717
- Mean Citation Score: 349.67076000000014
- Max Citation Score: 382.98785
- Similarity Product: 359.28502640264924

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test