PATENT CLAIM ANALYSIS

Application Number: 15898671
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "343000"]

Abstract:
A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.

Claim (Index 20):
A device comprising:\n a substrate with a device region; a transistor in the device region, the transistor includes a gate disposed on the substrate, the gate includes first and second gate sidewalls, a first source/drain (S/D) region disposed adjacent to the first gate sidewall, and a second S/D region disposed adjacent to the second gate sidewall; a body well disposed in the device region, the body well encompasses the second S/D region and extends under a portion of the gate beyond the second gate sidewall; a drift well disposed in the substrate, wherein the drift well comprises\n a non-cut out region disposed under a first portion of the first S/D region, the non-cut out region extends under the gate to the body well and couples the first S/D region to the body well, the cut out region encompasses the first portion of the first S/D region completely, and \n a cut out region is disposed under a second portion of the first S/D region, the cut out region is devoid of the drift well; \n a device well encompassing the drift well and body well; and a deep trench isolation region surrounding the device region, wherein the deep trench isolation region extends from a surface of the substrate to a depth in the substrate to a depth in the substrate below the device well, wherein the deep trench isolation region is configured to serve as a vertical plate to reduce an on resistance.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.06349
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14808991', '15872939', '15137018', '15640613', '15898669']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9194438960206218
- 35 USC 102 Novelty (BERT): 0.4895289293605011
- Combined Prediction Score: 0.8764523993546097
- Mean Citation Score: 236.994976
- Max Citation Score: 244.54065
- Similarity Product: 194.5601406294108

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test