PATENT CLAIM ANALYSIS

Application Number: 16160051
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["345", "501000"]

Abstract:
A system and method to interconnect heterogeneous compute resources using graph based execution flow for image and video processing is disclosed. The system includes a mix of compute engines (SIMDs, fixed-function pipelines and hardware kernels) which work on pipelined streams of data based on programming instructions and/or configuration data. The nodes act as proxies for compute engines in graph and message based routing system to establish graph based flow control mechanism between these nodes. A message based routing mechanism to assign tasks to heterogeneous compute engines and receive their status in time-multiplexed manner thus allowing compute engines to be reused. A configuration method that allows hardware compute engines are uniquely configured based on graph node thus allows reusability and programming or selecting heterogeneous compute system for physical implementation using simple standard definition file generation method.

Claim (Index 6):
A method to interconnect heterogeneous compute resources using graph based execution flow for image and video processing, comprising the steps of:\n a. creating different types of graph based execution pipelines using a group of homogeneous node blocks that act as proxy for said heterogeneous compute engines ( 25 ); b. creating a communication scheme between said nodes to establish graph relationship in data movement; c. establishing data flow control scheme between said proxy nodes to aid pipelined processing with said compute engines ( 25 ) to work simultaneously on pipelined streams of data; d. establishing a scheme to share said compute engines ( 25 ) within same execution graph or between different graphs allowing reuse of said compute engines ( 25 ); e. working on various granularities of data by changing granularity between intermediate stages of the execution pipeline; f. establishing a scheme to share direct memory access as part of multiple graphs; g. configuring and programming direct memory access nodes ( 26 ) and said compute engines to work concurrently on run time execution; h. allowing said compute engines ( 25 ) to get instructions and data based on the context or the nodes requesting computation; and i. gathering physical implementation requirements from the application developer's design entry information.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 97.0
- Lexical Diversity: 1.70238
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14664725', '14664743', '14664736', '15450959', '15996300']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6263386023642651
- 35 USC 102 Novelty (BERT): 0.4940315442570774
- Combined Prediction Score: 0.6131078965535464
- Mean Citation Score: 184.317812
- Max Citation Score: 194.1963
- Similarity Product: 126.1979236412108

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test