PATENT CLAIM ANALYSIS

Application Number: 15923097
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "401000"]

Abstract:
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Claim (Index 2):
The method of  claim 1 , wherein the dummy gate layer comprises polysilicon.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 90.0
- Lexical Diversity: 2.4
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15237802', '14680099', '15203847', '15494586', '15918674']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9417858447836824
- 35 USC 102 Novelty (BERT): 0.5452699204937936
- Combined Prediction Score: 0.9021342523546936
- Mean Citation Score: 350.811014
- Max Citation Score: 396.12167
- Similarity Product: 390.3966912066424

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test