PATENT CLAIM ANALYSIS

Application Number: 15984779
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185180"]

Abstract:
A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Claim (Index 17):
The method of  claim 16 , wherein applying the programming voltage to the drain terminal of the first transistor and to the drain terminal of the second transistor comprises linearly changing a voltage at the drain terminal of the first transistor and the drain terminal of the second transistor from an initial voltage to the programming voltage.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.375
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15682102', '15221318', '14795742', '14724229', '15276462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8015093389256697
- 35 USC 102 Novelty (BERT): 0.5730024225096494
- Combined Prediction Score: 0.7786586472840676
- Mean Citation Score: 321.40461399999987
- Max Citation Score: 487.25003
- Similarity Product: 382.4712180544567

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test