PATENT CLAIM ANALYSIS

Application Number: 16164542
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-07
Patent Classification: ["257", "758000"]

Abstract:
Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

Claim (Index 10):
The semiconductor device of  claim 4 , wherein each of the at least three portions of the fill material comprises the same material.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 97.0
- Lexical Diversity: 3.51111
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15858072', '15624422', '16020817', '15271924', '16020637']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9233032561323758
- 35 USC 102 Novelty (BERT): 0.5376407786166509
- Combined Prediction Score: 0.8847370083808033
- Mean Citation Score: 245.12176600000004
- Max Citation Score: 380.10376
- Similarity Product: 219.110423603406

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test