PATENT CLAIM ANALYSIS

Application Number: 16006368
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-07
Patent Classification: ["257", "668000"]

Abstract:
A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Claim (Index 1):
A semiconductor package comprising:\n a support member having first and second surfaces opposing each other, having a cavity penetrating through the first and second surfaces, and including a wiring structure; a semiconductor chip disposed in the cavity and having an active surface having connection pads disposed thereon; a connection member including a first insulating layer disposed on the second surface of the support member, a first redistribution layer on the first insulating layer, and a plurality of first vias penetrating through the first insulating layer and connecting the wiring structure and the connection pads to the first redistribution layer; and an encapsulant encapsulating the semiconductor chip disposed in the cavity and covering the first surface of the support member, wherein the wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating disposed on the second surface of the support member and covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 94.0
- Lexical Diversity: 2.93333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15981311', '15969480', '15941334', '15962867', '15970307']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9306400581780174
- 35 USC 102 Novelty (BERT): 0.5113290129995769
- Combined Prediction Score: 0.8887089536601734
- Mean Citation Score: 315.30936600000007
- Max Citation Score: 320.13873
- Similarity Product: 279.1758877758515

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test