PATENT CLAIM ANALYSIS

Application Number: 16014110
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "692000"]

Abstract:
A wiring board, includes a core substrate that includes first pads for mounting a semiconductor chip, second pads provided at the periphery of the first pads, and a solder resist layer that selectively exposes the first pads and the second pads; a first insulation layer, formed on the solder resist layer, including an opening to be formed in a frame shape such that to expose the first pads and cover the second pads; and external connection terminals penetrating the first insulation layer to be electrically connected to the second pads, respectively, and partially exposed from the first insulation layer, wherein the core substrate includes a second insulation layer, wherein the first pads, the second pads and the solder resist layer are directly formed on the second insulation layer, and wherein a rim of an inner wall surface of the opening at the core substrate side contacts the solder resist layer.

Claim (Index 1):
A wiring board, comprising:\n a core substrate that includes, at one side of the core substrate, a plurality of first pads for mounting a semiconductor chip, a plurality of second pads provided at the periphery of the first pads, and a solder resist layer that selectively exposes the first pads and the second pads; a first insulation layer, formed on an upper surface of the solder resist layer, including an opening to be formed in a frame shape such that to expose the first pads and cover the second pads; and a plurality of external connection terminals penetrating the first insulation layer to be electrically connected to the second pads exposed from the solder resist layer, respectively, and partially exposed from an upper surface of the first insulation layer, wherein the core substrate includes a second insulation layer, wherein the first pads, the second pads and the solder resist layer are directly formed on one surface of the second insulation layer, and wherein a rim of an inner wall surface of the opening at the core substrate side contacts the upper surface of the solder resist layer.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 94.0
- Lexical Diversity: 2.64516
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12562956', '13429764', '14680371', '13754185', '14799887']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9238697486067332
- 35 USC 102 Novelty (BERT): 0.4869361011815844
- Combined Prediction Score: 0.8801763838642184
- Mean Citation Score: 264.450246
- Max Citation Score: 270.25375
- Similarity Product: 252.811951854378

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test