PATENT CLAIM ANALYSIS

Application Number: 16201315
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-10
Patent Classification: ["327", "158000"]

Abstract:
A semiconductor apparatus may include an internal clock generation circuit, a receiver, and a sampling circuit. The internal clock generation circuit may generate a receiving clock signal and a sampling clock signal based on a reference clock signal, the sampling clock signal having a phase different from the receiving clock signal. The receiver may receive an input signal in synchronization with the receiving clock signal and to generate an amplified signal. The sampling circuit may sample the amplified signal in synchronization with the sampling clock signal and to generate an output signal.

Claim (Index 12):
The semiconductor apparatus according to  claim 9 , wherein the internal clock generation circuit comprises:\n a receiving clock generator configured to generate a delayed clock signal by delaying the reference clock signal by a predetermined time and a first time, and generate the receiving clock signal by delaying the delayed clock signal by a second time; and a sampling clock generator configured to generate the sampling clock signal by delaying the delayed clock signal by the second time and a third time.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 98.0
- Lexical Diversity: 2.67568
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14244010', '16142960', '15432731', '16012453', '14268492']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7811702758351058
- 35 USC 102 Novelty (BERT): 0.4654662297218679
- Combined Prediction Score: 0.749599871223782
- Mean Citation Score: 177.71243599999997
- Max Citation Score: 187.74615
- Similarity Product: 153.50172446299194

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test