PATENT CLAIM ANALYSIS

Application Number: 16166112
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "458000"]

Abstract:
A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a plurality of metal layers; a thermal isolation layer overlaying the first level; a second level of memory circuits, the memory circuits include an array of memory cells, where the second level is overlaying the thermal isolation layer; and connections from the logic circuits to the memory array including vias, where the vias have a diameter of less than 400 nm, and where a majority of the thermal isolation layer includes a material with a less than 0.5 W/m·K thermal conductivity.

Claim (Index 19):
The device according to  claim 15 ,\n wherein said memory cells comprise second transistors, and wherein said second transistors are aligned to said first transistors with a less than 200 nm misalignment.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 97.0
- Lexical Diversity: 2.2549
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16004404', '16024911', '15904377', '16115519', '16113860']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8537185699003448
- 35 USC 102 Novelty (BERT): 0.5148765403482548
- Combined Prediction Score: 0.8198343669451358
- Mean Citation Score: 243.560566
- Max Citation Score: 253.44907
- Similarity Product: 162.9099855213654

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test