PATENT CLAIM ANALYSIS

Application Number: 15902949
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "686000"]

Abstract:
A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.

Claim (Index 6):
The chip package of  claim 5 , wherein the inter-die portion of the signal transmission line has a non-linear path defined across an inter-die region defined between first and second dies.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 88.0
- Lexical Diversity: 1.53191
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12116079', '15891481', '15644849', '11830377', '11712152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.927002415639731
- 35 USC 102 Novelty (BERT): 0.499040778910881
- Combined Prediction Score: 0.884206251966846
- Mean Citation Score: 208.744728
- Max Citation Score: 214.97595
- Similarity Product: 139.98812221850753

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test