PATENT CLAIM ANALYSIS

Application Number: 16165549
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "156000"]

Abstract:
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

Claim (Index 25):
A memory system, comprising:\n a memory array comprising one or more memory bit cell rows each comprising a plurality of memory bit cells, each memory bit cell of the plurality of memory bit cells in the one or more memory bit cell rows configured to provide data in response to a read operation; one or more wordlines each associated with a respective memory bit cell row among the one or more memory bit cell rows; each memory bit cell of the plurality of memory bit cells in each memory bit cell row among the one or more memory bit cell rows comprising one or more P-type Field-Effect Transistor (PFET) access transistors each comprising a gate configured to be activated by a wordline among the one or more wordlines associated with the memory bit cell row containing the memory bit cell in response to the read operation; one or more read-assist circuits each associated with one or more memory bit cells of the plurality of memory bit cells in the one or more memory bit cell rows, the one or more read-assist circuits configured to boost a voltage in the one or more memory bit cells in response to the read operation; and a plurality of bitline drivers each configured to activate a plurality of bitlines each associated with a respective memory bit cell column among one or more memory bit cell columns; wherein the one or more read-assist circuits comprise a plurality of bitline positive boost circuits coupled to the plurality of bitlines; and\n the plurality of bitline positive boost circuits is configured to positively boost a voltage on the plurality of bitlines in response to the read operation.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 1.77778
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15645355', '14862712', '14862555', '14862483', '14862636']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8777241453284816
- 35 USC 102 Novelty (BERT): 0.6496311561742714
- Combined Prediction Score: 0.8549148464130607
- Mean Citation Score: 669.7922259999998
- Max Citation Score: 725.4755
- Similarity Product: 592.0149365151226

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test