PATENT CLAIM ANALYSIS

Application Number: 15862241
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["710", "106000"]

Abstract:
A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Claim (Index 10):
The memory device of  claim 6 , wherein the column command signal is activated with the read command signal and the write command signal.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 3.01786
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15395598', '14926834', '14303230', '15149989', '14696030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7317349493146114
- 35 USC 102 Novelty (BERT): 0.5607146620870592
- Combined Prediction Score: 0.7146329205918562
- Mean Citation Score: 327.047572
- Max Citation Score: 470.20425
- Similarity Product: 353.82211080998184

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test