PATENT CLAIM ANALYSIS

Application Number: 15886045
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["365", "185130"]

Abstract:
A semiconductor memory device may include a data-determining circuit and a memory cell array. The data-determining circuit may receive data to determine a majority level of data among the received data. The data-determining circuit may provide data bus inversion information to invert data of an address including a minority level of data. The memory cell array may store the data bus inversion information through a redundant bit line.

Claim (Index 13):
The semiconductor system of  claim 12 , wherein the semiconductor memory device further comprises a global input and output (GIO) data-driving circuit configured to receive the data, and the GIO data-driving circuit comprises a data-processing circuit configured to coincide the minority level of the data with the majority level of the data in accordance with the data bus inversion information based on the write command and to restore the minority level of the data in accordance with the data bus inversion information based on the read command.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 88.0
- Lexical Diversity: 1.89474
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14176218', '14282379', '12327024', '12846053', '15490614']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8133814564116885
- 35 USC 102 Novelty (BERT): 0.4934838179084208
- Combined Prediction Score: 0.7813916925613618
- Mean Citation Score: 218.458644
- Max Citation Score: 258.84576
- Similarity Product: 194.21248032291408

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test