PATENT CLAIM ANALYSIS

Application Number: 15891028
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["712", "225000"]

Abstract:
A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.

Claim (Index 8):
The processor of  claim 1 , wherein the execution unit, in response to the decode of the instruction, is to store times indicative of when said at least all initial writes are performed to a time log.

Metadata:
- Claim Count in Document: 34.0
- Percentile: 88.0
- Lexical Diversity: 2.01786
- Patent Class: 712.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14628954', '15283259', '15396177', '13725907', '14969249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6066400295069112
- 35 USC 102 Novelty (BERT): 0.4948838440973767
- Combined Prediction Score: 0.5954644109659578
- Mean Citation Score: 216.82778
- Max Citation Score: 241.59464
- Similarity Product: 173.87266205922126

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test