PATENT CLAIM ANALYSIS

Application Number: 16215539
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["361", "763000"]

Abstract:
A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

Claim (Index 17):
A time delay filter comprising:\n a substrate comprising a first isolative layer, the first isolative layer comprising a first surface and a second surface, the second surface substantially parallel to the first surface; a resonator, comprising a capacitive element coupled to an inductive element, the inductive element comprising:\n a first conductive region coupled to the first surface of the first isolative layer, \n a second conductive region coupled to the second surface of the first isolative layer, \n a first via that is electrically coupled to and extends between the first and second conductive region; \n a second via that is electrically coupled to and extends between the first conductive region and a first portion of the capacitive element; and \n a third via that is electrically coupled to and extends between the second conductive region and a second portion of the capacitive element; wherein the first conductive region, the first via, the second conductive region, the second via, the capacitive element, and the third via form a loop; \n a first coupling point, electrically coupled to the first conductive region of the resonator; and a second coupling point, electrically coupled to the second conductive region of the resonator; wherein the capacitive element comprises:\n first and second interdigitated capacitor electrodes, both parallel to and intersecting a third surface; wherein the first electrode defines a first capacitor region within the third surface and the second electrode defines a second capacitor region within the third surface; third and fourth interdigitated capacitor electrodes, both parallel to and intersecting a fourth surface, the fourth surface parallel to and separated by a non-zero distance from the third surface; wherein the third electrode defines a third capacitor region within the fourth surface and the fourth electrode defines a fourth capacitor region within the fourth surface; a first set of capacitor coupling vias that electrically couples the first electrode to the third electrode; and a second set of capacitor coupling vias that electrically couples the second electrode to the fourth electrode.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 98.0
- Lexical Diversity: 2.33333
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15497167', '15652643', '15382335', '15496948', '15976287']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8460135087203485
- 35 USC 102 Novelty (BERT): 0.5251959223664265
- Combined Prediction Score: 0.8139317500849563
- Mean Citation Score: 235.83581
- Max Citation Score: 362.48898
- Similarity Product: 355.8117886324848

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test