PATENT CLAIM ANALYSIS

Application Number: 15912449
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "203000"]

Abstract:
An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.

Claim (Index 10):
The method of  claim 8 , wherein maintaining the particular voltage level on the true bit line comprises sourcing a maintenance current, via the second device, to the true bit line that is substantially equal to an amount of leakage current flowing from memory cells coupled to the true bit line.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.52174
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11218009', '11775546', '13570305', '15645355', '14801837']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8079020694958291
- 35 USC 102 Novelty (BERT): 0.4805582062819026
- Combined Prediction Score: 0.7751676831744364
- Mean Citation Score: 192.672104
- Max Citation Score: 195.73906
- Similarity Product: 137.65608223610758

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test