PATENT CLAIM ANALYSIS

Application Number: 15965456
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["365", "096000"]

Abstract:
A memory device includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; a plurality of row circuits respectively arranged along the plurality of rows; a plurality of column circuits respectively arranged along the plurality of columns; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits.

Claim (Index 19):
The device of  claim 15 , wherein when the number of the plurality of rows is smaller than the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a last row of the plurality of rows, and from a first column to a first intermediate column of the plurality of columns, wherein the first intermediate column is associated with a first column number equal to the number of the plurality of rows.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 91.0
- Lexical Diversity: 2.4359
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11240160', '11062496', '14958149', '11229771', '12696766']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7626436354491114
- 35 USC 102 Novelty (BERT): 0.4927171223927325
- Combined Prediction Score: 0.7356509841434735
- Mean Citation Score: 153.42507799999996
- Max Citation Score: 156.22008
- Similarity Product: 95.54613486243724

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test