PATENT CLAIM ANALYSIS

Application Number: 15940811
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["710", "307000"]

Abstract:
Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

Claim (Index 32):
The memory device of  claim 28 , wherein a first section and a second section of an array tile are located in between the first set of lines of the global data bus and the second set of lines of the global data bus, and wherein the local data bus is located in between the first section and the second section of the array tile.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.54054
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14975298', '14975293', '14975305', '10792425', '11153338']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6661668982415816
- 35 USC 102 Novelty (BERT): 0.4987128572013773
- Combined Prediction Score: 0.6494214941375612
- Mean Citation Score: 198.717605
- Max Citation Score: 259.3285
- Similarity Product: 193.12427176857

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test