PATENT CLAIM ANALYSIS

Application Number: 16162205
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["363", "021020"]

Abstract:
Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.

Claim (Index 8):
The method of  claim 6 , wherein the filtering the sampled input voltage in the digital filter comprises filtering the sampled input voltage in a low-pass digital filer.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 97.0
- Lexical Diversity: 2.41791
- Patent Class: 363.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15712024', '15713415', '10689863', '10626149', '10626433']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8292742230703011
- 35 USC 102 Novelty (BERT): 0.5446715875951097
- Combined Prediction Score: 0.8008139595227819
- Mean Citation Score: 276.439144
- Max Citation Score: 429.77347
- Similarity Product: 270.23552728025084

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test