PATENT CLAIM ANALYSIS

Application Number: 16204409
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["365", "104000"]

Abstract:
Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

Claim (Index 34):
The memory cell of  claim 33 , wherein both of the p-channel transistors are over both of the n-channel transistors.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 2.71698
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15796611', '10801334', '15797462', '13746395', '16043653']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8023491023707962
- 35 USC 102 Novelty (BERT): 0.5618730995189816
- Combined Prediction Score: 0.7783015020856147
- Mean Citation Score: 313.302702
- Max Citation Score: 485.1104
- Similarity Product: 321.77947159233094

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test