PATENT CLAIM ANALYSIS

Application Number: 15923174
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["711", "129000"]

Abstract:
In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

Claim (Index 20):
The system of  claim 18 , wherein the cache controller comprises a set of hit counters associated with corresponding positions within a least recently used stack of the shared cache memory, and to be updated in response to hits within the shared cache memory, and wherein the control circuit is to dynamically update a size of the virtual write buffer based on hit histogram information obtained from the set of hit counters.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 90.0
- Lexical Diversity: 1.81633
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13942291', '15701795', '14671411', '14137359', '15476816']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.53324144705534
- 35 USC 102 Novelty (BERT): 0.4884554750058602
- Combined Prediction Score: 0.5287628498503921
- Mean Citation Score: 178.78918000000004
- Max Citation Score: 185.46117
- Similarity Product: 123.87582121404472

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test