PATENT CLAIM ANALYSIS

Application Number: 15865892
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "185170"]

Abstract:
A method of operating a three-dimensional memory device includes applying a target string bias voltage to a selected drain select gate electrode which partially surrounds a row of memory stack structures that directly contact a drain select isolation structure, and applying a neighboring string bias voltage that has a greater magnitude than the target string bias voltage to an unselected drain select gate electrode that contacts the drain select level isolation structure.

Claim (Index 1):
A method of operating a three-dimensional memory device, comprising a stack of alternating insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the stack in a vertical direction perpendicular to the layers and the substrate, wherein:\n each of the memory stack structures comprises a memory film that surrounds a vertical semiconductor channel; the electrically conductive layers comprise drain select gate electrode layers located over word line electrically conductive layers; the memory stack structures are arranged in multiple groups that are spaced apart from each other in a horizontal direction by drain select level isolation structures that each extend in the vertical direction through the drain select gate electrode layers dividing each drain select gate electrode layer into horizontal drain select gate electrode layer sections; within each group of memory stack structures, at least one row of memory stack structures is arranged, each of the memory stack structures in the at least one row is only partially surrounded by a respective drain select gate electrode layer section due to each of the at least one row of memory stack structures in the at least one row also directly contacting a respective one of the drain select level isolation structures; applying a target string bias voltage to a selected drain select gate electrode layer section, which partially surrounds a first row of memory stack structures in a respective group of memory stack structures, wherein each of the memory stack structures of the first row is in direct contact with a first one of the drain select isolation structures; and applying a neighboring string bias voltage, which has a greater magnitude than the target string bias voltage, to a first unselected drain select gate electrode layer section that neighbors the selected drain gate electrode layer section and contacts the first one of the drain select level isolation structures.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 86.0
- Lexical Diversity: 1.68182
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15850073', '15818146', '15818061', '15628495', '15704286']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7945783891779497
- 35 USC 102 Novelty (BERT): 0.5202637236914253
- Combined Prediction Score: 0.7671469226292973
- Mean Citation Score: 322.257094
- Max Citation Score: 343.7213700000001
- Similarity Product: 301.34728044352244

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test