PATENT CLAIM ANALYSIS

Application Number: 15866423
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["257", "020000"]

Abstract:
A transistor including a buffer layer, a channel layer, a barrier layer, a superlattice structure, a gate, a source and a drain is provided. The buffer layer, the channel layer, the barrier layer, the superlattice structure and the gate are sequentially disposed on a substrate. The source and drain are disposed on the barrier layer and respectively at two sides of the superlattice structure, or on the channel layer and respectively at two sides of the barrier layer. The superlattice structure includes at least one first metal nitride layer and at least one second metal nitride layer stacked to each other. The average lattice constant of the superlattice structure is greater than that of GaN. The metal of each of the first and second metal nitride layers is at least one selected from the group consisting of Al, Ga and In. The first and second metal nitride layers are different.

Claim (Index 17):
The transistor according to  claim 12 , wherein each of the third metal nitride layers has the same thickness.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 86.0
- Lexical Diversity: 2.87931
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14872661', '15687369', '14976814', '11358241', '15699251']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9253868822083126
- 35 USC 102 Novelty (BERT): 0.5094482039303109
- Combined Prediction Score: 0.8837930143805124
- Mean Citation Score: 224.56396400000003
- Max Citation Score: 239.2966
- Similarity Product: 144.24534031105043

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test