PATENT CLAIM ANALYSIS

Application Number: 15960686
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["375", "287000"]

Abstract:
A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.

Claim (Index 1):
An electronic circuit, comprising:\n a data recovery circuit to recover data from a received signal based on at least a first clock signal and a second clock signal which provide different timings; and a clock recovery circuit to adjust skew between the first clock signal and the second clock signal when a signal level of the recovered data is changed from a level lower than a first reference level to a level higher than the first reference level, or from the level higher than the first reference level to the level lower than the first reference level, at a time point between a first timing of the first clock signal and a second timing of the second clock signal following the first timing, wherein: the clock recovery circuit is to adjust the skew between the first clock signal and the second clock signal based on a result of a comparison between a first signal level of the recovered data at the first timing and at least one of a second reference level and a third reference level and a comparison between a second signal level of the recovered data at the second timing and at least one of the second reference level and the third reference level, the second reference level higher than the first reference level and the third reference level lower than the first reference level, the clock recovery circuit is to adjust the skew based on a first sign of an error of the first signal level with respect to one of the second and third reference levels, the first sign being opposite to a second sign of an error of the second signal level with respect to another one of the second and third reference levels.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 3.40909
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15392244', '11197118', '13055982', '12289073', '09978726']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.479487989593936
- 35 USC 102 Novelty (BERT): 0.4791733730763112
- Combined Prediction Score: 0.4794565279421736
- Mean Citation Score: 197.809936
- Max Citation Score: 209.17325
- Similarity Product: 163.32658478826283

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test