PATENT CLAIM ANALYSIS

Application Number: 16000199
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["711", "141000"]

Abstract:
A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

Claim (Index 7):
The processing system of  claim 1 , wherein:\n the first processing unit is a central processing unit; and the second processing unit is a graphics processing unit.

Metadata:
- Claim Count in Document: 55.0
- Percentile: 94.0
- Lexical Diversity: 2.92157
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15475435', '15846392', '15825880', '15370734', '12105405']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5320037041763752
- 35 USC 102 Novelty (BERT): 0.4914825042964834
- Combined Prediction Score: 0.5279515841883861
- Mean Citation Score: 173.62784399999995
- Max Citation Score: 180.3968
- Similarity Product: 115.27838280868532

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test