PATENT CLAIM ANALYSIS

Application Number: 16105305
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["714", "755000"]

Abstract:
A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Claim (Index 1):
A memory controller, comprising:\n an input configured to:\n receive an indication related to an indicator of a likelihood that a first type of data read will be successful; and \n receive data in conjunction with the first type of data read when the indicator is determined to have a first value; and \n an error correction code (ECC) component configured to apply an error correction technique to the data consistent with the first type of data read when the indicator is determined to have the first value.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.0
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15583678', '14657878', '13001300', '14285848', '13114049']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.351664248946564
- 35 USC 102 Novelty (BERT): 0.4865897400510408
- Combined Prediction Score: 0.3651567980570118
- Mean Citation Score: 201.119252
- Max Citation Score: 283.78867
- Similarity Product: 259.9203998126894

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test