PATENT CLAIM ANALYSIS

Application Number: 15938393
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-10
Patent Classification: ["365", "189090"]

Abstract:
A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.

Claim (Index 14):
The method of  claim 11 , further comprising receiving an enable signal at another input terminal of the logic circuit, wherein the using the logic circuit to couple the bit line with the voltage node is further in response to the enable signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.21429
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13804405', '13780772', '14659642', '15434541', '14504596']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7868268423291632
- 35 USC 102 Novelty (BERT): 0.4689070103254547
- Combined Prediction Score: 0.7550348591287923
- Mean Citation Score: 185.340002
- Max Citation Score: 191.39548
- Similarity Product: 146.10030414079188

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test