PATENT CLAIM ANALYSIS

Application Number: 15927494
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "712000"]

Abstract:
A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

Claim (Index 17):
A microelectronic device comprising:\n a first integrated circuit with circuitry; a first layer over the first integrated circuit, with at least one of properties (i) and (ii) being true with regard to a thermal conductivity of the first layer in at least one lateral direction: (i) the first layer comprises a metal, and said thermal conductivity is at least as high as a thermal conductivity of a layer of such metal in at least one lateral direction; (ii) the first layer comprises carbon, and said thermal conductivity is at least as high as a thermal conductivity of a layer of such carbon in at least one lateral direction; one or more first vias each of which passes through the first layer and exposes a corresponding first region of the circuitry of the first integrated circuit; a second integrated circuit comprising circuitry and attached to the first integrated circuit, at least part of the first layer lying between the first and second integrated circuits, the circuitry of the second integrated circuit being electrically connected to each first region by a corresponding electrical connection reaching the first region through the corresponding first via; and an electrically insulating layer between the first layer and the second integrated circuit.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 2.11111
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14639942', '11464784', '15149834', '14201473', '14213890']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8898356591458846
- 35 USC 102 Novelty (BERT): 0.5092207565479479
- Combined Prediction Score: 0.8517741688860909
- Mean Citation Score: 183.54219
- Max Citation Score: 299.1315600000001
- Similarity Product: 277.140351258545

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test