PATENT CLAIM ANALYSIS

Application Number: 16020806
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2020-01
Patent Classification: ["365", "185090"]

Abstract:
An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.

Claim (Index 5):
The apparatus of  claim 1  further comprising a data path comprising a multi-purpose register, the data path is coupled between the I/O circuit and the counter circuit.

Metadata:
- Claim Count in Document: 31.0
- Percentile: 94.0
- Lexical Diversity: 2.875
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14798634', '14817212', '14958149', '13771838', '12463358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.764686572534534
- 35 USC 102 Novelty (BERT): 0.4828379480060221
- Combined Prediction Score: 0.7365017100816827
- Mean Citation Score: 129.33039399999998
- Max Citation Score: 135.34403999999998
- Similarity Product: 80.35472348106622

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test