PATENT CLAIM ANALYSIS

Application Number: 15894108
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "004000"]

Abstract:
Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.

Claim (Index 2):
The method of  claim 1 , wherein forming the recess in the portion of the trench contact further comprises:\n applying an organic planarization layer (OPL) to mask portions of semiconductor structure; etching a portion of the trench contact to form the recess therein below a top surface of the cap; and removing the OPL.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 88.0
- Lexical Diversity: 2.88235
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15894128', '15894162', '15881778', '15729758', '15880757']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9313181542444292
- 35 USC 102 Novelty (BERT): 0.5881452904090252
- Combined Prediction Score: 0.8970008678608888
- Mean Citation Score: 336.869658
- Max Citation Score: 483.89224
- Similarity Product: 470.6722330836295

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test