PATENT CLAIM ANALYSIS

Application Number: 15965505
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["327", "175000"]

Abstract:
A duty cycle correction circuit includes a first inverter suitable for driving a second clock in response to a first clock; a second inverter suitable for driving the first clock in response to the second clock; and a duty cycle detector suitable for detecting a duty cycle of the first clock or the second clock, wherein driving forces of one or more inverters among the first inverter and the second inverter are controlled based on a duty detection result of the duty cycle detector.

Claim (Index 10):
The clock correction circuit of  claim 8 , wherein when the detection result of the phase skew detector shows that a phase difference between the first clock and the third clock is greater than approximately 90\u00b0, the second delay value is controlled to be decreased, and\n when the detection result of the phase skew detector shows that a phase difference between the first clock and the third clock is smaller than approximately 90\u00b0, the first delay value is controlled to be decreased.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 91.0
- Lexical Diversity: 2.31579
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13522745', '12071635', '14710326', '11323511', '14800392']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7979028490241369
- 35 USC 102 Novelty (BERT): 0.4967663689166762
- Combined Prediction Score: 0.7677892010133909
- Mean Citation Score: 235.270278
- Max Citation Score: 241.35959
- Similarity Product: 166.77061113712787

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test