PATENT CLAIM ANALYSIS

Application Number: 15776780
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["327", "355000"]

Abstract:
A self-reconfigurable returnable mixer includes a self-reconfigurable transconductance stage. The input RF voltage signal is converted into RF current through the self-reconfigurable transconductance stage. The RF current is converted into an IF signal through down-conversion and low-pass filtering. The IF signal is fed back to the reconfigurable transconductance stage; the self-reconfigurable transconductance stage presents an open-loop structure to the input RF voltage signal, and the self-reconfigurable transconductance stage presents the topology structure of the negative feedback amplifier to the fed-back IF signal. The self-reconfigurable transconductance stage circuit achieves a high-linearity IF gain while providing a high bandwidth for the RF signal, effectively alleviating the contradiction between the conversion gain and the IF linearity in the conventional returnable structure.

Claim (Index 2):
The self-reconfigurable returnable mixer according to  claim 1 , wherein\n the self-reconfigurable transconductance stage comprises a first PMOS transistor MP 1 , a second PMOS transistor MP 2 , a third PMOS transistor MP 3 , a fourth PMOS transistor MP 4 , a fifth PMOS transistor MPS, a sixth PMOS transistor MP 6 , a first NMOS transistor MN 1 , a second NMOS transistor MN 2 , a fifth NMOS transistor MN 5 , a sixth NMOS transistor MN 6 , a first capacitor C 1 , a second capacitor C 2 , a third capacitor C 3 , a fourth capacitor C 4 , a fifth capacitor C 5 , a sixth capacitor C 6 , a seventh capacitor C 7 , an eighth capacitor C 8 , a ninth capacitor C 9 , a tenth capacitor C 10 , an eleventh capacitor C 11 , a twelfth capacitor C 12 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , an eighth resistor R 8 , a ninth resistor R 9  and a tenth resistor R 10 ; a source of the first PMOS transistor MP 1  is connected to a supply voltage, a gate of the MP 1  is connected to a lower electrode plate of the third capacitor C 3 , a drain of the MP 1  is connected to a source of the third PMOS transistor MP 3 ; a gate of the third PMOS transistor MP 3  is connected to a bias voltage Vb 1 , a drain of the MP 3  is connected to a drain of the fifth NMOS transistor MN 5 ; a gate of the fifth NMOS transistor MN 5  is connected to a bias voltage Vb 2 , a source of the MN 5  is connected to a drain of the first NMOS transistor MN 1 ; a gate of the first NMOS transistor MN 1  is connected to a lower electrode plate of the ninth capacitor C 9 , a source of the MN 1  is grounded; a gate of the fifth PMOS transistor MP 5  is connected to the lower electrode plate of the first capacitor C 1 , a source of the MP 5  is connected to the power source, a drain of the MP 5  is connected to the lower electrode plate of the fifth capacitor C 5 ; an upper electrode plate of the first capacitor C 1 , an upper electrode plate of the third capacitor C 3  and an upper electrode plate of the ninth capacitor C 9  are connected to a positive terminal of an input voltage Vinp; an upper electrode plate of the fifth capacitor C 5  is connected to the drain of the first PMOS transistor MP 1 ; an upper electrode plate of the seventh capacitor C 7  is connected to the drain of the third PMOS transistor MP 3 ; an upper electrode plate of the eleventh capacitor C 11  is connected to a drain of the first NMOS transistor MN 1 ; a lower electrode plate of the fifth capacitor C 5 , a lower electrode plate of the seventh capacitor C 7  and a lower electrode plate of the eleventh capacitor C 11  are connected to the drain of the fifth PMOS transistor MP 5 ; a positive terminal of the first resistor R 1  is connected to the gate of the first PMOS transistor MP 1 , a negative terminal of the R 1  is connected to a reference voltage Vb 0 ; a positive terminal of the third resistor R 3  is connected to the reference voltage Vb 0 , a negative terminal of the R 3  is connected to the drain of the third PMOS transistor MP 3 ; a positive terminal of the fifth resistor R 5  is connected to the drain of the third PMOS transistor MP 3 , a negative terminal of R 5  is connected to the gate of the first NMOS transistor MN 1 ; a positive terminal of the ninth resistor R 9  is connected to the gate of the NMOS transistor MN 1 , a negative terminal of the R 9  is connected to the drain of the third NMOS transistor MN 3 ; a positive terminal of the seventh resistor R 7  is connected to the gate of the fifth PMOS transistor MPS, a negative terminal of the seventh resistor R 7  is connected to a reference voltage Vb 3 ; a source of the second PMOS transistor MP 2  is connected to the supply voltage, a gate of the second PMOS transistor is connected to a lower electrode plate of the fourth capacitor C 4 , the drain of the second PMOS transistor MP 2  is connected to a source of the fourth PMOS transistor MP 4 ; a gate of the fourth PMOS transistor MP 4  is connected to the bias voltage Vb 1 , the drain of the MP 4  is connected to a drain of the sixth NMOS transistor MN 6 ; a gate of the sixth NMOS transistor MN 6  is connected to the bias voltage Vb 2 , the source of the MN 6  is connected to a drain of the second NMOS transistor MN 2 ; a gate of the second NMOS transistor MN 2  is connected to a lower electrode plate of the tenth capacitor C 10 , a source of MN 2  is grounded; a gate of the sixth PMOS transistor MP 6  is connected to a lower electrode plate of the second capacitor C 2 , a source of MP 6  is connected to the power source, a drain of MP 6  is connected to a lower electrode plate of the sixth capacitor C 6 ; an upper electrode plate of the second capacitor C 2 , an upper electrode plate of the fourth capacitor C 4  and an upper electrode plate of the tenth capacitor C 10  are connected to a negative terminal of the input voltage Vinn; an upper electrode plate of the sixth capacitor C 6  is connected to the drain of the second PMOS transistor MP 2 ; an upper electrode plate of the eighth capacitor C 8  is connected to a drain of the fourth PMOS transistor MP 4 ; an upper electrode plate of the twelfth capacitor C 12  is connected to the drain of the second NMOS transistor MN 2 ; the lower electrode plate of the sixth capacitor C 6 , the lower electrode plate of the eighth capacitor C 8  and a lower electrode plate of the twelfth capacitor C 12  are connected to the drain of the sixth PMOS transistor MP 6 ; a positive terminal of the second resistor R 2  is connected to the gate of the second PMOS transistor MP 2 , a negative terminal of the R 2  is connected to the reference voltage Vb 0 ; a positive terminal of the fourth resistor R 4  is connected to the reference voltage Vb 0 , a negative terminal of the R 4  is connected the drain of the fourth PMOS transistor MP 4 ; a positive terminal of the sixth resistor R 6  is connected to the drain of the fourth PMOS transistor MP 4 , a negative terminal of the R 6  is connected to the gate of the second NMOS transistor MN 2 ; a positive terminal of the tenth resistor R 10  is connected to the gate of the second NMOS transistor MN 2 , a negative terminal of the R 10  is connected to the drain of the fourth NMOS transistor MN 4 ; a positive terminal of the eighth resistor R 8  is connected to the gate of the sixth PMOS transistor MP 6 , a negative terminal of the R 8  is connected to the reference voltage Vb 3 .

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.17241
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15509202', '13978864', '13980355', '11567114', '14407027']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8154309393969611
- 35 USC 102 Novelty (BERT): 0.5179833818902241
- Combined Prediction Score: 0.7856861836462874
- Mean Citation Score: 303.3156140000001
- Max Citation Score: 331.42685
- Similarity Product: 247.01442484235764

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test