PATENT CLAIM ANALYSIS

Application Number: 16126316
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["365", "185050"]

Abstract:
A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

Claim (Index 1):
A method of erasing a memory cell, the method comprising:\n applying a first voltage to a control gate of the memory cell, wherein the control gate is disposed over and insulated from a floating gate of the memory cell, wherein the floating gate comprises an embedded portion disposed over and insulated from a selection gate of the memory cell, wherein the embedded portion of the floating gate is located between a first substrate region of a semiconductor substrate and a second substrate region of the semiconductor substrate, wherein the floating gate further comprises a projecting portion extending out of the semiconductor substrate and disposed over the embedded portion of the floating gate and below the control gate, wherein the selection gate is embedded in the semiconductor substrate and below the embedded portion of the floating gate, wherein the selection gate is located between the first substrate region of the semiconductor substrate and the second substrate region of the semiconductor substrate, wherein the semiconductor substrate further comprises a source region disposed below the selection gate, the first substrate region of the semiconductor substrate, and the second substrate region of the semiconductor substrate; applying a second voltage to the first substrate region of the semiconductor substrate; and applying a third voltage to the second substrate region of the semiconductor substrate, wherein the third voltage is different from the second voltage, wherein a potential difference between the second voltage and the first voltage is greater than an erasure threshold of the memory cell so as to perform an erasing operation on the memory cell.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 2.61538
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15895732', '13786197', '10511712', '14864354', '13786202']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7720665362990388
- 35 USC 102 Novelty (BERT): 0.5373087255735076
- Combined Prediction Score: 0.7485907552264857
- Mean Citation Score: 273.135776
- Max Citation Score: 385.00443
- Similarity Product: 306.17910958862905

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test