PATENT CLAIM ANALYSIS

Application Number: 15946697
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "071000"]

Abstract:
A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole.

Claim (Index 3):
The TFT array substrate of  claim 2 , further comprising a gate insulating layer between the initialization power line and the one of the source electrode and the drain electrode of the switching TFT wherein the gate insulating layer and initialization power line overlap at the overlapping region.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 91.0
- Lexical Diversity: 2.7451
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14838036', '13798686', '13794407', '13802224', '13801937']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239859609004132
- 35 USC 102 Novelty (BERT): 0.5149263817505525
- Combined Prediction Score: 0.8830800029854271
- Mean Citation Score: 285.941036
- Max Citation Score: 333.61102
- Similarity Product: 319.0930327863813

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test