PATENT CLAIM ANALYSIS

Application Number: 15976287
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["327", "536000"]

Abstract:
An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

Claim (Index 4):
The analog time delay filter circuit of  claim 3 , wherein the analog time delay filter circuit is fabricated using an integrated passive device (IPD) process.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 2.7037
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15496948', '15652643', '15382335', '15497167', '13494263']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7875129854945241
- 35 USC 102 Novelty (BERT): 0.4950924935108402
- Combined Prediction Score: 0.7582709362961557
- Mean Citation Score: 169.500123
- Max Citation Score: 289.7153
- Similarity Product: 225.84716955642705

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test