PATENT CLAIM ANALYSIS

Application Number: 16387377
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["365", "185140"]

Abstract:
A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

Claim (Index 3):
The memory device of  claim 1 , wherein for each of the memory cells, the select gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 100.0
- Lexical Diversity: 2.25714
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15593231', '15987735', '16271673', '15374588', '16107282']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8343740409603814
- 35 USC 102 Novelty (BERT): 0.5191825020354698
- Combined Prediction Score: 0.8028548870678902
- Mean Citation Score: 310.5469740000001
- Max Citation Score: 351.6929
- Similarity Product: 348.1169438684702

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test