PATENT CLAIM ANALYSIS

Application Number: 15904284
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["375", "260000"]

Abstract:
An embedded system is described. The embedded system includes a processing circuit comprising a processing circuit comprising ‘Q’ processing units that can be operated in parallel. The processing circuit is configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers. A memory is operably coupled to the processing circuit and includes at least input data. The processing circuit is configured to: employ a customized instruction configured to perform an FFT operation of length less than ‘Q’ using a first of the at least two smaller FFTs.

Claim (Index 6):
The embedded system of  claim 1 , wherein the customized instruction is configured to turn-off at least a last multiplier of the Q processing units.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 88.0
- Lexical Diversity: 1.86765
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15904066', '11002478', '11650557', '12354180', '15288548']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5147325675370711
- 35 USC 102 Novelty (BERT): 0.5588941632725889
- Combined Prediction Score: 0.5191487271106229
- Mean Citation Score: 244.717908
- Max Citation Score: 463.4449
- Similarity Product: 299.5652469981194

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test