PATENT CLAIM ANALYSIS

Application Number: 16382580
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["327", "105000"]

Abstract:
A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Claim (Index 2):
The circuit of  claim 1 , wherein the first phase-locked loop circuit comprises a fractional-N phase-locked loop circuit and wherein the second phase-locked loop circuit comprises an integer-N phase locked loop circuit.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 100.0
- Lexical Diversity: 1.69014
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13830007', '15605932', '14746618', '15993254', '13766035']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7983797557280226
- 35 USC 102 Novelty (BERT): 0.4996936952321511
- Combined Prediction Score: 0.7685111496784354
- Mean Citation Score: 250.182538
- Max Citation Score: 306.36957
- Similarity Product: 297.580508667621

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test