PATENT CLAIM ANALYSIS

Application Number: 15903298
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["716", "116000"]

Abstract:
Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Claim (Index 3):
A Network on Chip (NoC), comprising:\n at least one first hardware element configured to consume data from at least one second hardware element configured to provide data, the first hardware element configured to be rendered inactive in response to a signal; wherein the at least one second hardware element, in response to sending the data to the at least one first hardware element when the at least one first hardware element is rendered inactive, is configured to conduct error handling.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 88.0
- Lexical Diversity: 1.53704
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15903702', '14498907', '15382722', '14620710', '14495689']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3739247323365212
- 35 USC 102 Novelty (BERT): 0.4942492612965574
- Combined Prediction Score: 0.3859571852325248
- Mean Citation Score: 223.7686
- Max Citation Score: 230.46239
- Similarity Product: 132.41629467985038

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test