PATENT CLAIM ANALYSIS

Application Number: 16023244
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.

Claim (Index 3):
The semiconductor device of  claim 1 , wherein the semiconductor fin is recessed below a surface of the top spacer.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 2.54839
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15248355', '15618611', '15918077', '15599878', '15255621']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9372440563394172
- 35 USC 102 Novelty (BERT): 0.541273444237236
- Combined Prediction Score: 0.8976469951291992
- Mean Citation Score: 337.0354
- Max Citation Score: 391.43384
- Similarity Product: 313.6203515793514

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test