PATENT CLAIM ANALYSIS

Application Number: 16161290
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-10
Patent Classification: ["710", "052000"]

Abstract:
Provided herein may be a memory controller and a method of operating the same. The memory controller may control a write operation of a memory device in response to a write command received from a host. The memory controller includes a host interface, a buffer, and a first processor. The host interface is configured to receive write data corresponding to the write command from the host. The buffer is configured to store the write data. The first processor is configured to control operations of the host interface and the buffer. The first processor is configured to, when the write command is received, set an operation mode based on an operating status of the memory controller.

Claim (Index 17):
The method according to  claim 13 , wherein, the deactivating of the busy signal based on the set operation mode comprises:\n activating the busy signal in response to completion of reception of the write data; generating, by the host interface, an interrupt signal, and transferring the interrupt signal to the first firmware; and deactivating, by the first firmware, the busy signal in response to the interrupt signal.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 97.0
- Lexical Diversity: 2.73913
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15993143', '15132466', '16139497', '16044024', '15919704']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6989494289787929
- 35 USC 102 Novelty (BERT): 0.4947027043745278
- Combined Prediction Score: 0.6785247565183664
- Mean Citation Score: 201.032032
- Max Citation Score: 209.72441
- Similarity Product: 135.02570462325932

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test