PATENT CLAIM ANALYSIS

Application Number: 15948543
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

Claim (Index 9):
An integrated circuit comprising:\n a plurality of field effect transistors, each field effect transistor comprising:\n a source region; \n a drain region; \n a channel region extending between the source region and the drain region; \n a gate on the channel region; \n a gate contact on the gate at an active region of the gate; \n a source contact on the source region; \n a drain contact on the drain region; and \n a via on the source contact or the drain contact, wherein the via is staggered relative to the gate contact.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.46154
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12983925', '15810557', '10668349', '15436905', '15844840']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919103501471312
- 35 USC 102 Novelty (BERT): 0.4977279220202049
- Combined Prediction Score: 0.8769659435262012
- Mean Citation Score: 238.256964
- Max Citation Score: 253.73509
- Similarity Product: 187.88470223463003

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test