PATENT CLAIM ANALYSIS

Application Number: 15911719
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["327", "333000"]

Abstract:
A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

Claim (Index 16):
A switch-mode power supply, comprising:\n a power transistor configured to drive an inductor; a gate driver coupled to the power transistor, and configured to drive a control terminal of the power transistor; and a level shifter coupled to the gate driver, the level shifter comprising:\n a low voltage rail; \n a high voltage rail; \n an input circuit powered via the low voltage rail; \n an interface circuit coupled to the input circuit; \n an output circuit coupled to the interface circuit and powered via the high voltage rail, the output circuit comprising:\n a first boost circuit, comprising a first transistor that is capacitively coupled to the interface circuit, the first transistor configured to switchably connect the high voltage rail to a first output node responsive to a first signal received from the interface circuit; \n a second boost circuit, comprising a second transistor that is capacitively coupled to the interface circuit, the second transistor configured to switchably connect the high voltage rail to a second output node responsive to a second signal received from the interface circuit; and \n a first inverter configured to drive the first output node responsive to signal present on the second output node; and \n a second inverter configured to drive the second output node responsive to signal present on the first output node.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 3.65625
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15478063', '13332730', '12273055', '12925916', '14843992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7719329094094779
- 35 USC 102 Novelty (BERT): 0.4801473763931563
- Combined Prediction Score: 0.7427543561078458
- Mean Citation Score: 217.00460200000003
- Max Citation Score: 225.6899
- Similarity Product: 176.91543892594575

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test