PATENT CLAIM ANALYSIS

Application Number: 16126562
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["257", "324000"]

Abstract:
A vertical memory device includes a gate electrode structure on a substrate, and a channel. The gate electrode structure includes gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrode structure in the vertical direction on the substrate. The channel includes a first portion having a slanted sidewall with respect to the upper surface of the substrate and a second portion contacting an upper surface of the first portion and having a slanted sidewall with respect to the upper surface of the substrate. A width of an upper surface of the second portion is less than a width of the upper surface of the first portion. An impurity region doped with carbon or p-type impurities is formed at an upper portion of the substrate. The channel contacts the impurity region.

Claim (Index 17):
The vertical memory device of  claim 16 , wherein upper surfaces of the lower channels included in the plurality of channel structures are substantially coplanar with each other.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 2.67241
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16118647', '14601496', '12620923', '15155732', '15610923']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9141750153430936
- 35 USC 102 Novelty (BERT): 0.5052714009717693
- Combined Prediction Score: 0.8732846539059611
- Mean Citation Score: 239.539354
- Max Citation Score: 259.13647000000003
- Similarity Product: 202.0781867029

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test