PATENT CLAIM ANALYSIS

Application Number: 15995452
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["257", "315000"]

Abstract:
Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Claim (Index 8):
An integrated circuit structure, comprising:\n a semiconductor substrate including isolation structures which delimit a plurality of active areas including a first active area for a first transistor, a second active area for a second transistor and a third active area for a memory cell; a dielectric layer which extends over the first and second active areas to form at least part of a gate insulator for the first and second transistors; a floating gate electrode for the memory cell over the third active area; a silicon oxide-nitride-oxide trilayer covering an upper surface and side surfaces of the floating gate electrode; a control gate electrode for the memory cell over the silicon oxide-nitride-oxide trilayer; a control gate electrode for the first transistor over the dielectric layer; and a control gate electrode for the second transistor over the dielectric layer.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 94.0
- Lexical Diversity: 2.73913
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15228236', '14982228', '15053365', '11059294', '10849152']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918720690266332
- 35 USC 102 Novelty (BERT): 0.5037424143632084
- Combined Prediction Score: 0.8772228626760198
- Mean Citation Score: 200.705484
- Max Citation Score: 287.0437
- Similarity Product: 238.42534755451683

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test