PATENT CLAIM ANALYSIS

Application Number: 15968184
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["361", "777000"]

Abstract:
Systems and methods for the design and use of a System-in-Package (SiP) device with a connection layout for minimizing a system Printed Circuit Board (PCB) using the SiP are provided.

Claim (Index 12):
A method for optimizing a system comprising a printed circuit board (PCB) and a System-in-Package (SiP) mounted on said PCB, comprising:\n identifying signals generated by or used by components of said SiP; grouping signals of said identified SiP components that are internal signals of said SiP; grouping signals of said identified SiP components that are external signals for said SiP; identifying and grouping power input, power output, and ground lines for said SiP components; and arranging one or more escape traces on a top layer of said PCB to properly interface with an array of package connectors of said SiP such that all of said escape traces are connected to external signals and such that at least one of said power input, power output, and ground lines is connected to a via of said PCB through at least one of said package connectors, wherein said via is electrically connected to a power or ground layer of said PCB.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 1.2963
- Patent Class: 361.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10442355', '11934340', '11696670', '13707175', '15085080']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8246445888795948
- 35 USC 102 Novelty (BERT): 0.461943467385945
- Combined Prediction Score: 0.7883744767302298
- Mean Citation Score: 166.60554399999995
- Max Citation Score: 170.70906000000005
- Similarity Product: 134.79216118461378

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test