PATENT CLAIM ANALYSIS

Application Number: 16044775
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-09
Patent Classification: ["257", "324000"]

Abstract:
A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.

Claim (Index 11):
A memory device, comprising:\n a first memory region including a plurality of first electrode layers and a semiconductor layer, the plurality of first electrode layers being stacked in a first direction, the semiconductor layer extending in the first direction through the plurality of first electrode layers; a first connection region including ends in a second direction of the plurality of first electrode layers, the second direction crossing the first direction, the ends of the plurality of first electrode layers being provided in a staircase configuration, the first connection region including a plurality of first contact plugs connected respectively to the ends of the plurality of first electrode layers; a second memory region including a plurality of second electrode layers and a semiconductor layer, the plurality of second electrode layers being stacked in the first direction and being arranged in a third direction when viewed from the first memory region, the third direction crossing the first direction and the second direction, the semiconductor layer extending in the first direction through the plurality of second electrode layers; a second connection region including ends in the second direction of the plurality of second electrode layers, the ends of the plurality of second electrode layers being provided in a staircase configuration, the second connection region including a plurality of second contact plugs connected respectively to the ends of the plurality of second electrode layers; and a third connection region provided between the first connection region and the second connection region in the third direction, the third connection region including a first insulating body and a plurality of third contact plugs, the first insulating body having a thickness in the first direction thicker than a stacked width in the first direction of the first electrode layers and a stacked width in the first direction of the second electrode layers, the plurality of third contact plugs extending in the first direction through the first insulating body.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 95.0
- Lexical Diversity: 3.125
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15855186', '15919250', '14204512', '15907984', '15906423']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9179982106742628
- 35 USC 102 Novelty (BERT): 0.48150167426493
- Combined Prediction Score: 0.8743485570333297
- Mean Citation Score: 224.369582
- Max Citation Score: 241.45198
- Similarity Product: 209.1761794265008

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test