PATENT CLAIM ANALYSIS

Application Number: 15884504
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-12
Patent Classification: ["257", "506000"]

Abstract:
A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.

Claim (Index 21):
A semiconductor device comprising:\n a substrate having a cell array region and a peripheral circuit region, the cell array region including a cell active region, and the peripheral circuit region including a peripheral circuit active region; a plurality of word line structures extending in the cell active region in the substrate in a first direction, the plurality of word line structures being spaced apart from each other in a second direction perpendicular to the first direction; a plurality of direct contact hole patterns opening the cell active region between the plurality of word line structures of the cell array region, and the plurality of direct contact holes patterns being spaced apart from each other in the substrate; a plurality of bit line structures extending on the direct contact hole patterns and the substrate of the cell array region, the plurality of bit line structures extending in the second direction perpendicular to the word line structures, the plurality of bit line structures being spaced apart from each other in the first direction; a multiple insulation pattern on an upper surface of the substrate in the cell array region where the direct contact hole patterns are not formed, the multiple insulation pattern being arranged in a third direction perpendicular to the first direction and the second direction, the multiple insulation pattern being arranged between the plurality of word line structures and the plurality of bit line structures; and a peripheral circuit gate structure on the peripheral circuit active region of the peripheral circuit region.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 86.0
- Lexical Diversity: 3.29787
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15608076', '14445829', '14859435', '14965532', '14591929']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9072262895236244
- 35 USC 102 Novelty (BERT): 0.4889050888333029
- Combined Prediction Score: 0.8653941694545921
- Mean Citation Score: 246.71885
- Max Citation Score: 252.1316
- Similarity Product: 227.97876468777656

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test