PATENT CLAIM ANALYSIS

Application Number: 15772410
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-03
Patent Classification: ["345", "055000"]

Abstract:
Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

Claim (Index 8):
The shift register circuitry according to  claim 7 , wherein the pull-down control circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;\n wherein a control electrode and a first electrode of the third transistor are coupled to the third clock signal terminal, and a second electrode of the third transistor is coupled to the pull-down point; wherein a control electrode of the fourth transistor is coupled to the first pull-up point, a first electrode of the fourth transistor is coupled to the pull-down point, and a second electrode of the fourth transistor is coupled to the third voltage terminal; wherein a control electrode of the fifth transistor is coupled to the first output signal terminal, a first electrode of the fifth transistor is coupled to the pull-down point, and a second electrode of the fifth transistor is coupled to the third voltage terminal; wherein a control electrode of the sixth transistor is coupled to the second pull-up point, a first electrode of the sixth transistor is coupled to the pull-down point, and a second electrode of the sixth transistor is coupled to the third voltage terminal; and wherein a control electrode of the seventh transistor is coupled to the second output signal terminal, a first electrode of the seventh transistor is coupled to the pull-down point, and a second electrode of the seventh transistor is coupled to the third voltage terminal.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 91.0
- Lexical Diversity: 2.97778
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15680452', '15232095', '15761749', '15780157', '15750679']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7246301198571229
- 35 USC 102 Novelty (BERT): 0.5098253916490177
- Combined Prediction Score: 0.7031496470363124
- Mean Citation Score: 288.8553100000001
- Max Citation Score: 305.9340200000001
- Similarity Product: 254.1054488746787

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test