PATENT CLAIM ANALYSIS

Application Number: 16056934
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "401000"]

Abstract:
A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

Claim (Index 18):
The method of  claim 1 , wherein the substrate comprises silicon.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 3.02128
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15876606', '15178871', '15631385', '15196386', '15176279']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9499568244017926
- 35 USC 102 Novelty (BERT): 0.5735211430488963
- Combined Prediction Score: 0.9123132562665032
- Mean Citation Score: 458.86349
- Max Citation Score: 495.5401
- Similarity Product: 388.0011011262537

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test