PATENT CLAIM ANALYSIS

Application Number: 16144141
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["257", "401000"]

Abstract:
Semiconductor devices include a semiconductor layer comprising a channel region and source/drain regions. A gate stack is formed on the channel region. A dielectric layer is formed on the semiconductor layer in the source/drain regions. Source/drain structures are formed over the dielectric layer in the source/drain regions.

Claim (Index 9):
The semiconductor device of  claim 1 , wherein a bottom surface of the source/drain structures has a height lower than a top surface of the semiconductor layer.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 1.96154
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15820947', '15680711', '15182995', '15486351', '16144196']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9157653052653948
- 35 USC 102 Novelty (BERT): 0.5401359071634779
- Combined Prediction Score: 0.8782023654552032
- Mean Citation Score: 274.531128
- Max Citation Score: 364.3075
- Similarity Product: 275.7852829813957

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test