PATENT CLAIM ANALYSIS

Application Number: 16020475
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["438", "300000"]

Abstract:
A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Claim (Index 10):
The device of  claim 8 , wherein the first fin structure comprises a PFET device having a tri-gate structure such that the PFET gate wraps around top and side surfaces of the first plurality of fin structures.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 2.24561
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14953574', '15635890', '14607256', '14833857', '15874813']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9061150149858248
- 35 USC 102 Novelty (BERT): 0.560639202099493
- Combined Prediction Score: 0.8715674336971917
- Mean Citation Score: 414.813038
- Max Citation Score: 496.33255
- Similarity Product: 313.0449525931805

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test