PATENT CLAIM ANALYSIS

Application Number: 15892584
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-07
Patent Classification: ["438", "527000"]

Abstract:
Methods of forming a portion of an integrated circuit include forming a patterned mask having an opening and exposing a surface of a semiconductor material, forming a first doped region at a first level of the semiconductor material through the opening, and isotropically removing a portion of the patterned mask to increase a width of the opening. The methods further include forming a second doped region at a second level of the semiconductor region through the opening after isotropically removing the portion of the patterned mask, wherein the second level is closer to the surface of the semiconductor material than the first level.

Claim (Index 19):
A method of forming a portion of memory, comprising:\n forming a patterned mask having an opening and exposing a surface of a semiconductor material; forming a first doped region at a first level of the semiconductor material through the opening, wherein the first level extends from a first depth from the surface of the semiconductor substrate to a second depth from the surface of the semiconductor material, and wherein the second depth is closer to the surface of the semiconductor material than the first depth; isotropically removing a portion of the patterned mask to increase a width of the opening; after isotropically removing the portion of the patterned mask, forming a second doped region at a second level of the semiconductor region through the opening, wherein the second level extends from the second depth from the surface of the semiconductor substrate to a third depth from the surface of the semiconductor substrate, and wherein the third depth is closer to the surface of the semiconductor material than the second depth; isotropically removing a second portion of the patterned mask to increase a width of the opening; after isotropically removing the second portion of the patterned mask, forming a third doped region at a third level of the semiconductor region through the opening, wherein the third level extends from the third depth from the surface of the semiconductor substrate to a fourth depth from the surface of the semiconductor substrate, and wherein the fourth depth is closer to the surface of the semiconductor material than the third depth; after forming the third doped region, removing the patterned mask; and forming a transistor on the third doped region, wherein the transistor is connected between an access line of a block of memory cells of an array of memory cells of the memory and a global access line of the memory.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.63415
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10639058', '11159514', '11451264', '11007510', '11692313']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8510940788521125
- 35 USC 102 Novelty (BERT): 0.4731408645371768
- Combined Prediction Score: 0.813298757420619
- Mean Citation Score: 176.84434000000005
- Max Citation Score: 188.70584
- Similarity Product: 147.91166520032886

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test