PATENT CLAIM ANALYSIS

Application Number: 16047054
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "288000"]

Abstract:
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.

Claim (Index 9):
A method of manufacturing comprising:\n providing a substrate including a gate structure traversing a channel region and separating source and drain (S/D) features, the gate structure including a gate electrode, the gate structure having a top surface in a first plane; forming a first dielectric layer over the S/D features; forming a first interconnect structure extending through the first dielectric layer and through an intermediate layer formed over the first dielectric layer, the first interconnect being in electrical contact with the S/D features, the first interconnect structure having a top surface in a second plane different from the first plane of the top surface of the gate structure; forming a second dielectric layer over the intermediate layer; forming a second interconnect structure extending through the second dielectric layer, the second interconnect being in electrical contact with the first interconnect structure; and forming a third interconnect structure extending through the second dielectric layer and through the intermediate layer, the third interconnect structure being in electrical contact with the gate structure.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 95.0
- Lexical Diversity: 2.9
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13368960', '14269748', '13486343', '13212904', '13302335']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9089475630177984
- 35 USC 102 Novelty (BERT): 0.47457450668119
- Combined Prediction Score: 0.8655102573841376
- Mean Citation Score: 169.25348200000005
- Max Citation Score: 185.65382
- Similarity Product: 142.18274706329106

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test