PATENT CLAIM ANALYSIS

Application Number: 15864330
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "347000"]

Abstract:
Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.

Claim (Index 6):
The semiconductor device of  claim 5 , further comprising inner spacers disposed on sidewalls of the gate electrode, each of the inner spacers being interposed between the channel semiconductor patterns adjacent to each other or between the substrate and a lowermost one of the channel semiconductor patterns,\n wherein the growth prevention regions and the inner spacers comprise same material.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 86.0
- Lexical Diversity: 1.93333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14989485', '15786864', '15724874', '15133424', '15245549']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.912910830970873
- 35 USC 102 Novelty (BERT): 0.5169151872530746
- Combined Prediction Score: 0.8733112665990931
- Mean Citation Score: 290.0187640000001
- Max Citation Score: 293.60925
- Similarity Product: 213.0829491198957

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test