PATENT CLAIM ANALYSIS

Application Number: 15992112
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["711", "114000"]

Abstract:
An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Claim (Index 26):
The integrated-circuit buffer component of  claim 21  wherein the internal data conductors comprise write data conductors and read data conductors, and wherein the number of write data conductors matches the number of read data conductors and matches the number of I/O transceivers of the first memory-side data signaling interface.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 1.33333
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15458166', '14874324', '13499029', '15793029', '11460582']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4924661173590487
- 35 USC 102 Novelty (BERT): 0.5108314648436115
- Combined Prediction Score: 0.494302652107505
- Mean Citation Score: 203.302042
- Max Citation Score: 279.7678
- Similarity Product: 217.2145630459666

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test