PATENT CLAIM ANALYSIS

Application Number: 15769452
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["257", "348000"]

Abstract:
An embodiment includes a system comprising: a first gate and a first contact that correspond to a transistor and are on a first fin; a second gate and a second contact that correspond to a transistor and are on a second fin; an interlayer dielectric (ILD) collinear with and between the first and second contacts; wherein (a) the first and second gates are collinear and the first and second contacts are collinear; (b) the ILD includes a recess that comprises a cap layer including at least one of an oxide and a nitride. Other embodiments are described herein.

Claim (Index 8):
The method of  claim 7 , comprising removing at least a portion of the planarized first portion of the capping layer to form the additional void.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 91.0
- Lexical Diversity: 2.22
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15790216', '15812288', '15188619', '15920303', '15890246']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8893313345901357
- 35 USC 102 Novelty (BERT): 0.4799990097340978
- Combined Prediction Score: 0.8483981021045319
- Mean Citation Score: 152.092582
- Max Citation Score: 155.71108999999996
- Similarity Product: 111.96993267393704

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test