PATENT CLAIM ANALYSIS

Application Number: 15910725
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["257", "048000"]

Abstract:
A semiconductor package includes a board, a plurality of semiconductor memory chips, a controller chip, and a sealing resin portion. The plurality of semiconductor memory chips are stacked in a thickness direction of the board. The controller chip is disposed between the board and the plurality of semiconductor memory chips or on a side of the plurality of semiconductor chips opposite to the board. The sealing resin portion seals the plurality of semiconductor memory chips and the controller chip. The plurality of semiconductor memory chips include at least one through via that penetrates one or more semiconductor memory chips of the plurality of semiconductor memory chips in the thickness direction of the board to be connected to the controller chip.

Claim (Index 1):
A semiconductor package comprising:\n a board; a plurality of semiconductor memory chips stacked in a thickness direction of the board; a controller chip disposed between the board and the plurality of semiconductor memory chips or on a side of the plurality of semiconductor chips opposite to the board; and a sealing resin portion that seals the plurality of semiconductor memory chips and the controller chip, wherein the plurality of semiconductor memory chips include at least one through via that penetrates one or more semiconductor memory chips included in the plurality of semiconductor memory chips in the thickness direction of the board to be connected to the controller chip, and the controller chip includes a first region and a second region where an amount of heat generated per unit area is larger than that generated in the first region, the at least one through via includes a plurality of through vias of a first group that are connected to the first region, and a plurality of through vias of a second group that are connected to the second region, and an arrangement density of the plurality of through vias of the second group is higher than an arrangement density of the plurality of through vias of the first group.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 90.0
- Lexical Diversity: 2.84444
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12712284', '12558814', '13613983', '13693458', '13798800']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9139362753867613
- 35 USC 102 Novelty (BERT): 0.4700909423118722
- Combined Prediction Score: 0.8695517420792723
- Mean Citation Score: 163.84733
- Max Citation Score: 169.12292
- Similarity Product: 128.3397306378126

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test