PATENT CLAIM ANALYSIS

Application Number: 15984834
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185110"]

Abstract:
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Claim (Index 6):
The memory device according to  claim 1 , further comprising:\n a plurality of word lines respectively connected to corresponding gates of the memory cell transistors among each block; a plurality of first transfer transistors connected between each block unit and the second selection circuit, one end of the first transfer transistors being individually connected to the first select gate lines and the second select gate lines; a plurality of second transfer transistors connected between each block and the second selection circuit, one end of the second transfer transistors being individually connected to the word lines; and a voltage generator configured to individually apply voltages on other ends of the first transfer transistors and other ends of the second transfer transistors, wherein the first selection circuit is configured to send a first selection signal to gates of a subset of the first transfer transistors and a subset of the second transfer transistors corresponding to each block unit in response to a first address signal.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.61667
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14688664', '13784512', '15151883', '15497928', '15498029']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8173485928027381
- 35 USC 102 Novelty (BERT): 0.5177920588450697
- Combined Prediction Score: 0.7873929394069713
- Mean Citation Score: 314.67297
- Max Citation Score: 343.40857
- Similarity Product: 276.1782988603896

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test