PATENT CLAIM ANALYSIS

Application Number: 16255536
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["375", "376000"]

Abstract:
A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY 1  at a first point t 1  in time and a second delay signal SDLY 2  at a second point in time t 2 . The sampler module is configured to provide a first sample S 1  of the oscillator output signal SOUT at the first point in time t 1  and a second sample S 2  of the oscillator output signal SOUT at the second point in time t 2 . The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S 1  and the second sample S 2 . The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.

Claim (Index 17):
The sub-sampling phase-locked loop according to  claim 1 , wherein\n the DTC comprises a digital-to-time converter module, the interpolator comprises a sampler, and the sub-sampling phase-locked loop further comprises a modulator and an analogue shift register; wherein the DTC module comprises a first input, and a second input, wherein the DTC module is configured to receive a reference signal on the first input, and a modulator signal from the output of the modulator on the second input; the modulator comprises an input and an output, wherein the modulator is configured to receive a control signal on the input and to provide control signals for controlling the digital-to-time converter module, wherein the control signal defines a factor between a desired frequency of the oscillator output signal and a frequency of the reference signal; the sampler comprises an input for the oscillator output signal, a delay signal input for the first delay signal and an output for a first sample and a second sample; the analogue shift register comprises a first cell and a second cell, wherein each of the first sample and the second sample is injected into the first cell and the second cell of the analogue shift register, and the interpolation is performed between the first sample S 1 =S [k] and the second sample S 2 =S [k\u22121], wherein k is an integer, and k\u22651; the interpolator comprises a first input for the first sample from the first cell, a second input for the second sample from the second cell and an output, wherein the interpolator is configured to interpolate between the first sample and the second sample to produce the sampler signal which is provided on the output of the interpolator.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 99.0
- Lexical Diversity: 3.14286
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15660424', '15224296', '15224280', '15224199', '16046513']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.540305341764703
- 35 USC 102 Novelty (BERT): 0.596616041689574
- Combined Prediction Score: 0.5459364117571901
- Mean Citation Score: 319.355008
- Max Citation Score: 553.2161
- Similarity Product: 441.74678273153296

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test