PATENT CLAIM ANALYSIS

Application Number: 16167903
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "231000"]

Abstract:
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Claim (Index 4):
The method of  claim 3 , wherein the PMOS transistor is a PMOS transistor with a width that is smaller than an adjacent PMOS transistor and wherein forming the PMOS gate forms an additional gate extension with a gap between a first edge of the gate extension and the PMOS gate and a second opposite edge aligned with an edge of a gate of the adjacent PMOS transistor.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 97.0
- Lexical Diversity: 1.66667
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14576659', '15409842', '14584348', '11849798', '13288664']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8766274023100693
- 35 USC 102 Novelty (BERT): 0.5181722430138972
- Combined Prediction Score: 0.840781886380452
- Mean Citation Score: 255.28350200000008
- Max Citation Score: 318.36716
- Similarity Product: 247.3446060249543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test