PATENT CLAIM ANALYSIS

Application Number: 15866704
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["257", "032000"]

Abstract:
A method of manufacturing a semiconductor device includes: receiving a semiconductor structure, the semiconductor structure including: a fin structure; a dummy gate across over the fin structure to define a channel region of the fin structure; and a dummy dielectric layer separating the channel region of the fin structure from the dummy gate; removing the dummy gate and the dummy dielectric layer to expose the channel region of the fin structure; and forming a doped interfacial layer covering the channel region of the fin structure, in which the doped interfacial layer includes a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.

Claim (Index 7):
The method of  claim 1 , wherein the channel region of the fin structure comprises first nanowires and second nanowires alternatively disposed with the first nanowires, and the method further comprises:\n removing the first nanowires to remain the second nanowires before forming the doped interfacial layer, wherein forming the doped interfacial layer comprises forming the doped interfacial layer surrounding the second nanowires.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 86.0
- Lexical Diversity: 2.4898
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15692124', '14994399', '15670701', '15860912', '14555439']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9257561585284032
- 35 USC 102 Novelty (BERT): 0.4819767743386993
- Combined Prediction Score: 0.8813782201094328
- Mean Citation Score: 217.591028
- Max Citation Score: 223.01215
- Similarity Product: 182.5829218646556

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test