PATENT CLAIM ANALYSIS

Application Number: 15927088
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["365", "230060"]

Abstract:
An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

Claim (Index 12):
The code generating method of  claim 11 , wherein the at least one current adjusting element comprises at least one dopant ion, and either the width or the thickness of the current paths is defined according to the de Broglie length (DBL), and the length of the current paths is longer than the width of the current path.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 90.0
- Lexical Diversity: 2.2931
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14335957', '14038772', '14224099', '14859237', '14979459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7898850793898032
- 35 USC 102 Novelty (BERT): 0.5762857582336444
- Combined Prediction Score: 0.7685251472741874
- Mean Citation Score: 302.741698
- Max Citation Score: 521.7953
- Similarity Product: 369.6696536589861

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test