PATENT CLAIM ANALYSIS

Application Number: 16017249
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["365", "148000"]

Abstract:
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Claim (Index 48):
An integrated circuit comprising:\n a semiconductor memory array comprising:\n a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:\n a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell; \n a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto; \n a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; \n a buried layer terminal electrically connected to said buried layer region; \n \n wherein when a first memory cell of said plurality of semiconductor memory cells is in a first charge level and a second memory cell of said plurality of semiconductor memory cells is in a second charge level, upon said transfer of data, said first memory cell stores a first nonvolatile memory state and second memory cell stores a second nonvolatile memory state, said first and second nonvolatile memory states being non-algorithmically determined by said first and second charge levels of said first and second memory cells, respectively; and \n a control circuit configured to perform said transfer operation.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 94.0
- Lexical Diversity: 1.75472
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15724651', '14738349', '15292098', '12545623', '13116924']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8433923448390215
- 35 USC 102 Novelty (BERT): 0.527072128353889
- Combined Prediction Score: 0.8117603231905083
- Mean Citation Score: 369.622278
- Max Citation Score: 385.98712
- Similarity Product: 382.2861822477722

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test