PATENT CLAIM ANALYSIS

Application Number: 16452089
Application Type: Utility
Filing Date: 2019-06
Publication Date: 2019-10
Patent Classification: ["326", "009000"]

Abstract:
The output driving circuit include a pull-down driver, an input/output (IO) control logic, a gate control logic, and an inverter. The pull-down driver includes first, second, and third transistors that are sequentially coupled between a pad and a ground node. The IO control logic is configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor. The inverter is configured to invert the enable signal and transfer an inverted enable signal to the gate control logic. Therefore, the reliability of the output driving circuit can be improved.

Claim (Index 3):
The output driving circuit according to  claim 1 , wherein the logical value of the enable signal received by the input/output control logic is different to the logical value of the inverted enable signal received by the gate control logic.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 100.0
- Lexical Diversity: 2.53704
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15858516', '12289132', '13799866', '12193299', '15471861']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.691469455459751
- 35 USC 102 Novelty (BERT): 0.525694113083576
- Combined Prediction Score: 0.6748919212221335
- Mean Citation Score: 241.630304
- Max Citation Score: 358.4004
- Similarity Product: 274.7283888915539

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test