PATENT CLAIM ANALYSIS

Application Number: 16044912
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "051000"]

Abstract:
According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

Claim (Index 2):
A semiconductor device comprising:\n a first nonvolatile semiconductor element; a second nonvolatile semiconductor element; a resistive element; a controller that controls the first nonvolatile semiconductor element and the second nonvolatile semiconductor element; a first signal line that connects the controller to the resistive element; a second signal line that connects the resistive element to the first nonvolatile semiconductor element; a third signal line that branches from the second signal line, the third signal line being connected to the second nonvolatile semiconductor element, at least one of the second signal line and the third signal line including a signal line formed on a first wiring layer and a signal line formed on a second wiring layer; a connector that allows connection to an external device; and a substrate on which the first nonvolatile semiconductor element, the second nonvolatile semiconductor element, the resistive element, the controller, and the connector are mounted, the first nonvolatile semiconductor element and the second nonvolatile semiconductor element being disposed symmetrically on opposite sides of the substrate, the substrate including:\n a front surface layer that includes a wiring pattern formed on a front surface of the substrate, the front surface layer being a layer on which the first nonvolatile semiconductor element and the resistive element are mounted, \n a rear surface layer that includes a wiring pattern formed on a rear surface of the substrate, the rear surface layer being a layer on which the second nonvolatile semiconductor element is mounted, and \n a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers including a wiring pattern, the first wiring layer being one of the plurality of internal wiring layers, the second wiring layer being one of the plurality of internal wiring layers, the second wiring layer being a different wiring layer from the first wiring layer.

Metadata:
- Claim Count in Document: 45.0
- Percentile: 95.0
- Lexical Diversity: 2.1
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15646360', '15236037', '14731712', '13731613', '13731599']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8037561132460112
- 35 USC 102 Novelty (BERT): 0.48128678990365
- Combined Prediction Score: 0.771509180911775
- Mean Citation Score: 221.598138
- Max Citation Score: 237.85179
- Similarity Product: 190.8117565472245

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test