PATENT CLAIM ANALYSIS

Application Number: 16039067
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["714", "727000"]

Abstract:
A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Claim (Index 7):
The IC of  claim 1 , further including:\n a plurality of bi-directional buffers coupled to a plurality of input/output (I/O) pins, in which each bi-directional buffer has an output port coupled to an input of the scan chain and an input port coupled to an output of the scan chain; a direction signal coupled to control the bi-directional buffers, in which the direction signal is a control signal generated by the decoding circuitry; and control logic coupled to the plurality of bi-directional buffers operable to cause the integrated circuit to: receive a test pattern from an external tester for the scan chain at a test port on the integrated circuit using the plurality of input/output (I/O) pins operating in parallel; scan a test pattern into the scan chain using a shift clock operating at the first rate; provide the test pattern to combinatorial logic circuitry coupled to the scan chain; capture a response pattern to the test pattern from the combinatorial logic in the scan chain; scan the response pattern from the scan chain using a shift clock operating at the second rate that is slower than the first rate; and provide the response pattern to the external tester using the same plurality of I/O pins operating in parallel.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 95.0
- Lexical Diversity: 2.19178
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15226898', '12410599', '12835358', '11936880', '13852223']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3086806412392338
- 35 USC 102 Novelty (BERT): 0.539580449627892
- Combined Prediction Score: 0.3317706220780996
- Mean Citation Score: 226.103994
- Max Citation Score: 390.03903
- Similarity Product: 363.59345953163086

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test