PATENT CLAIM ANALYSIS

Application Number: 16207064
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["327", "198000"]

Abstract:
A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.

Claim (Index 3):
A method of operating a clock circuit, the method comprising:\n causing, by a first latch, a first latch output signal to transition from a first voltage level to a second voltage level in response to a transition of an enable signal from the second voltage level to the first voltage level, the second voltage level being different from the first voltage level; causing a clock trigger circuit to pull a first node from the first voltage level to the second voltage level in response to a transition of a first clock signal from the first voltage level to the second voltage level, the pulling of the first node thereby causing a first control signal of the clock trigger circuit to transition from the first voltage level to the second voltage level, the clock trigger circuit being coupled to at least an input of a first latch or a first trigger circuit by the first node, and the first control signal being fed back from the clock trigger circuit to the input of the first latch from the first node; and causing, by the first trigger circuit, an output clock signal to transition from the second voltage level to the first voltage level in response to the transition of the first clock signal to the second voltage level, and in response to the transition of the first latch output signal to the second voltage level.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 98.0
- Lexical Diversity: 4.78788
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16039824', '15443504', '14539407', '15405423', '14420230']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7751181874249639
- 35 USC 102 Novelty (BERT): 0.5299679969969169
- Combined Prediction Score: 0.7506031683821592
- Mean Citation Score: 227.80722000000003
- Max Citation Score: 372.0688
- Similarity Product: 347.4107162631034

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test