PATENT CLAIM ANALYSIS

Application Number: 16241270
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["363", "021020"]

Abstract:
A switch control circuit includes a first pin connected to a first voltage, and a second pin connected to another end of a first resistor including an end connected to the first pin and a first capacitor. In the switch control circuit, at least two of first dead time information, second dead time information, and a protection mode are set by using a multi-voltage of the second pin. The first dead time information is information about a dead time of a first switch and a second switch controlling power supply, the second dead time information is information about a dead time for synchronous rectification, and the protection mode includes an auto-restart mode and a latch mode.

Claim (Index 9):
The switch control circuit of  claim 8 , further comprising:\n a second register configured to include a plurality of input ends connected to a plurality of output ends of the second counter and be synchronized with the second register read signal to store inputs of the plurality of input ends, wherein the plurality of output ends of the second counter have a level according to a count result.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 99.0
- Lexical Diversity: 2.60417
- Patent Class: 363.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15446513', '15730490', '14964998', '14965125', '14619201']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7775908312749589
- 35 USC 102 Novelty (BERT): 0.5241318166549588
- Combined Prediction Score: 0.7522449298129589
- Mean Citation Score: 228.346994
- Max Citation Score: 332.62817
- Similarity Product: 260.49450558300083

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test