PATENT CLAIM ANALYSIS

Application Number: 16212169
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["375", "326000"]

Abstract:
The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

Claim (Index 9):
The device of  claim 1  further comprising:\n a first output terminal coupled to the first plurality of inverters; \n a second input terminal; \n a second plurality of inverters; \n a second output terminal coupled to the second plurality of inverters; and \n a second equalization element coupled to the second plurality of inverters.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.66667
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15699882', '14679934', '15074530', '15951069', '15827989']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3943810582883842
- 35 USC 102 Novelty (BERT): 0.5489253407343857
- Combined Prediction Score: 0.4098354865329844
- Mean Citation Score: 210.808136
- Max Citation Score: 398.1237
- Similarity Product: 288.87208009466525

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test