PATENT CLAIM ANALYSIS

Application Number: 16262661
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["365", "233110"]

Abstract:
A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

Claim (Index 9):
The electronic device of  claim 8 , comprising:\n detecting an occurrence of the falling edge of the EDC hold reset; triggering the transmission of the EDC hold pattern, based upon the occurrence of the falling edge of the EDC hold reset, such that the transmission is synchronous to the rising edge of the CK_t clock.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 99.0
- Lexical Diversity: 1.94
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15606185', '16026890', '15606194', '15081071', '12217064']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7844318223977481
- 35 USC 102 Novelty (BERT): 0.5410569422425916
- Combined Prediction Score: 0.7600943343822325
- Mean Citation Score: 245.244272
- Max Citation Score: 401.87314
- Similarity Product: 317.2680402323925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test