PATENT CLAIM ANALYSIS

Application Number: 16176634
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-03
Patent Classification: ["257", "326000"]

Abstract:
This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Claim (Index 1):
A non-volatile semiconductor memory device, comprising:\n a memory cell array including NAND cell units arranged therein, the NAND cell unit being configured to extend in a first direction vertical to a surface of a semiconductor substrate, the NAND cell unit being formed by coupling a plurality of memory cells and selection transistors in series; and a local source line formed on the semiconductor substrate, the local source line being electrically coupled to one end of the NAND cell unit, wherein the memory cell array includes:\n a laminated body where a plurality of conductive films are laminated sandwiching an interlayer insulating film, the conductive film being a control gate line of the memory cell or a selection gate line of the selection transistor; \n a semiconductor layer that extends in the first direction; and \n an electric charge accumulating layer sandwiched between the semiconductor layer and the conductive film, \n the local source line includes a silicide layer, and the electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.01351
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14645793', '15677361', '15151846', '15071463', '14849748']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9155801959729926
- 35 USC 102 Novelty (BERT): 0.4729231434879575
- Combined Prediction Score: 0.8713144907244891
- Mean Citation Score: 209.568676
- Max Citation Score: 247.2536
- Similarity Product: 242.89461214447024

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test