PATENT CLAIM ANALYSIS

Application Number: 16261080
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["438", "269000"]

Abstract:
A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N +  layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N +  layer; forming an insulating SiO 2  layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.

Claim (Index 1):
A method for producing a pillar-shaped semiconductor device, the method comprising:\n a step of providing a stack structure including a semiconductor structure including at least one semiconductor pillar formed on a substrate so as to be perpendicular to a surface of the substrate, a gate insulating layer formed so as to surround an outer periphery of the at least one semiconductor pillar, a gate conductor layer formed so as to surround the gate insulating layer, a first impurity region connected to the at least one semiconductor pillar, and a second impurity region connected to the at least one semiconductor pillar so as to be separated from the first impurity region, and a first wiring conductor layer, a second wiring conductor layer, and a third wiring conductor layer that individually connect to any one of the gate conductor layer, the first impurity region, and the second impurity region of the semiconductor structure, that extend in a horizontal direction along the surface of the substrate, that at least partially overlap in plan view, and that are present in this order from a lower level to a higher level; a step of forming a first contact region that extends through the third wiring conductor layer and the second wiring conductor layer to an upper surface or inside of the first wiring conductor layer; a step of forming a first tubular insulating layer in a portion that is on a side surface of the first contact region and is on a side surface of the second wiring conductor layer; a step of filling the first contact region to form a first conductor layer; a step of exposing a top portion of the first conductor layer and subsequently forming a first material layer so as to surround the top portion of the first conductor layer; a step of forming a first insulating layer over an entirety of the stack structure, and subsequently planarizing upper surfaces of the first conductor layer, the first material layer, and the first insulating layer so as to expose upper surfaces of the first conductor layer and the first material layer; a step of removing the first material layer; a step of forming a second contact region, through the first insulating layer serving as a mask, so as to extend to an upper surface of the third wiring conductor layer; and a step of filling the second contact region to form a second conductor layer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 99.0
- Lexical Diversity: 2.45614
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15712637', '15655168', '16203982', '15729040', '14976691']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9090951274068036
- 35 USC 102 Novelty (BERT): 0.6033819561125967
- Combined Prediction Score: 0.8785238102773829
- Mean Citation Score: 484.12255000000016
- Max Citation Score: 522.3979
- Similarity Product: 507.1974595672965

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test