PATENT CLAIM ANALYSIS

Application Number: 15901606
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-03
Patent Classification: ["327", "109000"]

Abstract:
According to one embodiment, a gate control circuit includes a controller, a delay circuit, a power circuit, a boosting circuit, a first transistor, and a control circuit. The controller outputs first and second control signals based on a control signal from outside. The delay circuit delays the first control signal. The power circuit is capable of controlling a power supply voltage to be output based on the delayed first control signal. The boosting circuit is capable of boosting and outputting an input voltage. The first transistor has one end connected to an output node of the boosting circuit, and the other end grounded. The control circuit is capable of controlling a gate voltage of the first transistor based on the second control signal.

Claim (Index 1):
A gate control circuit comprising:\n a controller that outputs each of first and second control signals based on a control signal from outside; a delay circuit that delays the first control signal; a power circuit that generates a power supply voltage from an input voltage from outside, and controls the power supply voltage to be output based on the delayed first control signal; a boosting circuit that boosts and outputs an input a voltage input thereto; a first transistor that has one end connected to an output node of the boosting circuit, and another end grounded; and a control circuit that controls a gate voltage of the first transistor based on the second control signal, wherein: the power circuit includes second to fifth transistors, one end of each of the second and the third transistors is connected respectively to a power supply wire on which the input voltage is applied, and a gate of the second transistor is connected to a gate of the third transistor and another end of the second transistor, and one end of the fourth transistor is connected to the another end of the second transistor, another end of the fourth transistor is connected to a ground wire, one end of the fifth transistor is connected to the power supply wire, another end of the fifth transistor is connected to the one end of the fourth transistor, and the delayed first control signal is input to a gate of each of the fourth and the fifth transistors.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 88.0
- Lexical Diversity: 2.91489
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15441078', '10950570', '11046128', '10237684', '14836805']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7493972267304154
- 35 USC 102 Novelty (BERT): 0.4641350124700116
- Combined Prediction Score: 0.7208710053043751
- Mean Citation Score: 150.68942199999995
- Max Citation Score: 156.52765
- Similarity Product: 116.86817604421972

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test