PATENT CLAIM ANALYSIS

Application Number: 15876500
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["712", "242000"]

Abstract:
Methods, circuitries, and systems for real-time protection of a stack are provided. A stack protection circuitry includes interface circuitry and computation circuitry. The interface is circuitry configured to receive a return instruction from a central processing unit (CPU). The computation circuitry is configured to, in response to the return instruction, generate protection data that i) identifies a new topmost return address location that is below a current protected topmost return address location and ii) specifies read only access for the new topmost return address location. The interface circuitry is configured to provide the protection data to a memory protection unit to cause the memory protection unit to enforce a read only access restriction on the new topmost return address location.

Claim (Index 6):
The stack protection circuitry of  claim 1 , further comprising the memory protection unit and a trap system, wherein the memory protection unit is configured to communicate an access violation to the trap system in response to an attempt to write access the new topmost return address location.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 2.25424
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13717315', '12263802', '11014111', '13285434', '11787832']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5524504802788462
- 35 USC 102 Novelty (BERT): 0.4625502738797541
- Combined Prediction Score: 0.5434604596389371
- Mean Citation Score: 152.95640199999997
- Max Citation Score: 156.08084
- Similarity Product: 118.28687728205205

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test