PATENT CLAIM ANALYSIS

Application Number: 15975023
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "288000"]

Abstract:
The present disclosure provides a trench power semiconductor component and a manufacturing method thereof. The trench gate structure of the trench power semiconductor component is located in the at least one cell trench that is formed in an epitaxial layer. The trench gate structure includes a shielding electrode, a gate electrode disposed above the shielding electrode, an insulating layer, an intermediate dielectric layer, and an inner dielectric layer. The insulating layer covers the inner wall surface of the cell trench. The intermediate dielectric layer interposed between the shielding electrode and the insulating layer has a bottom opening. The inner dielectric layer interposed between the shielding electrode and the intermediate dielectric layer is made of a material different from that of the intermediate dielectric layer, and fills the bottom opening so that the space of the cell trench beneath the shielding electrode is filled with the same material.

Claim (Index 10):
A method of manufacturing a trench power semiconductor component, comprising:\n forming an epitaxial layer on a substrate; forming a cell trench in the epitaxial layer; and forming a trench gate structure in the cell trench; wherein the step of forming the trench gate structure in the cell trench further includes:\n forming an insulating layer covering an inner wall surface of the cell trench; \n forming an intermediate dielectric layer and an inner dielectric layer in the cell trench, wherein the intermediate dielectric layer has a bottom opening located at a bottom of the cell trench, and the inner dielectric layer covers the intermediate dielectric layer and fills the bottom opening; \n forming a heavily doped semiconductor material in a lower half part of the cell trench; \n performing a thermal oxidation process so as to oxidize a top portion of the heavily doped semiconductor material, thereby forming an inter-electrode dielectric layer, in which another portions of the heavily-doped semiconductor material are remained un-oxidized form a shielding electrode; and \n forming a gate electrode in an upper half part of the cell trench, wherein the gate electrode is isolated from the shielding electrode by the inter-electrode dielectric layer.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 2.67797
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15186685', '15358182', '15005130', '14994250', '15189478']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.930195797248489
- 35 USC 102 Novelty (BERT): 0.5110849153547583
- Combined Prediction Score: 0.8882847090591159
- Mean Citation Score: 292.656842
- Max Citation Score: 318.15808
- Similarity Product: 274.84741805908203

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test