PATENT CLAIM ANALYSIS

Application Number: 15944032
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "171000"]

Abstract:
The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.

Claim (Index 21):
The structure of  claim 1 , further comprising:\n a fourth NMOS transistor which has a gate connected to the first row line and a source connected to a second reference data magnetic tunnel junction (reference data MTJ2); a fifth NMOS transistor which has a gate connected to the second row line and a source connected to a third data magnetic tunnel junction (data MTJ3) of the at least two data magnetic tunnel junctions; and a sixth NMOS transistor which has a gate connected to the third row line and a source connected to a fourth data magnetic tunnel junction (data MTJ4) of the at least two data magnetic tunnel junctions.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.24138
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13613205', '15636970', '12784848', '14970564', '13764139']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7543925819464266
- 35 USC 102 Novelty (BERT): 0.4797607175727554
- Combined Prediction Score: 0.7269293955090596
- Mean Citation Score: 180.946558
- Max Citation Score: 188.29303
- Similarity Product: 137.23311145143626

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test