PATENT CLAIM ANALYSIS

Application Number: 15878453
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["708", "505000"]

Abstract:
An arithmetic operation unit includes: a first multiplier configured to multiply two first input data to calculate first arithmetic data; a second multiplier configured to multiply two second input data to calculate second arithmetic data; a first adder configured to add the first arithmetic data and the second arithmetic data to calculate third arithmetic data; a first arithmetic selector configured to select one of the first arithmetic data and the third arithmetic data; a second arithmetic selector configured to select one of the second arithmetic data and the third arithmetic data; a second adder configured to add third input data and arithmetic data selected by the first arithmetic selector to calculate first arithmetic result data; and a third adder configured to add input fourth data and arithmetic data selected by the second arithmetic selector to calculate second arithmetic result data.

Claim (Index 5):
The arithmetic operation unit according to  claim 4 ,\n wherein when implementing one butterfly arithmetic operation in two divided operations, the first input selector is configured to alternately output input data received from the first memory and input data received from the second memory to the second adder in a first arithmetic operation and a second arithmetic operation; the second input selector is configured to output, to the third adder, input data identical with input data that the first input selector outputs to the second adder, out of input data received from the first memory and input data received from the second memory; the third input selector is configured to alternately output input data received from the third memory and input data received from the fourth memory to the first multiplier in the first arithmetic operation and the second arithmetic operation; the fourth input selector is configured to output, to the second multiplier, input data different from input data that the third input selector outputs to the first multiplier, out of input data received from the third memory and input data received from the fourth memory; the first arithmetic selector is configured to output the third arithmetic data received from the first adder to the second adder; and the second arithmetic selector is configured to output the third arithmetic data received from the first adder to the third adder, and when implementing product-sum operation, the first input selector is configured to output input data received from the first memory to the second adder; the second input selector is configured to output input data received from the second memory to the third adder; the third input selector is configured to output input data received from the third memory to the first multiplier; the fourth input selector is configured to output input data received from the fourth memory to the second multiplier; the first arithmetic selector is configured to output the first arithmetic data received from the first multiplier to the second adder; and the second arithmetic selector is configured to output the second arithmetic data received from the second multiplier to the third adder.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 4.625
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15204304', '10935193', '12772146', '15649406', '09487483']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4076671295600136
- 35 USC 102 Novelty (BERT): 0.4847261043522455
- Combined Prediction Score: 0.4153730270392368
- Mean Citation Score: 174.214814
- Max Citation Score: 192.78731
- Similarity Product: 155.98987224321246

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test