PATENT CLAIM ANALYSIS

Application Number: 15753100
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["257", "291000"]

Abstract:
The present disclosure relates to a solid-state imaging element and an electronic apparatus, in which the number of wires controlling readout can be reduced in a case where a pixel signal of each pixel is read out in a predetermined order for each unit pixel region. The unit pixel region is configured by a plurality of pixels arranged in an array. A readout circuit is provided for each unit pixel region and reads out, in a predetermined order, pixel signals of the plurality of pixels configuring the unit pixel regions. Pixel drive wires, which control readout of the pixels configuring the unit pixel regions adjacent in the vertical direction and having the same readout order, are shared. The present disclosure can be applied to, for example, a CMOS image sensor and the like.

Claim (Index 11):
The solid-state imaging element according to  claim 1 ,\n wherein the unit pixel regions are formed in a first chip, the readout circuit is formed in a second chip, and the first chip and the second chip are configured to be connected to each of the unit pixel regions.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 88.0
- Lexical Diversity: 2.13235
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14767055', '16092062', '12091138', '13473082', '14529573']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.907797094406493
- 35 USC 102 Novelty (BERT): 0.483751318757145
- Combined Prediction Score: 0.8653925168415583
- Mean Citation Score: 188.81433
- Max Citation Score: 191.67963
- Similarity Product: 149.05386011548163

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test