PATENT CLAIM ANALYSIS

Application Number: 15976856
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "071000"]

Abstract:
A display panel including a display region and a non-display region, a plurality of gate lines, a plurality of data lines, a pixel array and a gate on array circuit. The non-display region is located at one side of the display region. The plurality of gate lines and the plurality of data lines are disposed in the display region. The pixel array is located in the display region, wherein the pixel array is composed of a plurality of pixel units that are repeatedly arranged. The pixel units consist of three gate lines, two data lines and six sub-pixels, and each sub-pixel is electrically connected to one of the gate lines and one of the data lines located in the pixel array respectively. The gate on array circuit is disposed in the pixel array.

Claim (Index 12):
The display panel according to  claim 2 , wherein each of the plurality of driving units comprises seven active elements, wherein the plurality of signal lines have a power signal line, a first clock signal line, a second clock signal line, a pre-stage input line, a post-stage input line and an output line.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 3.15217
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14788553', '13969618', '15924830', '13447309', '15180220']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9265286676231744
- 35 USC 102 Novelty (BERT): 0.5091050985085885
- Combined Prediction Score: 0.884786310711716
- Mean Citation Score: 234.40719
- Max Citation Score: 243.18643
- Similarity Product: 150.3670595304191

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test