PATENT CLAIM ANALYSIS

Application Number: 15873006
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-11
Patent Classification: ["257", "401000"]

Abstract:
Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

Claim (Index 1):
A semiconductor structure comprising:\n a semiconductor fin having a first top surface and first opposing sides; an isolation region in the semiconductor fin, the isolation region having a second top surface that is substantially co-planar with the first top surface of the semiconductor fin and further having second opposing sides; an isolation bump on the second top surface of the isolation region and having a third top surface; a bump sidewall spacer positioned laterally adjacent to the isolation bump and having at least an outer portion above and immediately adjacent to the first top surface of the semiconductor fin; a non-functional gate structure above and immediately adjacent to the third top surface of the isolation bump; a transistor comprising:\n a channel region within the semiconductor fin; \n a functional gate structure adjacent to the first top surface and the first opposing sides of the semiconductor fin at the channel region; and \n a source/drain region in the semiconductor fin between the channel region and the isolation region, the source/drain region having a first side adjacent to the channel region and a second side opposite the first side and physically separated from the isolation region; and \n gate sidewall spacers positioned laterally adjacent to the non-functional gate structure and the functional gate structure, wherein a gate sidewall spacer positioned laterally adjacent to the non-functional gate is above and immediately adjacent to the third top surface of the isolation bump and further extends laterally onto the bump sidewall spacer.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 86.0
- Lexical Diversity: 2.07895
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15589292', '15487636', '15387933', '15862064', '15658835']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9298669754929224
- 35 USC 102 Novelty (BERT): 0.569313972658555
- Combined Prediction Score: 0.8938116752094858
- Mean Citation Score: 360.567114
- Max Citation Score: 473.23163
- Similarity Product: 392.24515926231385

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test