PATENT CLAIM ANALYSIS

Application Number: 15917218
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["455", "083000"]

Abstract:
A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Claim (Index 1):
A multiple-MOSFET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the circuit comprising:\n a. a series transistor stack of J MOSFETs M N , N being an integer between 1 and J and J being an integer 2 or greater, each MOSFET M N  having a source S N , a gate G N  and a drain D N , b. an input signal node connected to the gate G 1  of a signal-input MOSFET M 1  of the MOSFET stack; c. for 0<N<J, a series coupling between each drain D N  and the source S (N+1)  of a next higher MOSFET M (N+1)  of the MOSFET transistor stack; d. for 1<N\u2264J, a gate coupling element that is predominately capacitive connected directly between each gate G N  and Vref, wherein, for 1<N\u2264J, each MOSFET M N  is biased to avoid exceeding breakdown characteristics of the FET M N ; and where each gate G N  is provided with a suitable bias voltage, and wherein the bias voltage is decoupled to Vref; e. a source coupling for the FET stack between S 1  and Vref; and f. a drain coupling for the FET stack between D 1  and Vdrive; wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M 2  to M N  has associated and corresponding bias voltages VB 2  to VB N , wherein the bias voltages VB 2  to VB N  may be individually selected to adjust the DC voltage divided across each corresponding and associated MOSFET M 2  to M N , and wherein the divided DC voltage across each MOSFET M 2  to M N  may be controlled by the bias voltages VB 2  to VB N  to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 1.92
- Patent Class: 455.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14052680', '14177062', '15586007', '11501125', '12903848']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6761938421570164
- 35 USC 102 Novelty (BERT): 0.5974891712415198
- Combined Prediction Score: 0.6683233750654668
- Mean Citation Score: 470.212596
- Max Citation Score: 514.64996
- Similarity Product: 470.23188741095305

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test