PATENT CLAIM ANALYSIS

Application Number: 16054465
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["365", "174000"]

Abstract:
A semiconductor memory device includes a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array; and a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively. The global lines are disposed in first direction pitches of some pass transistors among the pass transistors.

Claim (Index 9):
The semiconductor memory device according to  claim 5 , wherein the metal lines comprise:\n power lines configured to transmit power; and signal lines configured to transmit signals other than power.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 2.02222
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15856933', '15091702', '15885328', '14219811', '15951692']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8092892118903889
- 35 USC 102 Novelty (BERT): 0.4728741827439879
- Combined Prediction Score: 0.7756477089757489
- Mean Citation Score: 196.516338
- Max Citation Score: 217.06566
- Similarity Product: 177.30135256731748

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test