PATENT CLAIM ANALYSIS

Application Number: 16166636
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["438", "199000"]

Abstract:
A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source.

Claim (Index 17):
The 3D semiconductor device according to  claim 15 ,\n wherein each of said junction-less transistors (JLT) comprise a JLT channel, a JLT drain, and a JLT source, and wherein said JLT channel, said JLT drain, and said JLT source comprise the same dopant type.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 2.91837
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15950169', '16004404', '16115519', '15990684', '12963659']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8879258055097494
- 35 USC 102 Novelty (BERT): 0.5258188677853454
- Combined Prediction Score: 0.851715111737309
- Mean Citation Score: 326.651402
- Max Citation Score: 351.8785
- Similarity Product: 301.4307587124705

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test