PATENT CLAIM ANALYSIS

Application Number: 16110203
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "206000"]

Abstract:
A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Claim (Index 7):
A semiconductor device comprising:\n a plurality of cell arrays arranged sequentially in a first direction, each of the plurality of cell arrays including a plurality of gates extending in the first direction and arranged in a second direction orthogonal to the first direction, wherein each of the plurality of cell arrays includes a first conductive type well region and a second conductive type region extending in the second direction and formed below the plurality of gates, wherein a first cell array of the plurality of cell arrays includes:\n a first well potential supply region in the first conductive type well region, the first well potential supply region including impurities of the same conductive type as the first conductive type well region; \n a second potential supply region in the second conductive type region, the second potential supply region including impurities of the same conductive type as the second conductive type region; \n a first impurity region in the second conductive type region, the first impurity region including impurities of the same conductive type as the first conductive type well region; and \n first, second and third adjacent gates of the plurality of gates, the first, second and third adjacent gates being disposed at the same pitch in the second direction, \n wherein a portion of the first well potential supply region is disposed between the first adjacent gate and the second adjacent gate, and the third adjacent gate is disposed adjacent to the first adjacent gate, and a portion of the first impurity region is disposed between the first adjacent gate and the second adjacent gate, and wherein a second cell array of the plurality of cell arrays adjacent to the first cell array in the first direction includes:\n a third well potential supply region in the first conductive type well region, the third well potential supply region including impurities of the same conductive type as the first conductive type well region; \n a fourth potential supply region in the second conductive type region, the fourth potential supply region including impurities of the same conductive type as the second conductive type region; and \n fourth, fifth and sixth adjacent gates, the fourth, fifth and sixth adjacent gates being opposed to the first, second and third adjacent gates of the first cell array in the first direction, respectively.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 96.0
- Lexical Diversity: 1.97959
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15651818', '15147656', '14179556', '14576158', '13421010']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9343115636684504
- 35 USC 102 Novelty (BERT): 0.5306269961469066
- Combined Prediction Score: 0.893943106916296
- Mean Citation Score: 362.713996
- Max Citation Score: 369.9488
- Similarity Product: 365.7529991195679

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test