PATENT CLAIM ANALYSIS

Application Number: 15777855
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["257", "737000"]

Abstract:
A microelectronic structure ( 200 ) and a fabrication method of microelectronic are described. A first package ( 10 ) has a first conductive pad ( 40, 41, 47, 48 ) formed on a first foundation layer ( 12 ). A loop of conductive wire ( 50 - 53 ) is wirebonded to the first conductive pad (( 40, 41, 47, 48 ) of the first foundation layer ( 12 ). A mold cap ( 70 ) is formed on the first foundation layer ( 12 ). A via ( 90 - 93 ) is formed in the mold cap ( 70 ) to reach the conductive wire ( 50 - 53 ). A solder structure ( 80 - 83 ) is coupled to the conductive wire ( 50 - 53 ). A second package ( 100 ) is connected to the first package ( 10 ) by attaching a second solder structure ( 110 - 113 ) of a second package ( 100 ) to the first solder structure ( 80 - 83 ) of the first package ( 10 ).

Claim (Index 3):
The microelectronic structure of  claim 1 , wherein the first foundation layer comprises a circuit board.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 3.37931
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13929240', '13174066', '13456886', '10952172', '10695356']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9142076957511798
- 35 USC 102 Novelty (BERT): 0.5047635605052958
- Combined Prediction Score: 0.8732632822265914
- Mean Citation Score: 217.300126
- Max Citation Score: 223.29552
- Similarity Product: 150.1878549413109

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test