PATENT CLAIM ANALYSIS

Application Number: 15909622
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["257", "256000"]

Abstract:
An electronic device can include a JFET that overlies a substrate and includes a first well region including a drain region or a source region, or both, and a second well region having the opposite the conductivity type. The second well region can be disposed within the first well region and includes a gate electrode of the JFET. Embodiments as described herein can be used to form a JFET integrated with n-channel and p-channel MISFETs without having to add an additional mask or other process operation to an existing process flow.

Claim (Index 2):
The electronic device of  claim 1 , wherein the portion of the first metal-insulator-semiconductor field-effect transistor includes a channel region within the third well region, wherein the third well region has the second conductivity type.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.68421
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15254837', '14540137', '13782122', '15666814', '12822992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9239852518248024
- 35 USC 102 Novelty (BERT): 0.4820270510560316
- Combined Prediction Score: 0.8797894317479253
- Mean Citation Score: 207.696632
- Max Citation Score: 216.07092000000003
- Similarity Product: 172.6491447080183

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test