PATENT CLAIM ANALYSIS

Application Number: 15985957
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["257", "782000"]

Abstract:
A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.

Claim (Index 16):
A semiconductor device comprising:\n a semiconductor chip having a first front surface to which a first electrode and a second electrode are exposed and a first rear surface which is located on the opposite side of the first front surface and over which a third electrode is formed; a chip mounting part having a second front surface over which the semiconductor chip is mounted and a second rear surface which is located on the opposite side of the second front surface; a first lead which is electrically coupled to the first electrode of the semiconductor chip via a first conductive member; a second lead which is electrically coupled to the second electrode of the semiconductor chip via a second conductive member; and a sealing body which seals the semiconductor chip, the first conductive member, the second conductive member, part of the chip mounting part, part of the first lead and part of the second lead, wherein the first rear surface of the semiconductor chip faces the second front surface of the chip mounting part with a first bonding material and a second boding material being interposed, wherein the second front surface of the chip mounting part has a plurality of first regions in which the first bonding material is located and a second region which is located between/among the respective first regions and in which the second bonding material is located in a planar view, wherein the semiconductor chip has a first side which extends in a first direction, a second side which is located on the opposite side of the first side and extends in the first direction, a third side which extends in a second direction which intersects the first direction and a fourth side which is located on the opposite side of the third side and extends in the second direction in the planar view, wherein the semiconductor chip further has a first corner at which the first side and the third side intersect each other, a second corner at which the third side and the second side intersect each other, a third corner at which the second side and the fourth side intersect each other and a fourth corner at which the fourth side and the first side intersect each other in the planar view, and wherein part of each of the first corner, the second corner, the third corner and the fourth corner is located in each of the first regions in the planar view.

Metadata:
- Claim Count in Document: 52.0
- Percentile: 93.0
- Lexical Diversity: 2.46429
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13639509', '12147676', '13196171', '14252740', '13490459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9029191184738647
- 35 USC 102 Novelty (BERT): 0.494617908241638
- Combined Prediction Score: 0.8620889974506422
- Mean Citation Score: 228.164784
- Max Citation Score: 243.84782
- Similarity Product: 198.57950922775987

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test