PATENT CLAIM ANALYSIS

Application Number: 15918431
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["324", "750300"]

Abstract:
To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.

Claim (Index 2):
A semiconductor device according to  claim 1 , further comprising:\n a second circuit under test; a second test pattern generator configured to generate a second test pattern to be supplied to the second circuit under test; and a second output response analyzer configured to compare an expected value to a test result of the second circuit under test, the test result being obtained as a result of supply of the second test pattern generated by the second test pattern generator to the second circuit under test, the first test control circuit being configured to perform a test in the first test mode by controlling the second test pattern generator and the second output response analyzer to cause the second test pattern to be supplied to the second circuit under test, a second test control circuit different from the first test control circuit being configured to perform a test in the second test mode by controlling the second test pattern generator and the second output response analyzer to cause the second test pattern to be supplied to the second circuit under test.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 90.0
- Lexical Diversity: 2.96
- Patent Class: 324.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11188159', '13327847', '15508168', '10516583', '13062937']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5459412437103744
- 35 USC 102 Novelty (BERT): 0.4721565894788808
- Combined Prediction Score: 0.5385627782872251
- Mean Citation Score: 160.007132
- Max Citation Score: 179.1672
- Similarity Product: 129.60609183912277

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test