PATENT CLAIM ANALYSIS

Application Number: 16026946
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["326", "029000"]

Abstract:
Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

Claim (Index 26):
The integrated circuit of  claim 23 , wherein the one or more second latches comprise one or more second phase-two latches.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 95.0
- Lexical Diversity: 3.29787
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14836657', '15490352', '14849902', '12551874', '15368480']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.681005438814397
- 35 USC 102 Novelty (BERT): 0.4883161542453152
- Combined Prediction Score: 0.6617365103574888
- Mean Citation Score: 186.287808
- Max Citation Score: 199.45488
- Similarity Product: 132.7289334508896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test