PATENT CLAIM ANALYSIS

Application Number: 16233210
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["174", "260000"]

Abstract:
A printed wiring board includes a core substrate having cavity to accommodate an electronic component and including a front conductor layer formed on front side of the core substrate, and a back conductor layer formed on back side of the core substrate, through-hole conductors formed through the core substrate such that the through-hole conductors connect the front and back conductor layers of the core substrate, a front build-up layer formed on front surface of the core substrate and including interlayer insulating layers and conductor layers, and a back build-up layer formed on back surface of the core substrate and including interlayer insulating layers and conductor layers. The conductor layers in the front build-up layer include a conductor layer sandwiching one of the interlayer insulating layers with the front conductor layer such that the conductor layer and the front conductor layer have the same electric potential in region surrounding the cavity.

Claim (Index 5):
The printed wiring board according to  claim 2 , wherein the first conductor layer formed in each of the front and back conductor layers of the core substrate is formed in a plurality such that the plurality of first conductor layers has adjacent first conductor layers having different electric potentials.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 98.0
- Lexical Diversity: 3.05882
- Patent Class: 174.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14857074', '14700313', '15609435', '14713064', '13685777']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8655330654473044
- 35 USC 102 Novelty (BERT): 0.501662507806789
- Combined Prediction Score: 0.8291460096832529
- Mean Citation Score: 271.517408
- Max Citation Score: 288.2922
- Similarity Product: 238.228808463192

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test