PATENT CLAIM ANALYSIS

Application Number: 15984071
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["711", "166000"]

Abstract:
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.

Claim (Index 34):
The method of  claim 31  wherein the scanning of only the first portion of the physical mapping is performed in a startup operation of the storage device.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 93.0
- Lexical Diversity: 2.50794
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14518560', '11801745', '14941517', '13239474', '13196820']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5217073841236985
- 35 USC 102 Novelty (BERT): 0.5452964091424013
- Combined Prediction Score: 0.5240662866255689
- Mean Citation Score: 201.673712
- Max Citation Score: 440.72345
- Similarity Product: 242.5258861241609

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test