PATENT CLAIM ANALYSIS

Application Number: 15748651
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "433000"]

Abstract:
A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.

Claim (Index 9):
A packaging method, comprising:\n providing a wafer to be packaged, wherein a first surface of the wafer to be packaged is provided with a plurality of chip units and sawing lane regions located between the chip units, and the chip units comprise sensing regions; providing a cover substrate, wherein a plurality of groove structures are formed on a first surface of the cover substrate, and the groove structures correspond to the sensing regions on the wafer to be packaged; attaching the first surface of the cover substrate with the first surface of the wafer to be packaged, wherein cavities are formed by the groove structures and the first surface of the wafer to be packaged, and the sensing regions are located within the cavities; cutting the wafer to be packaged and the cover substrate along the sawing lane regions, to form a plurality of chip package structures, wherein the chip package structure comprises the chip unit and an upper cover plate structure which is located on the chip unit and formed by cutting the cover substrate, the upper cover plate structure comprises a first surface on a side on which the chip unit is located and a second surface opposite to the first surface, and the cutting causes an area of the second surface of the upper cover plate structure to be less than an area of the first surface of the upper cover plate structure.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 3.32558
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15507901', '14450143', '15549987', '15765802', '15765968']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.913300353083662
- 35 USC 102 Novelty (BERT): 0.4771225278249022
- Combined Prediction Score: 0.869682570557786
- Mean Citation Score: 194.468208
- Max Citation Score: 203.85362
- Similarity Product: 160.61315072854998

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test