PATENT CLAIM ANALYSIS

Application Number: 15969855
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "288000"]

Abstract:
Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets.

Claim (Index 1):
A method of fabricating a semiconductor device, the method comprising:\n performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate; wherein the fabrication operations include:\n forming a gate spacer along a gate region of the nanosheet FET device; \n forming channel nanosheets to a desired final channel nanosheet width dimension (Wf) for each of the channel nanosheets; and \n forming an inner spacer between the channel nanosheets; wherein the gate spacer and the inner spacer comprise the same type of spacer material; wherein forming the gate spacer and the inner spacer comprises, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material having a first thickness dimension to extend along a sidewall of the gate region, sidewalls of the channel nanosheets, and within a space between the channel nanosheets; wherein forming the gate spacer further comprises trimming a portion of the layer of the spacer material that is along the sidewall of the gate region such that the portion of the spacer layer that is along the sidewall of the gate region comprises a second thickness dimension that is less than the first thickness dimension; wherein the gate spacer comprises the portion of the layer of the spacer material that comprises the second thickness dimension and is along the sidewall of the gate region; wherein the inner spacer comprises a portion of the layer of the spacer material that is within the space between the channel nanosheets.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 93.0
- Lexical Diversity: 2.74138
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15944322', '15926664', '15924799', '15468755', '15629306']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9283461282329664
- 35 USC 102 Novelty (BERT): 0.5469381565296562
- Combined Prediction Score: 0.8902053310626352
- Mean Citation Score: 350.451002
- Max Citation Score: 408.97647
- Similarity Product: 345.99183300405986

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test