PATENT CLAIM ANALYSIS

Application Number: 16423242
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["716", "114000"]

Abstract:
Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Claim (Index 2):
The method of  claim 1 , further comprising continuing to prune solutions from the set of solutions until a target number of solutions remains.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.17778
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15630343', '15848053', '15896176', '16423391', '10255469']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3946586554009146
- 35 USC 102 Novelty (BERT): 0.5521573945940934
- Combined Prediction Score: 0.4104085293202325
- Mean Citation Score: 374.114172
- Max Citation Score: 443.37048
- Similarity Product: 429.56087110613817

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test