PATENT CLAIM ANALYSIS

Application Number: 16049693
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["365", "193000"]

Abstract:
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Claim (Index 21):
The apparatus of  claim 19 , wherein the apparatus is configured such that the determination of the DQS delay element delay tap setting of the DQS delay element is performed before the capture clock delay tap setting is determined.

Metadata:
- Claim Count in Document: 80.0
- Percentile: 95.0
- Lexical Diversity: 2.11475
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15996365', '15926902', '15722209', '13172740', '14882226']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.871079600824494
- 35 USC 102 Novelty (BERT): 0.6317482089249559
- Combined Prediction Score: 0.8471464616345402
- Mean Citation Score: 599.8854240000003
- Max Citation Score: 637.52344
- Similarity Product: 547.7558842062758

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test