PATENT CLAIM ANALYSIS

Application Number: 16029577
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["326", "098000"]

Abstract:
A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Claim (Index 1):
A plurality of dynamic decode circuits, each dynamic decode circuit connected between a first power source and a second power source, the each dynamic decode circuit comprising a respective decoder, a respective first node, a respective second node and a respective third node,\n wherein each decoder is configured to decode a respective plurality of input signals, wherein the each decoder is conductively connected to the respective first node and to the respective third node, wherein the each dynamic decode circuit further comprises one or more respective evaluate transistors, wherein the one or more evaluate transistors are connected to the first power source, wherein the one or more evaluate transistors are configured to evaluate a respective dynamic logic during an evaluate phase of the dynamic logic, wherein each of the one or more evaluate transistors are configured to conduct at the same time based on the same evaluation clock signal, wherein the each dynamic decode circuit further comprises one or more respective precharge circuits, each precharge circuit connected to the second power source, the each precharge circuit configured to precharge a respective node in a precharge phase of the dynamic logic, wherein each first node is connected to a respective precharge circuit, wherein each the third node is connected to a respective evaluate transistor, wherein the each dynamic decode circuit further comprises a respective conditioning circuit configured to condition a shared node of the dynamic decode circuit, the shared node shared by the each dynamic decode circuit of the plurality of dynamic decode circuits, wherein each conditioning circuit is connected in parallel between the shared node and a common power source and wherein the each conditioning circuit is any one of a precharge circuit and an evaluate transistor.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 95.0
- Lexical Diversity: 1.91111
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15796819', '15613185', '15274322', '11050895', '11050933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7230263462691842
- 35 USC 102 Novelty (BERT): 0.5731424352432448
- Combined Prediction Score: 0.7080379551665902
- Mean Citation Score: 381.345018
- Max Citation Score: 480.05124000000006
- Similarity Product: 460.47308709913017

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test