PATENT CLAIM ANALYSIS

Application Number: 16059255
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["365", "156000"]

Abstract:
A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Claim (Index 24):
The semiconductor integrated circuit according to  claim 21 ,\n wherein the first and second signals set the memory cell array to a second state in which the first N-channel transistor is set to an OFF state and the second N-channel transistor is set to an ON state.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 2.55172
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15648702', '15050074', '14490461', '14692566', '12855691']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9184697114656672
- 35 USC 102 Novelty (BERT): 0.6595254604578815
- Combined Prediction Score: 0.8925752863648887
- Mean Citation Score: 752.337168
- Max Citation Score: 758.0986
- Similarity Product: 629.3404391169788

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test