PATENT CLAIM ANALYSIS

Application Number: 15862397
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "185130"]

Abstract:
A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

Claim (Index 1):
A method for reading a memory cell of a non-volatile memory device provided with a memory array with memory cells arranged in wordlines and bitlines, the bitlines including a first bitline associated with the memory cell to be read and a second bitline distinct from the first bitline, wherein a first circuit branch is associated to the first bitline and a second circuit branch is associated to the second bitline, each of the first and second circuit branches having a local node and a global node, each local node coupled to a first dividing capacitor, each global node coupled to a second dividing capacitor, the method comprising:\n pre-charging the global nodes and the local nodes to a pre-charging voltage; equalizing the global nodes by coupling the global nodes of the first circuit branch and the second circuit branch so that the global nodes reach a common initial voltage; and reading a datum stored in the memory cell by:\n coupling the local node of the first circuit branch to the first bitline and to the memory cell so that a respective voltage value discharges as a function of the datum stored; \n coupling the local node to the global node to generate a charge division between the first dividing capacitor and the second dividing capacitor so that the voltage of the global node goes to a value that is different from the common initial voltage as a function of the datum stored; and \n generating an output signal based upon a comparison between a first comparison voltage that is a function of the voltage of the global node of the first circuit branch, and a second comparison voltage that is a function of the voltage of the global node of the second circuit branch.

Metadata:
- Claim Count in Document: 15.0
- Percentile: 86.0
- Lexical Diversity: 2.72414
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15275362', '15212211', '13746653', '15475609', '12883072']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7952239152385948
- 35 USC 102 Novelty (BERT): 0.5280283221829678
- Combined Prediction Score: 0.7685043559330321
- Mean Citation Score: 253.401934
- Max Citation Score: 376.0495
- Similarity Product: 355.41705007815364

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test