PATENT CLAIM ANALYSIS

Application Number: 15939211
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-05
Patent Classification: ["257", "774000"]

Abstract:
A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

Claim (Index 20):
The interconnect of  claim 16 , wherein the width is approximately 15 nm or less.

Metadata:
- Claim Count in Document: 8.0
- Percentile: 90.0
- Lexical Diversity: 2.39344
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15812033', '11364953', '12869113', '15870213', '15262231']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9232233858307922
- 35 USC 102 Novelty (BERT): 0.495108960259887
- Combined Prediction Score: 0.8804119432737016
- Mean Citation Score: 166.85100000000003
- Max Citation Score: 178.15816
- Similarity Product: 114.726484312253

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test