PATENT CLAIM ANALYSIS

Application Number: 16250343
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-10
Patent Classification: ["711", "100000"]

Abstract:
A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Claim (Index 13):
A memory system comprising:\n the memory controlling device of  claim 1 ; the first memory module; and the second memory module.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 99.0
- Lexical Diversity: 2.2
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12035398', '13629172', '15398775', '14253785', '12901452']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5253914529623006
- 35 USC 102 Novelty (BERT): 0.5088911806673085
- Combined Prediction Score: 0.5237414257328015
- Mean Citation Score: 237.64096
- Max Citation Score: 244.80775
- Similarity Product: 145.51058661076428

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test