PATENT CLAIM ANALYSIS

Application Number: 16000536
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["375", "229000"]

Abstract:
A transmitter may include a driver having a PMOS transistor and an NMOS transistor connected in series between a first power supply and a second power supply. The driver may be configured to output an output signal. The transmitter may further include a driver control circuit configured to control a gate voltage of the PMOS transistor and a gate voltage of the NMOS transistor based on a level of a data signal, an occurrence of a level transition of the data signal, and a direction of the level transition of the data signal.

Claim (Index 4):
The transmitter of  claim 3 , wherein the first equalization controller provides the gate of the PMOS transistor with a first equalization voltage lower than the voltage of the second power supply when the data signal transitions from the low level to the high level, and wherein the second equalization controller provides the gate of the NMOS transistor with a second equalization voltage higher than the voltage of the first power supply when the data signal transitions from the high level to the low level.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 94.0
- Lexical Diversity: 2.33333
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15205420', '15902969', '11421318', '14305804', '13292244']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5356155212160235
- 35 USC 102 Novelty (BERT): 0.4907887992380862
- Combined Prediction Score: 0.5311328490182298
- Mean Citation Score: 224.657978
- Max Citation Score: 233.04462
- Similarity Product: 177.7833497486329

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test