PATENT CLAIM ANALYSIS

Application Number: 15873225
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["716", "118000"]

Abstract:
Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).

Claim (Index 15):
A manufacturing system comprising:\n electronic storage maintaining an original integrated circuit (IC) design, wherein a smallest spacing between elements in the original IC design is an original minimum spacing, and the original IC design utilizes multiple lithographic masks to land vias on conductive structures; a processor operatively connected to the electronic storage, wherein the processor automatically converts the original IC design to a reduced IC design, wherein a smallest spacing between elements in the reduced IC design is a reduced minimum spacing that is less than the original minimum spacing, and the reduced IC design utilizes a single lithographic mask to land the same vias on the same conductive structures in the original IC design, wherein the processor automatically measures unaltered spacing of the vias in the reduced IC design in locations where the vias were located in the original IC design, wherein the processor automatically replaces a single via in the original IC design with multiple vias in the reduced IC design in areas where the single via was located in the original IC design, if the unaltered spacing around the single via equals or exceeds a first spacing measure, and wherein the processor automatically replaces the single via in the original IC design with a via bar in the reduced IC design in areas where the single via was located in the original IC design, if the unaltered spacing around the single via is between the reduced minimum spacing and the first spacing measure; and manufacturing equipment operatively connected to the processor, wherein the manufacturing equipment manufactures ICs using the reduced IC design.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 3.06122
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10726140', '10604962', '11403332', '15624764', '11780459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3290533738771027
- 35 USC 102 Novelty (BERT): 0.4663022667197286
- Combined Prediction Score: 0.3427782631613653
- Mean Citation Score: 172.27488799999998
- Max Citation Score: 181.86337
- Similarity Product: 125.14512431928276

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test