PATENT CLAIM ANALYSIS

Application Number: 15984187
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["365", "145000"]

Abstract:
A plate line segment selector circuit, coupled to a plate line segment, a plate line and a word line, may include (a) a P-channel transistor having a gate terminal connected to the plate line, a source terminal connected to the word line, and a drain terminal connected to the plate line segment; and (b) a N-channel transistor having a gate terminal connected to the plate line, a drain terminal connected to the plate line, and a source terminal connected to a ground reference voltage source. Alternatively, the plate line segment selector circuit may include: (a) a P-channel transistor having a gate terminal connected to the plate line, a source terminal connected to a predetermined voltage source, and a drain terminal; (b) a N-channel transistor having a gate terminal connected to the plate line, a source terminal connected to a ground reference voltage source, and a drain terminal; and (c) a field effect transistor having a gate terminal connected to the word line, a first drain or source terminal connected to the drain terminals of the P-channel and N-channel transistors and a second drain or source terminal connected to the plate line segment.

Claim (Index 4):
A ferroelectric memory circuit, comprising:\n one or more arrays of memory cells, each organized into a plurality of rows and a plurality of columns; a plurality of groups of bit lines, each group having associated with multiple adjacent columns, and each bit line in each group coupled to memory cells of a different one of the group's associated adjacent columns; a plurality of word lines, each providing a control signal to an associated rows of memory cells in one or more of the memory arrays; a plurality of plate lines, each plate line serving memory cells of a different one of the groups of bit lines; a plurality of plate line segments each providing a voltage to an associated row of memory cells in an associated array; and a plurality of plate line segment selector circuits each coupled to an associated plate line segment, an associated plate line and an associated word line, each plate line segment selector circuit comprising:\n a P-channel transistor having a gate terminal connected to the associated plate line, a source terminal connected to a predetermined voltage source, and a drain terminal; \n a N-channel transistor having a gate terminal connected to the associated plate line, a source terminal connected to a predetermined voltage source, and a drain terminal; and \n a field effect transistor having a gate terminal connected to the word line, a first drain or source terminal connected to the drain terminals of the P-channel and N-channel transistors, and a second drain or source terminal connected to the plate line segment.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 5.02273
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['10988673', '10403120', '11134332', '10120146', '11417154']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8028287981951441
- 35 USC 102 Novelty (BERT): 0.4813309698006277
- Combined Prediction Score: 0.7706790153556924
- Mean Citation Score: 236.255204
- Max Citation Score: 253.19063
- Similarity Product: 211.3405399811554

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test