PATENT CLAIM ANALYSIS

Application Number: 15963440
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-11
Patent Classification: ["385", "014000"]

Abstract:
An active optoelectronic optical engine layer is assembled on a SOI silicon substrate side, including multiple VCSEL input ports and multiple PD output ports. Each passive straight silicon waveguide terminated with two 45 degree reflectors is fabricated on the silicon-on-oxide surface of the SOI substrate to form an optical path to transmit optical signals from the VCSEL lasers to photodetectors. The active and passive sides are designed and developed as an on-chip optical interconnect module to carry high-speed electrical traces, Improved RF performance is achieved. A method of fabricating the device is disclosed as: on the substrate surface, patterning a plurality of conductive lines and the optical engine has an emitter (VCSEL) and a receiver (PD); on the SOI device layer, patterning a straight portion and two 45 degree end reflectors as the silicon waveguide and align the two 45 degree end reflectors with active optical devices VCSEL and PD.

Claim (Index 15):
The optical interconnect apparatus of  claim 1 , wherein the conductive lines are high speed RF transmission lines capable of operating at 25 Gbps per channel.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 1.92941
- Patent Class: 385.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15963665', '15963780', '15963815', '15963030', '15963014']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8487544756598677
- 35 USC 102 Novelty (BERT): 0.5391491112655812
- Combined Prediction Score: 0.8177939392204391
- Mean Citation Score: 324.317172
- Max Citation Score: 384.9688
- Similarity Product: 366.430554846096

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test