PATENT CLAIM ANALYSIS

Application Number: 15881022
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "774000"]

Abstract:
A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

Claim (Index 12):
A semiconductor package comprising\n a first substrate, a plurality of low-k dielectric layers overlying the first substrate; a passivation layer overlying the plurality of low-k dielectric layers, the passivation layer comprising a non-low-k dielectric material; a plurality of seal ring structures disposed in the plurality of low-k dielectric layers, the plurality of seal ring structures comprising alternating layers of metal lines and metal vias; a first group of dummy bumps comprising a plurality of dummy bump connectors, the first group of dummy bumps disposed over a top surface of the first substrate in a first corner of the first substrate, the first corner being disposed immediately adjacent two intersecting edges of the first substrate; a second group of dummy bumps comprising one or more dummy bump connectors, the second group of dummy bumps disposed over the top surface of the first substrate in a second corner of the first substrate, the second corner being disposed immediately adjacent two intersecting edges of the first substrate, wherein the first and second groups of dummy bumps are disposed in different corners of the first substrate; a plurality of active bump connectors disposed over the top surface of the first substrate; an outer seal ring structure of the plurality of seal ring structures, the outer seal ring structure disposed around a periphery of the first substrate; a first seal ring structure of the plurality of seal ring structures, the first seal ring structure disposed around the first group of dummy bumps, wherein the first seal ring structure encircles all of the first group of dummy bumps in top down view such that the first group of dummy bumps are disposed within a single continuous seal ring structure; a second seal ring structure of the plurality of seal ring structures, the second seal ring structure disposed around the second group of dummy bumps, wherein the second seal ring structure encircles all of the second group of dummy bumps in top down view such that the second group of dummy bumps are disposed within a single continuous seal ring structure, wherein the passivation layer is interposed between the dummy bump connectors and the plurality of low-k dielectric layers, and wherein each the plurality of active bump connectors are electrically coupled to a corresponding device in the first substrate.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 3.51351
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12915170', '12953130', '14730231', '13712665', '15232959']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9116722293269444
- 35 USC 102 Novelty (BERT): 0.4710671768847171
- Combined Prediction Score: 0.8676117240827217
- Mean Citation Score: 169.65573200000003
- Max Citation Score: 172.6217
- Similarity Product: 131.05295018836262

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test