PATENT CLAIM ANALYSIS

Application Number: 15978497
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "782000"]

Abstract:
A semiconductor device ( 100 ) comprising a leadframe ( 120 ) having an assembly pad ( 121 ) in a first horizontal plane ( 180 ), the pad's first surface ( 121 a ) with a semiconductor chip ( 110 ) attached; further a plurality of leads ( 122 ) in a parallel second horizontal plane ( 190 ) offset from the first plane in the direction of the attached chip, the leads having a third surface ( 122 a ) with bonding wires, and an opposite fourth surface ( 122 b ); a package ( 140 ) encapsulating leadframe, chip, and wires, the package having a fifth surface ( 140 a ) parallel to the first and second planes; a plurality of recess holes ( 150 ) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder ( 160 ) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Claim (Index 17):
A semiconductor device comprising:\n a lead frame including a die attach pad, the die attach pad including a first surface and an opposite second surface; a semiconductor chip attached to the die attach pad and electrically connected to a plurality of leads, each of the plurality of leads including a first lead surface, a second lead surface opposite to the first lead surface, a third lead surface and a fourth lead surface opposite to the third lead surface, wherein a plane along the third lead surface is below a plane along the first lead surface, and a plane along the fourth lead surface is below a plane along the second lead surface, the semiconductor chip including a third surface and an opposite fourth surface, the opposite fourth surface of the semiconductor chip attached to the first surface of the die attach pad; a packaging compound covering portions of the semiconductor chip, the die attach pad and the plurality of leads forming a package, the opposite second surface of the die attach pad exposed from the package on a package surface, the opposite second surface being coplanar with the package surface; and a plurality of recess holes having a conductive adhesive, each of the plurality of recess holes extending from a first surface of each of the plurality of leads to the package surface;\n wherein a first distance between a plane along the package surface and a plane along the opposite fourth surface of the semiconductor chip is less than a second distance between the plane along the package surface and the plane along the third lead surface of each of the plurality of leads.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.78788
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14453650', '14215896', '14683277', '13542827', '11051061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9018151624397064
- 35 USC 102 Novelty (BERT): 0.5417921172750477
- Combined Prediction Score: 0.8658128579232406
- Mean Citation Score: 250.4113
- Max Citation Score: 375.82388
- Similarity Product: 286.6631253115463

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test