PATENT CLAIM ANALYSIS

Application Number: 16111263
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "329000"]

Abstract:
Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Claim (Index 17):
The method of  claim 15 ,\n wherein the forming of the first source/drain region comprises:\n forming a semiconductor layer comprising the second semiconductor material on a substrate and an additional semiconductor layer comprising the first semiconductor material on the semiconductor layer; \n patterning a semiconductor body in an upper portion of the additional semiconductor layer; \n doping a lower portion of the additional semiconductor layer for the first source/drain region; \n depositing a sacrificial layer; \n forming a mask section on the sacrificial layer aligned above the semiconductor body, the mask section being wider than the semiconductor body; and \n performing an anisotropic etch process to form trenches that extend through the sacrificial layer, through the lower portion of the additional semiconductor layer, through the semiconductor layer and into the substrate, the anisotropic etch process shaping the first source/drain region in the lower portion of the additional semiconductor layer, \n wherein the performing of the anisotropic etch process further shapes the semiconductor region in the semiconductor layer below the first source/drain region, \n wherein, following the performing of the anisotropic etch process, an isotropic etch process is performed in order to etch back the semiconductor region, and \n wherein, after the isotropic etch process is performed, the mask section is removed, the conductor is deposited and an additional anisotropic etch process is performed to create the bitline.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 1.85542
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15661058', '16009331', '15994392', '15873156', '15920748']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9339487347556672
- 35 USC 102 Novelty (BERT): 0.5585291754415695
- Combined Prediction Score: 0.8964067788242573
- Mean Citation Score: 352.76871199999994
- Max Citation Score: 460.6132
- Similarity Product: 340.987037439394

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test