PATENT CLAIM ANALYSIS

Application Number: 15906116
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "659000"]

Abstract:
Certain aspects of the present disclosure generally relate to layout techniques for high-speed and low-power signal paths in integrated circuits with small channel devices. More specifically, according to certain aspects, an integrated circuit may comprise a plurality of layers, wherein at least a portion of the plurality of layers is configured to form a power/ground grid having odd-numbered metal layers and even-numbered metal layers, wherein a majority of traces of the even-numbered metal layers have a first orientation, and wherein a majority of traces of at least one of the odd-numbered metal layers are oriented parallel to the majority of the traces of the even-numbered metal layers; and one or more circuit components configured to use high-speed, low-power signals carried by one or more of the plurality of layers and to be powered by the power/ground grid.

Claim (Index 20):
The method of  claim 19 , wherein the at least one of the odd-numbered metal layers is M 5 .

Metadata:
- Claim Count in Document: 5.0
- Percentile: 88.0
- Lexical Diversity: 2.11594
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12578426', '15085080', '15479633', '11656733', '13707175']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.91479121512953
- 35 USC 102 Novelty (BERT): 0.4975173909307215
- Combined Prediction Score: 0.8730638327096493
- Mean Citation Score: 146.476648
- Max Citation Score: 156.50882
- Similarity Product: 91.77742074011444

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test