PATENT CLAIM ANALYSIS

Application Number: 15955395
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "734000"]

Abstract:
A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 μm. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.

Claim (Index 9):
The semiconductor device of  claim 7 , further including a build-up interconnect structure formed over the encapsulant and the active surface of the semiconductor die.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 3.45455
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14305640', '15235008', '15827478', '14329464', '13771825']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9382995319868572
- 35 USC 102 Novelty (BERT): 0.5710745597610279
- Combined Prediction Score: 0.9015770347642744
- Mean Citation Score: 373.176216
- Max Citation Score: 467.43445
- Similarity Product: 387.0987788761318

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test