PATENT CLAIM ANALYSIS

Application Number: 15883503
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["257", "401000"]

Abstract:
A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.

Claim (Index 5):
The method of  claim 1 , wherein the gate dielectric layer is composed of a high-k gate dielectric.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 86.0
- Lexical Diversity: 1.98246
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15819567', '15802067', '15801967', '15802021', '15602225']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9384616084774162
- 35 USC 102 Novelty (BERT): 0.5278363721429721
- Combined Prediction Score: 0.8973990848439719
- Mean Citation Score: 331.928208
- Max Citation Score: 344.4151
- Similarity Product: 226.7529451056361

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test