PATENT CLAIM ANALYSIS

Application Number: 16109645
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-09
Patent Classification: ["327", "306000"]

Abstract:
A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Claim (Index 8):
The decimated phase detector circuit of  claim 7 , wherein:\n the UP N-bit rolling counter comprises an UP 2-bit rolling counter configured to output the decimated UP signal after every fourth UP signal received from the BBPD; and the DOWN N-bit rolling counter comprises a DOWN 2-bit rolling counter configured to output the decimated DOWN signal after every fourth DOWN signal received from the BBPD.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.61905
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14362563', '14982910', '12999596', '15256444', '11861505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7472707461135496
- 35 USC 102 Novelty (BERT): 0.4928557011816978
- Combined Prediction Score: 0.7218292416203644
- Mean Citation Score: 192.442444
- Max Citation Score: 199.42598
- Similarity Product: 138.7171759894681

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test