PATENT CLAIM ANALYSIS

Application Number: 15961157
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-05
Patent Classification: ["257", "427000"]

Abstract:
The present disclosure provides a method for manufacturing the semiconductor structure. The method includes forming an N th  metal layer, forming a plurality of magnetic tunneling junctions (MTJs) over the N th  metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, forming a top electrode via concaving upward over each of the plurality of MTJs, and forming an (N+M) th  metal layer over the plurality of MTJs. A semiconductor structure manufactured according to present disclosure is also provided.

Claim (Index 19):
The method of  claim 18 , further comprising:\n planarizing the oxide layer over the plurality of MTJs until the oxide layer and the planarization etch stop layer being coplanar in the memory region and until an exposure of the planarization etch back layer in the periphery region.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 91.0
- Lexical Diversity: 1.88235
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15933777', '15151207', '15867427', '14948046', '15130216']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8994322551365692
- 35 USC 102 Novelty (BERT): 0.4969209846059202
- Combined Prediction Score: 0.8591811280835044
- Mean Citation Score: 208.27046
- Max Citation Score: 213.8969
- Similarity Product: 151.80529203433397

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test