PATENT CLAIM ANALYSIS

Application Number: 15972510
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["327", "212000"]

Abstract:
A memory circuit includes, a latch circuit that includes a first node, a second node, a first inverter having an input coupled to the first node and an output coupled to the second node, and a second inverter having an input coupled to the second node and an output coupled to the first node, a writing circuit that includes a first transistor coupled to the first node and a second transistor coupled to the second node and executes writing to the latch circuit using the first transistor and the second transistor, a command circuit detects the execution of the writing to the latch circuit and output a command signal to increase the potential of the second node before the termination of the writing of a low level to the first node, and a potential control circuit increases the potential of the second node based on the command signal.

Claim (Index 15):
The memory circuit according to  claim 1 , further comprising:\n a plurality of writing circuits for the single latch circuit.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 3.9
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11510733', '10486638', '12036938', '15603284', '11153113']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7511985526585643
- 35 USC 102 Novelty (BERT): 0.4844480126789104
- Combined Prediction Score: 0.724523498660599
- Mean Citation Score: 163.525448
- Max Citation Score: 170.29054
- Similarity Product: 109.33566510566592

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test