PATENT CLAIM ANALYSIS

Application Number: 16193286
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["710", "301000"]

Abstract:
Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Claim (Index 11):
An apparatus, comprising:\n a controller; a memory; and a data bus configured to provide a first data signal from the controller to the memory and provide a second data signal from the memory to the controller, the data bus comprising at least one conductor for transmitting respective symbols of the first or second data signals, wherein at least one symbol of the respective symbols is encoded with at least two data bits, wherein the first data signal has a first voltage swing; wherein the second data signal has a second voltage swing, and wherein the first voltage swing is greater than the second voltage swing.

Metadata:
- Claim Count in Document: 42.0
- Percentile: 98.0
- Lexical Diversity: 2.17073
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15963615', '14712610', '14831517', '15412826', '11368012']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.672304922432621
- 35 USC 102 Novelty (BERT): 0.5100308252584094
- Combined Prediction Score: 0.6560775127151999
- Mean Citation Score: 218.04207
- Max Citation Score: 296.2348
- Similarity Product: 240.62371382784843

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test