PATENT CLAIM ANALYSIS

Application Number: 15924584
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["331", "002000"]

Abstract:
Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.

Claim (Index 13):
The circuit of  claim 6 , wherein the calibration logic, in an initial startup phase, disables the PLL, opens the switch, enables the oscillator, and enables the FLL.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.75
- Patent Class: 331.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15251570', '15718715', '15471483', '11854917', '12981619']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7707648669622601
- 35 USC 102 Novelty (BERT): 0.5342897479644262
- Combined Prediction Score: 0.7471173550624767
- Mean Citation Score: 296.9770680000001
- Max Citation Score: 336.89383
- Similarity Product: 206.59026745563023

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test