PATENT CLAIM ANALYSIS

Application Number: 15881509
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-08
Patent Classification: ["375", "355000"]

Abstract:
Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Claim (Index 11):
An apparatus comprising:\n a plurality of logic branches of a dynamically-weighted XOR gate, the plurality of logic branches configured to receive a reference clock signal and a phase of a local oscillator signal and to responsively generate a plurality of weighted segments of a phase-error signal, each weighted segment of the phase-error signal generated by a corresponding logic branch enabled responsive to a respective input logic combination of the reference clock and the phase of the local oscillator and having a respective weight selectively applied by a corresponding logic branch of the plurality of logic branches, wherein at least two weighted segments of the plurality of weighted segments have different weights, the plurality of logic branches comprising:\n a first subset of the plurality of logic branches configured to generate positive weighted segments when the reference clock signal and the phase of the local oscillator signal have equal logic levels; \n a second subset of the plurality of logic branches configured to generate negative weighted segments when the reference clock signal and the phase of the local oscillator signal have different logic levels; and \n a common node connected to the plurality of logic branches configured to generate an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and to responsively output the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.4
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15791373', '15602080', '15494439', '15603404', '15802365']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5292159653583282
- 35 USC 102 Novelty (BERT): 0.5076344913439934
- Combined Prediction Score: 0.5270578179568948
- Mean Citation Score: 267.35878
- Max Citation Score: 302.3437
- Similarity Product: 223.5262513705552

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test