PATENT CLAIM ANALYSIS

Application Number: 16282553
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-08
Patent Classification: ["719", "312000"]

Abstract:
Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

Claim (Index 16):
The method of  claim 15 , wherein the queue is implemented by the buffer, and the buffer is to allow data to be at least one of written to or read from either end of the buffer.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 99.0
- Lexical Diversity: 1.98718
- Patent Class: 719.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14574545', '15537357', '15971988', '15808077', '14320985']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5403998386404429
- 35 USC 102 Novelty (BERT): 0.5236753391310871
- Combined Prediction Score: 0.5387273886895073
- Mean Citation Score: 210.05315600000003
- Max Citation Score: 300.12778
- Similarity Product: 193.36636680519936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test