PATENT CLAIM ANALYSIS

Application Number: 15895321
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["326", "038000"]

Abstract:
A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.

Claim (Index 14):
The method of  claim 13 , further comprising:\n mapping the Boolean function to a first PLU and a second PLU of the plurality of PLUs in response to the Boolean function meeting a decomposition condition, the second PLU being coupled with the first PLU to receive the output of the first PLU; and mapping the Boolean function to a third PLU, a fourth PLU, and a fifth PLU of the plurality of PLUs in response to the Boolean function not meeting the decomposition condition, the fifth PLU being coupled with the third PLU and the fourth PLU to receive the outputs of the third PLU and the fourth PLU.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 88.0
- Lexical Diversity: 2.0303
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['09754632', '14458456', '14089238', '14890911', '15224224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6462804676536804
- 35 USC 102 Novelty (BERT): 0.4862695072425024
- Combined Prediction Score: 0.6302793716125626
- Mean Citation Score: 170.86310399999996
- Max Citation Score: 185.4701
- Similarity Product: 118.97001449623706

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test