PATENT CLAIM ANALYSIS

Application Number: 16051025
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "299000"]

Abstract:
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

Claim (Index 17):
A method for manufacturing a semiconductor structure, the method comprising forming a first dielectric layer over a gate structure and over a source drain structure adjacent to the gate structure;\n forming a recess in the first dielectric layer over the source drain structure, a bottom of the recess being between the source drain structure and an upper surface of the first dielectric layer; forming a protection layer along sidewalls and a bottom of the recess; deepening the recess by an anisotropic etch process to expose the source drain structure, wherein the anisotropic etch process removes the protection layer from the bottom of the recess, wherein after the anisotropic etch process, a remaining portion of the first dielectric layer extends along a sidewall of the gate structure; filling a first metal in the recess to form a bottom conductor that is electrically coupled to the source drain structure; forming a second dielectric layer over the gate structure and over the bottom conductor; forming an opening in the second dielectric layer to expose the bottom conductor; and filling a second metal in the opening to form an upper conductor that is electrically coupled to the bottom conductor.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 4.0
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15016144', '15652176', '15790129', '15921947', '15074986']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8690721829856646
- 35 USC 102 Novelty (BERT): 0.4656157103737294
- Combined Prediction Score: 0.8287265357244711
- Mean Citation Score: 202.625542
- Max Citation Score: 212.72882
- Similarity Product: 193.43349807855847

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test