PATENT CLAIM ANALYSIS

Application Number: 16155352
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-10
Patent Classification: ["327", "277000"]

Abstract:
A semiconductor integrated circuit device may include first and second delay circuits and a control circuit block connected between the first and second delay circuits. The first and second delay circuits may each include a plurality of delay elements serially connected with each other. The control circuit block may receive an output signal of the first delay circuit. The control circuit block may input an inversion signal, which may be generated by inverting the output signal of the first delay circuit, into the second delay circuit in response to a compensation signal.

Claim (Index 15):
The semiconductor integrated circuit device of  claim 7 , wherein each delay element of the plurality of delay elements comprises at least one of an inverter and a NAND logic gate.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 97.0
- Lexical Diversity: 2.22727
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15486689', '15000154', '14325852', '12929753', '13208976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.779271613991959
- 35 USC 102 Novelty (BERT): 0.4691638204671488
- Combined Prediction Score: 0.748260834639478
- Mean Citation Score: 174.82381
- Max Citation Score: 192.00414
- Similarity Product: 154.1208616115713

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test