PATENT CLAIM ANALYSIS

Application Number: 16105277
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "616000"]

Abstract:
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Claim (Index 22):
The CMOS device of  claim 11 , wherein the stressed buried structure comprises a stressed buried insulator structure.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 96.0
- Lexical Diversity: 1.71951
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12869978', '15191369', '13762677', '15594436', '12110030']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.943497186913072
- 35 USC 102 Novelty (BERT): 0.5479777484182463
- Combined Prediction Score: 0.9039452430635896
- Mean Citation Score: 388.146878
- Max Citation Score: 428.02505
- Similarity Product: 293.2505064501882

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test