PATENT CLAIM ANALYSIS

Application Number: 15993612
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["341", "161000"]

Abstract:
A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.

Claim (Index 3):
The SAR ADC of  claim 1 , wherein the voltage corresponding with an lsb of the DAC is substantially equal to the voltage corresponding with an lsb of the SAR ADC.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 93.0
- Lexical Diversity: 2.91228
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15993625', '15993623', '15878375', '14587825', '15146890']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6626574715343349
- 35 USC 102 Novelty (BERT): 0.5619246098790986
- Combined Prediction Score: 0.6525841853688112
- Mean Citation Score: 346.721154
- Max Citation Score: 430.14645
- Similarity Product: 347.81265422818063

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test