PATENT CLAIM ANALYSIS

Application Number: 16180953
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["375", "260000"]

Abstract:
Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Claim (Index 11):
An apparatus comprising:\n an encoder configured to obtain a set of inputs comprising at least one input data signal and at least one clock signal, and to responsively generate symbols of a codeword of a vector signaling code, the symbols representing a transformation of the set of inputs with a plurality of mutually orthogonal sub-channel vectors that collectively form an orthogonal matrix, each sub-channel vector weighted by a respective input of the set of inputs; and a plurality of drivers configured to transmit each symbol of the codeword as an analog signal over a respective wire of a multi-wire bus.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 98.0
- Lexical Diversity: 1.15909
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15285316', '14816899', '14952491', '16107839', '14612241']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.541059457709973
- 35 USC 102 Novelty (BERT): 0.5560744521518147
- Combined Prediction Score: 0.5425609571541572
- Mean Citation Score: 407.267538
- Max Citation Score: 422.6285
- Similarity Product: 360.3463002580404

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test