PATENT CLAIM ANALYSIS

Application Number: 16035458
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["257", "351000"]

Abstract:
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Claim (Index 19):
The device of  claim 18 , further comprising a third trench isolation region extending through the insulating layer and into the substrate, the second, third, and fourth semiconductor layers extending between the first trench isolation region and the third trench isolation region.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 95.0
- Lexical Diversity: 2.1087
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15162441', '14675156', '14048263', '15191369', '12869978']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9246265747730544
- 35 USC 102 Novelty (BERT): 0.5263363468506168
- Combined Prediction Score: 0.8847975519808106
- Mean Citation Score: 301.394978
- Max Citation Score: 352.56107000000014
- Similarity Product: 274.3850163001609

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test