PATENT CLAIM ANALYSIS

Application Number: 15951290
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["713", "322000"]

Abstract:
Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Claim (Index 5):
The processor of  claim 1 , wherein the separate frequencies include a first frequency to be applied to the first subset, a second frequency to be applied to the second subset, and a third frequency to be applied to the uncore circuit, the processor further comprising:\n a first PLL to deliver a first clock signal at the first frequency, a second PLL to deliver a second clock signal at the second frequency and a third PLL to deliver a third clock signal at the third frequency, wherein the separate voltages comprise a first voltage to be applied to the first subset, a second voltage to be applied to the second subset, and a third voltage to be applied to the uncore circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 1.58065
- Patent Class: 713.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15951310', '15951299', '13486948', '12899311', '13471222']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3938379520711325
- 35 USC 102 Novelty (BERT): 0.4844632302282634
- Combined Prediction Score: 0.4029004798868456
- Mean Citation Score: 217.98038000000005
- Max Citation Score: 265.6264
- Similarity Product: 254.0005617266178

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test