PATENT CLAIM ANALYSIS

Application Number: 15863404
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["365", "185020"]

Abstract:
A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.

Claim (Index 14):
The apparatus of  claim 12 , wherein:\n the control circuit is configured to apply a first set of increasing program voltages to the first block when making the detection and to apply a second set of increasing program voltages to the first block after making the detection; and a first program voltage of the second set of increasing program voltages is lower than a last program voltage of the first set of increasing program voltages.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 86.0
- Lexical Diversity: 1.90123
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15062661', '15814769', '14928853', '14617182', '14887976']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7929499451185947
- 35 USC 102 Novelty (BERT): 0.5111234525466495
- Combined Prediction Score: 0.7647672958614001
- Mean Citation Score: 246.733848
- Max Citation Score: 266.43085
- Similarity Product: 171.4916931905091

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test