PATENT CLAIM ANALYSIS

Application Number: 15911183
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["257", "737000"]

Abstract:
A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.

Claim (Index 8):
The chip package structure as claimed in  claim 7 , comprising an under fill material, wherein the under fill material is disposed between the chip package layer and the redistribution layer and encapsulates the first conductive pillars and the second conductive pillars.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 90.0
- Lexical Diversity: 3.08511
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15599477', '15842822', '15287729', '14985423', '13944224']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917819331012895
- 35 USC 102 Novelty (BERT): 0.4971157367424645
- Combined Prediction Score: 0.8757489715858521
- Mean Citation Score: 234.31522200000003
- Max Citation Score: 268.83298
- Similarity Product: 217.0868949345732

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test