PATENT CLAIM ANALYSIS

Application Number: 16102391
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-07
Patent Classification: ["257", "737000"]

Abstract:
A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

Claim (Index 21):
A semiconductor device comprising:\n a printed circuit board (PCB); an interposer mounted on the PCB, the interposer including an interposer body, through-vias extending vertically through the interposer body, and pads disposed on and electrically connected to the through-vias, respectively; a high bandwidth (HBM) package mounted on the interposer, the HBM package comprising a buffer chip, and a memory chip on the buffer chip, the buffer chip including a buffer chip body, first TSVs electrically connected to the memory chip and extending vertically through the buffer chip body, and bumps on a lower surface of the buffer chip body, the bumps being electrically connected to the first TSVs, respectively; a processor chip mounted on the interposer as laterally spaced apart from the HBM package, the processor chip including a processor chip body and bumps on a lower surface of the processor chip body; and an adhesive layer interposed between the HBM package and the interposer and between the processor chip and the interposer, wherein the bumps are bonded to corresponding ones of the pads of the interposer, respectively, each of the bumps including a pillar and a solder layer, each of the pillars of the bumps and the pads of the interposer has a centerline extending in a direction perpendicular to an upper surface of the interposer body, the centerlines of the pillars of the bumps extend through geometric centers of the pillars, respectively, as viewed in a plan view of the semiconductor device, the centerlines of the pads of the interposer extend vertically through geometric centers of the pads of the interposer, respectively, as viewed in a plan view of the semiconductor device, in a peripheral region of an interface between the buffer chip and the interposer, the centerline of the pillar of the bump of the buffer chip is offset from the centerline of the corresponding one of the pads of the interposer to which the bump is bonded, and in a peripheral region of an interface between the processor chip and the interposer, the centerline of the pillar of a bump is offset from the centerline of the corresponding one of the pads of the interposer to which the bump is bonded for each of a plurality of the bumps and the corresponding ones of the pads bonded to each other.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 96.0
- Lexical Diversity: 2.65217
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12907028', '15493096', '13188554', '15943072', '10424096']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9217509076059788
- 35 USC 102 Novelty (BERT): 0.4973107134159411
- Combined Prediction Score: 0.8793068881869751
- Mean Citation Score: 252.506064
- Max Citation Score: 268.55466
- Similarity Product: 214.39407561171768

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test