PATENT CLAIM ANALYSIS

Application Number: 16372642
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-07
Patent Classification: ["257", "004000"]

Abstract:
Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Claim (Index 18):
A method, comprising:\n forming a resistive random access memory (RRAM) stack over a semiconductor substrate; forming a blocking layer over a top surface of the RRAM stack; etching back the blocking layer to expose a first part of the top surface of the RRAM stack while leaving a portion of the blocking layer covering a second part of the top surface of the RRAM stack; and forming a contact contacting an upper surface of the blocking layer and contacting the second part of the top surface of the RRAM stack.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 100.0
- Lexical Diversity: 2.18919
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14087082', '15715413', '14880358', '15262703', '14332577']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9168056979815388
- 35 USC 102 Novelty (BERT): 0.4938923110290878
- Combined Prediction Score: 0.8745143592862937
- Mean Citation Score: 228.978086
- Max Citation Score: 247.87207
- Similarity Product: 200.2689973640567

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test