PATENT CLAIM ANALYSIS

Application Number: 16120823
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-08
Patent Classification: ["257", "072000"]

Abstract:
An array substrate and a method for manufacturing the same, a display panel and a display device are provided. The array substrate includes a gate layer, a gate insulation layer, a source-drain layer, a first passivation layer and an ITO layer successively formed on a base substrate, a first through hole in the first passivation layer and a second through hole in the gate insulation layer, and a second passivation layer; and a part of the second passivation layer is arranged in the first and second through holes to cover a part of the ITO layer in the first through hole and the second through hole.

Claim (Index 11):
The method of  claim 10 , wherein the ashing process is performed on the photoresist layer before the exposed part of the ITO layer is etched; or\n the ashing process is performed on the photoresist layer after the exposed part of the ITO layer is etched.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 97.0
- Lexical Diversity: 2.67442
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14408717', '15544562', '14897525', '13458478', '11354789']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.925419749681726
- 35 USC 102 Novelty (BERT): 0.5051737425286114
- Combined Prediction Score: 0.8833951489664145
- Mean Citation Score: 227.520654
- Max Citation Score: 236.28479
- Similarity Product: 152.0232850902235

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test