PATENT CLAIM ANALYSIS

Application Number: 16020807
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "076000"]

Abstract:
A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Claim (Index 4):
The transistor of  claim 1 , wherein the gate electrode extends to a first depth, and the source contact and the drain contact extend to a second depth that is greater than the first depth.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 94.0
- Lexical Diversity: 2.10714
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15156740', '15832680', '16004272', '15393945', '14597128']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9230124929355392
- 35 USC 102 Novelty (BERT): 0.5069199222375497
- Combined Prediction Score: 0.8814032358657403
- Mean Citation Score: 232.919794
- Max Citation Score: 259.716
- Similarity Product: 191.2375420968533

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test