PATENT CLAIM ANALYSIS

Application Number: 15921877
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "349000"]

Abstract:
A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.

Claim (Index 2):
The method of  claim 1 , further comprising forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator before forming the sacrificial gate.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 90.0
- Lexical Diversity: 2.71667
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15282349', '15840122', '15439078', '15072920', '13690867']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9300830656567806
- 35 USC 102 Novelty (BERT): 0.5536215086761181
- Combined Prediction Score: 0.8924369099587144
- Mean Citation Score: 334.076676
- Max Citation Score: 456.77396
- Similarity Product: 312.0103059065914

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test