PATENT CLAIM ANALYSIS

Application Number: 16026946
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["326", "029000"]

Abstract:
Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

Claim (Index 14):
An integrated circuit, comprising:\n clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; and second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; wherein the read-write circuitry comprises a column multiplexer along with a write driver for write operations and a sense amplifier for read operations, and wherein the read-write circuitry is used for fixing an external hold margin with the enable signal as an external control signal.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 95.0
- Lexical Diversity: 3.29787
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14836657', '15490352', '14849902', '12551874', '15368480']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.658362651761691
- 35 USC 102 Novelty (BERT): 0.4696404629684549
- Combined Prediction Score: 0.6394904328823674
- Mean Citation Score: 186.287808
- Max Citation Score: 199.45488
- Similarity Product: 157.16254904485703

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test