PATENT CLAIM ANALYSIS

Application Number: 15871793
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-09
Patent Classification: ["257", "369000"]

Abstract:
A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

Claim (Index 1):
A semiconductor device including a 2-input NAND circuit,\n the 2-input NAND circuit including: a first P channel FET and a second P channel FET coupled in parallel between a first power potential wiring and an output wiring; a first N channel FET and a second N channel FET coupled in series between the output wiring and a second power potential wiring; a first input wiring coupled to a first P gate electrode of the first P channel FET and a first N gate electrode of the first N channel FET; and a second input wiring coupled to a second P gate electrode of the second P channel FET and a second N gate electrode of the second N channel FET, comprising: a semiconductor substrate having a main surface; an element isolation film formed on the main surface of the semiconductor substrate; a first semiconductor layer penetrating the element isolation film, protruding from the main surface of the semiconductor substrate, and extending in a first direction in plan view; the first N gate electrode and the second N gate electrode disposed over the first semiconductor layer through a first gate insulating film and extending in a second direction perpendicular to the first direction; a first local wiring disposed between the first N gate electrode and the second N gate electrode in the first direction and extending in the second direction; a first interlayer insulating film formed over the main surface of the semiconductor substrate, covering the first N gate electrode and the second N gate electrode, exposing a main surface of the first local wiring and abutting on a sidewall thereof; a second interlayer insulating film disposed over the first interlayer insulating film; and a first wiring coupled to the first local wiring and disposed over the second interlayer insulating film.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 2.30769
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15719830', '14826730', '15677546', '12216061', '15512933']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9139306032109148
- 35 USC 102 Novelty (BERT): 0.4725992567941291
- Combined Prediction Score: 0.8697974685692362
- Mean Citation Score: 205.791446
- Max Citation Score: 214.66031
- Similarity Product: 186.36200451530456

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test