PATENT CLAIM ANALYSIS

Application Number: 16128879
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["365", "200000"]

Abstract:
A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Claim (Index 14):
The memory device of  claim 12 , wherein the control circuit further comprises:\n a row access counter configured to count a row access number to a first row address associated with the write operation to output a counting value when the decoded command directs the write operation; a register configured to store a reference value; a comparator configured to output a comparison signal by comparing the counting value with the reference value; a pointer table configured to output a table pointing signal in response to the access address and the comparison signal; and a storing table configured to output a replacement address to replace the access address in response to the table pointing signal, and wherein when the counting value exceeds the reference value, the control circuit is configured to control the write/read circuit such that a first write data associated with a first row address is stored in the write buffer and the first write data is written in a second page designated by the replacement address, in the memory cell array in a stand-by mode of the memory device, and the second page is different from a first page designated by the first row address, in the memory cell array.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 97.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15795595', '15498855', '13753165', '15398409', '12552738']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8354518195546405
- 35 USC 102 Novelty (BERT): 0.5012872060874847
- Combined Prediction Score: 0.802035358207925
- Mean Citation Score: 284.283722
- Max Citation Score: 289.2221
- Similarity Product: 218.8037261988044

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test