PATENT CLAIM ANALYSIS

Application Number: 16152421
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-01
Patent Classification: ["257", "133000"]

Abstract:
A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.

Claim (Index 9):
The semiconductor device of  claim 7 , wherein the second spacer contacts the first STI and the second STI directly.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.74419
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15493150', '13117864', '11692313', '11512313', '10970085']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9158387917429568
- 35 USC 102 Novelty (BERT): 0.4934671993191185
- Combined Prediction Score: 0.8736016325005731
- Mean Citation Score: 170.987778
- Max Citation Score: 234.41711
- Similarity Product: 177.9732649807179

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test