PATENT CLAIM ANALYSIS

Application Number: 16220174
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["257", "618000"]

Abstract:
Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.

Claim (Index 17):
A method comprising:\n forming a conductive layer over a substrate; and patterning the conductive layer according to a desired layout, such that the conductive layer includes a first conductive feature, a second conductive feature, a third conductive feature, and a fourth conductive feature, wherein the desired layout includes:\n a first desired layout feature pattern formed from a first sub-layout of the desired layout, a second desired layout feature pattern formed from a second sub-layout of the desired layout, a third desired layout feature pattern formed from a third sub-layout of the desired layout, and a fourth desired layout feature pattern formed from the third sub-layout of the desired layout, \n wherein the third desired layout feature pattern is separated from the first desired layout feature pattern by a first minimum spacing and from the second desired layout feature pattern by a second minimum spacing, and \n wherein the first conductive feature corresponds with the first desired layout feature pattern, the second conductive feature corresponds with the second desired layout feature pattern, the third conductive feature corresponds with the third desired layout feature pattern, and the fourth conductive feature corresponds with the fourth desired layout feature pattern.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.84906
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15668930', '15173840', '14262279', '14266878', '15174131']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9052935040249412
- 35 USC 102 Novelty (BERT): 0.5213893360573968
- Combined Prediction Score: 0.8669030872281869
- Mean Citation Score: 254.466194
- Max Citation Score: 285.2498
- Similarity Product: 180.6776719335914

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test