PATENT CLAIM ANALYSIS

Application Number: 16110850
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-05
Patent Classification: ["257", "421000"]

Abstract:
The present disclosure provides a method for manufacturing a semiconductor structure. The method includes (1) providing a substrate, (2) depositing a first electrode layer over the substrate, (3) depositing a magnetic tunneling junction (MTJ) layer on the first electrode layer, (4) depositing a second electrode layer on the MTJ layer, (5) patterning the first electrode layer, the MTJ layer and the second electrode layer to form a first electrode, an MTJ and a second electrode, (6) forming a first dielectric layer over the first electrode, the MTJ, and the second electrode, (7) removing a portion of the first dielectric layer, (8) forming a second dielectric layer over the first electrode, the MTJ, the second electrode, and an unremoved portion of the first dielectric layer. A semiconductor structure is also disclosed.

Claim (Index 3):
The method of  claim 1 , wherein prior to the removing the first dielectric layer, the first dielectric layer at a sidewall of the MTJ is thinner than the first dielectric layer at a top surface of the second electrode.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 96.0
- Lexical Diversity: 3.17308
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15151207', '15825972', '14332018', '15130065', '15442225']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.920350272412721
- 35 USC 102 Novelty (BERT): 0.4899660971403894
- Combined Prediction Score: 0.8773118548854879
- Mean Citation Score: 185.411992
- Max Citation Score: 194.15184
- Similarity Product: 133.6661677524948

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test