PATENT CLAIM ANALYSIS

Application Number: 16055199
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-07
Patent Classification: ["365", "149000"]

Abstract:
A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.

Claim (Index 4):
The memory device of  claim 3 , wherein the second volatile memory chip further comprises:\n a data clock pin receiving a data clock, a frequency of the data clock is higher than a frequency of the second clock.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 96.0
- Lexical Diversity: 2.72
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16006082', '16052815', '13462338', '15093769', '15292834']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8017386973404861
- 35 USC 102 Novelty (BERT): 0.489089323887846
- Combined Prediction Score: 0.770473759995222
- Mean Citation Score: 180.562198
- Max Citation Score: 215.08775
- Similarity Product: 146.1493791089058

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test