PATENT CLAIM ANALYSIS

Application Number: 16165732
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "191000"]

Abstract:
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Claim (Index 6):
The apparatus of  claim 5 , wherein each microcontroller of the plurality of microcontrollers is configured to calculate a respective biasing signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 97.0
- Lexical Diversity: 2.70732
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15474353', '15895290', '13651093', '14989678', '12205867']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8600408525624802
- 35 USC 102 Novelty (BERT): 0.5160808339230043
- Combined Prediction Score: 0.8256448506985326
- Mean Citation Score: 275.276722
- Max Citation Score: 324.7241
- Similarity Product: 271.2467919183612

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test