PATENT CLAIM ANALYSIS

Application Number: 15980577
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "777000"]

Abstract:
A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

Claim (Index 19):
The method for forming a chip package as claimed in  claim 18 , further comprising:\n providing a cover plate; and forming a spacer layer on the cover plate.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 93.0
- Lexical Diversity: 3.10204
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15409289', '15287729', '15630940', '15936444', '15383560']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9022809529297436
- 35 USC 102 Novelty (BERT): 0.4963232815721812
- Combined Prediction Score: 0.8616851857939872
- Mean Citation Score: 224.05711
- Max Citation Score: 230.15958
- Similarity Product: 173.62572334627393

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test