PATENT CLAIM ANALYSIS

Application Number: 15903304
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "758000"]

Abstract:
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

Claim (Index 4):
The integrated circuit structure of  claim 3 , wherein the low-k dielectric material selected from the group consisting of carbon doped silicon dioxide, porous silicon dioxide.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 88.0
- Lexical Diversity: 1.80769
- Patent Class: 257.0
- Transitional Phrase Type: closed
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15201420', '14139363', '15529484', '14709430', '15528736']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9306435666918637
- 35 USC 102 Novelty (BERT): 0.4788589915368441
- Combined Prediction Score: 0.8854651091763617
- Mean Citation Score: 186.38134
- Max Citation Score: 190.21263
- Similarity Product: 140.68634089925942

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test