PATENT CLAIM ANALYSIS

Application Number: 16217956
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["716", "112000"]

Abstract:
Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

Claim (Index 7):
A method comprising:\n by a computing system:\n extracting layout data from a design file comprising representations of one or more photonic device designs; \n determining a reference curve from a source netlist; \n comparing a shape of the reference curve with a curved shape from the extracted layout data; and \n responsive to the comparing, validating the one or more photonic device designs.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 1.39024
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14693851', '14142201', '13017788', '13627933', '12708524']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3273724451464445
- 35 USC 102 Novelty (BERT): 0.4886778126249952
- Combined Prediction Score: 0.3435029818942995
- Mean Citation Score: 218.439098
- Max Citation Score: 301.26886
- Similarity Product: 256.110753082757

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test