PATENT CLAIM ANALYSIS

Application Number: 15971109
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["257", "347000"]

Abstract:
A method for fabricating a Fin-FET device includes forming a plurality of discrete fin structures on a substrate which includes a first device region and a second device region, forming a plurality of dummy gate electrodes across the fin structures, and forming an interlayer dielectric layer exposing the dummy gate electrodes on a portion of the fin structures exposed by the dummy gate electrodes, forming a first opening by removing each dummy gate electrode, forming an initial metal gate electrode in the first opening and between adjacent fin structures, and forming a second opening through the initial metal gate electrode. The initial metal gate electrode formed in the first device region is a first metal gate electrode, and the initial metal gate electrode formed in the second device region is a second metal gate electrode. The second opening separates the first metal gate electrode from the second metal gate electrode.

Claim (Index 19):
The Fin-FET device according to  claim 18 , wherein:\n the dielectric layer is made of one or more of SiO x , SiN x , and SiON.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 93.0
- Lexical Diversity: 3.11765
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15473726', '15332271', '15335248', '15243775', '15491501']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9300429576562144
- 35 USC 102 Novelty (BERT): 0.5124855718509067
- Combined Prediction Score: 0.8882872190756835
- Mean Citation Score: 263.72441000000003
- Max Citation Score: 282.3838
- Similarity Product: 192.51101499437087

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test