PATENT CLAIM ANALYSIS

Application Number: 15744073
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["345", "208000"]

Abstract:
The invention provides an AMOLED display and driving method thereof, wherein a display panel is provided with a plurality of multiplexers, with each multiplexer having a multiplexer control end receiving a multiplexing control signal, a first input end connected to gate driver and a second input end to a constant low voltage. The first and second output ends are respectively connected to the first and second control ends of corresponding rows of sub-pixel driving circuits. When driving AMOLED display, the multiplexer receives scan signal from gate driver, and under control of multiplex control signal, the first and second output ends selectively output scan signal or the constant low voltage, respectively to generate two different control signals respectively outputted to the first and second control ends of corresponding row of sub-pixel driving circuits. The invention can reduce the number of the output channels of gate drivers to reduce production cost.

Claim (Index 9):
An active matrix organic light-emitting diode (AMOLED) display, which comprises: a display panel and a gate driver electrically connected to the display panel;\n the display panel comprising: a plurality of sub-pixel driving circuits arranged in an array, and a plurality of multiplexers corresponding to the plurality of rows of sub-pixel driving circuits; each multiplexer having a control end connected to a multiplexing control signal, a first input end electrically connected to the gate driver, a second input end connected to a constant low voltage, a first output end connected to a first control end corresponding to a row of sub-pixel driving circuits, and a second output connected to a second control end corresponding to a row of sub-pixel driving circuits; the gate driver being for outputting scan signals to the first ends of the plurality of multiplexers; the multiplexers being for receiving scan signals, and under the control of the multiplexing control signal, making the first output end selectively outputting the scan signal or constant low voltage and making the second output end selectively outputting the constant low voltage or scan signal; wherein when the multiplexing control signal being at high voltage, the first output end outputting the scan signal and the second output end outputting the constant low voltage; when the multiplexing control signal being at low voltage, the first output end outputting the constant low voltage and the second output end outputting the scan signal; wherein the scan signal and the multiplexing control signal being combined to correspond to a reset phase, a sensing phase, a data-writing phase, and a light-emitting phase sequentially; in the reset phase, the scan signal from the gate driver being first at high voltage and then becoming low voltage, the multiplexing control signal being at high voltage, the first output end outputting a high voltage and then a low voltage, and the second output end outputting the constant low voltage; in the sensing phase, the scan signal from the gate driver being at high voltage, the multiplexing control signal being at low voltage, the first output end outputting the constant low voltage, and the second output end outputting a high voltage; in the data-writing phase, the scan signal from the gate driver being at high voltage, the multiplexing control signal being at low voltage, the first output end outputting the constant low voltage, and the second output end outputting a high voltage; in the light-emitting phase, the scan signal from the gate driver being at low voltage, the multiplexing control signal being at high voltage, the first output end outputting a low voltage, and the second output end outputting the constant low voltage; wherein the gate driver being connected to receive a gate output control signal, the gate output control signal being a pulse signal, and the scan signal outputted from the gate driver at the low voltage in the reset phase having a duration equal to a duration of the gate output control signal at high voltage in a cycle; wherein each sub-pixel driving circuit comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a capacitor, and an OLED; the first TFT having a gate as the second control end of the sub-pixel driving circuit, a source receiving a data signal, and a drain electrically connected to a gate of the second TFT; the second TFT having a drain receiving a power source voltage, and a source electrically connected to an anode of the OLED; the third TFT having a gate as the first control end of the sub-pixel driving circuit, a drain electrically connected to the gate of the second TFT, and a source electrically connected to a source of the fourth TFT, the fourth TFT having a gate electrically connected to the gate of the third TFT, a source receiving an initialization voltage, and a drain electrically connected to the anode of the OLED; the capacitor having two ends electrically connected respectively to the gate and the source of the second TFT; and the OLED having a cathode connected to ground.

Metadata:
- Claim Count in Document: 3.0
- Percentile: 86.0
- Lexical Diversity: 2.31884
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14914649', '15328493', '14241068', '15328891', '15328494']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6787687153062077
- 35 USC 102 Novelty (BERT): 0.4989592541190308
- Combined Prediction Score: 0.6607877691874902
- Mean Citation Score: 278.59158800000006
- Max Citation Score: 283.3233
- Similarity Product: 235.60002381713392

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test