PATENT CLAIM ANALYSIS

Application Number: 16207564
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-06
Patent Classification: ["257", "365000"]

Abstract:
A semiconductor structure and a method for fabricating the same. The structure includes a substrate and at least one semiconductor fin. The semiconductor structure further includes a channel region within the semiconductor fin. The channel region includes a higher content of germanium than remaining portions of the semiconductor fin. The semiconductor structure also includes a gate stack in contact with the semiconductor fin. The method includes removing a dummy gate formed on at least one semiconductor fin. The removal of the dummy gate exposes a channel region of the semiconductor fin. A germanium dioxide layer is formed in contact with the channel region. A condensation process is performed after the germanium dioxide layer has been formed. The condensation process increases germanium content only in the channel region.

Claim (Index 19):
The integrated circuit of  claim 18 , wherein the gate stack further comprises:\n an interfacial layer in contact with the channel region and the insulating layer.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 98.0
- Lexical Diversity: 2.63462
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15660192', '15378290', '16112841', '14979720', '14750190']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9181989754614538
- 35 USC 102 Novelty (BERT): 0.5385403855133403
- Combined Prediction Score: 0.8802331164666424
- Mean Citation Score: 284.62756
- Max Citation Score: 350.33652
- Similarity Product: 201.90679674272064

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test