PATENT CLAIM ANALYSIS

Application Number: 15879457
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-05
Patent Classification: ["257", "774000"]

Abstract:
A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

Claim (Index 12):
A method of fabricating a stacked via structure, the method comprising:\n forming a first conductive via; forming a first dielectric layer to cover the first conductive via; performing a first polishing process to polish the first dielectric layer to expose a top surface of the first conductive via such that a first level height offset is between the top surface of the first conductive via and a top surface of the first dielectric layer after polishing the first dielectric layer; forming a first redistribution wiring on the first conductive via and a portion of the first dielectric layer; forming a second conductive via on the first redistribution wiring; forming a second dielectric layer on the first dielectric layer to cover the second conductive via and the first redistribution wiring; and performing a second polishing process to polish the second dielectric layer to expose a top surface of the second conductive via such that a second level height offset being between the top surface of the second conductive vias and a top surface of the second dielectric layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 4.37838
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15164888', '15795281', '15281086', '15215594', '15257920']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9123840880841976
- 35 USC 102 Novelty (BERT): 0.4839889966823497
- Combined Prediction Score: 0.8695445789440127
- Mean Citation Score: 190.244746
- Max Citation Score: 198.61655
- Similarity Product: 143.78339015238882

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test