PATENT CLAIM ANALYSIS

Application Number: 15905802
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["365", "185260"]

Abstract:
A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Claim (Index 1):
A memory array comprising:\n a plurality of memory pages, each memory page comprising a plurality of memory cells, and each memory cell comprising:\n a floating gate module comprising:\n a floating gate transistor, and configured to control the floating gate transistor according to a source line, a bit line and a word line, the floating gate transistor having a first terminal, a second terminal and a floating gate; \n a source transistor having a first terminal coupled to the source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to the word line; and \n a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to the bit line, and a control terminal coupled to the word line; \n \n a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and \n an erase element having a body terminal configured to receive a first voltage during a program operation and a program inhibit of the memory cell and receive a second voltage during an erase operation of the memory cell, a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element or being floating, and a control terminal coupled to the floating gate; \n wherein: the floating gate module is disposed in a first well; the erase element is disposed in a second well; the control element is disposed in a third well; the first well, the second well and the third well are disposed in a deep doped region; memory cells of the plurality of memory pages are all disposed in the deep doped region; the control line is at the first voltage during the program operation; memory cells in different memory pages are coupled to different control lines, different word lines, and different erase lines; during the erase operation of the memory cell:\n the erase line is at the second voltage; \n the control line is at a fifth voltage; and \n the source line and the bit line are both at a fourth voltage or at the fifth voltage; while the word line is at the fourth voltage or at the fifth voltage; \n the second voltage is greater than the fourth voltage, and the fourth voltage is greater than the fifth voltage; and a difference between the fourth voltage and the fifth voltage is smaller than half of a difference between the second voltage and the fifth voltage.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 2.80392
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15352609', '15150440', '15408434', '15406802', '15860786']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7934541232973822
- 35 USC 102 Novelty (BERT): 0.548202933971601
- Combined Prediction Score: 0.768929004364804
- Mean Citation Score: 333.20145200000013
- Max Citation Score: 406.0545
- Similarity Product: 396.7107924224139

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test