PATENT CLAIM ANALYSIS

Application Number: 15869769
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["365", "189050"]

Abstract:
A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

Claim (Index 10):
The non-volatile memory device of  claim 1 , wherein:\n the processing constraints comprise an implant concentration applied to ion implant processing for forming a transistor, and a first implant concentration with respect to the first transistor is greater than a second implant concentration with respect to the second transistor.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 86.0
- Lexical Diversity: 2.54
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['11618513', '15251345', '13477161', '15822320', '14177457']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8222827521683534
- 35 USC 102 Novelty (BERT): 0.4942230429910111
- Combined Prediction Score: 0.7894767812506193
- Mean Citation Score: 242.963166
- Max Citation Score: 257.2659
- Similarity Product: 188.1773013686836

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test