PATENT CLAIM ANALYSIS

Application Number: 16204909
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["398", "182000"]

Abstract:
A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Claim (Index 10):
A receiver, comprising:\n an ingress signal path comprising an ingress line-side interface and an ingress host-side interface, the ingress signal path configured to receive an analog signal vector at the ingress line-side interface, to convert the analog signal vector to a digital signal vector, to demodulate the digital signal vector to generate a digital receive signal, and to output the digital receive signal at the ingress host-side interface, the ingress signal path comprising a plurality of different ingress path clock domains operating according to different ingress path clock signals having different clock rates; an ingress-side data storage buffer between two adjacent ingress path clock domains, the ingress-side data storage buffer configured to prevent loss of data samples when an ingress path signal transitions between the two adjacent ingress path clock domains; clock and timing circuitry configured to receive a single reference clock signal, to generate the plurality of ingress path clock signals from the single reference clock, and to provide the plurality of ingress path clock signals to different components of the ingress signal path in the plurality of different ingress path clock domains; an optical module to convert an optical signal received over an optical network operating at 100 Gigahertz or higher to the analog signal vector; a physical layer processor to de-map and de-frame the digital receive signal into an output data signal; a fabric interface to transmit the output data signal to a host device; wherein the plurality of ingress path clock domains comprises: an ingress analog-to-digital converter clock domain including an analog-to-digital converter operating at a first sampling rate according to a first clock signal, the analog-to-digital converter to convert the analog signal vector to the digital signal vector; an ingress digital signal processor clock domain including an ingress digital signal processor operating at a second sampling rate according to a second clock signal, the ingress digital signal processor to demodulate the digital signal vector to generate the digital receive signal; and an ingress host interface clock domain including an ingress host interface operating at a third sampling rate according to a third clock signal, the ingress host interface to output the digital receive signal, wherein the first, second, and third sampling rates are different; wherein the ingress digital signal processor clock domain further comprises: an ingress interpolator filter to perform a sampling rate conversion between samples received from the analog-to-digital converter clock domain and samples processed in the ingress digital signal processor clock domain; and wherein the ingress interpolator filter receives an input block size having a variable number of input samples and outputs an output block having a fixed number of samples based on a parallelization factor.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.44615
- Patent Class: 398.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15647765', '15148645', '14093306', '14743660', '13655302']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.728784223742795
- 35 USC 102 Novelty (BERT): 0.6097373515949492
- Combined Prediction Score: 0.7168795365280104
- Mean Citation Score: 410.025968
- Max Citation Score: 521.692
- Similarity Product: 467.04524112081526

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test