PATENT CLAIM ANALYSIS

Application Number: 16109607
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-03
Patent Classification: ["365", "230060"]

Abstract:
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Claim (Index 13):
The memory controller IC chip according to  claim 9 , wherein:\n the timing circuitry includes circuitry to select one from a plurality of transmit delays, each of the plurality of transmit delays corresponding to a combination of memory system topology and data rate.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 96.0
- Lexical Diversity: 2.23529
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15626097', '14863366', '13720720', '12477703', '11252957']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7787046296792565
- 35 USC 102 Novelty (BERT): 0.4875968662377213
- Combined Prediction Score: 0.749593853335103
- Mean Citation Score: 195.723404
- Max Citation Score: 210.8771
- Similarity Product: 155.23020677925945

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test