PATENT CLAIM ANALYSIS

Application Number: 15748842
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-08
Patent Classification: ["257", "329000"]

Abstract:
Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

Claim (Index 16):
The non-planar transistor device of  claim 15 , wherein the gate dielectric is formed along all of the sidewalls of the channel, and wherein the gate electrode encircles the semiconductor channel.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 2.52381
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15248355', '15139478', '15435894', '15434753', '15618611']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.931498304496705
- 35 USC 102 Novelty (BERT): 0.5152424528978727
- Combined Prediction Score: 0.8898727193368218
- Mean Citation Score: 273.415784
- Max Citation Score: 282.97717
- Similarity Product: 181.4202364432484

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test