PATENT CLAIM ANALYSIS

Application Number: 15907745
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-02
Patent Classification: ["365", "189020"]

Abstract:
A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor.

Claim (Index 6):
The device of  claim 2 , wherein the non-select voltage is a voltage between the first voltage and the second voltage.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 88.0
- Lexical Diversity: 3.87179
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15051546', '14806629', '12929531', '14283209', '14979459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8032433781184808
- 35 USC 102 Novelty (BERT): 0.4760259699923005
- Combined Prediction Score: 0.7705216373058628
- Mean Citation Score: 166.52148
- Max Citation Score: 170.21468000000004
- Similarity Product: 117.28721980756048

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test