PATENT CLAIM ANALYSIS

Application Number: 15892002
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["375", "296000"]

Abstract:
A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.

Claim (Index 10):
The crosstalk cancellation circuit of  claim 9 , further comprising:\n a buffer stage having an input connected to an output of the adder.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 88.0
- Lexical Diversity: 2.25424
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15334970', '14361929', '14259485', '12727194', '14986421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4807795282780034
- 35 USC 102 Novelty (BERT): 0.5987290806490472
- Combined Prediction Score: 0.4925744835151078
- Mean Citation Score: 372.133292
- Max Citation Score: 584.8977
- Similarity Product: 421.59840060396186

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test