PATENT CLAIM ANALYSIS

Application Number: 15978235
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["326", "039000"]

Abstract:
An integrated circuit comprising a first memory array and programmable/configurable logic circuitry including a plurality of logic tiles wherein each logic tile includes a perimeter, a plurality of external I/O disposed in an I/O layout on the perimeter, wherein the I/O layout of each tile is identical. Each external I/O is configurable as an external I/O to connect to and communicate with external circuitry, or a memory I/O to point-to-point connect to memory located adjacent thereto, or an unused I/O. The first memory array is physically adjacent to a first logic tile on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and point-to-point connected to the memory I/O. In operation, circuitry of the first logic tile is configured to read data from and write data to the first memory array via the memory I/O.

Claim (Index 19):
The integrated circuit of  claim 18  wherein the first memory array includes parity or ECC circuitry.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 93.0
- Lexical Diversity: 2.59016
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15239958', '15975037', '14972553', '14712864', '15347045']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7417955913088782
- 35 USC 102 Novelty (BERT): 0.5868656261623364
- Combined Prediction Score: 0.726302594794224
- Mean Citation Score: 390.231684
- Max Citation Score: 530.7966
- Similarity Product: 443.4549335787535

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test