PATENT CLAIM ANALYSIS

Application Number: 16118863
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-07
Patent Classification: ["365", "193000"]

Abstract:
A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

Claim (Index 15):
The memory controller of  claim 14 , further comprising:\n a code generator configured to generate a code for adjusting a first delay amount of the first delay cell or a second delay amount of the second delay cell, based on at least one first value not matched with the first rising sampling value among the plurality of second rising sampling values and the plurality of third rising sampling values, or at least one second value not matched with the first falling sampling value among the plurality of second falling sampling values and the plurality of third falling sampling values.

Metadata:
- Claim Count in Document: 39.0
- Percentile: 96.0
- Lexical Diversity: 1.69767
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12044174', '12482190', '15264946', '13024448', '10931358']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.776287297713327
- 35 USC 102 Novelty (BERT): 0.4950067159183419
- Combined Prediction Score: 0.7481592395338286
- Mean Citation Score: 240.87781000000004
- Max Citation Score: 246.19704
- Similarity Product: 181.35708496264456

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test