PATENT CLAIM ANALYSIS

Application Number: 15897204
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["257", "369000"]

Abstract:
Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.

Claim (Index 2):
The method of  claim 1 , further comprising removing the masking layer and removing the first work function metal layer from over the fins within a first device region of the substrate.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 88.0
- Lexical Diversity: 1.64815
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15467536', '15830217', '15486387', '15860840', '15705888']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9282981482025534
- 35 USC 102 Novelty (BERT): 0.5199096464781622
- Combined Prediction Score: 0.8874592980301144
- Mean Citation Score: 309.4815040000001
- Max Citation Score: 321.95813
- Similarity Product: 217.19925054162383

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test