PATENT CLAIM ANALYSIS

Application Number: 15899948
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["714", "764000"]

Abstract:
Systems and methods for efficiently implementing data protection techniques that protect data stored in volatile and non-volatile memory devices from soft errors are described. The error correction overprovisioning for a plurality of memory banks may be reduced by implementing localized single-bit error parity to detect single-bit errors within each memory bank of the plurality of memory banks and then sharing a single-error correcting parity or a single-error correcting and double-error detecting parity (SECDEC) over multiple memory banks or over all of the plurality of memory banks. The single-error correcting code (e.g., a Hamming code) may be generated and shared over the plurality of memory banks such that the single-error correcting code may correct single-bit errors across multiple sets of data stored within the plurality of memory banks that correspond with a particular line or row across all of the plurality of memory banks.

Claim (Index 6):
The apparatus of  claim 1 , wherein:\n the plurality of memory banks is arranged on a first integrated circuit; and the shared memory bank is arranged on the first integrated circuit.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 88.0
- Lexical Diversity: 2.09722
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14068003', '11748595', '11836264', '12437438', '11769324']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3141478226360247
- 35 USC 102 Novelty (BERT): 0.4902077343038334
- Combined Prediction Score: 0.3317538138028056
- Mean Citation Score: 184.777582
- Max Citation Score: 201.47862
- Similarity Product: 133.30072759052754

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test