PATENT CLAIM ANALYSIS

Application Number: 16161377
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["708", "230000"]

Abstract:
A computing device (e.g., an FPGA or integrated circuit) processes an incoming packet comprising data to compute a Galois hash. The computing device includes a plurality of circuits, each circuit providing a respective result used to determine the Galois hash, and each circuit including: a first multiplier configured to receive a portion of the data; a first exclusive-OR gate configured to receive an output of the first multiplier as a first input, and to provide the respective result; and a second multiplier configured to receive an output of the first exclusive-OR gate, wherein the first exclusive-OR gate is further configured to receive an output of the second multiplier as a second input. In one embodiment, the computing device further comprises a second exclusive-OR gate configured to output the Galois hash, wherein each respective result is provided as an input to the second exclusive-OR gate.

Claim (Index 8):
The system of  claim 1 , further comprising a state machine configured to control selection by the first multiplexer of the one pre-computed key.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 2.69492
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15468331', '11716916', '14524526', '15650987', '11778151']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4313465039862946
- 35 USC 102 Novelty (BERT): 0.5701976820395988
- Combined Prediction Score: 0.445231621791625
- Mean Citation Score: 228.945574
- Max Citation Score: 440.2336
- Similarity Product: 403.0462920370103

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test