PATENT CLAIM ANALYSIS

Application Number: 16458852
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["716", "052000"]

Abstract:
A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

Claim (Index 1):
A method of fabricating an integrated circuit, the method comprising:\n defining a via grid having a first minimum pitch in a first direction and a second minimum pitch in a second direction different from the first direction; generating a first layout design of the integrated circuit based on at least the via grid or design criteria, the first layout design having a first set of vias arranged in first rows and first columns based on the via grid, the first rows of the first set of vias being arranged in the first direction, the first columns of the first set of vias being arranged in the second direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set; generating a standard cell layout design of the integrated circuit, the standard cell layout design having standard cells and a second set of vias arranged in the standard cells; generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, the via color layout design having a third set of vias, the third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias; performing a color check on the via color layout design based on design rules, and at least one of the above operations being performed by a hardware processor, and fabricating the integrated circuit based on at least the via color layout design.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 3.48889
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15258932', '15465167', '15966693', '14554958', '14484588']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3294770542100026
- 35 USC 102 Novelty (BERT): 0.510804214674902
- Combined Prediction Score: 0.3476097702564926
- Mean Citation Score: 222.11727
- Max Citation Score: 357.15204
- Similarity Product: 322.4265241956353

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test