PATENT CLAIM ANALYSIS

Application Number: 16070738
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["365", "063000"]

Abstract:
A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

Claim (Index 15):
A method for manufacturing a layered semiconductor device including, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chip, and a control chip which includes a storage unit and controls operating states of the plurality of semiconductor chips and an operating state of the reserve semiconductor chip on the basis of information stored in the storage unit, the method, the method comprising:\n a wafer inspection step of inspecting a semiconductor wafer including a plurality of the semiconductor chips and a semiconductor wafer including the reserve semiconductor chip to detect information on a defective semiconductor chip; a first layering step of layering the inspected semiconductor wafer including a plurality of the semiconductor chip and the inspected semiconductor wafer including the reserve semiconductor chip; a dicing step of dicing the layered semiconductor wafer group to form a layered semiconductor chip in which a plurality of the semiconductor chips and the reserve semiconductor chip are layered; a second layering step of layering the layered semiconductor chip and the control chip; and a storage step of storing the information on the defective semiconductor in the storage unit of the control chip.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 95.0
- Lexical Diversity: 3.125
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13200649', '13364017', '12392547', '13137849', '11837261']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7576696006670471
- 35 USC 102 Novelty (BERT): 0.4864152312453344
- Combined Prediction Score: 0.7305441637248759
- Mean Citation Score: 194.315902
- Max Citation Score: 204.48343
- Similarity Product: 145.79035983630897

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test