PATENT CLAIM ANALYSIS

Application Number: 15927270
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["257", "773000"]

Abstract:
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Claim (Index 12):
The device of  claim 11 , wherein a highest point of the lower void is higher than top surfaces of the capping patterns of the lower metal lines.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 2.95833
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15618811', '15155539', '14284674', '14703842', '14697829']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9198708840924902
- 35 USC 102 Novelty (BERT): 0.5447257093663422
- Combined Prediction Score: 0.8823563666198755
- Mean Citation Score: 303.375498
- Max Citation Score: 377.33826
- Similarity Product: 376.301374710896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test