PATENT CLAIM ANALYSIS

Application Number: 16351159
Application Type: Utility
Filing Date: 2019-03
Publication Date: 2019-07
Patent Classification: ["708", "625000"]

Abstract:
A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h-1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

Claim (Index 11):
The binary logic circuit of  claim 10 , wherein each linear segment represents part of a line that crosses the y axis at the base value.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.11268
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15696385', '14701818', '14208591', '15606351', '12396720']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4533937407505147
- 35 USC 102 Novelty (BERT): 0.5924204309852551
- Combined Prediction Score: 0.4672964097739888
- Mean Citation Score: 315.17173
- Max Citation Score: 490.05695
- Similarity Product: 459.64860233033

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test