PATENT CLAIM ANALYSIS

Application Number: 16211259
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-07
Patent Classification: ["341", "159000"]

Abstract:
A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

Claim (Index 3):
The flash ADC of  claim 1 , wherein:\n the zero crossing comparator receives a zero crossing clock to initiate the zero crossing comparator to compare the input analog voltage to the zero reference voltage; and the clock used by the reference voltage control circuit to switch the second reference voltage to the first reference node and to the second reference node comprises an inverse of the zero crossing clock.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 3.625
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15883623', '13600559', '15864090', '16139113', '12578076']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.643077620719706
- 35 USC 102 Novelty (BERT): 0.5866913471176229
- Combined Prediction Score: 0.6374389933594977
- Mean Citation Score: 307.00436
- Max Citation Score: 462.4963
- Similarity Product: 454.5380587843895

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test