PATENT CLAIM ANALYSIS

Application Number: 16220268
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-04
Patent Classification: ["257", "737000"]

Abstract:
An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.

Claim (Index 16):
An integrated circuit package assembly, comprising:\n a first integrated circuit package including a first die disposed over a first substrate, a second die disposed over the first die, and a third die disposed over the second die; wherein the first substrate has outermost sidewalls spaced apart by a first substrate width, the first die has outermost sidewalls spaced apart by a first die width that is less than the first substrate width, the second die has outermost sidewalls spaced apart by a second die width that is less than the first die width, and the third die has outermost sidewalls spaced apart by a third die width that is greater than the second die width, wherein the first substrate has a first substrate thickness less than 300 micrometers, and the third die has a third thickness less than 200 micrometers; a molding compound disposed over the first substrate, the first die, the second die, and the third die, wherein a wire bond extends through the molding compound from an upper surface of the first die to an upper surface of the first substrate; a second integrated circuit package including a second integrated circuit die mounted on a second substrate, the second integrated circuit package being disposed under the first integrated circuit package; and solder bumps disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first die and the second integrated circuit die; and wherein the solder bumps extend between the first substrate and the second substrate, and wherein the solder bumps have solder bump sidewalls that extend past outer sidewalls of the second integrated circuit die.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 98.0
- Lexical Diversity: 3.77143
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15716959', '14818877', '13353644', '14534838', '14199545']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9173341529127028
- 35 USC 102 Novelty (BERT): 0.5180279661760103
- Combined Prediction Score: 0.8774035342390336
- Mean Citation Score: 243.193156
- Max Citation Score: 281.13962000000004
- Similarity Product: 160.74943271875622

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test