PATENT CLAIM ANALYSIS

Application Number: 15912450
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["714", "747000"]

Abstract:
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

Claim (Index 41):
The memory module of  claim 40 , wherein the logic of the memory controller is further to:\n read data for locations in the cache line, wherein the data returned to the read operation includes the data read from the cache line for locations other than the location having the error and the substitute data.

Metadata:
- Claim Count in Document: 77.0
- Percentile: 90.0
- Lexical Diversity: 1.84211
- Patent Class: 714.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14757905', '14497834', '14396327', '11508758', '15875136']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2649135490902063
- 35 USC 102 Novelty (BERT): 0.5155295256723632
- Combined Prediction Score: 0.289975146748422
- Mean Citation Score: 185.915798
- Max Citation Score: 301.5376
- Similarity Product: 234.28954198350905

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test