PATENT CLAIM ANALYSIS

Application Number: 16246373
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["438", "637000"]

Abstract:
Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

Claim (Index 15):
The method of  claim 14 , wherein removing the sacrificial or permanent placeholder material of the subset of the plurality of holes or trenches through the openings in the patterning layer comprises applying an isotropic etch technique.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 99.0
- Lexical Diversity: 1.71698
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15743616', '14911991', '14914095', '14133385', '14133262']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8702066856110721
- 35 USC 102 Novelty (BERT): 0.5708988109824475
- Combined Prediction Score: 0.8402758981482096
- Mean Citation Score: 343.219122
- Max Citation Score: 457.45953
- Similarity Product: 361.6445194080305

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test