PATENT CLAIM ANALYSIS

Application Number: 16038852
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-03
Patent Classification: ["257", "173000"]

Abstract:
An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Claim (Index 9):
An electrostatic discharge (ESD), protection device comprising:\n a first bi-directional silicon controlled rectifier in a semiconductor substrate that includes:\n a first doped well of a first conductivity type; \n a first transistor in the first doped well that has an emitter connected to a first electrode of a second conductivity type, a collector coupled to a doped buried region of the second conductivity type, and a base connected to a second electrode of the first conductivity type; \n a second transistor in the first doped well that has an emitter connected to a third electrode of the second conductivity type, a collector coupled to the doped buried region, and a base connected to the second electrode, wherein the first, second and third electrodes are in the first doped well; \n a first doped substrate region of the second conductivity type adjacent the first doped well; \n a second doped well of the first conductivity type; and \n a third transistor in the first doped substrate region that has a first emitter connected to the second electrode, a base coupled to the doped buried region, and a second emitter connected to a fourth electrode of the first conductivity type, wherein the fourth electrode is in the second doped well and the doped buried region is below the first doped substrate region and the first and second doped wells.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 3.58333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13764523', '15007163', '14846168', '15587485', '11844965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9269696369915896
- 35 USC 102 Novelty (BERT): 0.5068217337069997
- Combined Prediction Score: 0.8849548466631307
- Mean Citation Score: 295.18314
- Max Citation Score: 300.70456
- Similarity Product: 245.9965711776925

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test