PATENT CLAIM ANALYSIS

Application Number: 15909987
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-11
Patent Classification: ["365", "227000"]

Abstract:
In a semiconductor device according to related art, there is a problem that it is impossible to increase an operation speed when a power supply noise is suppressed. According to one embodiment, a semiconductor device includes a first power supply line, a second power supply line that is branched off from a branching point on the first power supply line, an internal circuit configured to receive power from the second power supply line, and a clock generation circuit configured to supply an operation clock to the internal circuit, in which, when a voltage difference between a determination threshold voltage VCC 0  acquired from a position on the first power supply line that is closer to a power supply source than the branching point is and a monitor voltage VCC 1  acquired from the second power supply line exceeds a predetermined voltage, the semiconductor device changes a timing of an edge of the operation clock until that the voltage difference between the monitor voltage VCC 1  and the determination threshold voltage VCC 0  returns to a predetermined recovery possible voltage.

Claim (Index 4):
The semiconductor device according to  claim 1 , wherein\n the power supply fluctuation detection circuit comprises:\n a first comparator configured to output a first power supply fluctuation detection signal, the first power supply fluctuation detection signal being switched to an enable state when a voltage difference between a first determination threshold voltage acquired from a first measurement point of the first power supply line, the distance from the first measurement point to the branching point being a first distance, and the monitor voltage becomes equal to or larger than a pre-configured third threshold voltage and switched to a disable state when the voltage difference between the first determination threshold voltage and the monitor voltage becomes equal to or smaller than a fourth threshold voltage smaller than the third threshold voltage; and \n a second comparator configured to output a second power supply fluctuation detection signal, the second power supply fluctuation detection signal being switched to an enable state when a voltage difference between a second determination threshold voltage acquired from a second measurement point of the first power supply line, the distance from the second measurement point to the branching point being a second distance smaller than the first distance, and the monitor voltage becomes equal to or larger than a pre-configured fifth threshold voltage and switched to a disable state when the voltage difference between the second determination threshold voltage and the monitor voltage becomes equal to or smaller than a sixth threshold voltage smaller than the fifth threshold voltage, \n the clock generation circuit comprises:\n a phase inversion circuit configured to switch a logic level of a first output signal in such a way that the logic level of the first output signal becomes opposite to the logic level of an input signal; \n a first buffer circuit configured to switch a logic level of a second output signal in such a way that the logic level of the second output signal matches the logic level of the first output signal; \n a second buffer circuit configured to switch a logic level of a third output signal in such a way that the logic level of the third output signal matches the logic level of the second output signal; \n a third buffer circuit configured to switch a logic level of a fourth output signal in such a way that the logic level of the fourth output signal matches the logic level of the third output signal; and \n a selection circuit configured to select any one of the second to fourth output signals in accordance with the first power supply fluctuation detection signal and the second power supply fluctuation detection signal and use the selected output signal as a signal input to the phase inversion circuit.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 90.0
- Lexical Diversity: 2.625
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13303153', '11036393', '13064237', '11313963', '14918905']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.809084855849179
- 35 USC 102 Novelty (BERT): 0.4694653729522852
- Combined Prediction Score: 0.7751229075594896
- Mean Citation Score: 186.59851200000003
- Max Citation Score: 191.96275
- Similarity Product: 148.92902450028058

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test