PATENT CLAIM ANALYSIS

Application Number: 15946957
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["711", "118000"]

Abstract:
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Claim (Index 19):
The apparatus of  claim 10 , further comprising a select circuit,\n wherein the select circuit is incorporated into the integrated circuit memory device, and wherein the select circuit is configured to:\n receive the result data, \n receive write data to be written into the at least one bank of memory cells, and \n route one of the result data and the write data to the write driver.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 91.0
- Lexical Diversity: 2.0566
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14609963', '13243917', '11893593', '11893604', '15669538']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4664326099723976
- 35 USC 102 Novelty (BERT): 0.4609358881523679
- Combined Prediction Score: 0.4658829377903946
- Mean Citation Score: 152.49474800000004
- Max Citation Score: 172.64613
- Similarity Product: 147.47199954541682

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test