PATENT CLAIM ANALYSIS

Application Number: 15741741
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-03
Patent Classification: ["257", "072000"]

Abstract:
The present application discloses a method of fabricating a thin film transistor. The method includes forming an active layer having a channel region, a source electrode contact region, and a drain electrode contact region, on a base substrate; forming a first photoresist layer on a side of the active layer distal to the base substrate, the first photoresist layer is formed in a region outside that corresponding to the channel region; forming an insulating material layer on a side of the first photoresist layer distal to the base substrate; forming a first conductive metal material layer on a side of the insulating material layer distal to the first photoresist layer; and removing the first photoresist layer, the insulating material layer, the first conductive metal material layer, in the region outside that corresponding to the channel region by a lift-off method.

Claim (Index 9):
The method of  claim 4 , wherein the second gate insulating layer is formed using Hf x O y , or Ta x O y , Hf x O y N z , or Ta x O y N z , or a combination thereof, x>0, y>0, z>0.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 86.0
- Lexical Diversity: 3.12245
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15565377', '15533109', '15543726', '15560724', '15153767']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9281392584271536
- 35 USC 102 Novelty (BERT): 0.522067446639042
- Combined Prediction Score: 0.8875320772483425
- Mean Citation Score: 255.504488
- Max Citation Score: 292.87448
- Similarity Product: 167.59641120635987

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test