PATENT CLAIM ANALYSIS

Application Number: 16190017
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["714", "764000"]

Abstract:
A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Claim (Index 1):
A method of damage recovery for storage class memory based on nonvolatile memory using a write cache, wherein input data is written to a selected write cache location as well as a selected nonvolatile memory location, the selected write cache location includes a timestamp, and contents in the selected nonvolatile memory location are flushed to a destined location in the nonvolatile memory if the timestamp indicates that the in the selected nonvolatile memory location are aged, the method comprising:\n dividing the nonvolatile memory into memory groups; and mapping N input group addresses corresponding to logic addresses of the memory groups to M output group addresses corresponding to physical group addresses of the memory groups using fixed mapping within a period T, wherein M and N are positive integers and M is greater than N, wherein N memory groups are used as data groups, and one or more memory groups are used as redundant groups, M is equal to a sum of N and number of the redundant groups, and wherein said mapping N input group addresses to M output group addresses causes N data groups among M memory groups to store the input data in a rotated fashion; and if a damaged address location in one of the data groups is found:\n creating a repair entry in the write cache for the damaged address location with a last known correct data content; and \n updating the repair entry in the write cache by updating the timestamp of the repair entry to prevent the contents in the repair entry from being flushed to the damaged address location.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 2.91228
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15230414', '16190043', '14457113', '12348895', '13772400']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.348702783712516
- 35 USC 102 Novelty (BERT): 0.5829278796610091
- Combined Prediction Score: 0.3721252933073653
- Mean Citation Score: 334.613976
- Max Citation Score: 538.4235
- Similarity Product: 422.81698720782987

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test