PATENT CLAIM ANALYSIS

Application Number: 15870220
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["714", "764000"]

Abstract:
An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from. the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.

Claim (Index 10):
A semiconductor memory device, comprising:\n a memory cell array including a plurality of bank arrays, wherein each of the plurality of bank arrays includes a normal cell region that stores main data, and a redundancy cell region that stores first parity data associated with the main data; an error correction circuit configured to generate the first parity data based on the main data using an error correction code (ECC), and to correct at least one error hit in the main data using the first parity data, wherein the ECC is represented by a generation matrix; and a control logic circuit configured to control the error correction circuit based on a command and an address, wherein the main data includes a plurality of data bits divided into a plurality of sub codeword groups; wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups, and wherein the column vectors have elements configured to restrict a location of a sub codeword group of the plurality of sub codeword groups in which a mis-corrected bit occurs, wherein the mis-corrected bit is generated due to error bits of the main data.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.28986
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14729295', '15398409', '15204536', '15696794', '15851197']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3392428045752588
- 35 USC 102 Novelty (BERT): 0.500950582315979
- Combined Prediction Score: 0.3554135823493308
- Mean Citation Score: 299.88725
- Max Citation Score: 304.69473
- Similarity Product: 260.7497326120734

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test