PATENT CLAIM ANALYSIS

Application Number: 15949531
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["345", "211000"]

Abstract:
An EL display panel including: a pixel array section in which EL display elements whose light emission state is controlled by an active matrix driving system are arranged in a form of a matrix; a first writing control line driving section and a second writing control line driving section configured to drive each writing control line from both sides of the pixel array section; and a first power supply line driving section and a second power supply line driving section configured to drive a power supply line disposed along a direction of a horizontal line from both sides of the pixel array section, the first power supply line driving section and the second power supply line driving section being respectively arranged between the first writing control line driving section and the pixel array section and between the second writing control line driving section and the pixel array section.

Claim (Index 1):
A display device comprising:\n a plurality of pixel circuits arranged in a display area; and driving circuitry configured to drive the pixel circuits, each of the pixel circuits including a first sampling transistor, drive transistor, a capacitor, a second sampling transistor and a light emitting element, the driving circuitry including writing control line driving circuitry configured to control operation of the first sampling transistor of each of the pixels, wherein the driving circuitry is configured to drive the pixel circuits by executing: a first process to provide an offset potential through the second sampling transistor to the capacitor during a first period; a second process to provide a current through the drive transistor to the capacitor, the first process occurring before the second process; and a third process to provide a driving current based on a voltage stored in the capacitor, to the light emitting element via the drive transistor during a third period, the second process occurring before the third process, and wherein the writing control line driving circuitry includes (i) a first write control circuit disposed on a first side of the display area, and (ii) a second write control circuit disposed on a second side of the display area, the second side being an opposite side of the first side, and the first write control circuit and the second write control circuit are configured to control the operation of the first sampling transistor of each of the pixels via first scanning lines connected to both of the first write control circuit and the second write control circuit.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 91.0
- Lexical Diversity: 2.78182
- Patent Class: 345.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14450801', '12379017', '13739270', '12475227', '13626925']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6940377527532433
- 35 USC 102 Novelty (BERT): 0.5871378680236954
- Combined Prediction Score: 0.6833477642802885
- Mean Citation Score: 372.502008
- Max Citation Score: 488.792
- Similarity Product: 478.3655427265168

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test