PATENT CLAIM ANALYSIS

Application Number: 16228757
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["438", "199000"]

Abstract:
A method for producing a 3D memory device including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form memory cells within the second level and within the third level, each of the first memory cells include one first transistor, each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, the memory is NAND, the first level includes memory peripheral circuits, at least one of the first memory cells is at least partially atop a portion of the peripheral circuits.

Claim (Index 1):
A method for producing a 3D memory device, the method comprising:\n providing a first level comprising a single crystal layer; forming at least one second level above said first level; performing a first etch step comprising etching holes within said second level; forming at least one third level above said at least one second level; performing a second etch step comprising etching holes within said third level; performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,\n wherein each of said first memory cells comprise one first transistor, \n wherein each of said second memory cells comprise one second transistor, \n wherein at least one of said first or second transistors has a channel, a source and a drain having the same doping type, \n wherein said memory is a NAND nonvolatile type memory, \n wherein said first etch step is directly followed by a deposition of tunneling dielectric and then a deposition comprising polysilicon, \n wherein said first level comprises memory peripheral circuits, and \n wherein at least one of said first memory cells is at least partially atop a portion of said memory peripheral circuits.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 98.0
- Lexical Diversity: 2.68254
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15950169', '13441923', '13869963', '13041404', '12963659']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.865300839367819
- 35 USC 102 Novelty (BERT): 0.5145797402181775
- Combined Prediction Score: 0.8302287294528549
- Mean Citation Score: 277.22591600000004
- Max Citation Score: 302.87222
- Similarity Product: 234.04050639544965

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test