PATENT CLAIM ANALYSIS

Application Number: 16167425
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["708", "520000"]

Abstract:
Aspects for submatrix operations in neural network are described herein. The aspects may include a controller unit configured to receive a submatrix instruction. The submatrix instruction may include a starting address of a submatrix of a matrix, a width of the submatrix, a height of the submatrix, and a stride that indicates a position of the submatrix relative to the matrix. The aspects may further include a computation module configured to select one or more values from the matrix as elements of the submatrix in accordance with the starting address of the matrix, the starting address of the submatrix, the width of the submatrix, the height of the submatrix, and the stride.

Claim (Index 4):
The apparatus of  claim 1 , wherein the submatrix instruction is an instruction selected from a submatrix-multiply-vector (SMMV) instruction, a vector-multiply-submatrix (VMSM) instruction, a submatrix-multiply-scalar (SMMS) instruction, a TENS instruction, a submatrix-addition (SMA) instruction, a submatrix-subtraction (SMS) instruction, a submatrix-multiply-submatrix (SMM) instruction, a convolution (CONV) instruction, and a submatrix-move (SMMOVE) instruction,\n wherein the SMMV instruction further includes a first address of a first vector and a first output address for storing a first output vector, wherein the VMSM instruction further includes a second address of a second vector and a second output address for storing a second output vector, wherein the SMMS instruction further includes a third address of a scalar value and a third output address for storing a third output matrix, wherein the TENS instruction further includes a fourth address of an additional submatrix and a fourth output address for storing a fourth output matrix, wherein the SMA instruction further includes a fifth address of an additional submatrix and a fifth output address for storing a fifth output matrix, wherein the SMS instruction further includes a sixth address of an additional submatrix and a sixth output address for storing a sixth output matrix, wherein the SMM instruction further includes a seventh address of an additional submatrix and a seventh output address for storing a seventh output matrix, wherein the CONV instruction further includes an eighth address of an additional submatrix and an eighth output address for storing an eighth output matrix, and wherein the SMMOVE instruction further includes a target address for storing the moved submatrix.

Metadata:
- Claim Count in Document: 56.0
- Percentile: 97.0
- Lexical Diversity: 2.5102
- Patent Class: 708.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16039567', '15467382', '15467294', '13755222', '10671934']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3924609054019589
- 35 USC 102 Novelty (BERT): 0.5102923948819803
- Combined Prediction Score: 0.4042440543499611
- Mean Citation Score: 159.00506
- Max Citation Score: 203.96588
- Similarity Product: 131.78043108069178

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test