PATENT CLAIM ANALYSIS

Application Number: 15942938
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["257", "773000"]

Abstract:
Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

Claim (Index 13):
An apparatus comprising a memory cell array comprising an array region and an end region proximate to the array region, wherein the memory cell array comprises:\n at least one buried bit line extending in a first direction, the at least one buried bit line comprising a first portion in the array region and a second portion in the end region, the first portion comprising first connection parts, and the second portion comprising at least one second connection part; pillar transistors in the array region, each of the pillar transistors in contact with an associated one of the first connection parts of the first portion of the at least one buried bit line; buried word lines in the array region, each of the buried word lines extending in a second direction along a sidewall of an associated one of the pillar transistors, and the second direction being substantially perpendicular to the first direction; at least one semiconductor pillar in the end region, the at least one semiconductor pillar in contact with the at least one second connection part of the second portion of the at least one buried bit line; and at least one conductive connection in the end region, the at least one conductive connection protruding upwardly from the at least one second connection part of the second portion of the at least one buried bit line along a sidewall of the at least one semiconductor pillar.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 91.0
- Lexical Diversity: 2.83673
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13354957', '13404759', '13354982', '14079821', '10429643']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9197329183251034
- 35 USC 102 Novelty (BERT): 0.5094226368383765
- Combined Prediction Score: 0.8787018901764307
- Mean Citation Score: 232.690534
- Max Citation Score: 295.00375
- Similarity Product: 221.1949976438284

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test