PATENT CLAIM ANALYSIS

Application Number: 16030936
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2020-01
Patent Classification: ["257", "668000"]

Abstract:
A chip package substrate and methods for fabricating the chip package substrate. An exemplary chip package substrate generally includes a first substrate and a second substrate embedded in the first substrate and having a plurality of layered traces embedded therein.

Claim (Index 10):
The chip package substrate of  claim 1 , further comprising a layer of solder resist arranged above the first and second substrates and having one or more trenches for exposing traces coupled to the second substrate for coupling to an electronic component.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 95.0
- Lexical Diversity: 1.68
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16016888', '14671623', '10702996', '13783168', '15673954']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9082100867515764
- 35 USC 102 Novelty (BERT): 0.463375190496097
- Combined Prediction Score: 0.8637265971260284
- Mean Citation Score: 157.106504
- Max Citation Score: 160.65164
- Similarity Product: 126.2235472185421

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test