PATENT CLAIM ANALYSIS

Application Number: 15957766
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["327", "107000"]

Abstract:
Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

Claim (Index 5):
The frequency synthesizer system of  claim 2 , wherein the phase adjustment signal is a multi-bit digital signal.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 91.0
- Lexical Diversity: 2.38333
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15147408', '14726913', '14034917', '15270751', '16084997']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8221012812362578
- 35 USC 102 Novelty (BERT): 0.5501122751351782
- Combined Prediction Score: 0.7949023806261499
- Mean Citation Score: 344.18091400000014
- Max Citation Score: 448.42108
- Similarity Product: 310.4868798525882

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test