PATENT CLAIM ANALYSIS

Application Number: 16184993
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

Claim (Index 1):
A semiconductor device comprising:\n a first chip having:\n a first substrate, \n at least three first logical circuits formed on the first substrate, and \n at least two first vias extending through the first substrate in a first direction; \n a second chip being stacked on the first chip in the first direction, and having:\n a second substrate, \n at least three second logical circuits formed on the second substrate, and \n at least two second vias extending through the second substrate in the first direction; \n a third chip being stacked on the second chip in the first direction, and having:\n a third substrate, \n at least three third logical circuits formed on the third substrate, and \n at least two third vias extending through the third substrate in the first direction; and \n a fourth chip being stacked on the third chip in the first direction, and having:\n a fourth substrate, and \n at least three fourth logical circuits formed on the fourth substrate, and \n wherein:\n first ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first logical operation on a first address input signal received at the respective chip to thereby output a first address output signal, \n second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a second logical operation on a second address input signal received at the respective chip and the first address output signal transmitted within the respective chip to thereby output a second address output signal, and \n third ones of the first to third logical circuits of the first to fourth chips are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 3.16327
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15819468', '15232391', '13843165', '14552177', '13371931']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9221428412555264
- 35 USC 102 Novelty (BERT): 0.5032229129383481
- Combined Prediction Score: 0.8802508484238085
- Mean Citation Score: 263.479202
- Max Citation Score: 287.80817
- Similarity Product: 233.1121126071644

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test