PATENT CLAIM ANALYSIS

Application Number: 15909369
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-03
Patent Classification: ["365", "185180"]

Abstract:
A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.

Claim (Index 6):
The semiconductor memory device according to claim  1 , wherein the third memory cell transistor is closer to a source-side selection gate transistor than a drain-side selection gate transistor, and the second memory cell transistor is between the third memory cell transistor and the drain-side selection gate transistor.

Metadata:
- Claim Count in Document: 25.0
- Percentile: 90.0
- Lexical Diversity: 2.61905
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15051546', '15397613', '15889119', '15233658', '15885076']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8119503244113906
- 35 USC 102 Novelty (BERT): 0.4842686721978168
- Combined Prediction Score: 0.7791821591900333
- Mean Citation Score: 207.266856
- Max Citation Score: 213.90514
- Similarity Product: 152.408299631896

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test