PATENT CLAIM ANALYSIS

Application Number: 15969042
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-08
Patent Classification: ["365", "185090"]

Abstract:
A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.

Claim (Index 1):
A method of operating a semiconductor memory device including a memory cell array and an error correction circuit, the method comprising:\n selecting at least one sub-page of a page of memory cells in the memory cell array in response to a first command received from an external memory controller; reading a first unit of data including at least two sub units of data and parity data from the sub-page, wherein the at least two sub units of data includes a first sub unit of data and a second sub unit of data, the first sub unit of data is read from a first memory location of the sub-page and the second sub unit of data is read from a second memory location of the sub-page; determining, in the error correction circuit, whether the first unit of data includes an error bit; when the first unit of data includes an error bit in the second sub unit of data, correcting the error bit using the parity data of the first unit of data in the error correction circuit to provide a corrected second sub unit of data; writing back the corrected second sub unit of data to the second memory location of the sub-page, wherein a size of the first unit of data corresponds to a size of a codeword unit of the semiconductor memory device and each size of the first sub unit of data and second sub unit of data corresponds to a size of data that is pre-fetched in a read operation and a write operation of the semiconductor memory device; and wherein each size of the first sub unit of data and second sub unit of data is less than the size of the codeword unit.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 93.0
- Lexical Diversity: 1.82143
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15290339', '15398409', '15348315', '15238216', '15204536']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8360285037036821
- 35 USC 102 Novelty (BERT): 0.5549293923174302
- Combined Prediction Score: 0.8079185925650569
- Mean Citation Score: 357.6728720000001
- Max Citation Score: 429.4095
- Similarity Product: 426.74648896005743

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test