PATENT CLAIM ANALYSIS

Application Number: 15993612
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-12
Patent Classification: ["341", "161000"]

Abstract:
A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.

Claim (Index 11):
A method of determining a digital output word having a value corresponding with an analog input value with a successive approximation register (SAR) analog to digital converter (ADC), the method comprising:\n with a DAC of the SAR ADC:\n receiving an analog input voltage at an input terminal, \n receiving a digital input word, and \n generating a first voltage based on the analog input voltage and the digital input word; \n with a comparator of the SAR ADC:\n receiving the first voltage and a reference voltage, and \n generating a second voltage based on the first voltage and on the reference voltage, wherein the second voltage has a value corresponding with a sign of a difference between the first voltage and the reference voltage; \n with the DAC of the SAR ADC:\n conditionally electrically connect the input terminal to the comparator such that the comparator receives the analog input voltage as the first voltage; and \n with an SAR logic circuit of the SAR ADC:\n receiving the second voltage from the comparator, \n generating the digital input word for the DAC based on one or more second voltages received from the comparator, and \n generating the digital output word based on a plurality of second voltages received from the comparator, wherein the digital output word represents the value of the analog input voltage, and wherein the digital output word has a greater number of bits than the digital input word of the DAC.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 93.0
- Lexical Diversity: 2.91228
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15993625', '15993623', '15878375', '14587825', '15146890']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6326388338953921
- 35 USC 102 Novelty (BERT): 0.5654398310497386
- Combined Prediction Score: 0.6259189336108268
- Mean Citation Score: 346.721154
- Max Citation Score: 430.14645
- Similarity Product: 403.632468806094

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test