PATENT CLAIM ANALYSIS

Application Number: 15919897
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-07
Patent Classification: ["257", "777000"]

Abstract:
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.

Claim (Index 14):
The package of  claim 13  further comprising:\n an additional dielectric layer underlying and in contact with the core dielectric layer, wherein the third portion of the encapsulating material further extends to a level lower than a top surface of the additional dielectric layer; and \n a conductive feature extending into the additional dielectric layer.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 3.12195
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14132709', '15830458', '15272491', '14690081', '15297670']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90622621214442
- 35 USC 102 Novelty (BERT): 0.5045820526983861
- Combined Prediction Score: 0.8660617961998165
- Mean Citation Score: 181.709106
- Max Citation Score: 219.68544
- Similarity Product: 138.06107389623642

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test