PATENT CLAIM ANALYSIS

Application Number: 15978497
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "782000"]

Abstract:
A semiconductor device ( 100 ) comprising a leadframe ( 120 ) having an assembly pad ( 121 ) in a first horizontal plane ( 180 ), the pad's first surface ( 121 a ) with a semiconductor chip ( 110 ) attached; further a plurality of leads ( 122 ) in a parallel second horizontal plane ( 190 ) offset from the first plane in the direction of the attached chip, the leads having a third surface ( 122 a ) with bonding wires, and an opposite fourth surface ( 122 b ); a package ( 140 ) encapsulating leadframe, chip, and wires, the package having a fifth surface ( 140 a ) parallel to the first and second planes; a plurality of recess holes ( 150 ) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder ( 160 ) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Claim (Index 11):
A semiconductor device comprising:\n a die attach pad; a semiconductor chip attached to the die attach pad and electrically connected to a plurality of leads, the semiconductor chip including a first chip surface and an opposite second chip surface, the opposite second chip surface attached to the die attach pad; a packaging compound covering portions of the semiconductor chip, the die attach pad and the plurality of leads forming a package, a surface of the die attach pad exposed from the package on a first package surface; and a plurality of recess holes having a conductive adhesive, each of the plurality of recess holes extending from a first lead surface of each of the plurality of leads to the first package surface;\n wherein a plane along the first lead surface, a plane along a second lead surface, a plane along a third lead surface parallel to an offset from the first lead surface, and a plane long a fourth lead surface parallel to and offset from the second lead surface of each of the plurality of leads are within planes between the first chip surface and the opposite second chip surface.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 2.78788
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14453650', '14215896', '14683277', '13542827', '11051061']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.901153391150929
- 35 USC 102 Novelty (BERT): 0.5423121277608651
- Combined Prediction Score: 0.8652692648119227
- Mean Citation Score: 250.4113
- Max Citation Score: 375.82388
- Similarity Product: 351.4200368323325

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test