PATENT CLAIM ANALYSIS

Application Number: 15922571
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-07
Patent Classification: ["257", "315000"]

Abstract:
A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

Claim (Index 8):
The method of  claim 1 , wherein the second lateral distance is at least 5 times as large as the first lateral distance.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 90.0
- Lexical Diversity: 2.24
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15921858', '14625356', '13200010', '10542833', '14528785']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9300986436603156
- 35 USC 102 Novelty (BERT): 0.5402533336645667
- Combined Prediction Score: 0.8911141126607406
- Mean Citation Score: 278.315294
- Max Citation Score: 403.5612
- Similarity Product: 218.7197291791677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test