PATENT CLAIM ANALYSIS

Application Number: 15985252
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["341", "166000"]

Abstract:
A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

Claim (Index 1):
A cascaded time-to-digital converter (TDC) comprising:\n a first first-order TDC for receiving a input signal, wherein the first first-order TDC is a first-order TDC of a plurality of first-order TDCs; a second first-order TDC configured to receive as input a first time quantization error produced by the first first-order TDC, wherein the second first-order TDC is a first-order TDC of the plurality of first-order TDCs; and a combiner circuit coupled to an output of the first first-order TDC and an output of the second first-order TDC, wherein the combiner circuit is configured to produce a digital output signal by combining the output of the first first-order TDC and the output of the second first-order TDC.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 93.0
- Lexical Diversity: 2.48276
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15667114', '15660514', '13363517', '14567496', '14997504']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6089028840945299
- 35 USC 102 Novelty (BERT): 0.5390161818869772
- Combined Prediction Score: 0.6019142138737746
- Mean Citation Score: 264.090824
- Max Citation Score: 370.49374
- Similarity Product: 280.74531000742195

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test