PATENT CLAIM ANALYSIS

Application Number: 16001991
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-02
Patent Classification: ["341", "118000"]

Abstract:
A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

Claim (Index 15):
A non-transitory computer-readable storage for storing a code, when executed, to implement a method in  claim 8 .

Metadata:
- Claim Count in Document: 3.0
- Percentile: 94.0
- Lexical Diversity: 2.14706
- Patent Class: 341.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10709996', '11755011', '13830382', '15979883', '14957418']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5686297366830301
- 35 USC 102 Novelty (BERT): 0.5258662265419011
- Combined Prediction Score: 0.5643533856689172
- Mean Citation Score: 222.214352
- Max Citation Score: 223.81844
- Similarity Product: 122.98724301282408

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test