PATENT CLAIM ANALYSIS

Application Number: 16166762
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["257", "401000"]

Abstract:
An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

Claim (Index 20):
The semiconductor device of  claim 13 , wherein the source/drain region is a first source/drain region, the dielectric layer is a first dielectric layer, and the contact is a first contact, and further wherein the semiconductor device further comprises:\n a third gate structure and a fourth gate structure disposed over a semiconductor layer, wherein third spacers are disposed along sidewalls of the third gate structure and fourth spacers are disposed along sidewalls of the fourth gate structure; a second source/drain region disposed in the semiconductor layer between the third gate structure and the fourth gate structure; a third interlevel dielectric layer disposed over the semiconductor layer and between the third spacers and the fourth spacers, wherein a portion of the third interlevel dielectric layer has a third recessed upper surface; a second dielectric layer disposed directly on the third spacers, the fourth spacers, and the third recessed upper surface of the first interlevel dielectric layer, wherein a portion of the second dielectric layer has a fourth recessed upper surface, wherein the portion of the dielectric layer having the fourth recessed upper surface is disposed over the portion of the third interlevel dielectric layer having the third recessed upper surface; a fourth interlevel dielectric layer disposed over the second dielectric layer; and a second contact that extends through the fourth interlevel dielectric layer, the second dielectric layer, and the third interlevel dielectric layer to the second source/drain region.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 97.0
- Lexical Diversity: 4.15385
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15445481', '14739233', '14832530', '15364488', '15153249']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.922157235064442
- 35 USC 102 Novelty (BERT): 0.4843498464304191
- Combined Prediction Score: 0.8783764962010396
- Mean Citation Score: 194.69188
- Max Citation Score: 199.36269
- Similarity Product: 147.38173322717068

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test