PATENT CLAIM ANALYSIS

Application Number: 16014011
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["365", "158000"]

Abstract:
A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

Claim (Index 24):
A memory device comprising:\n a memory cell array including memory cells; a row decoder connected with the memory cell array through word lines; a column decoder connected with the memory cell array through bit lines and source lines; a write driver configured to output a write voltage in a write operation; and a sense amplifier configured to output a read voltage in a read operation, wherein the column decoder includes switches connected to the bit lines and the source lines,\n wherein each of the switches is connected to a corresponding bit line of the bit lines and a corresponding source line of the source lines, and \n a read and write decoder configured to connect the bit lines and the source lines with the write driver in the write operation and to connect the bit lines and the source lines with the sense amplifier in the read operation, wherein each of the switches includes a first NMOS transistor and a first PMOS transistor, which connect the corresponding bit line and the write driver, wherein, in the write operation, in a switch selected from the switches, a power supply voltage is transferred to a gate of the first NMOS transistor, and a ground voltage is transferred to a gate of the first PMOS transistor, and wherein, in the write operation, in an unselected switch of the switches, the ground voltage is transferred to the gate of the first NMOS transistor, and the write voltage is transferred to the gate of the first PMOS transistor.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 2.7
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['13186245', '15989340', '12686176', '14839606', '14501352']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8138982131231676
- 35 USC 102 Novelty (BERT): 0.4967226967016065
- Combined Prediction Score: 0.7821806614810115
- Mean Citation Score: 274.909048
- Max Citation Score: 302.7223
- Similarity Product: 267.138479839325

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test