PATENT CLAIM ANALYSIS

Application Number: 15925741
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["709", "226000"]

Abstract:
A method, apparatus and system for a secure memory with restricted access by processors. System has a plurality of processor units (PUs) coupled to a block of memory with at least one section secured (BMSS) against hacking by not allowing all PUs to access BMSS. One or more PUs has access to BMSS and is implemented with a dedicated function(s) that no other PU can perform such as a security function for encryption key checks. A thread running on a given PU that lacks access to a given memory location in BMSS is transferred to another PU with i) access to given memory location in BMSS; ii) implemented dedicated function; and/or iii) locked down instruction memory not free to run other code. Any attempt to breach protocol issues a fault. Existing code is hardened against less secure user code by only permitting authorized routines to transfer to the implemented PU.

Claim (Index 4):
The computer-readable medium of  claim 3 , wherein:\n the another PU is an only PU implemented for performing a SECURITY function.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.77895
- Patent Class: 709.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['11959793', '11959804', '11959652', '14563608', '10806633']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.268959968838364
- 35 USC 102 Novelty (BERT): 0.4911688295461763
- Combined Prediction Score: 0.2911808549091452
- Mean Citation Score: 129.22304
- Max Citation Score: 132.70207
- Similarity Product: 75.67676112715363

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test