PATENT CLAIM ANALYSIS

Application Number: 16126680
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-03
Patent Classification: ["712", "225000"]

Abstract:
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

Claim (Index 1):
A digital data processor comprising:\n an instruction memory storing instructions each specifying a data processing operation and at least one data operand field; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results; a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including\n an address generator for generating stream memory addresses corresponding to said stream of an instruction specified sequence of a plurality of data elements, \n a stream buffer receiving and temporarily storing data corresponding to said stream memory addresses, said stream buffer including a plurality of cache lines, each cache line including a plurality of data bits and a plurality of address tag bits corresponding to said data bits, \n a stream head register storing a data element of said stream next to be used by said at least one functional unit; and \n wherein said at least one functional unit is responsive to a stream operand instruction to receive at least one operand from said stream head register.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 97.0
- Lexical Diversity: 1.81395
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15384342', '15384416', '15384355', '15384378', '15384514']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6638002286664508
- 35 USC 102 Novelty (BERT): 0.5735084265469489
- Combined Prediction Score: 0.6547710484545007
- Mean Citation Score: 430.39085
- Max Citation Score: 472.44138
- Similarity Product: 451.5611590992057

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test