PATENT CLAIM ANALYSIS

Application Number: 16111263
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["257", "329000"]

Abstract:
Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Claim (Index 8):
A method comprising:\n forming a semiconductor layer on a substrate and an additional semiconductor layer on the semiconductor layer, the additional semiconductor layer comprising a first semiconductor material and the semiconductor layer comprising a second semiconductor material that is different from the first semiconductor material; patterning a semiconductor body in an upper portion of the additional semiconductor layer; doping a lower portion of the additional semiconductor layer for a first source/drain region of a vertical field effect transistor of a memory cell of a memory array; depositing a sacrificial layer; forming a mask section on the sacrificial layer aligned above the semiconductor body, the mask section being wider than the semiconductor body; performing an anisotropic etch process to form trenches that extend through the sacrificial layer, through the lower portion of the additional semiconductor layer, through the semiconductor layer and into the substrate, the anisotropic etch process shaping the first source/drain region in the lower portion of the additional semiconductor layer and a semiconductor region in the semiconductor layer such that the first source/drain region and the semiconductor region have essentially equal widths; performing an isotropic etch process to etch back sidewalls of the semiconductor region such that the semiconductor region is narrower than the first source/drain region and such that cavities are created below the first source/drain region and positioned laterally adjacent to the semiconductor region; removing the mask section; depositing a conductor to fill the cavities; performing an additional anisotropic etch process to form additional trenches extending vertically through the conductor, the additional anisotropic etch process shaping a bitline for the memory array below the first source/drain region, the bitline comprising:\n a pair of essentially parallel, elongated, bitline sections extending a length of the bitline and comprising a first bitline section and a second bitline section; and \n the semiconductor region positioned laterally between the first bitline section and the second bitline section; and \n depositing a blanket layer of interlayer dielectric material in the additional trenches, wherein the blanket layer is deposited such that an airgap formed.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 1.85542
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15661058', '16009331', '15994392', '15873156', '15920748']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9336810602774775
- 35 USC 102 Novelty (BERT): 0.560813864978041
- Combined Prediction Score: 0.8963943407475341
- Mean Citation Score: 352.76871199999994
- Max Citation Score: 460.6132
- Similarity Product: 356.47845392665863

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test