PATENT CLAIM ANALYSIS

Application Number: 15925491
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["330", "297000"]

Abstract:
A receiver front end having low noise amplifiers (LNAs) with enhanced input third order intercept point is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured load FET have a degeneration circuit comprising a tank circuit tuned to a harmonic of the operating frequency.

Claim (Index 21):
The method of  claim 20 , wherein determining total impedance required for an input impedance matching circuit and a degeneration circuit at an operating frequency further includes:\n (a) determining a gate to source capacitance of the input FET, (b) determining a value of a blocking capacitor within the input impedance matching circuit; and (c) based on the gate to source capacitance of the input FET, and based on the determination of the value of the blocking capacitor, and further based on the ratio of impedance between the input impedance matching circuit and the degeneration circuit at the operating frequency, determining the value of the components of the tank circuit within the degeneration circuit and the value of an inductor within the input impedance matching circuit.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 90.0
- Lexical Diversity: 1.31111
- Patent Class: 330.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15895863', '15616824', '11969375', '15430332', '15887816']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7756746428248013
- 35 USC 102 Novelty (BERT): 0.5191598502855674
- Combined Prediction Score: 0.750023163570878
- Mean Citation Score: 243.597264
- Max Citation Score: 261.65985
- Similarity Product: 171.75342287995218

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test