PATENT CLAIM ANALYSIS

Application Number: 15755757
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-01
Patent Classification: ["257", "401000"]

Abstract:
A TFT device is manufactured starting from a substrate with mutually insulated elongated strips of semi-conductor material. A stack of layers over the strips on the substrate, the stack comprising a gate electrode layer. A multi-level resist layer is provided over the gate electrode layer. The multi-level resist layer defines gate and source drain regions, the channel running in parallel with the direction of the strips. Gate portions in the resist layer cross source drain regions in the resist layer, overreaching the source drain regions on either side at least by a distance corresponding to a pitch of the strips.

Claim (Index 4):
A method according  claim 1  comprising applying a conductivity increasing treatment to the strips after said etching of the multi-level resist layer at least down from the first resist height level.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 88.0
- Lexical Diversity: 1.96364
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['11144204', '13172543', '10482101', '12807215', '10849000']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8971548742943954
- 35 USC 102 Novelty (BERT): 0.4942208336467805
- Combined Prediction Score: 0.8568614702296339
- Mean Citation Score: 175.62777
- Max Citation Score: 179.41284
- Similarity Product: 118.15600877423286

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test