PATENT CLAIM ANALYSIS

Application Number: 16239165
Application Type: Utility
Filing Date: 2019-01
Publication Date: 2019-05
Patent Classification: ["716", "052000"]

Abstract:
An apparatus including a memory storing instructions and a processor executing the instructions to perform a method including: performing error processing of an initial design file layout; detecting a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules; retargeting the Vx for generating a resulting design file layout of the semiconductor structure; and generating a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.

Claim (Index 17):
The system of  claim 16 , wherein the third processor retargets the design values for the Vx is based on adjusting design values for any of the Ma, a metal layer (Mb) below the Vx that connects the Ma through the Vx and the Vx that connects the Ma and the Mb, and adjusting design values of both the Ma and the Mb provide fixing metal tip or metal ending across cell boundaries.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 99.0
- Lexical Diversity: 2.09259
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15811006', '13760571', '14525833', '14699705', '13628278']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3163939365504489
- 35 USC 102 Novelty (BERT): 0.5525884025305826
- Combined Prediction Score: 0.3400133831484623
- Mean Citation Score: 188.9610508
- Max Citation Score: 442.241
- Similarity Product: 419.7639431016445

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test