PATENT CLAIM ANALYSIS

Application Number: 15884911
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["370", "411000"]

Abstract:
Significantly optimized multi-stage networks with scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several slices of rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ multi-drop links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block

Claim (Index 1):
A programmable integrated circuit comprising a plurality of programmable logic blocks and a network, and\n said plurality of programmable logic blocks comprising a plurality of inlet links and a plurality of outlet links; and said network further comprising a plurality of subnetworks and with each subnetwork coupled with at least one of said plurality of programmable logic blocks; and, said network further comprising a plurality of external links and a plurality of internal links; and said plurality of subnetworks coupled with said plurality of programmable logic blocks arranged in a two-dimensional grid of rows and columns; and each subnetwork comprising y stages, where y\u22651; and each stage comprising a switch of size d i \u00d7d o , where d 1 \u22652 and d o \u22652 and each switch of size d i \u00d7d o  further comprising multiplexers of variable size d\u22652 with each multiplexer comprising d inputs and one output; and Said inlet links are connected to the output of one of said multiplexers of one said switch of one said stage of one said subnetwork, and said outlet links are connected to one of the inputs of one or more of said multiplexers of one or more said switches of one or more said stages of one of more said subnetworks; and each programmable logic block may or may not be comprising the same number of said inlet links and may or may not be comprising the same number of said outlet links; each subnetwork of the plurality of subnetworks may or may not be comprising the same number of said stages; each stage may or may not be comprising the same number of said switches; and each switch in each stage may or may not be of the same size, each multiplexer in each stage may or may not be of the same size; and each internal link of said plurality of internal links connected from output of one multiplexer in one subnetwork to input of another multiplexer in the same subnetwork; and each external link of said plurality of external links is connected from the output of one of said multiplexers of one said switch of one said stage of one said subnetwork to one of the inputs of one or more of said multiplexers of one or more said switches of one or more said stages of one of more said subnetworks; and said one or more external links may be connected between same numbered switches in two different subnetworks or said one or more external links may be connected between different numbered switches in two different subnetworks.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 86.0
- Lexical Diversity: 2.05333
- Patent Class: 370.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15140470', '14329876', '14199168', '15859726', '15331855']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.643138319793387
- 35 USC 102 Novelty (BERT): 0.6250174870791458
- Combined Prediction Score: 0.6413262365219629
- Mean Citation Score: 566.998606
- Max Citation Score: 595.89307
- Similarity Product: 532.1900546395291

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test