PATENT CLAIM ANALYSIS

Application Number: 15859895
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-01
Patent Classification: ["257", "659000"]

Abstract:
Provided is a semiconductor package having high electric reliability. The semiconductor package includes a lower sub-semiconductor package including a lower semiconductor chip and a lower mold layer on the lower semiconductor chip and having a mold via hole, an upper sub-semiconductor package including an upper semiconductor chip, a filling layer that is between the lower sub-semiconductor package and the upper sub-semiconductor package, a connection via in the mold via hole that penetrates the lower mold layer and the filling layer and electrically connects the lower sub-semiconductor package to the upper sub-semiconductor package. The filling layer includes an extending part of the filling layer that extends into the mold via hole of the filling layer from a portion having a higher level than a top surface of the lower mold layer.

Claim (Index 11):
A semiconductor package comprising:\n a lower sub-semiconductor package comprising a lower package base substrate, a lower semiconductor chip on the lower package base substrate, and a lower mold layer on the lower semiconductor chip on a top surface of the lower package base substrate, wherein the lower mold layer comprises a mold via hole; an upper sub-semiconductor package comprising an upper package base substrate and an upper semiconductor chip on the upper package base substrate; a filling layer that is between the lower sub-semiconductor package and the upper sub-semiconductor package; a connection via in the mold via hole that penetrates the lower mold layer and the filling layer, and electrically connects the lower package base substrate to the upper package base substrate; and an electromagnetic wave shielding member that is on a side surface of the lower sub-semiconductor package, a side surface of the filling layer, and/or side and/or top surfaces of the upper sub-semiconductor package, wherein the connection via comprises a widest width at a level lower than a top surface of the lower mold layer.

Metadata:
- Claim Count in Document: 35.0
- Percentile: 86.0
- Lexical Diversity: 2.89362
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14531994', '15392275', '13243704', '15806618', '14504972']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9063427306181688
- 35 USC 102 Novelty (BERT): 0.4913378979359642
- Combined Prediction Score: 0.8648422473499484
- Mean Citation Score: 242.16214200000005
- Max Citation Score: 245.61641
- Similarity Product: 209.0607495829964

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test