PATENT CLAIM ANALYSIS

Application Number: 15980966
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["257", "314000"]

Abstract:
According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.

Claim (Index 3):
The semiconductor memory device according to  claim 2 ,\n the first through third wiring lines being provided in an identical wiring line layer.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 93.0
- Lexical Diversity: 2.70213
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14845796', '14834636', '15269082', '15237984', '15699300']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.921213106459412
- 35 USC 102 Novelty (BERT): 0.4999749955244342
- Combined Prediction Score: 0.8790892953659142
- Mean Citation Score: 204.65247
- Max Citation Score: 271.7597
- Similarity Product: 223.13683491718768

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test