PATENT CLAIM ANALYSIS

Application Number: 15949692
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-08
Patent Classification: ["711", "137000"]

Abstract:
Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Claim (Index 17):
A device comprising:\n a plurality of processing units, each of the processing units configured to execute one or more of a plurality of work unit handlers (WU handlers) for processing stream fragments, and wherein each of the processing units include a level one (L1) buffer cache; a memory to store the stream fragments; a plurality of queues configured to hold work units, each of the work units associated with one or more stream fragments, and wherein each of the work units identifies one of the WU handlers for processing the one or more stream fragments; and a load store unit configured to:\n identify, prior to completion of processing of a first work unit by a first processing unit of the plurality of processing units, a second work unit that is expected to be processed by the first processing unit after the first work unit, wherein the first processing unit processes the first work unit by accessing data associated with the first work unit in an active segment of the L1 buffer cache included within the first processing unit, \n prefetch, from the memory, data associated with the second work unit into a standby cache segment of the L1 buffer cache included within the first processing unit, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the first processing unit, \n flush, after the processing of the first work unit is complete, the active cache segment of the buffer cache, wherein flushing the active first cache segment includes storing, in the memory, the data modified by the first work unit, and generate a message indicating that the data processed by the first work unit can be accessed from the memory.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 91.0
- Lexical Diversity: 2.27536
- Patent Class: 711.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15949892', '11250054', '14701371', '14796167', '13712094']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4519964681233338
- 35 USC 102 Novelty (BERT): 0.4999394741945722
- Combined Prediction Score: 0.4567907687304577
- Mean Citation Score: 179.710804
- Max Citation Score: 240.94691
- Similarity Product: 177.7252338282341

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test