PATENT CLAIM ANALYSIS

Application Number: 16138252
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["257", "773000"]

Abstract:
A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.

Claim (Index 9):
The semiconductor device as claimed in  claim 1 , wherein the conductive paste is in direct contact with the interconnect trace.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12446899', '15852479', '13753570', '11886904', '13682510']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.92366091023874
- 35 USC 102 Novelty (BERT): 0.4595362979360174
- Combined Prediction Score: 0.8772484490084677
- Mean Citation Score: 181.85871
- Max Citation Score: 186.2088
- Similarity Product: 164.60382948832512

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test