PATENT CLAIM ANALYSIS

Application Number: 15990517
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-01
Patent Classification: ["375", "376000"]

Abstract:
A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.

Claim (Index 18):
An integrated circuit, comprising:\n a quarter-rate clock source configured to generate a quarter-rate clock signal; means for doubling a frequency of the quarter-rate clock signal to produce a first half-rate clock signal having a frequency that is twice a frequency of the quarter-rate clock signal; and a serializer transmitter configured to serialize a parallel input data stream into a serialized data stream responsive to the first half-rate clock signal, wherein a data rate for the serialized data stream is twice the frequency for the first half-rate clock signal.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 93.0
- Lexical Diversity: 1.2
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14320736', '15479423', '15273621', '15667251', '15367071']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4926000158141241
- 35 USC 102 Novelty (BERT): 0.4944803960477262
- Combined Prediction Score: 0.4927880538374843
- Mean Citation Score: 234.69520000000003
- Max Citation Score: 248.81186
- Similarity Product: 187.7734921382904

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test