PATENT CLAIM ANALYSIS

Application Number: 15872124
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["375", "233000"]

Abstract:
A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Claim (Index 1):
A device configured to simultaneously generate a plurality of bias levels, comprising:\n a first bias level generator comprising a first output, wherein the first bias level generator is configured to generate a first bias level of the plurality of bias levels and transmit the bias level having a first voltage value from the first output; a second bias level generator comprising a second output, wherein the second bias level generator is configured to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value from the second output; and a voltage divider coupled to the first output and the second output, wherein the voltage divider is configured to interpolate a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level, wherein the plurality of bias levels comprises the first bias level, the second bias level and the subset of bias levels, wherein the voltage divider comprises a third output configured to supply a selected bias level of the plurality of bias levels and transmit the selected bias level as a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 86.0
- Lexical Diversity: 2.77083
- Patent Class: 375.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15872140', '15864972', '15716162', '15716132', '15841144']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.4844372422924504
- 35 USC 102 Novelty (BERT): 0.5232298314250406
- Combined Prediction Score: 0.4883165012057094
- Mean Citation Score: 249.96935
- Max Citation Score: 344.20184
- Similarity Product: 282.22283612668986

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test