PATENT CLAIM ANALYSIS

Application Number: 16092001
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-04
Patent Classification: ["365", "148000"]

Abstract:
The invention relates to an electronic memristive device that has a complementary analogue reconfigurable memristive bidirectional resistive switch. The device has a memristive layer sequence having a BFTO/BFO/BFTO three-ply layer and two electrodes. Titanium traps are arranged in the BFTO interfaces. As a result of mobile acid vacancies, the potential barriers at the interfaces of the electrodes with respect to the memristive layer sequence are in flexible form. By applying voltage pulses, the acid vacancies can be shifted from the interface with respect to the first electrode to the interface with respect to the second electrode, with raising of the potential barrier at one electrode bringing about complementary lowering of the potential barrier of the other electrode. The method according to the invention for operating the device proposes adapted writing processes that use the overlaying of writing pulse sequences to achieve stipulation of a state pair of complementary resistor states. In conjunction with reading pulses of adapted polarity, the device can implement fuzzy logic and be operated as an artificial synapse with the realisation of all four learning curves for complementary learning. A plurality of options for the use of the device operated according to the invention are proposed

Claim (Index 9):
Method for operating a memristive complementary analogue reconfigurable device according to  claim 1 , as an artificial synapse, characterised in that\n the first and second electrode correspond to artificial neurons, and in this case the first electrode is used as an artificial presynaptic neuron and the second electrode is used as an artificial postsynaptic neuron, a writing pulse sequence applied to the presynaptic neuron corresponds to a presynaptic pulse, and a writing pulse sequence applied to the postsynaptic neuron corresponds to a postsynaptic pulse, and\n a writing pulse sequence pair that is applied between the presynaptic and postsynaptic neuron corresponds to a spike-timing dependent plasticity pair (referred to in the following as STDP pair), \n a negative STDP pair corresponds to a negative writing pulse sequence pair, and \n a positive STDP pair corresponds to a positive writing pulse sequence pair, \n learning curves of the synapses are defined in that\n the complementary resistance states of the continuous transition between the complementary end states PHRS and PLRS correspond to an LTP learning curve, \n the complementary resistance states of the continuous transition between the complementary end states NHRS and NLRS correspond to an anti-LTP learning curve, \n the complementary resistance states of the continuous transition between the complementary end states PLRS and PHRS correspond to an LTD learning curve, \n the complementary resistance states of the continuous transition between the complementary end states NLRS and NHRS correspond to an anti-LTD learning curve, \n the LTP and anti-LTD learning curves are a pair of mutually complementary learning curves and the anti-LTP and LTD learning curves are a pair of mutually complementary learning curves, \n the current output signal s of the reading pulses correspond to the conductivities of the artificial synapses, and complementary learning is implemented by means of complementary resistance states of one of the two state pairs being written, by means of an initialisation pulse, as defined in  claim 3 , being applied to the presynaptic neuron or postsynaptic neuron, and a) subsequently, a writing process, as defined in claim  1 a), being carried out by means of the pair of the presynaptic and postsynaptic pulse being superimposed with one another, the presynaptic pulse being applied to the presynaptic neuron and the postsynaptic pulse being applied to the postsynaptic neuron, and the determination of the state pair of complementary resistance states takes place when, due to the temporal superimposition of the writing pulse, having the falling edge, of the presynaptic pulse, and the guide pulse of the postsynaptic pulse, the absolute value of the voltage of the superimposed pulses reaches or exceeds the absolute value of a minimum writing voltage for the minimum writing period that is dependent on the minimum writing voltage, and the absolute value of the temporal offset of the superimposed pulses determining the position of the written complementary resistance states of the state pair between the respective complementary end states, and thus the position thereof on the learning curves, b) the written complementary resistance states subsequently being read out in a reading process, by means of two reading pulses, which are temporally mutually offset and are of opposing polarities, being applied to the presynaptic neuron or the postsynaptic neuron,\n the reading pulses reading out the state pair on the LTP and anti-LTD learning curves for a preceding positive STDP pair, or \n the reading pulses reading out the state pair on the anti-LTP and LTD learning curves for a preceding negative STDP pair.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 97.0
- Lexical Diversity: 2.0
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14038197', '14126397', '14126410', '14862187', '13408134']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7619882212593441
- 35 USC 102 Novelty (BERT): 0.4767083839740765
- Combined Prediction Score: 0.7334602375308172
- Mean Citation Score: 162.47133200000005
- Max Citation Score: 177.66513
- Similarity Product: 132.7384890904033

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test