PATENT CLAIM ANALYSIS

Application Number: 16104382
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "329000"]

Abstract:
A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D 1 , between two vertical fin segments.

Claim (Index 6):
The method of  claim 1 , further comprising removing the fin liner and a portion of a doped region beneath the vertical fins to extend each of the one or more fin trench(es) to the substrate and form two doped region segments from each of the doped regions.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 96.0
- Lexical Diversity: 2.41071
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15177362', '15178193', '15789620', '15177358', '16046273']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9410468148816534
- 35 USC 102 Novelty (BERT): 0.611833058130271
- Combined Prediction Score: 0.9081254392065152
- Mean Citation Score: 466.875316
- Max Citation Score: 581.73004
- Similarity Product: 501.2515666632653

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test