PATENT CLAIM ANALYSIS

Application Number: 15928587
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["365", "201000"]

Abstract:
The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.

Claim (Index 10):
A circuit, comprising:\n a built-in self test (BIST) control configured to route a plurality of activity factors to a BIST circuit, wherein: the BIST circuit includes at least one activity register configured to store a programmable value, and the BIST circuit is configured to run a BIST pattern in a loop mode on a memory and measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory, wherein the at least one activity register comprises a read activity register, a write activity register, a search activity register, and any other modes register.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 90.0
- Lexical Diversity: 1.55814
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13569276', '13685779', '10876864', '14060872', '10893412']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7775793138759738
- 35 USC 102 Novelty (BERT): 0.4671323711378548
- Combined Prediction Score: 0.7465346196021619
- Mean Citation Score: 156.0627
- Max Citation Score: 168.13541999999995
- Similarity Product: 122.71556948771948

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test