PATENT CLAIM ANALYSIS

Application Number: 16006981
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["257", "076000"]

Abstract:
An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Claim (Index 16):
The method of  claim 10 , wherein the second etch results in the spacer layer being thicker in the gate region than outside the gate region, and the thickness of the spacer layer outside the gate region is substantially uniform.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 1.94118
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12756088', '13292487', '14445988', '12756960', '13403400']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.919909319728137
- 35 USC 102 Novelty (BERT): 0.5240293259706285
- Combined Prediction Score: 0.8803213203523862
- Mean Citation Score: 281.235038
- Max Citation Score: 291.93982
- Similarity Product: 187.7127297539914

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test