PATENT CLAIM ANALYSIS

Application Number: 15909404
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-04
Patent Classification: ["365", "185030"]

Abstract:
A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.

Claim (Index 1):
A semiconductor memory device, comprising:\n a plurality of memory cells that store first data values for multiple bits according to a first threshold voltage and second data values for the multiple bits according to a second threshold voltage higher than the first threshold voltage; a plurality of word lines and plurality of bit lines connected to the plurality of memory cells, each memory cell being respectively connected to one word line and one bit line; and a controller configured to write data to the plurality of memory cells in a write operation including a program loop with a verification operation following a program operation, wherein the controller is configured to, during the verification operation: apply a first verification voltage to a word line connected to a first memory cell, and then apply a second verification voltage higher than the first verification voltage to the word line, apply a first voltage to a bit line connected to the first memory cell while the first verification voltage is being applied to the word line, apply a second voltage lower than the first voltage to a bit line connected to a second memory cell that is connected to the word line while the first verification voltage is being applied to the word line, and if the first memory cell passes verification at the first verification voltage, apply the first voltage to the bit line connected to the first memory cell and to the bit line connected to the second memory cell while the second verification voltage is being applied the word line.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 90.0
- Lexical Diversity: 2.51282
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15405098', '15690256', '15908449', '15195560', '14630505']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7740067045849215
- 35 USC 102 Novelty (BERT): 0.4977667278328423
- Combined Prediction Score: 0.7463827069097136
- Mean Citation Score: 251.253478
- Max Citation Score: 284.98608
- Similarity Product: 248.14480344311715

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test