PATENT CLAIM ANALYSIS

Application Number: 15984779
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185180"]

Abstract:
A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Claim (Index 16):
A method for executing a programming step of a writing operation performed on a first memory cell of a memory location of an electrically-erasable and programmable memory type, wherein the first memory cell comprises a first transistor having a first control gate, a first floating gate underlying the first control gate, and a first gate dielectric underlying the first floating gate, the memory location further comprising a second memory cell comprising a second transistor having a second control gate, a second floating gate underlying the second control gate, and a second gate dielectric underlying the second floating gate, wherein the second floating gate is coupled to the first floating gate to form a common floating gate, the method comprising:\n applying a programming voltage to a drain terminal of the first transistor and to a drain terminal of the second transistor and applying a first voltage, different from the programming voltage, to the first control gate and to the second control gate in a first programming phase, wherein an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric in the first programming phase; and maintaining the programming voltage on the drain terminal of the first transistor and applying an auxiliary voltage to the drain terminal of the second transistor in a second programming phase subsequent to the first programming phase, the auxiliary voltage having a value chosen so as to decrease a potential of the second floating gate of the second transistor, and wherein a voltage across the second gate dielectric but not the first gate dielectric is decreased in the second programming phase.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 93.0
- Lexical Diversity: 2.375
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15682102', '15221318', '14795742', '14724229', '15276462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.77815490584515
- 35 USC 102 Novelty (BERT): 0.5830765386183228
- Combined Prediction Score: 0.7586470691224673
- Mean Citation Score: 321.40461399999987
- Max Citation Score: 487.25003
- Similarity Product: 451.11610037035217

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test