PATENT CLAIM ANALYSIS

Application Number: 16124946
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["438", "130000"]

Abstract:
Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Claim (Index 13):
The FinFet structure of  claim 10 , further comprising a second transistor; and\n wherein the second transistor is floated by shorting a drain terminal and a source terminal of the second transistor to the common power net.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 97.0
- Lexical Diversity: 1.83516
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15613712', '15629728', '15629725', '13735227', '16109512']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8603127017345165
- 35 USC 102 Novelty (BERT): 0.5602876684162009
- Combined Prediction Score: 0.8303101984026849
- Mean Citation Score: 280.30061
- Max Citation Score: 478.28415
- Similarity Product: 321.0229137798965

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test