PATENT CLAIM ANALYSIS

Application Number: 15860318
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "751000"]

Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

Claim (Index 19):
A method comprising:\n forming a lower level wiring structure; forming a via which exposes the lower level wiring structure; forming a wiring trench above the via; filling the via with cobalt and lining sidewalls of the wiring trench with the cobalt in a same deposition process; lining the cobalt with a barrier liner such that the barrier liner separates the cobalt from conductive material in both the wiring structure and the via structure, the barrier liner also extending over the via to separate the cobalt in the via and the conductive material in the wiring trench; and filling the wiring trench, over the cobalt lining, with the conductive material which is different than the cobalt.

Metadata:
- Claim Count in Document: 24.0
- Percentile: 86.0
- Lexical Diversity: 1.72973
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15437065', '15709956', '15643742', '15338070', '15345882']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9137693252309572
- 35 USC 102 Novelty (BERT): 0.4819457490385276
- Combined Prediction Score: 0.8705869676117143
- Mean Citation Score: 199.287438
- Max Citation Score: 206.79254
- Similarity Product: 156.6622092596805

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test