PATENT CLAIM ANALYSIS

Application Number: 16505411
Application Type: Utility
Filing Date: 2019-07
Publication Date: 2019-10
Patent Classification: ["257", "329000"]

Abstract:
A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

Claim (Index 14):
The VFET of  claim 13 , wherein the dielectric spacers comprise an oxide material and the encapsulation layer comprises a nitride material.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 100.0
- Lexical Diversity: 2.41176
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15791095', '15843318', '15833543', '15863000', '15994720']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9426913729673112
- 35 USC 102 Novelty (BERT): 0.6351822991788397
- Combined Prediction Score: 0.911940465588464
- Mean Citation Score: 461.10919400000006
- Max Citation Score: 629.39825
- Similarity Product: 546.7089072441458

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test