PATENT CLAIM ANALYSIS

Application Number: 15987735
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185010"]

Abstract:
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Claim (Index 5):
A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:\n a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein one of the plurality of memory cells is a selected memory cell; each of the memory cells includes:\n spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, \n a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, \n a control gate disposed over and insulated from the floating gate, \n a select gate disposed over and insulated from a second portion of the channel region adjacent the drain region, and \n an erase gate disposed over and insulated from the source region; \n each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells; each of the rows of memory cells includes a select gate line that electrically connects together all the select gates for the row of memory cells; and each of the columns of memory cells includes an erase gate line that electrically connects together all the erase gates for the column of memory cells; the method comprising:\n applying a ground voltage to one of the control gate lines that is electrically connected to the control gate of the selected memory cell, and a positive voltage to all the others of the control gate lines; \n applying a ground voltage to all of the source lines; \n applying a ground voltage to all of the bit lines; \n applying a ground voltage to all of the select gate lines; and \n applying a positive voltage to one of the erase gate lines that is electrically connected to the erase gate of the selected memory cell, and a ground voltage to all the others of the erase gate lines.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 93.0
- Lexical Diversity: 3.52381
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15374588', '15593231', '14190010', '11593398', '15158460']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8182264344163459
- 35 USC 102 Novelty (BERT): 0.5665330269965857
- Combined Prediction Score: 0.7930570936743699
- Mean Citation Score: 386.168134
- Max Citation Score: 483.21915
- Similarity Product: 472.5994679720162

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test