PATENT CLAIM ANALYSIS

Application Number: 15920251
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["375", "355000"]

Abstract:
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

Claim (Index 18):
The method of  claim 17 , wherein generating the second phase interpolator control signal during the clock cycle comprises generating the second phase interpolator control signal based upon the next phase interpolator code if no boundary crossing is detected.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 90.0
- Lexical Diversity: 2.35714
- Patent Class: 375.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14989323', '14235242', '14798340', '14409165', '13397303']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5211433557002421
- 35 USC 102 Novelty (BERT): 0.4923254765850938
- Combined Prediction Score: 0.5182615677887272
- Mean Citation Score: 229.511208
- Max Citation Score: 248.10484
- Similarity Product: 198.3423370872545

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test