PATENT CLAIM ANALYSIS

Application Number: 16027263
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-02
Patent Classification: ["710", "316000"]

Abstract:
A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.

Claim (Index 3):
The reconfigurable pin-to-pin interface of  claim 2 , wherein when the reconfigurable pin-to-pin interface is configured to support a first lane combination in which one lane is used as one clock lane and a single remaining lane is used as one data lane, the reconfiguration circuit is arranged to redirect a received signal of a lane circuit associated with said one lane of the first lane combination to a lane circuit associated with said single remaining lane of the first lane combination for acting as a clock input; when the reconfigurable pin-to-pin interface is configured to support a second lane combination in which one lane is used as one clock lane and remaining lanes are used as a plurality of data lanes, the reconfiguration circuit is arranged to redirect a received signal of a lane circuit associated with said one lane of the second lane combination to lane circuits associated with said remaining lanes of the second lane combination for acting as clock inputs; and the first lane circuit and the second lane circuit are comprised in the lane circuit associated with said one lane of the first lane combination and the lane circuit associated with said single remaining lane of the first lane combination, and are also comprised in the lane circuit associated with said one lane of the second lane combination and the lane circuits associated with said remaining lanes of the second lane combination.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 95.0
- Lexical Diversity: 3.58537
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15262280', '14491884', '14250119', '14939692', '14462327']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6957663486794137
- 35 USC 102 Novelty (BERT): 0.4785962468831999
- Combined Prediction Score: 0.6740493384997923
- Mean Citation Score: 173.56991999999997
- Max Citation Score: 181.8552
- Similarity Product: 134.82337028446196

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test