PATENT CLAIM ANALYSIS

Application Number: 16165549
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "156000"]

Abstract:
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

Claim (Index 18):
The method of  claim 16 , wherein positively boosting the voltage comprises positively boosting the voltage on the at least one bitline in response to a pre-discharge enable signal indicating the read operation.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 97.0
- Lexical Diversity: 1.77778
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15645355', '14862712', '14862555', '14862483', '14862636']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8901607639772765
- 35 USC 102 Novelty (BERT): 0.6501759571165382
- Combined Prediction Score: 0.8661622832912026
- Mean Citation Score: 669.7922259999998
- Max Citation Score: 725.4755
- Similarity Product: 587.5270524559916

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test