PATENT CLAIM ANALYSIS

Application Number: 16023584
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["365", "200000"]

Abstract:
A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Claim (Index 14):
The semiconductor memory device of  claim 13 , wherein each of the plurality of bank arrays further comprises:\n a plurality of block control circuits disposed in the plurality of conjunction regions; and a plurality of local sense amplifier circuits disposed in the plurality of bit-line sense amplifier regions, wherein each of the plurality of block control circuits is configured to perform a column repair by selectively activating a local sense amplifier circuit in a corresponding sub-array block, in response to a selection signal and an enable signal of the repair control signals.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12320892', '14030066', '13008431', '10657790', '12320891']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8307845776820311
- 35 USC 102 Novelty (BERT): 0.5024489926758784
- Combined Prediction Score: 0.7979510191814158
- Mean Citation Score: 271.242584
- Max Citation Score: 280.63547
- Similarity Product: 198.08629703706563

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test