PATENT CLAIM ANALYSIS

Application Number: 16139512
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-05
Patent Classification: ["257", "040000"]

Abstract:
A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower groove. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper groove extends from the lower groove. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower groove and the upper groove. A light emitting element is disposed on the organic layer.

Claim (Index 14):
A method for manufacturing a display panel, comprising:\n forming, on a base layer comprising a first area and a second area extending from the first area, at least one inorganic layer overlapping the first area and the second area along a direction orthogonal to an upper surface of the base layer; forming a silicon semiconductor pattern on the at least one inorganic layer to overlap the first area along the direction orthogonal to the upper surface of the base layer; forming a first control electrode on a first insulation layer to overlap the silicon semiconductor pattern along the direction orthogonal to the upper surface of the base layer, wherein the first insulation layer overlaps the first area and the second area along the direction orthogonal to the upper surface of the base layer; forming a second control electrode spaced apart from the first control electrode on a second insulation layer overlapping the first area and the second area along the direction orthogonal to the upper surface of the base layer, wherein the second insulation layer substantially covers upper and side surfaces of the first control electrode; forming a third insulation layer overlapping the first area and the second area along the direction orthogonal to the upper surface of the base layer, wherein the third insulation layer substantially covers upper and side surfaces of the second control electrode; performing a first etching partially removing the first, second and third insulation layers to form a first contact hole and a second contact hole exposing a first portion and a second portion of the silicon semiconductor pattern, respectively, and to form a first upper groove exposing the at least one inorganic layer in the second area; forming an oxide semiconductor pattern overlapping the second control electrode on the third insulation layer along the direction orthogonal to the upper surface of the base layer; forming a first input electrode and a first output electrode, which are connected to the silicon semiconductor pattern through the first contact hole and the second contact hole, respectively, on the third insulation layer and forming a second input electrode and a second output electrode, which are connected to the oxide semiconductor pattern, on the third insulation layer; forming a fourth insulation layer on the third insulation layer, wherein the fourth insulation layer overlaps the first area and the second area along the direction orthogonal to the upper surface of the base layer; performing a second etching partially removing the fourth insulation layer to form a third contact hole exposing the first output electrode in the fourth insulation layer, and to form a second upper groove exposing the at least one inorganic layer in the second area; performing a third etching removing a portion of the at least one inorganic layer, which overlaps the second area, to form a lower groove aligned with the first upper groove along the direction orthogonal to the upper surface of the base layer in the at least one inorganic layer; forming an organic layer disposed on the fourth insulation layer within the first area and disposed in the first upper groove, the second upper groove, and the lower groove within the second area; performing a fourth etching partially removing the organic layer to form a fourth contact hole connected to the third contact hole in the organic layer; and forming a light emitting element electrically connected to the first output electrode on the organic layer.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 97.0
- Lexical Diversity: 2.90566
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['16133404', '15657369', '14506061', '15662105', '15654485']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9248246342041496
- 35 USC 102 Novelty (BERT): 0.5128470034852959
- Combined Prediction Score: 0.8836268711322643
- Mean Citation Score: 283.001324
- Max Citation Score: 323.7502
- Similarity Product: 287.5892521834612

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test