PATENT CLAIM ANALYSIS

Application Number: 15895882
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-06
Patent Classification: ["257", "368000"]

Abstract:
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Claim (Index 64):
The memory array of  claim 60  wherein an entirety of the liner comprises a single layer of material, and wherein the liner comprises an upper section over a lower section, the upper section of the liner comprises a lateral width dimension that is less than a lateral width dimension of the lower section of the liner.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 88.0
- Lexical Diversity: 1.81818
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15385783', '14480454', '12835042', '11218231', '12886459']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9372237429765358
- 35 USC 102 Novelty (BERT): 0.5642999045789717
- Combined Prediction Score: 0.8999313591367795
- Mean Citation Score: 406.617848
- Max Citation Score: 454.28552
- Similarity Product: 334.66491214776994

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test