PATENT CLAIM ANALYSIS

Application Number: 15874175
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["710", "110000"]

Abstract:
Upon receiving a request ( 203 ) in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device ( 200 ) allocates, to the ordered request, entries in a first ordered queue (e.g.,  211 ) and a first static queue (e.g.,  213 ) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g.,  217 ) and a second static queue (e.g.,  218 ) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue ( 211 ) for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.

Claim (Index 9):
A device comprising:\n a logical transaction request queue comprising: a first static hardware queue comprising a first plurality of unshifting entries, where each unshifting entry stores major data associated with a corresponding transaction request, and a first ordered hardware queue comprising a second plurality of shifting entries for storing a plurality of ordered initiator transaction requests in order of receipt, where each shifting entry in the first ordered hardware queue comprises a first pointer which points to a corresponding shifting entry in the first static hardware queue; and an allocation module to allocate entries in the first static hardware queue and first ordered hardware queue for processing an ordered initiator transaction request received at an initiator protocol interface circuit that identifies first information to be returned in-order to a requesting device and that is split into multiple target transaction requests that are processed out-of-order over a target protocol interface circuit as a plurality of target responses, where the allocation module shifts an entry for the ordered initiator transaction request in the first ordered hardware queue only after the plurality of target responses associated with the ordered initiator transaction request are received over the target protocol interface circuit.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 86.0
- Lexical Diversity: 2.70769
- Patent Class: 710.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['11757248', '12483556', '11769747', '13626758', '11769737']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6745931201766506
- 35 USC 102 Novelty (BERT): 0.4700787819611826
- Combined Prediction Score: 0.6541416863551038
- Mean Citation Score: 198.220322
- Max Citation Score: 203.58261
- Similarity Product: 163.80135463674543

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test