PATENT CLAIM ANALYSIS

Application Number: 16113773
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2019-01
Patent Classification: ["326", "016000"]

Abstract:
Aggressive technology scaling impacts parametric yield, life span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10nm domain. To mitigate them various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks; large area, power, or performance penalty; false positives; false negatives; and in sufficient coverage of the failures encountered in the deep nanometric domain. The invention presents a highly efficient double-sampling architecture, which allow mitigating all these failures at low area and performance penalties, and also enable significant power reduction.

Claim (Index 3):
A circuit protected against timing errors and parasitic disturbances, the circuit comprising:\n a combinatory logic circuit having at least one input and one output; at least a first sampling element having its output connected to said at least one input and activated by the rising edge of a clock signal; at least a second sampling element having its input connected to said at least one output and activated by the rising edge of said clock signal; at least a third sampling element having its input connected to the input of said at least first sampling element and activated by the falling edge of said clock signal; at least a fourth sampling element having its input connected to the input of said at least second sampling element and activated by the falling edge of said clock signal; a comparator circuit for comparing the outputs of each pair of said first and said second sampling elements and the outputs of each pair of said second and said fourth sampling elements and providing on its output an error detection signal, the comparator circuit setting said error detection signal at predetermined value if the outputs of any pair of said first and said second sampling elements or the outputs of any pair of said second and said fourth sampling elements are different; and at least a fifth sampling element having its input connected to the output of said comparator and activated by said clock signal delayed by a predetermined delay, say predetermined delay is shorter than: the duration of the high level of said clock signal, plus the minimum delay of said comparator for the transitions from the non error to the error state, plus the minimum delay of said third and said fourth sampling elements, minus the hold time of the fifth sampling Whereby: the duration of the low level period of said clock signal is selected to be larger than a selected duration of detectable faults; the duration of the high level of said clock signal is larger than the largest delay of said combinatory logic circuit plus the propagation delay of a said first sampling element plus the setup time of a said fourth sampling element; and the minimum propagation delay of said combinatory logic circuit plus the minimum propagation delay of a said first sampling element is larger than the duration of the high level of said clock signal minus the said predetermined delay plus the hold time of the fourth sampling element plus the maximum delay of the comparator for the transitions from the non error to the error state

Metadata:
- Claim Count in Document: 11.0
- Percentile: 96.0
- Lexical Diversity: 1.43529
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12932201', '12456477', '12101716', '12379019', '11206142']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6680756655273735
- 35 USC 102 Novelty (BERT): 0.4766289165456492
- Combined Prediction Score: 0.6489309906292011
- Mean Citation Score: 212.43157
- Max Citation Score: 238.28308
- Similarity Product: 201.15075399559737

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test