PATENT CLAIM ANALYSIS

Application Number: 16109045
Application Type: Utility
Filing Date: 2018-08
Publication Date: 2018-12
Patent Classification: ["257", "622000"]

Abstract:
A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S 11 , providing a MEMS sealing cap silicon substrate ( 100 ); step S 12 , forming n stacked mask layers ( 101, 102, 103 ) on the MEMS sealing cap silicon substrate ( 100 ), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D 1 , D 2 , D 3 ); step S 13 , etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S 14 , removing the current uppermost mask layer; step S 15 , repeating the step S 13  and the step S 14  until all the n mask layers are removed. The present invention can form a plurality of deep trenches with high aspect ratio on the MEMS sealing cap silicon substrate using conventional semiconductor processes, avoiding the problem that the conventional spin coating cannot be conducted on a sealing cap wafer with deep trenches using photoresist.

Claim (Index 15):
A multiple silicon trenches forming method for MEMS sealing cap wafer, characterized in comprising:\n providing a MEMS sealing cap silicon substrate; forming a silicon oxide layer on the MEMS sealing cap silicon substrate as a first mask layer; photolithographing and etching the first mask layer to form a first etching window in the first mask layer; forming an aluminum layer or a silicon nitride layer on the first mask layer as a second mask layer; photolithographing and etching the second mask layer and the first mask layer to form a second etching window in the second mask layer and the first mask layer; forming a photoresist layer on the second mask layer as a third mask layer; photolithographing and etching the third mask layer, the second mask layer and the first mask layer to form a third etching window in the third mask layer, the second mask layer and the first mask layer; etching the MEMS sealing cap silicon substrate by using the third mask layer, the second mask layer and the first mask layer as a mask to form a first silicon trench with a depth of d 3  in the MEMS sealing cap silicon substrate; removing the third mask layer; etching the MEMS sealing cap silicon substrate by using the second mask layer and the first mask layer as a mask to form a second silicon trench with a depth of d 2  in the MEMS sealing cap silicon substrate, while the depth of the first silicon trench being deepened to d 3 +d 2 ; removing the second mask layer; etching the MEMS sealing cap silicon substrate by using the first mask layer as a mask to form a third silicon trench with a depth of d 1  in the MEMS sealing cap silicon substrate, while the depth of the first silicon trench being deepened to d 3 +d 2 +d 1  and the depth of the second silicon trench being deepened to d 2 +d 1 ; removing the first mask layer.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 96.0
- Lexical Diversity: 2.33333
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14389565', '14712987', '14706095', '13904194', '11808876']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9184911375637832
- 35 USC 102 Novelty (BERT): 0.5476303673523686
- Combined Prediction Score: 0.8814050605426418
- Mean Citation Score: 270.646716
- Max Citation Score: 403.29025
- Similarity Product: 355.2217816240638

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test