PATENT CLAIM ANALYSIS

Application Number: 16232893
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "150000"]

Abstract:
A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Claim (Index 1):
A circuit, comprising:\n a selection circuit coupled to receive a plurality of reference clocks, the selection circuit controlled by a control signal to output one of the plurality of reference clocks; a phase-locked loop coupled to an output of the selection circuit and to use the output reference clock from the selection circuit for phase locking an output clock from the phase-locked loop; and a plurality of reference clock window detector circuits, each reference clock window detector circuit coupled to receive a separate one of the plurality of reference clocks, and wherein each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window; wherein each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 98.0
- Lexical Diversity: 2.9434
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16226938', '15904124', '15675160', '09466665', '13397551']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7672300605327597
- 35 USC 102 Novelty (BERT): 0.4825123902968617
- Combined Prediction Score: 0.7387582935091699
- Mean Citation Score: 221.737844
- Max Citation Score: 238.6097
- Similarity Product: 193.0650749916136

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test