PATENT CLAIM ANALYSIS

Application Number: 16208940
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2020-01
Patent Classification: ["257", "499000"]

Abstract:
A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Claim (Index 24):
The multi-cell transistor of  claim 16 , wherein each unit cell transistor comprises a drain finger that extends in the first direction on the top surface of the semiconductor structure, and\n wherein the multi-cell transistor further comprises:\n an input bond wire electrically connected to at least one of the gate fingers; \n an output bond wire electrically connected to at least one of the drain fingers; and \n a secondary isolation material extending in the second direction between the input bond wire and the output bond wire.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 98.0
- Lexical Diversity: 2.04878
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16039703', '16032571', '15628932', '15723286', '14568507']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9264470066438872
- 35 USC 102 Novelty (BERT): 0.5240642786333085
- Combined Prediction Score: 0.8862087338428294
- Mean Citation Score: 236.32080800000003
- Max Citation Score: 340.48636
- Similarity Product: 283.4668214120388

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test