PATENT CLAIM ANALYSIS

Application Number: 15960096
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["438", "587000"]

Abstract:
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.

Claim (Index 19):
A semiconductor device, comprising:\n a first gate structure disposed over one or more fin structures, the first gate structure including a first gate dielectric layer and a first gate electrode layer formed over the first gate dielectric layer and extending in a first direction; a second gate structure disposed over one or more fin structures, the second gate structure including a second gate dielectric layer and a second gate electrode layer formed over the second gate dielectric layer and extending in the first direction; a third gate structure disposed over one or more fin structures, the third gate structure including a third gate dielectric layer and a third gate electrode layer formed over the third gate dielectric layer, extending in the first direction and arranged in parallel with the first gate structure; a fourth gate structure disposed over one or more fin structures, the fourth gate structure including a fourth gate dielectric layer and a fourth gate electrode layer formed over the fourth gate dielectric layer, extending in the first direction and arranged in parallel with the second gate structure; first sidewall spacers, between which the first and second gate structures are disposed; and second sidewall spacers, between which the third and fourth gate structures are disposed, wherein: the first gate structure and the second gate structure are separated by a first separation plug made of an insulating material, the third gate structure and the fourth gate structure are separated by a second separation plug made of the insulating material, the first and second gate structures are in direct contact with the first separation plug, and the third and fourth gate structures are in direct contact with the second separation plug, a first additional insulating layer is disposed between the first separation plug and the first sidewall spacers, and a second additional insulating layer is disposed between the second separation plug and the second sidewall spacers.

Metadata:
- Claim Count in Document: 48.0
- Percentile: 91.0
- Lexical Diversity: 2.78
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14932383', '15481672', '15486549', '15392693', '15086433']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8580519948278061
- 35 USC 102 Novelty (BERT): 0.4757298726266661
- Combined Prediction Score: 0.8198197826076921
- Mean Citation Score: 215.637522
- Max Citation Score: 222.4193
- Similarity Product: 190.5126500037134

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test