PATENT CLAIM ANALYSIS

Application Number: 15744163
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "324000"]

Abstract:
A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

Claim (Index 20):
A method for manufacturing a semiconductor integrated circuit device including:\n a memory circuit region in which a memory cell including a memory gate structure between a first select gate structure and a second select gate structure is disposed; and a peripheral circuit region in which a peripheral circuit including a logic gate structure is disposed, the method comprising: a first dummy electrode layer forming process of forming a layered lower memory gate insulating film and a layered charge storage layer in this order on a semiconductor substrate in the memory circuit region, and then stacking a layered first insulating film and a layered logic dummy electrode layer in this order on the charge storage layer in the memory circuit region and the semiconductor substrate in the peripheral circuit region; a dummy memory gate structure forming process of patterning the logic dummy electrode layer, the first insulating film, the charge storage layer, and the lower memory gate insulating film in the memory circuit region by using a patterned resist so that a dummy memory gate structure in which the lower memory gate insulating film, the charge storage layer, an upper memory gate insulating film, and a dummy memory gate electrode provided by patterning are stacked in this order is formed in the memory circuit region and the first insulating film and the logic dummy electrode layer remain intact in the peripheral circuit region using the resist; a sidewall insulating film forming process of forming sidewall insulating films along facing sidewalls of the dummy memory gate structure in the memory circuit region; a second dummy electrode layer forming process of forming a layered second insulating film across the memory circuit region and the peripheral circuit region to form sidewall spacers composed of the sidewall insulating films and the second insulating film on the respective facing sidewalls of the dummy memory gate structure, stacking a layered memory dummy electrode layer on the second insulating film, and removing the memory dummy electrode layer and the second insulating film in this order in the peripheral circuit region by using a patterned resist so that the second insulating film and the memory dummy electrode layer remain in the memory circuit region; a dummy gate electrode forming process of patterning the logic dummy electrode layer and the first insulating film in the peripheral circuit region by using another patterned resist to form a dummy logic gate structure in which a dummy logic gate electrode is stacked on the semiconductor substrate through a logic gate insulating film, and etching back the memory dummy electrode layer and the second insulating film in the memory circuit region so that a sidewall-shaped dummy first select gate electrode is formed along one of the sidewall spacers of the dummy memory gate structure whereas the second insulating film remains below the dummy first select gate electrode to form a first select gate insulating film, and a sidewall-shaped dummy second select gate electrode is formed along the other sidewall spacer of the dummy memory gate structure whereas the second insulating film remains below the dummy second select gate electrode to form a second select gate insulating film; an electrode exposing process of forming an interlayer insulating layer in the memory circuit region and the peripheral circuit region, and then processing the interlayer insulating layer to expose, on the interlayer insulating layer, top surfaces of the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode; and a metal gate electrode forming process of removing the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode, and then forming, in electrode formation spaces in which the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode have been formed, a metal memory gate electrode, a metal first select gate electrode, a metal second select gate electrode, and a metal logic gate electrode each containing a metallic material.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 3.23529
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15570981', '11553251', '12913759', '15515199', '15602448']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9190648324492132
- 35 USC 102 Novelty (BERT): 0.5099088134273
- Combined Prediction Score: 0.878149230547022
- Mean Citation Score: 253.618924
- Max Citation Score: 310.42038
- Similarity Product: 262.3119833924139

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test