PATENT CLAIM ANALYSIS

Application Number: 15977543
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["365", "185170"]

Abstract:
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Claim (Index 1):
A semiconductor memory device, comprising:\n a memory cell array having a plurality of memory strings disposed in columns, each memory string having a first selection transistor, a second selection transistor, and a memory cell connected between the first selection transistor and second selection transistor, the memory cell being capable of holding data; a word line connected to a gate of each memory cell of the memory cell array; a plurality of bit lines, each connected to first selection transistors included in a corresponding column of memory string; a plurality of first selection gate lines, each connected to a gate of first selection transistors included in a corresponding row of the memory cell strings; and a controller configured to read the data stored in the memory cells included in a target row of the memory strings by performing a read operation, the read operation including: in a first period, applying a first voltage to the first selection gate lines, in a second period after the first period, applying a second voltage to the first selection gate lines to turn on the first selection transistors, the second voltage being higher than the first voltage, and in a third period after the second period, applying a third voltage to a subset of the first selection gate lines corresponding to a non-target row of the memory strings to turn off the first selection transistors included in the non-target row of the memory strings, while maintaining the second voltage being applied to a different subset of the first selection gate lines corresponding to the target row of the memory strings, the third voltage being higher than the first voltage and lower than the second voltage.

Metadata:
- Claim Count in Document: 14.0
- Percentile: 93.0
- Lexical Diversity: 2.56
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15231715', '15498029', '15174114', '14634702', '15051546']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7754500021526072
- 35 USC 102 Novelty (BERT): 0.4920020848302693
- Combined Prediction Score: 0.7471052104203735
- Mean Citation Score: 250.302798
- Max Citation Score: 285.19125
- Similarity Product: 272.9356295748801

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test