PATENT CLAIM ANALYSIS

Application Number: 15878806
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-02
Patent Classification: ["365", "185130"]

Abstract:
A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Claim (Index 20):
The memory device according to  claim 13 , further comprising:\n a global line controller disposed at one side of the memory cell array in the second direction that is parallel to the top surface of the substrate; and a pass transistor disposed at the other side of the memory cell array in the second direction, coupled to one of the gate lines and electrically coupled to the global line controller through one of the wiring lines, and transferring an operation voltage provided from the global line controller, to the gate line.

Metadata:
- Claim Count in Document: 40.0
- Percentile: 86.0
- Lexical Diversity: 1.75676
- Patent Class: 365.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15792983', '15856933', '10944910', '15586307', '15792965']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7895190872943854
- 35 USC 102 Novelty (BERT): 0.4691684066417931
- Combined Prediction Score: 0.7574840192291262
- Mean Citation Score: 191.060012
- Max Citation Score: 205.12762
- Similarity Product: 162.96931998758794

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test