PATENT CLAIM ANALYSIS

Application Number: 15861127
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2019-07
Patent Classification: ["257", "288000"]

Abstract:
Embodiments of the invention are directed to a semiconductor device that includes a substrate formed from a first type of semiconductor material, along with a fin formed on the substrate. The fin includes a fin channel region configured to include a bottom region, a central region, and a top active region. The central region includes a dielectric material and couples the bottom region to the top active region. The top active region includes a second type of semiconductor material, and the bottom region includes a third type of semiconductor material.

Claim (Index 9):
A method of forming a semiconductor device, the method comprising:\n forming a substrate comprising a first type of semiconductor material; and forming a fin formed on the substrate; wherein:\n the fin comprises a fin channel region configured to include an inactive bottom region configured to not conduct current through the semiconductor device, an inactive central region configured to not conduct current through the semiconductor device, and a top active region configured to conduct current through the semiconductor device; \n the central region comprises a dielectric material and couples the bottom region to the top active region; \n the top active region comprises a second type of semiconductor material; and \n the bottom region comprises a third type of semiconductor material; \n wherein forming the fin comprises:\n forming the bottom region; \n forming the top region over the bottom region; and \n converting a top portion of the bottom region to the central region by depositing a layer of a fourth type of semiconductor material on sidewalls of the top portion of the central region, applying an anneal, without an oxygen ambient, to the layer and the top portion of the bottom region such that the anneal causes a first portion of the fourth type of semiconductor material in the layer to enter the top portion of the bottom region and react with a first portion of the third type of semiconductor material in the top portion of the bottom region, wherein the anneal further causes a second portion of the third type of semiconductor material in the top portion of the bottom region to enter the layer and react with a second portion of the fourth type of material in the layer.

Metadata:
- Claim Count in Document: 36.0
- Percentile: 86.0
- Lexical Diversity: 2.57895
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14703953', '14809089', '15183390', '14165930', '15861167']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9190463031207602
- 35 USC 102 Novelty (BERT): 0.4998561043427963
- Combined Prediction Score: 0.8771272832429639
- Mean Citation Score: 235.676606
- Max Citation Score: 259.5684
- Similarity Product: 191.02809353613853

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test