PATENT CLAIM ANALYSIS

Application Number: 15979983
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-09
Patent Classification: ["345", "633000"]

Abstract:
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.

Claim (Index 15):
The HMD device of  claim 12 , wherein, in the act for retrieving one or more rows of decompressed GPU image data and writing the one or more rows of decompressed GPU image data into the third cache, the first row needed to construct the output image being placed at or near the middle of the third cache and each of the other rows of the one or more rows being placed in the third cache above or below the first row based on their relative positions in the GPU image.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 93.0
- Lexical Diversity: 1.41509
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15415542', '15415569', '15485899', '15470790', '15403649']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6509038450896956
- 35 USC 102 Novelty (BERT): 0.5589980085675891
- Combined Prediction Score: 0.641713261437485
- Mean Citation Score: 295.7729720000001
- Max Citation Score: 421.43912
- Similarity Product: 342.0071707253361

Labels:
- Claim Label 101: 0
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test