PATENT CLAIM ANALYSIS

Application Number: 16049257
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-12
Patent Classification: ["257", "534000"]

Abstract:
A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer formed on a base structure that has one or more recesses each comprising contours formed at two or more planar levels. The first dielectric layer is formed along the contours of the one or more recesses. A first electrode is formed on the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the first electrode. A second electrode is formed over the second dielectric layer. The first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.

Claim (Index 9):
The semiconductor structure of  claim 6 , further comprising a first metal, a second metal and a third metal deposited on each of the fourth via, the fifth via and the sixth via, respectively.

Metadata:
- Claim Count in Document: 12.0
- Percentile: 95.0
- Lexical Diversity: 2.74359
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15473782', '15218445', '15951208', '15137362', '15229209']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9010831105256676
- 35 USC 102 Novelty (BERT): 0.5322757811773056
- Combined Prediction Score: 0.8642023775908315
- Mean Citation Score: 246.538152
- Max Citation Score: 342.68213
- Similarity Product: 248.21848357688305

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test