PATENT CLAIM ANALYSIS

Application Number: 16196366
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-04
Patent Classification: ["257", "774000"]

Abstract:
A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Claim (Index 20):
A method for manufacturing a semiconductor device comprising:\n forming a plurality of lower conductive lines extending in a first direction over a semiconductor substrate, the plurality of lower conductive lines being embedded in a first dielectric layer; forming a second dielectric layer over the plurality of lower conductive lines and the first dielectric layer; forming a third dielectric layer over the second dielectric layer; forming a first opening in the third dielectric layer by etching the third dielectric layer; etching the second dielectric layer and a part of the first dielectric layer in the first opening; after the second dielectric layer and the part of the first dielectric layer are etched, filling the first opening with a first conductive material, thereby forming a first via; forming a second opening in the third dielectric layer by etching the third dielectric layer; etching the second dielectric layer and a part of the first dielectric layer in the second opening; after the second dielectric layer and the part of the first dielectric layer are etched, filling the second opening with a second conductive material, thereby forming a second via, wherein: an average width in the first direction of the first via measured at a center of the first via is different from an average width in the first direction of the second via measured at a center of the second via.

Metadata:
- Claim Count in Document: 13.0
- Percentile: 98.0
- Lexical Diversity: 3.22449
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15061627', '16116412', '15812119', '16015714', '16116421']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9070477517714424
- 35 USC 102 Novelty (BERT): 0.4755838914777995
- Combined Prediction Score: 0.8639013657420782
- Mean Citation Score: 147.224448
- Max Citation Score: 184.24911
- Similarity Product: 139.41415935722532

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test