PATENT CLAIM ANALYSIS

Application Number: 15973539
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-09
Patent Classification: ["710", "104000"]

Abstract:
A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit.

Claim (Index 2):
The phase-locked loop circuit calibration method as claimed in  claim 1 , wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 93.0
- Lexical Diversity: 1.96078
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14659233', '15718715', '15224199', '15224280', '15224258']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6889544359656978
- 35 USC 102 Novelty (BERT): 0.4842170360702719
- Combined Prediction Score: 0.6684806959761553
- Mean Citation Score: 177.53841000000003
- Max Citation Score: 185.06093
- Similarity Product: 125.89987326494754

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test