PATENT CLAIM ANALYSIS

Application Number: 16181813
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["710", "104000"]

Abstract:
A storage device includes a controller and a nonvolatile memory device. The controller includes a field programmable gate array (FPGA) and receives an FPGA image for updating the FPGA from an outside in response to a first command received from the outside. The nonvolatile memory device stores the FPGA image. The controller receives the FPGA image through a main interface or a sideband interface, and executes the FPGA image in response to a second command received from the outside.

Claim (Index 10):
The storage device of  claim 1 , wherein the nonvolatile memory device includes:\n a memory cell array including a plurality of memory cells formed perpendicular to a substrate, the plurality of memory cells being connected to a plurality of word lines and a plurality of bit lines; the plurality of memory cells arranged in a plurality of cell strings that each include ones of the plurality of memory cells that are serially connected together and are associated with a same one of the plurality of bit lines; and a page buffer configured to store data read from the memory cell array.

Metadata:
- Claim Count in Document: 43.0
- Percentile: 98.0
- Lexical Diversity: 2.09756
- Patent Class: 710.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15052175', '15093769', '15059094', '15984445', '15438644']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7133350952585211
- 35 USC 102 Novelty (BERT): 0.4649287238517491
- Combined Prediction Score: 0.688494458117844
- Mean Citation Score: 214.742278
- Max Citation Score: 233.15749
- Similarity Product: 225.7632393736237

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test