PATENT CLAIM ANALYSIS

Application Number: 15961080
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-02
Patent Classification: ["365", "185220"]

Abstract:
There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.

Claim (Index 18):
The method of  claim 17 , wherein, when the erase pulse is applied to the well, bit lines or source line plural times, the erase pulse is consecutively applied to the well, bit lines or source line.

Metadata:
- Claim Count in Document: 27.0
- Percentile: 91.0
- Lexical Diversity: 1.80645
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15628808', '13325787', '15466070', '15651477', '13455016']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8251536724681898
- 35 USC 102 Novelty (BERT): 0.4916239884742163
- Combined Prediction Score: 0.7918007040687924
- Mean Citation Score: 252.749738
- Max Citation Score: 260.07977
- Similarity Product: 200.14174279038428

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test