PATENT CLAIM ANALYSIS

Application Number: 15924112
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-08
Patent Classification: ["345", "426000"]

Abstract:
Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

Claim (Index 12):
The system on a chip integrated circuit as in  claim 11 , wherein the bounding logic is additionally configured to encode the reference bounding volume and child bounding volumes using lower and upper bounds in multiple directions.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.47059
- Patent Class: 345.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14975294', '15182694', '15477035', '15482701', '13848011']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6425015811072368
- 35 USC 102 Novelty (BERT): 0.5657390566057737
- Combined Prediction Score: 0.6348253286570905
- Mean Citation Score: 284.57845800000007
- Max Citation Score: 425.45078
- Similarity Product: 397.5114976410878

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test