PATENT CLAIM ANALYSIS

Application Number: 16013450
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["327", "333000"]

Abstract:
A low voltage level shifter that is suitable for use with subthreshold logic. In one embodiment, the low voltage level shifter includes first and second input transistors coupled to first and second input nodes, respectively, that receive complementary low voltage input signals. A circuit is coupled to the first and second input transistors and to first and second output nodes that generate complementary high voltage output signals. The circuit is configured to transmit a first current to the second output node when the first input transistor is activated, wherein the first current is substantially equal to current drawn by the first input transistor when it is activated. The circuit is also configured to transmit a second current to the first output node when the second input transistor is activated, wherein the second current is substantially equal to current drawn by the second input transistor when it is activated.

Claim (Index 8):
An apparatus comprising:\n first and second input nodes; first and second output nodes; a first supply voltage node; first and second input transistors coupled to the first and second input nodes, respectively; third and fourth transistors; first and second intermediate nodes; a circuit coupled to the first and second input transistors and to the first and second output nodes; wherein the circuit is configured to transmit a first current to the second output node when the first input transistor is activated, wherein the first current is substantially equal to current drawn by the first input transistor when it is activated; wherein the circuit is configured to transmit a second current to the first output node when the second input transistor is activated, wherein the second current is substantially equal to current drawn by the second input transistor when it is activated; wherein the circuit includes:\n first and second transistors coupled to the first supply node; and \n first and second diode connected transistors coupled to the first and second transistors, respectively; \n wherein the first output node is connected between the first transistor and the first diode connected transistor; wherein the second output node is connected between the second transistor and the second diode connected transistor; wherein current in the second transistor is substantially equal to current in the first diode connected transistor when the first input transistor is activated; wherein current in the first transistor is substantially equal to current in the second diode connected transistor when the second input transistor is activated; wherein the first intermediate node is connected between the first diode connected transistor and the first input transistor, and wherein the second intermediate node is connected between the second diode connected transistor and the second input transistor; wherein the third transistor is connected between the first output node and first intermediate node; wherein the fourth transistor is connected between the second output node and the second intermediate node; wherein gates of the third and fourth transistors are connected to the second and first output nodes, respectively.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 3.03846
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['13137057', '12070841', '15227979', '10947257', '15185781']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7588116469887725
- 35 USC 102 Novelty (BERT): 0.4679924048422033
- Combined Prediction Score: 0.7297297227741156
- Mean Citation Score: 175.83316200000004
- Max Citation Score: 181.39764
- Similarity Product: 139.59387731600762

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test