PATENT CLAIM ANALYSIS

Application Number: 15744163
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["257", "324000"]

Abstract:
A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

Claim (Index 19):
A method for manufacturing a semiconductor integrated circuit device including:\n a memory circuit region in which a memory cell including a memory gate structure between a first select gate structure and a second select gate structure is disposed; and a peripheral circuit region in which a peripheral circuit including a logic gate structure is disposed, the method comprising: a sidewall insulating film forming process of providing, in the memory circuit region, a dummy memory gate structure in which a lower memory gate insulating film, a charge storage layer, and a dummy memory gate electrode provided by patterning are stacked in this order on a semiconductor substrate, and then forming sidewall insulating films along facing sidewalls of the dummy memory gate structure; a dummy electrode layer forming process of forming a layered logic dummy electrode layer in the memory circuit region and the peripheral circuit region; a dummy gate electrode forming process of patterning the logic dummy electrode layer in the peripheral circuit region by using a patterned resist to form a dummy logic gate electrode on the semiconductor substrate, and etching back the logic dummy electrode layer in the memory circuit region so that a sidewall-shaped dummy first select gate electrode is formed along one of the sidewall insulating films of the dummy memory gate structure and a sidewall-shaped dummy second select gate electrode is formed along the other sidewall insulating film of the dummy memory gate structure; an electrode exposing process of forming an interlayer insulating layer in the memory circuit region and the peripheral circuit region, and then processing the interlayer insulating layer to expose, on the interlayer insulating layer, top surfaces of the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode; and a metal gate electrode forming process of removing the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode, forming a layered insulating film in spaces in which the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode have been formed, and then forming a metal memory gate electrode, a metal first select gate electrode, a metal second select gate electrode, and a metal logic gate electrode each containing a metallic material, in electrode formation spaces enclosed by the insulating film in the spaces.

Metadata:
- Claim Count in Document: 2.0
- Percentile: 86.0
- Lexical Diversity: 3.23529
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15570981', '11553251', '12913759', '15515199', '15602448']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9190618126773002
- 35 USC 102 Novelty (BERT): 0.5099937991513369
- Combined Prediction Score: 0.878155011324704
- Mean Citation Score: 253.618924
- Max Citation Score: 310.42038
- Similarity Product: 261.75966536996134

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test