PATENT CLAIM ANALYSIS

Application Number: 15863494
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "066000"]

Abstract:
A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.

Claim (Index 10):
The process of  claim 9 , wherein forming the silicon oxide layer comprises treating the amorphous silicon layer with ozone in deionized water.

Metadata:
- Claim Count in Document: 18.0
- Percentile: 86.0
- Lexical Diversity: 1.88
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15288799', '13271446', '14083971', '13673396', '13365228']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.917147701506441
- 35 USC 102 Novelty (BERT): 0.502717640768449
- Combined Prediction Score: 0.8757046954326417
- Mean Citation Score: 183.62834
- Max Citation Score: 266.23438
- Similarity Product: 204.4180982235468

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test