PATENT CLAIM ANALYSIS

Application Number: 16132462
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-01
Patent Classification: ["174", "251000"]

Abstract:
A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

Claim (Index 1):
A method for manufacturing a circuit board, comprising:\n forming a first sacrificial metal layer on a carrier, wherein the first sacrificial metal layer has a plurality of first openings; forming a first etching stop layer on the carrier, wherein the first etching stop layer covers the first sacrificial metal layer; forming a patterned resist on the first etching stop layer, wherein the patterned resist has a plurality of second openings and an intaglioed pattern, the second openings respectively correspond to the first openings to expose a part of the first sacrificial metal layer, and the intaglioed pattern exposes a part of the first etching stop layer; forming a plurality of metal bump in the first openings and the second openings and forming a first circuit layer in the intaglioed pattern; removing the patterned resist; forming a build-up structure on the first etching stop layer, wherein the build-up structure includes a dielectric layer, a plurality of conductive vias, and at least one second circuit layer, the dielectric layer covers the metal bumps and the first circuit layer, the conductive vias is formed in the dielectric layer, the second circuit layer is formed on the dielectric layer, the conductive vias connects the first circuit layer and the second circuit layer; a second etching stop layer is formed on the dielectric layer, wherein the second etching stop layer covers the second circuit layer; separating the carrier and the first sacrificial metal layer; performing a first etching process to remove the first sacrificial metal layer; and performing a second etching process to remove the first etching stop layer and the second etching stop layer.

Metadata:
- Claim Count in Document: 6.0
- Percentile: 97.0
- Lexical Diversity: 3.06061
- Patent Class: 174.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15813222', '15867199', '11527632', '11808028', '14520117']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8336972936725625
- 35 USC 102 Novelty (BERT): 0.475498206189684
- Combined Prediction Score: 0.7978773849242746
- Mean Citation Score: 195.976212
- Max Citation Score: 198.94604
- Similarity Product: 152.4472559621358

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test