PATENT CLAIM ANALYSIS

Application Number: 15898034
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["365", "193000"]

Abstract:
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Claim (Index 8):
The IC memory controller according to  claim 2 , wherein the strobe signal is associated with a first clock domain, and wherein the mask circuit further comprises:\n latching circuitry to, in response to an edge transition of the strobe signal that indicates the start of a valid region of the strobe signal, latch the masked timing signal into the clock domain of the strobe signal.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 88.0
- Lexical Diversity: 1.93478
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15646024', '15202773', '14821101', '14284312', '11019432']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8587404629882572
- 35 USC 102 Novelty (BERT): 0.5534738604683479
- Combined Prediction Score: 0.8282138027362663
- Mean Citation Score: 402.242912
- Max Citation Score: 437.47128
- Similarity Product: 394.78749312941545

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test