PATENT CLAIM ANALYSIS

Application Number: 15742394
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["341", "120000"]

Abstract:
Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

Claim (Index 32):
The ADC of  claim 31 , further comprising a comparator coupled at the first node and a successive approximation register (SAR) coupled to an output of the comparator, an output of the SAR comprising a digital output of the ADC.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 86.0
- Lexical Diversity: 1.26
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14793118', '15742435', '14487166', '14732676', '13675387']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6104539692238543
- 35 USC 102 Novelty (BERT): 0.5571921498880947
- Combined Prediction Score: 0.6051277872902784
- Mean Citation Score: 306.551896
- Max Citation Score: 433.21707
- Similarity Product: 322.3619751471769

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test