PATENT CLAIM ANALYSIS

Application Number: 16235956
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-05
Patent Classification: ["326", "038000"]

Abstract:
The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.

Claim (Index 12):
The electronic device of  claim 11 , wherein minimizing the timing skew in the clock tree comprises:\n receiving, in a first phase difference detector of the timing strip a reference clock from a first portion of the clock tree disposed in the first programmable logic die; receiving in the first phase difference detector of the timing strip a feedback clock from a second portion of the clock tree disposed in the second programmable logic die; determining a phase difference between the reference clock and the feedback clock; and adjusting a first delay element of the plurality of the timing strip.

Metadata:
- Claim Count in Document: 10.0
- Percentile: 98.0
- Lexical Diversity: 1.37838
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['16236062', '14882065', '16146849', '15392225', '15338074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6745169085436622
- 35 USC 102 Novelty (BERT): 0.4708454145453991
- Combined Prediction Score: 0.6541497591438359
- Mean Citation Score: 165.987802
- Max Citation Score: 189.29652
- Similarity Product: 146.47877839572428

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test