PATENT CLAIM ANALYSIS

Application Number: 15887673
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-08
Patent Classification: ["326", "068000"]

Abstract:
A voltage conversion circuit and method that includes applying a positive bias to a PMOS gate to source voltage and/or a negative bias to an NMOS gate to source voltage. These biases serve to further reduce the leakage current of the unselected device of a driver while in standby mode, as well as convert an input signal at one voltage potential to an output voltage at a different voltage potential.

Claim (Index 3):
The integrated circuit facility of  claim 2  wherein said positive bias is further characterized as a difference between said first supply voltage and said second supply voltage.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 1.52083
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12701583', '11683855', '15687781', '10948524', '11650485']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7004554353938764
- 35 USC 102 Novelty (BERT): 0.4875644620271355
- Combined Prediction Score: 0.6791663380572024
- Mean Citation Score: 221.67038
- Max Citation Score: 228.46815
- Similarity Product: 166.72134546135663

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test