PATENT CLAIM ANALYSIS

Application Number: 15881534
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-07
Patent Classification: ["327", "119000"]

Abstract:
An accumulation-mode MOS varactor is formed with a standard CMOS process and having an anti-symmetric-CV curve. The asymmetric varactor (ASVAR) can efficiently generate even-order harmonics while simultaneously suppressing odd-order harmonics over broad bandwidths. This is achieved without degradation of dynamic cut-off frequency. The improved cut-off frequency of the asymmetric varactor results in efficient even-harmonic generation well into sub-millimeter or terahertz frequencies. This and the inherent adaptive-CV features of the asymmetric varactor result in even-harmonic generation with process variation resilience and can also be utilized for frequency response shaping and for optimizing performance at various driving conditions.

Claim (Index 7):
The frequency multiplier of  claim 1 ,\n wherein the first bias signal is a first bias signal of a second stage, the second bias signal is a second bias signal of the second stage, the input signal is a first stage output signal, the output signal is a second stage output signal, and the frequency multiplier further comprises:\n a first stage; \n the second stage; \n the first stage comprising a symmetric varactor; \n the second stage comprising the asymmetric varactor; \n the symmetric varactor comprising:\n a first varactor of the symmetric varactor, and \n a second varactor of the symmetric varactor; \n \n the first varactor of the symmetric varactor comprising:\n a first layer, and \n a third layer; \n \n the second varactor of the symmetric varactor comprising:\n a first layer, and \n a third layer; \n \n the first layer of the first varactor of the symmetric varactor electrically connected to the first layer of the second varactor of the symmetric varactor and to a first bias signal of the first stage; the third layer of the first varactor of the symmetric varactor connected to a potential; the third layer of the second varactor of the symmetric varactor connected to a second bias signal of the first stage; and, in response to the first bias signal of the first stage, the second bias signal of the first stage, and a first stage input signal, the symmetric varactor generates the first stage output signal comprising a first stage output frequency that is an odd order multiple of a first stage input frequency of the first stage input signal.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 86.0
- Lexical Diversity: 1.41096
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14338598', '13774387', '10897156', '14801919', '11618605']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7601934644259164
- 35 USC 102 Novelty (BERT): 0.4763896566978791
- Combined Prediction Score: 0.7318130836531126
- Mean Citation Score: 195.571618
- Max Citation Score: 215.5224
- Similarity Product: 170.38552253179554

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test