PATENT CLAIM ANALYSIS

Application Number: 15988805
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-05
Patent Classification: ["257", "066000"]

Abstract:
The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.

Claim (Index 7):
An array substrate, comprising the thin film transistor of  claim 1 .

Metadata:
- Claim Count in Document: 3.0
- Percentile: 93.0
- Lexical Diversity: 3.975
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['14764307', '14769577', '14912822', '11316967', '15127262']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9191858780070364
- 35 USC 102 Novelty (BERT): 0.4757932802196367
- Combined Prediction Score: 0.8748466182282966
- Mean Citation Score: 230.082852
- Max Citation Score: 236.87231
- Similarity Product: 213.7434393004787

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test