PATENT CLAIM ANALYSIS

Application Number: 15771752
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-10
Patent Classification: ["257", "029000"]

Abstract:
Techniques are disclosed for co-integrating transition metal dichalcogenide (TMDC)-based p-channel transistor devices and III-N semiconductor-based n-channel transistor devices. In accordance with some embodiments, a p-channel transistor device configured as described herein may include a layer of TMDC material such as, for example, tungsten diselenide, tungsten disulfide, molybdenum diselenide, or molybdenum disulfide, and an n-channel transistor device configured as described herein may include a layer of III-V material such as, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum nitride. Transistor structures provided as described herein may be utilized, for instance, in power delivery applications where III-N semiconductor-based n-channel power transistor devices can benefit from being integrated with low-leakage, high-performance p-channel devices providing logic and control circuitry. In some cases, a TMDC-based transistor provided as described herein may exhibit p-channel mobility in excess of bulk Si and thus may exhibit faster performance than traditional Si-based p-channel transistors.

Claim (Index 21):
An integrated circuit comprising:\n a silicon (Si) substrate; a first transistor device disposed over the Si substrate and comprising:\n a gallium nitride (GaN) layer disposed over the Si substrate; \n at least one of an aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and indium aluminum nitride (InAlN) layer disposed over the GaN layer; \n a transition metal dichalcogenide (TMDC) layer disposed over the at least one of an AlN, AlGaN, and InAlN layer; \n a metal gate disposed over the TMDC layer; and \n p-type source/drain contacts disposed either over or adjacent to the TMDC layer, over the at least one of an AlN, AlGaN, and InAlN layer; \n a second transistor device disposed over the Si substrate and comprising:\n a GaN layer disposed over the Si substrate; \n at least one of an AlN, AlGaN, and InAlN layer disposed over the GaN layer; \n a metal gate disposed over the at least one of an AlN, AlGaN, and InAlN layer; and \n n-type source/drain contacts disposed within the at least one of an AlN, AlGaN, and InAlN layer, over the GaN layer.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 91.0
- Lexical Diversity: 2.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15774446', '13535127', '14169334', '14265214', '14578146']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8938053376094759
- 35 USC 102 Novelty (BERT): 0.4760679927914934
- Combined Prediction Score: 0.8520316031276777
- Mean Citation Score: 175.35176799999996
- Max Citation Score: 181.42827
- Similarity Product: 143.91680086713194

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test