PATENT CLAIM ANALYSIS

Application Number: 15763970
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-09
Patent Classification: ["714", "764000"]

Abstract:
A computer device comprises a first processing device; a plurality of memory circuits, a first one of which comprises one or more other processing devices; a data bus coupling the first processing device to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processing device and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting the first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Claim (Index 16):
A method comprising:\n performing, by a first processing device, a read or write operation of an n-bit data value to or from a first memory circuit of a plurality of memory circuits via a data bus coupling the first processing device to each of the memory circuits, the first memory circuit comprising one or more further processing devices, wherein each of the memory circuits has a data port that is m bits wide and the data bus has a width of n bits, where n is larger than m, the data port of each of the memory circuits being coupled to a corresponding m-bit slice of the data bus, the read or write operation comprising:\n providing, by the first processing device, one or more first addresses for an n-bit data value to be read or written via the data bus; \n converting the first address into a plurality of second addresses corresponding to m-bit memory locations in the first memory circuit, at least two of the plurality of second addresses being contiguous addresses; and \n performing the read or write operation of the n-bit data value to the first memory circuit over a plurality memory access operations.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 90.0
- Lexical Diversity: 2.55932
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['10097499', '15551418', '11394949', '15428719', '14265270']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2938864150376186
- 35 USC 102 Novelty (BERT): 0.470783788774844
- Combined Prediction Score: 0.3115761524113411
- Mean Citation Score: 188.390398
- Max Citation Score: 190.32498
- Similarity Product: 145.35510259049536

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 0

Dataset: test