PATENT CLAIM ANALYSIS

Application Number: 16038503
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["716", "104000"]

Abstract:
A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Claim (Index 6):
The computer-implemented method of  claim 1 , wherein the ranking the plurality of macros is based at least in part on an instruction from a human designer of at least one of the plurality of macros.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.13514
- Patent Class: 716.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15352895', '14861697', '15358615', '15454919', '15392883']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3980286822928958
- 35 USC 102 Novelty (BERT): 0.5935245038293744
- Combined Prediction Score: 0.4175782644465437
- Mean Citation Score: 350.59920800000015
- Max Citation Score: 527.79486
- Similarity Product: 525.408504188633

Labels:
- Claim Label 101: 0
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test