PATENT CLAIM ANALYSIS

Application Number: 16314475
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-10
Patent Classification: ["323", "282000"]

Abstract:
A switching regulator control circuit, having: a slope circuit  3  for generating a slope voltage V SLP  on the basis of a clock signal CLK of a prescribed frequency; an error amplifier  1  for generating an error signal Vc corresponding to the difference between a reference voltage V REF  and a voltage V FB  corresponding to the output voltage of a switching regulator; a comparator  4  for comparing the error signal Vc and the slope voltage V SLP ; and an RS flip-flop  6  set on the basis of the clock signal CLK and reset by a signal outputted by the comparator  4 . The timing at which the RS flip-flop  6  is set is delayed with respect to the timing at which the sloping of the slope voltage V SLP  is started.

Claim (Index 7):
The switching regulator control circuit according to  claim 1 ,\n wherein the latch portion is set at one of a first inversion timing at which the clock signal is inverted from low level to high level and a second inversion timing at which the clock signal is inverted from high level to low level, and the sloping of the slope voltage starts at an other of the first inversion timing and the second inversion timing.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 98.0
- Lexical Diversity: 2.2623
- Patent Class: 323.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13266206', '12554076', '15740729', '12479059', '15387787']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7616232839111904
- 35 USC 102 Novelty (BERT): 0.4775658373211923
- Combined Prediction Score: 0.7332175392521906
- Mean Citation Score: 227.170062
- Max Citation Score: 229.56984
- Similarity Product: 190.3828809355259

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test