PATENT CLAIM ANALYSIS

Application Number: 15996430
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-12
Patent Classification: ["326", "041000"]

Abstract:
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.

Claim (Index 12):
The integrated circuit of  claim 9  wherein:\n wherein each logic tile of the first plurality of logic tiles of the array of logic tiles further generates the tile clock using (i) the second external clock signal received by the first logic tile or (ii) a delayed version of the second external clock signal \n wherein each logic tile of the second plurality of logic tiles of the array of logic tiles further generates the tile clock using (i) the first external clock signal received by the first logic tile or (ii) a delayed version of the first external clock signal.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 94.0
- Lexical Diversity: 3.375
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14712864', '15347045', '14972553', '15975037', '15978235']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7185829449807707
- 35 USC 102 Novelty (BERT): 0.5558831411761754
- Combined Prediction Score: 0.7023129646003112
- Mean Citation Score: 389.332028
- Max Citation Score: 427.03516
- Similarity Product: 364.8274478921413

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test