PATENT CLAIM ANALYSIS

Application Number: 15906889
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-07
Patent Classification: ["257", "143000"]

Abstract:
To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P +  type first collector region and a relatively heavily-doped P ++  type second collector region. The P ++  type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N +  type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N +  type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P ++  type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.

Claim (Index 1):
A method of manufacturing a semiconductor device, comprising the steps of:\n (a) providing a semiconductor substrate of a first conductivity type having a first main surface and a second main surface on the side opposite thereto; (b) forming a first trench and a second trench each having a first depth from the first main surface of the semiconductor substrate while separating the trenches from each other; (c) forming, in the first trench, a first trench gate electrode having a first conductive film via a first gate insulating film having a first insulating film and forming, in the second trench, a second trench gate electrode having the first conductive film via a second gate insulating film having the first insulating film; (d) forming a first semiconductor region of a second conductivity type different from the first conductivity type having, from the first main surface of the semiconductor substrate, a second depth smaller than the first depth; (e) forming, in the first semiconductor region, a second semiconductor region of the first conductivity type having, from the first main surface of the semiconductor substrate, a third depth smaller than the second depth so as to be contiguous to a first side surface of the first trench; (f) forming an interlayer insulating film over the first main surface of the semiconductor substrate and then forming, over the interlayer insulating film, a first electrode to be electrically coupled to the first trench gate electrode and a second electrode to be electrically coupled to the second trench gate electrode, the first semiconductor region, and the second semiconductor region; (g) grinding the semiconductor substrate from the side of the second main surface; (h) forming a third semiconductor region on the side of the second main surface by ion implantation of an impurity of the second conductivity type into the second main surface of the semiconductor substrate; (i) forming a resist film over the second main surface of the semiconductor substrate and then patterning the resist film; (j) form a fourth semiconductor region on the side of the second main surface by ion implantation of an impurity of the second conductivity type into the second main surface of the semiconductor substrate, with the patterned resist film as a mask; and (k) forming a third electrode that electrically couples the third semiconductor region to the fourth semiconductor region over the second main surface of the semiconductor substrate, wherein the fourth semiconductor region is famed in a region including, in plan view, an interface between the first trench and the second semiconductor region.

Metadata:
- Claim Count in Document: 7.0
- Percentile: 88.0
- Lexical Diversity: 2.47761
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15180988', '14715648', '15138687', '15798209', '15390491']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9233137193717018
- 35 USC 102 Novelty (BERT): 0.5741797781440279
- Combined Prediction Score: 0.8884003252489345
- Mean Citation Score: 394.932166
- Max Citation Score: 481.6934
- Similarity Product: 373.4580539616585

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test