PATENT CLAIM ANALYSIS

Application Number: 16194821
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-05
Patent Classification: ["327", "094000"]

Abstract:
A sample hold circuit includes at least one capacitor C S  and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal V GN  of the NMOS transistor is adjusted to a voltage level V REG  lower than a power supply voltage V DD  of a chip on which the CMOS switch is integrated.

Claim (Index 1):
A sample hold circuit, comprising:\n at least one capacitor; and at least one complementary metal-oxide semiconductor (CMOS) switch, wherein each of the at least one CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel, and a high level of a gate signal of the NMOS transistor is adjusted to a voltage level lower than a power supply voltage of a chip on which the CMOS switch is integrated.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 98.0
- Lexical Diversity: 1.66038
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['12630708', '12630662', '10986630', '16019150', '15293675']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7856673456932087
- 35 USC 102 Novelty (BERT): 0.4918556545311633
- Combined Prediction Score: 0.7562861765770043
- Mean Citation Score: 254.650006
- Max Citation Score: 268.15918
- Similarity Product: 216.52159658405543

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test