PATENT CLAIM ANALYSIS

Application Number: 15874783
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-06
Patent Classification: ["257", "676000"]

Abstract:
A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.

Claim (Index 9):
The IC chip of  claim 8 , further comprising a substrate including a plurality of signal pads; and\n wherein the first lead is electrically coupled to one of the signal pads.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 86.0
- Lexical Diversity: 1.94253
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15338162', '12199667', '10987468', '13177734', '11030484']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9197627684921807
- 35 USC 102 Novelty (BERT): 0.5511566847182114
- Combined Prediction Score: 0.8829021601147838
- Mean Citation Score: 256.780678
- Max Citation Score: 414.57584
- Similarity Product: 338.99931862682337

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test