PATENT CLAIM ANALYSIS

Application Number: 15775924
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-11
Patent Classification: ["438", "479000"]

Abstract:
A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Claim (Index 24):
A method of preparing a multilayer structure, the method comprising:\n depositing a layer of polycrystalline silicon carbide on a back surface of a single crystal semiconductor handle wafer, wherein the single crystal semiconductor handle wafer comprises two major, parallel surfaces, one of which is the back surface of the single crystal semiconductor handle wafer and the other of which is a front surface of the single crystal semiconductor handle wafer, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle wafer, a central axis perpendicular to the front surface and the back surface of the single crystal semiconductor handle wafer, and a bulk region between the front and back surfaces of the semiconductor handle wafer; bonding the front surface of the single crystal semiconductor handle wafer to a front surface of a single crystal semiconductor donor wafer to thereby form a bonded structure, wherein the single crystal semiconductor donor wafer comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor donor wafer and the other of which is a back surface of the single crystal semiconductor donor wafer, a circumferential edge joining the front and back surfaces of the single crystal semiconductor donor wafer, and a bulk region between the front and back surfaces of the single crystal semiconductor donor wafer, and further wherein the front surface of the single crystal semiconductor donor wafer comprises a dielectric layer and the bulk region comprises a cleave plane; mechanically cleaving the bonded structure at the cleave plane of the single crystal semiconductor donor wafer to thereby prepare a cleaved structure comprising the layer of polycrystalline silicon carbide or the layer of carbon-doped silicon in contact with the back surface of the single crystal semiconductor handle wafer, the single crystal semiconductor handle wafer, the dielectric layer in contact with the front surface of the single crystal semiconductor handle wafer, and a single crystal semiconductor device layer, wherein the single crystal semiconductor device layer comprises an exposed surface; and smoothing the exposed surface of the single crystal semiconductor device layer to a root mean square surface roughness over a 30 micrometer by 30 micrometer surface region of less than about 2 angstroms to thereby prepare the multilayer structure.

Metadata:
- Claim Count in Document: 112.0
- Percentile: 93.0
- Lexical Diversity: 1.43056
- Patent Class: 438.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15435428', '16072203', '16077142', '16077176', '15554034']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8893206799900242
- 35 USC 102 Novelty (BERT): 0.5127554908690207
- Combined Prediction Score: 0.8516641610779239
- Mean Citation Score: 314.9788240000001
- Max Citation Score: 327.30637
- Similarity Product: 304.7232235551137

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test