PATENT CLAIM ANALYSIS

Application Number: 16174782
Application Type: Utility
Filing Date: 2018-10
Publication Date: 2019-02
Patent Classification: ["365", "189070"]

Abstract:
A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.

Claim (Index 11):
The memory module of  claim 10 , wherein the circuitry configured to compare the first and second reference clock signals includes:\n circuitry configured to count edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.

Metadata:
- Claim Count in Document: 37.0
- Percentile: 97.0
- Lexical Diversity: 2.58333
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15666375', '15977125', '11837631', '11876526', '13291975']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8007572446150288
- 35 USC 102 Novelty (BERT): 0.4593912607525419
- Combined Prediction Score: 0.7666206462287801
- Mean Citation Score: 122.1248848
- Max Citation Score: 182.05746
- Similarity Product: 151.30845181235074

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test