PATENT CLAIM ANALYSIS

Application Number: 16412447
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-09
Patent Classification: ["257", "296000"]

Abstract:
A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.

Claim (Index 5):
The method according to  claim 1 , wherein said forming the sacrificial spacer in the second gate trench comprises:\n depositing a conformal spacer material layer on the semiconductor substrate, and in the first gate trench and the second gate trench; selectively etching the spacer material layer, thereby forming a first spacer in the first gate trench and a second spacer in the second gate trench; forming a planarization layer on the semiconductor substrate, and in the first gate trench and the second gate trench; forming a photoresist pattern on the planarization layer; etching the planarization layer, the first spacer, and the second spacer not covered by the photoresist pattern; and removing remnants of the photoresist pattern and the planarization layer.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 100.0
- Lexical Diversity: 1.61538
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15655909', '15258588', '11772341', '13599844', '15209502']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918845770666748
- 35 USC 102 Novelty (BERT): 0.4893626418816246
- Combined Prediction Score: 0.8758974577882357
- Mean Citation Score: 198.358388
- Max Citation Score: 218.47694
- Similarity Product: 163.1086657321739

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test