PATENT CLAIM ANALYSIS

Application Number: 16020722
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "392000"]

Abstract:
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Claim (Index 7):
The integrated circuit structure of  claim 2 , wherein the uppermost surface of the second bulk material is above an uppermost surface of the second work function layer.

Metadata:
- Claim Count in Document: 21.0
- Percentile: 94.0
- Lexical Diversity: 1.68333
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13606768', '15221515', '14548215', '11391377', '14778063']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9050435567462928
- 35 USC 102 Novelty (BERT): 0.505923331918649
- Combined Prediction Score: 0.8651315342635284
- Mean Citation Score: 186.171074
- Max Citation Score: 213.99503
- Similarity Product: 140.76817965161027

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test