PATENT CLAIM ANALYSIS

Application Number: 16039050
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2019-06
Patent Classification: ["327", "261000"]

Abstract:
A delay control circuit includes: a first step delay cell including a first switch having a first end connected to a first node, and a first capacitor connected to a second end of the first switch; a second step delay cell including a second switch having a first end connected to a second node, and a second capacitor connected to a second end of the second switch; and a first inverter configured to couple an output signal of the first step delay cell to an input of the second step delay cell, wherein the first switch and the second switch are turned on and off by a same control signal.

Claim (Index 14):
The delay control circuit of  claim 13 , wherein the first step delay cell comprises a first capacitor and a first switch connected to the first capacitor,\n the second step delay cell comprises a second capacitor, and a second switch connected to the second capacitor, the control signal input is coupled to the first and to the second switches, and when the control signal is does not indicate the minimum delay value, the control signal is configured to turn on the first and the second switches.

Metadata:
- Claim Count in Document: 33.0
- Percentile: 95.0
- Lexical Diversity: 3.0
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15290076', '13032326', '10507117', '11055564', '11838952']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7867864754511609
- 35 USC 102 Novelty (BERT): 0.472966245540015
- Combined Prediction Score: 0.7554044524600463
- Mean Citation Score: 189.679232
- Max Citation Score: 200.69855
- Similarity Product: 159.32978445917666

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test