PATENT CLAIM ANALYSIS

Application Number: 15881022
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["257", "774000"]

Abstract:
A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

Claim (Index 1):
A device comprising a chip, the chip comprising:\n a first group of dummy bumps comprising a plurality of dummy bump connectors, the first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, the first corner being disposed immediately adjacent two intersecting edges of the chip; a second group of dummy bumps comprising one or more dummy bump connectors, the second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, the second corner being disposed immediately adjacent two intersecting edges of the chip, wherein the first and second groups of dummy bumps are disposed in different corners of the chip; a plurality of active bump connectors disposed at the top surface of the chip, the plurality of active bump connectors and the first and second groups of dummy bumps arranged in a pattern in a top down view of the chip; an outer seal ring disposed around a periphery of the chip; a first seal ring arrangement disposed around the first group of dummy bumps; a second seal ring arrangement disposed around the second group of dummy bumps; and dielectric layers underlying the first and second groups of dummy bumps and the plurality of active bump connectors, wherein the first seal ring arrangement is disposed in the dielectric layers, the first seal ring arrangement encircling all of the first group of dummy bumps in top down view such that the first group of dummy bumps are disposed within a single continuous seal ring structure, wherein the second seal ring arrangement is disposed in the dielectric layers, the second seal ring arrangement encircling each dummy bump connector of the second group of dummy bumps in top down view such that each dummy bump is individually disposed within a corresponding separate seal ring structure, and wherein the outer seal ring, first seal ring arrangement, and second seal ring arrangement have matching layer-by-layer arrangements of alternating metal lines and metal vias disposed within respective layers of the dielectric layers.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 86.0
- Lexical Diversity: 3.51351
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['12915170', '12953130', '14730231', '13712665', '15232959']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9114593572499472
- 35 USC 102 Novelty (BERT): 0.4735875597248839
- Combined Prediction Score: 0.8676721774974409
- Mean Citation Score: 169.65573200000003
- Max Citation Score: 172.6217
- Similarity Product: 128.2342841193557

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test