PATENT CLAIM ANALYSIS

Application Number: 15889315
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-08
Patent Classification: ["340", "146200"]

Abstract:
The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.

Claim (Index 6):
The comparator of  claim 5 , wherein the result bit outputs are delayed by one clock cycle.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 88.0
- Lexical Diversity: 2.29688
- Patent Class: 340.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['10317918', '14287701', '15334649', '09956399', '12499771']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.6372642834585228
- 35 USC 102 Novelty (BERT): 0.5243720813785836
- Combined Prediction Score: 0.6259750632505289
- Mean Citation Score: 162.507096
- Max Citation Score: 164.9381
- Similarity Product: 85.2903920995593

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test