PATENT CLAIM ANALYSIS

Application Number: 15911719
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-09
Patent Classification: ["327", "333000"]

Abstract:
A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

Claim (Index 13):
The level shifter of  claim 12 , wherein the interface circuit is configured to drive the second signal onto the first output node.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 90.0
- Lexical Diversity: 3.65625
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15478063', '13332730', '12273055', '12925916', '14843992']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.79178931846665
- 35 USC 102 Novelty (BERT): 0.4849551847740481
- Combined Prediction Score: 0.7611059050973898
- Mean Citation Score: 217.00460200000003
- Max Citation Score: 225.6899
- Similarity Product: 171.9171520084977

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test