PATENT CLAIM ANALYSIS

Application Number: 15906160
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2018-09
Patent Classification: ["327", "149000"]

Abstract:
Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.

Claim (Index 4):
The clock system of  claim 2 , wherein the phase noise detector comprises a sub-sampling phase detector (SSPD) configured to generate a sampled signal by sampling the input clock signal based on the reference clock signal.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 88.0
- Lexical Diversity: 2.32653
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13559909', '14613271', '13323195', '10759915', '15147408']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7995093448713249
- 35 USC 102 Novelty (BERT): 0.4982552038587169
- Combined Prediction Score: 0.7693839307700642
- Mean Citation Score: 240.879522
- Max Citation Score: 258.60336
- Similarity Product: 197.6485104949379

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test