PATENT CLAIM ANALYSIS

Application Number: 16203605
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["257", "351000"]

Abstract:
Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

Claim (Index 3):
The structure of  claim 1 , wherein the host substrate comprises a semiconductor device.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 1.94444
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['15685137', '14607077', '16113860', '16115519', '15990684']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.918360316819874
- 35 USC 102 Novelty (BERT): 0.4759809152307535
- Combined Prediction Score: 0.8741223766609619
- Mean Citation Score: 174.90955
- Max Citation Score: 225.92696
- Similarity Product: 200.47252254257683

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test