PATENT CLAIM ANALYSIS

Application Number: 16202853
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-11
Patent Classification: ["341", "172000"]

Abstract:
An SAR ADC and a conversion method are disclosed, which includes an SAR control logic circuit configured to control A/D conversion by steps: 1) sampling analog input signal for first time; 2) subjecting sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting sampled signal in step 3) to conversion comprising: 41) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step 42); 42) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, repeating steps 3) and 4) until analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.

Claim (Index 8):
A successive approximation register (SAR) analog-to-digital (A/D) conversion method implemented by an SAR analog-to-digital converter (ADC), the SAR ADC comprising a sample-and-hold circuit, an N-bit digital-to-analog converter (DAC), a comparator and an SAR control logic circuit,\n the SAR control logic circuit having a data output that outputs an N-bit digital output signal resulting from an A/D conversion performed by the SAR ADC, where N is a positive integer, the SAR control logic circuit further having a control signal output that provides an N-bit logic control signal to the N-bit DAC, the SAR control logic circuit configured to control an SAR A/D conversion process by sequential steps including: 1) sampling an analog input signal for a first time to acquire a sampled signal; 2) subjecting the sampled signal to each of an N-th SAR A/D conversion to a first SAR A/D conversion to obtain bits, from the highest N-th bit to the lowest first bit, of an N-bit digital output signal, outputting the N-bit digital output signal and taking the output N-bit digital output signal as a previous N-bit digital output signal; 3) sampling the analog input signal for another time to acquire a new sampled signal; and 4) subjecting the new sampled signal acquired in step 3) to the SAR A/D conversion comprising the sub-steps of: 41) determining whether each of an M-th to a first bits of the previous N-bit digital output signal has a value of 1 or whether each of an M-th to a first bits of the previous N-bit digital output signal has a value of 0, looping back to step 2) if each of the M-th to first bits of the previous N-bit digital output signal has a value of 1 or if each of the M-th to first bits of the previous N-bit digital output signal has a value of 0, or proceeding to step 42) if the values of the M-th to first bits of the previous N-bit digital output signal are not all 1's or 0's, where M is an integer smaller than N and greater than 1; and 42) directly taking the N-th to (M+1)-th bits of the previous N-bit digital output signal as the N-th to (M+1)-th bits of a new N-bit digital output signal, subjecting the new sampled signal to each of the M-th SAR A/D conversion to the first SAR A/D conversion to obtain bits, from the M-th to first bits of the new N-bit digital output signal, taking the new N-bit digital output signal with the N-th to first bits as updated previous N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and A/D-converted.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 98.0
- Lexical Diversity: 2.0
- Patent Class: 341.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: True
- Related Applications: ['15007368', '14576315', '14587825', '15146890', '12539406']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5785575534763178
- 35 USC 102 Novelty (BERT): 0.5203873757894284
- Combined Prediction Score: 0.5727405357076288
- Mean Citation Score: 297.696316
- Max Citation Score: 309.77963
- Similarity Product: 269.2320351129597

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test