PATENT CLAIM ANALYSIS

Application Number: 16042388
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["438", "197000"]

Abstract:
Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.

Claim (Index 4):
The method of  claim 2 , wherein forming the merged source and drain regions comprises epitaxially growing the source and drain regions from exposed faces of the layers of the channel material.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 95.0
- Lexical Diversity: 2.78
- Patent Class: 438.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15045759', '15007920', '15493441', '15140557', '15819708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8923855502931668
- 35 USC 102 Novelty (BERT): 0.5770842109308549
- Combined Prediction Score: 0.8608554163569356
- Mean Citation Score: 362.706052
- Max Citation Score: 457.96228
- Similarity Product: 455.2298551334262

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test