PATENT CLAIM ANALYSIS

Application Number: 15988458
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2018-12
Patent Classification: ["708", "190000"]

Abstract:
An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such that the specialized processing block operates as a signal processing device that handles signals in a given sequence. For example, the sequencer circuit may control the signal arrival at the specialized processing block and the configuration of the configurable circuitry in the specialized processing block. In certain embodiments, the sequencer circuit and the specialized processing block may implement finite impulse response (FIR) filters.

Claim (Index 24):
The method of  claim 23 , further comprising:\n receiving at a fourth input a control signal from the sequencer circuit; and decoupling the register from the second adder input port at least in part based on the control signal, with a multiplexer.

Metadata:
- Claim Count in Document: 23.0
- Percentile: 93.0
- Lexical Diversity: 2.0
- Patent Class: 708.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14875323', '14326828', '14919429', '13752661', '15277955']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.448767448374626
- 35 USC 102 Novelty (BERT): 0.5474823590003343
- Combined Prediction Score: 0.4586389394371968
- Mean Citation Score: 254.481054
- Max Citation Score: 389.96216
- Similarity Product: 331.76334062513826

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test