PATENT CLAIM ANALYSIS

Application Number: 15946264
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["365", "149000"]

Abstract:
A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

Claim (Index 11):
The control method of  claim 10 , wherein the filter activates the DLL to update the delay line every clock cycle.

Metadata:
- Claim Count in Document: 44.0
- Percentile: 91.0
- Lexical Diversity: 2.27119
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['12059593', '12416822', '11648314', '12493756', '10210406']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8107732558210722
- 35 USC 102 Novelty (BERT): 0.4781374460704424
- Combined Prediction Score: 0.7775096748460092
- Mean Citation Score: 197.813726
- Max Citation Score: 209.78352
- Similarity Product: 157.8116943848419

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test