PATENT CLAIM ANALYSIS

Application Number: 16184794
Application Type: Utility
Filing Date: 2018-11
Publication Date: 2019-03
Patent Classification: ["327", "115000"]

Abstract:
Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

Claim (Index 12):
A system comprising:\n a first die having a synchronization circuit which comprises:\n a clock generator; \n a I/Q phase generator coupled to the clock generator; \n a first phase interpolator coupled to a first output of the I/Q phase generator; and \n a phase detector having a first input coupled to an output of the first phase interpolator; \n a second die coupled to the first die via a pair of interconnects, wherein the second die comprises:\n a clock multiplier; \n a phase locked loop (PLL) coupled to the clock multiplier; \n a clock distribution network coupled to an input and output of the PLL, wherein the clock multiplier is to receive an input from the clock synchronization circuit of the first die; and \n a wireless interface coupled to one of the first or second dies.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 98.0
- Lexical Diversity: 1.77419
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15214364', '16102113', '15064799', '14059366', '11112162']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7063598484477085
- 35 USC 102 Novelty (BERT): 0.5446245479045151
- Combined Prediction Score: 0.6901863183933892
- Mean Citation Score: 197.455896
- Max Citation Score: 390.76187
- Similarity Product: 333.0288222180027

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test