PATENT CLAIM ANALYSIS

Application Number: 15936350
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-08
Patent Classification: ["716", "102000"]

Abstract:
A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.

Claim (Index 12):
The method of  claim 1  further comprising calculating wire length.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 90.0
- Lexical Diversity: 1.79121
- Patent Class: 716.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14975844', '13436944', '14722046', '14789409', '14789401']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.3253835883738549
- 35 USC 102 Novelty (BERT): 0.5661481013209256
- Combined Prediction Score: 0.349460039668562
- Mean Citation Score: 248.108894
- Max Citation Score: 480.6039
- Similarity Product: 456.814241619873

Labels:
- Claim Label 101: 0
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 0

Dataset: test