PATENT CLAIM ANALYSIS

Application Number: 16011356
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-10
Patent Classification: ["714", "724000"]

Abstract:
Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.

Claim (Index 1):
An apparatus comprising:\n a combinational logic to provide a data on a data node; a multiplexer coupled to the data node and one of a supply node or a ground node, the multiplexer having an output node; a sequential logic having a data input, an output, and a clock input, wherein the output node of the multiplexer is coupled to the data input; and a compare logic having a first input coupled to the data input, and a second input coupled to the output of the sequential logic, wherein the compare logic is to detect a V min  threshold of the sequential logic during a test mode.

Metadata:
- Claim Count in Document: 50.0
- Percentile: 94.0
- Lexical Diversity: 1.70968
- Patent Class: 714.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15072280', '15462732', '15663852', '15254272', '15903507']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.2643924843542932
- 35 USC 102 Novelty (BERT): 0.4696694083669839
- Combined Prediction Score: 0.2849201767555622
- Mean Citation Score: 128.1874268
- Max Citation Score: 193.94409
- Similarity Product: 152.9538979332912

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test