PATENT CLAIM ANALYSIS

Application Number: 15568312
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-10
Patent Classification: ["257", "040000"]

Abstract:
The present disclosure relates to a memory device having a hybrid insulating layer and a method for preparing the same. In detail, a memory device including a gate electrode on a substrate, a source electrode, and a drain electrode has a hybrid memory insulating layer between the gate electrode and the source and drain electrodes that is polarizable and includes a mixed material of inorganic matter and organic matter to lead to hysteresis. According to the present disclosure, a memory insulating layer is formed as a hybrid insulating layer including a mixture of polyvinylphenol as the organic matter and vinyltriethoxysilane as the inorganic matter to complement the properties of an inorganic memory and an organic memory whereby increasing memory performance, and it stably operates at both low and high temperatures whereby having a wide usage range.

Claim (Index 7):
The memory device of  claim 4 , wherein the charge transport layer is a hole transport layer.

Metadata:
- Claim Count in Document: 1.0
- Percentile: 86.0
- Lexical Diversity: 2.14925
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14811849', '11791502', '12073497', '11976127', '14884744']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.916105739868436
- 35 USC 102 Novelty (BERT): 0.5067833094054284
- Combined Prediction Score: 0.8751734968221353
- Mean Citation Score: 167.29852599999995
- Max Citation Score: 174.2833
- Similarity Product: 95.21016585962772

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test