PATENT CLAIM ANALYSIS

Application Number: 15881265
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["365", "226000"]

Abstract:
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Claim (Index 6):
The system according to  claim 5 , wherein when the first semiconductor memory device receives a first signal from the signal line, the first semiconductor memory device goes into a waiting state, the first signal indicating peak current which is larger than a reference current, and\n when the second semiconductor memory device receives a second signal from the signal line, the second semiconductor memory device goes into the waiting state, the second signal indicating, peak current which is larger than the reference current.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 86.0
- Lexical Diversity: 2.42857
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12027546', '12645104', '14539522', '15430983', '13598099']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7907855421263449
- 35 USC 102 Novelty (BERT): 0.4992274051141031
- Combined Prediction Score: 0.7616297284251208
- Mean Citation Score: 232.65328
- Max Citation Score: 240.6618
- Similarity Product: 169.4528740568161

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test