PATENT CLAIM ANALYSIS

Application Number: 15944270
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2018-08
Patent Classification: ["365", "050000"]

Abstract:
A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

Claim (Index 5):
The memory cell of  claim 4  wherein one of the types is a diode and the other of the types is a field effect transistor.

Metadata:
- Claim Count in Document: 30.0
- Percentile: 91.0
- Lexical Diversity: 2.82
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15176624', '15005250', '14519021', '15677252', '15208206']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8273295638196436
- 35 USC 102 Novelty (BERT): 0.5403494640160674
- Combined Prediction Score: 0.7986315538392861
- Mean Citation Score: 297.7260500000001
- Max Citation Score: 444.74713
- Similarity Product: 255.3882646324629

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test