PATENT CLAIM ANALYSIS

Application Number: 15919508
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2019-02
Patent Classification: ["327", "147000"]

Abstract:
A frequency locking circuitry has a counter to count a cycle number of a first clock signal included in one cycle of a second clock signal synchronized with the first clock signal, a generator to generate a frequency output code based on a result of comparison between the counted cycle number and a predetermined reference cycle number, and an oscillator to generate an oscillation signal having a frequency in accordance with the generated frequency output code. The generator changes a change value of the frequency output code in a plurality of ways until the counted cycle number reaches from an initial value to the reference cycle number.

Claim (Index 18):
The clock data recovery circuitry of  claim 11 , wherein the code generator updates a change value of the frequency code based on the exponential function having an index number expressing the number of change count of the frequency output code until the counted cycle number first exceeds the reference cycle number, and changes the frequency output code per a minimum change value after the counted cycle number first exceeds the reference cycle number.

Metadata:
- Claim Count in Document: 19.0
- Percentile: 90.0
- Lexical Diversity: 2.09434
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['13190705', '13049645', '13964584', '13344513', '12626554']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.77335371715628
- 35 USC 102 Novelty (BERT): 0.4724074640771261
- Combined Prediction Score: 0.7432590918483646
- Mean Citation Score: 158.790648
- Max Citation Score: 163.2218
- Similarity Product: 117.74023259611128

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test