PATENT CLAIM ANALYSIS

Application Number: 15863924
Application Type: Utility
Filing Date: 2018-01
Publication Date: 2018-05
Patent Classification: ["326", "038000"]

Abstract:
A 3D device, the device including: a first stratum including an array of memory bit cells, the array of memory bit cells is controlled via a plurality of bit-lines and a plurality of word-lines; and a second stratum overlaying the first stratum, the second stratum including memory control circuits, where the control circuits provide control of the plurality of bit-lines and the plurality of word-lines.

Claim (Index 4):
The 3D device according to  claim 1 ,\n wherein said memory control circuits comprise a memory sense amplifier functionality.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 86.0
- Lexical Diversity: 2.32258
- Patent Class: 326.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15482761', '13098997', '12941075', '15089394', '12941074']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.755242207270645
- 35 USC 102 Novelty (BERT): 0.5636846879667152
- Combined Prediction Score: 0.7360864553402521
- Mean Citation Score: 470.557628
- Max Citation Score: 522.7022
- Similarity Product: 350.8333742142677

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test