PATENT CLAIM ANALYSIS

Application Number: 16023584
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-03
Patent Classification: ["365", "200000"]

Abstract:
A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Claim (Index 10):
The semiconductor memory device of  claim 9 , wherein the repair control circuit comprises:\n an address comparison circuit configured to:\n compare the access address with address information of at least one defective cell generated in the first cell region and the second cell region, and \n output a column repair signal to repair the at least one defective cell based on a result of the comparison; and \n a fuse information circuit configured to:\n store the fuse information corresponding to a row address of the access address and a spare row address for replacing the row address, and \n selectively output the spare row address according to the fuse information.

Metadata:
- Claim Count in Document: 20.0
- Percentile: 94.0
- Lexical Diversity: 2.5
- Patent Class: 365.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12320892', '14030066', '13008431', '10657790', '12320891']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8310697672119133
- 35 USC 102 Novelty (BERT): 0.4997205909668255
- Combined Prediction Score: 0.7979348495874046
- Mean Citation Score: 271.242584
- Max Citation Score: 280.63547
- Similarity Product: 208.8842253834636

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test