PATENT CLAIM ANALYSIS

Application Number: 16004718
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2018-11
Patent Classification: ["257", "140000"]

Abstract:
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.

Claim (Index 1):
A semiconductor device structure, comprising:\n a semiconductor substrate having first major surface and an opposing second major surface, wherein the semiconductor substrate comprises:\n a floating buried doped region of a first conductivity type; \n a first doped region of a second conductivity type interposed between the floating buried doped region and the first major surface; and \n a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface; \n a trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein:\n the floating buried doped region adjoins the trench isolation structure; and \n the trench isolation structure defines a perimeter for an active region of the semiconductor device structure; \n an insulated trench structure extending from the first major surface through the first doped region and terminating within the floating buried doped region, wherein:\n the insulated trench structure is disposed within the perimeter of the trench isolation structure; \n the insulated trench structure defines a first portion and a second portion of the active region; and \n the floating buried doped region electrically couples the first portion and the second portion of the active region together; \n a first semiconductor device disposed within a first portion of the first doped region and within the first portion of the active region; and a second semiconductor device disposed in the second portion of the active region and comprising a second portion of the first doped region and the floating buried doped region, wherein the second semiconductor device is configured as a first bias semiconductor device adapted to set a potential of the floating buried doped region.

Metadata:
- Claim Count in Document: 26.0
- Percentile: 94.0
- Lexical Diversity: 3.0
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15669579', '15140152', '15659450', '13404759', '14712462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9256581927461892
- 35 USC 102 Novelty (BERT): 0.507963646949048
- Combined Prediction Score: 0.8838887381664752
- Mean Citation Score: 257.282152
- Max Citation Score: 311.20764
- Similarity Product: 293.2970612199212

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test