PATENT CLAIM ANALYSIS

Application Number: 15964492
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-10
Patent Classification: ["257", "368000"]

Abstract:
A memory cell array includes a first memory cell arranged in a first row in a first direction and a second memory cell arranged in a second row in the first direction. The first memory cell or the second memory cell includes a set of active regions, a set of gates and a first set of conductive structures. Each of the active regions of the set of active regions is separated from an adjacent active region in the first direction by a first pitch. The set of active regions extends in a second direction. The set of active regions includes a first active region adjacent to a first side of the first memory cell, and a second active region adjacent to a second side of the first memory cell. A length of the first active region is different from a length of the second active region.

Claim (Index 1):
A method of forming a memory cell array, the method comprising:\n generating a first set of tiles extending in a first direction, wherein the generating the first set of tiles comprises:\n generating a first layout design of a first set of memory cells, each tile of the first set of tiles corresponds to the first layout design of the first set of memory cells, and each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction; \n generating a second set of tiles, wherein the generating the second set of tiles comprises:\n generating a second layout design of a second set of memory cells, each tile of the second set of tiles corresponds to the second layout design of the second set of memory cells, and each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction, \n wherein each tile of the first set of tiles extends in a third direction different from the first direction and the second direction, the first set of tiles and the second set of tiles alternate with each other in the second direction, and each tile of the second set of tiles extends in the third direction, and at least one of the above generating operations is performed by a hardware processor, and the first layout design is stored in a non-transitory computer-readable medium; and manufacturing the memory cell array based on at least the first layout design.

Metadata:
- Claim Count in Document: 38.0
- Percentile: 91.0
- Lexical Diversity: 3.94872
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15863090', '15682885', '15861128', '14554958', '15380936']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8922713579749413
- 35 USC 102 Novelty (BERT): 0.4820833959402009
- Combined Prediction Score: 0.8512525617714672
- Mean Citation Score: 168.22874199999995
- Max Citation Score: 186.12898
- Similarity Product: 142.10483425940754

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test