PATENT CLAIM ANALYSIS

Application Number: 15922642
Application Type: Utility
Filing Date: 2018-03
Publication Date: 2018-10
Patent Classification: ["712", "007000"]

Abstract:
An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.

Claim (Index 27):
A processor comprising:\n a destination vector register to store a plurality of destination data elements; a first vector register to store a source vector comprising a plurality of source data elements, the source data elements including valid source data elements and invalid source data elements; a second vector register to store a control vector comprising a plurality of control data elements, each of the control data elements corresponding to one of the plurality of destination data elements and identifying one of the plurality of source data elements to be copied to the corresponding destination data element; and shuffle circuitry to copy the plurality of source data elements to the destination vector register based on the control vector, wherein the shuffle circuitry is to copy all of the valid source data elements contiguously to one side of the destination vector register followed by all of the invalid data elements, wherein a first valid source data element is copied to a least-significant data element position in the destination vector register, a second valid source data element is copied to a second least-significant data element position in the destination vector register, and so on, until all of the valid source data elements have been copied to the destination vector register.

Metadata:
- Claim Count in Document: 68.0
- Percentile: 90.0
- Lexical Diversity: 2.7
- Patent Class: 712.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14499038', '13994060', '14580069', '13993058', '13991858']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5983893294557221
- 35 USC 102 Novelty (BERT): 0.5277514643857897
- Combined Prediction Score: 0.5913255429487289
- Mean Citation Score: 297.37766
- Max Citation Score: 367.53796
- Similarity Product: 260.7598634045005

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test