PATENT CLAIM ANALYSIS

Application Number: 16032209
Application Type: Utility
Filing Date: 2018-07
Publication Date: 2018-11
Patent Classification: ["250", "208100"]

Abstract:
A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Claim (Index 63):
The image device of  claim 61 , wherein the barrier region is disposed within a substrate, and is controlled by the shutter gate.

Metadata:
- Claim Count in Document: 59.0
- Percentile: 95.0
- Lexical Diversity: 1.53061
- Patent Class: 250.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13920677', '12232994', '10721191', '10721190', '12437160']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8139000323294711
- 35 USC 102 Novelty (BERT): 0.5466971648348694
- Combined Prediction Score: 0.7871797455800109
- Mean Citation Score: 440.969304
- Max Citation Score: 453.45087
- Similarity Product: 281.76242373468875

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test