PATENT CLAIM ANALYSIS

Application Number: 16382580
Application Type: Utility
Filing Date: 2019-04
Publication Date: 2019-08
Patent Classification: ["327", "105000"]

Abstract:
A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Claim (Index 6):
The circuit of  claim 1  wherein the first phase-locked loop comprises:\n a phase detector to generate a phase difference signal based on a difference in phase between the input signal having the first frequency and a phase-locked loop feedback signal; \n a control element to generate the control signal based on the phase difference signal; \n a variable frequency oscillator to generate the intermediate signal having a frequency adjusted based on the control signal; \n a circuit element to generate a first phase signal and a second phase signal based on the intermediate signal, both the first and second phase signals having a same frequency as the intermediate signal, and the second phase signal phase-shifted relative to the first phase signal; \n a modulator to receive a frequency selection signal and generate a modulated phase control signal specifying a selected phase for each period of the modulated phase control signal; \n a phase interpolator to receive the modulated phase control signal and the first and second phase signals, the phase interpolator outputting an interpolated signal for each period of the modulated phase control signal, the interpolated signal having the selected phase selected from a plurality of selectable phases in between phases of the first phase signal and the second phase signal; and \n a frequency divider circuit to divide a frequency of the interpolated signal and generate the phase-locked loop feedback signal.

Metadata:
- Claim Count in Document: 4.0
- Percentile: 100.0
- Lexical Diversity: 1.69014
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['13830007', '15605932', '14746618', '15993254', '13766035']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7983593173122617
- 35 USC 102 Novelty (BERT): 0.4999352725934455
- Combined Prediction Score: 0.7685169128403802
- Mean Citation Score: 250.182538
- Max Citation Score: 306.36957
- Similarity Product: 296.1269656582886

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test