PATENT CLAIM ANALYSIS

Application Number: 16233283
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-09
Patent Classification: ["327", "156000"]

Abstract:
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Claim (Index 18):
The method of  claim 16 , further comprising low pass filtering the TDC output values before changing the TDC input to the second reference clock to produce a low pass filtered output, and wherein generating the second value comprises generating the second value based on the average value, the current TDC output values, and the low pass filtered output.

Metadata:
- Claim Count in Document: 5.0
- Percentile: 98.0
- Lexical Diversity: 1.95652
- Patent Class: 327.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['16227777', '16226938', '16218970', '12956498', '12874462']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7823368100393437
- 35 USC 102 Novelty (BERT): 0.5196375720331377
- Combined Prediction Score: 0.7560668862387232
- Mean Citation Score: 252.211654
- Max Citation Score: 322.83585
- Similarity Product: 251.9898315829754

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test