PATENT CLAIM ANALYSIS

Application Number: 16006685
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-07
Patent Classification: ["257", "043000"]

Abstract:
A thin film transistor is provided, including a base substrate, a semiconductor active layer, a gate electrode, a gate insulating layer, a source electrode and a drain electrode. The gate insulating layer is formed on the base substrate, the gate insulating layer is provided with a through hole and an annular groove surrounding the through hole. The gate electrode is formed in the through hole, the semiconductor active layer is formed in the annular groove, a height of the gate electrode in the through hole is at least higher than a bottom of the annular groove. The source electrode and the drain electrode are formed on the gate insulating layer at intervals and connected to the semiconductor active layer, respectively. A method of manufacturing the thin film transistor and an array substrate including the thin film transistor are also provided.

Claim (Index 4):
The thin film transistor according to  claim 1 , wherein a height of the gate electrode is at least flush with an upper surface of the gate insulating layer.

Metadata:
- Claim Count in Document: 9.0
- Percentile: 94.0
- Lexical Diversity: 3.14286
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['12886894', '14388182', '13737355', '15308991', '14361396']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9282270714902674
- 35 USC 102 Novelty (BERT): 0.5036286610149657
- Combined Prediction Score: 0.8857672304427372
- Mean Citation Score: 243.650038
- Max Citation Score: 250.66434
- Similarity Product: 173.26854921727897

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 0
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test