PATENT CLAIM ANALYSIS

Application Number: 16000174
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-12
Patent Classification: ["257", "632000"]

Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

Claim (Index 12):
A method, comprising:\n forming lower metal lines within dielectric material; forming an interlevel dielectric material above the lower metal lines; forming at least one trench within the interlevel dielectric material above the lower metal lines; filling the at least one trench with material that is different than the interlevel dielectric material; forming an upper dielectric material over the material; forming at least one airgap structure in the interlevel dielectric material by subjecting the material to a UV curing process; and forming metal structures above the at least one airgap structure.

Metadata:
- Claim Count in Document: 28.0
- Percentile: 94.0
- Lexical Diversity: 1.76744
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['15901411', '15817629', '15875212', '15377592', '14667085']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.90288539529079
- 35 USC 102 Novelty (BERT): 0.5141122454023269
- Combined Prediction Score: 0.8640080803019438
- Mean Citation Score: 242.426814
- Max Citation Score: 283.54254
- Similarity Product: 209.0713726258421

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test