PATENT CLAIM ANALYSIS

Application Number: 15891751
Application Type: Utility
Filing Date: 2018-02
Publication Date: 2019-12
Patent Classification: ["711", "108000"]

Abstract:
A memory subsystem is interfaced to a CPU through memory controllers. The memory subsystem is composed of a first tier of first memory devices having a first set of performance characteristics and a second tier of second memory devices having a second set of performance characteristics that are different from the first set of performance characteristics. A content addressable memory stores the memory addresses that are used to access the first memory devices and/or second memory devices. Logic is provided that updates one or more registers or memory structures to count the frequency and timing of occurrences of the memory address accesses. Both the content addressable memory and logic can be implemented on the same semiconductor substrate. The content addressable memory may be interfaced to a random access memory that stores counters. The logic may comprise one or more state machines implemented on the same semiconductor substrate as the CPU.

Claim (Index 3):
The system of  claim 2 , wherein the content addressable memory comprises a plurality of cells that comprise both storage circuitry and comparison circuitry.

Metadata:
- Claim Count in Document: 22.0
- Percentile: 88.0
- Lexical Diversity: 2.41538
- Patent Class: 711.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['14314366', '14501112', '15661598', '15270360', '14101246']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.5083895198915388
- 35 USC 102 Novelty (BERT): 0.4943905105668196
- Combined Prediction Score: 0.5069896189590669
- Mean Citation Score: 186.403834
- Max Citation Score: 199.57643
- Similarity Product: 133.1405436813271

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test