PATENT CLAIM ANALYSIS

Application Number: 16127575
Application Type: Utility
Filing Date: 2018-09
Publication Date: 2019-02
Patent Classification: ["257", "773000"]

Abstract:
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Claim (Index 35):
An electronic device comprising:\n a signal redistribution structure (SRS) comprising a first SRS side and a second SRS side opposite the first SRS side, wherein the SRS comprises at least a first SRS conductive layer and a first SRS dielectric layer; a high routing density patch bonded to the first SRS side, wherein the high routing density patch comprises a dielectric layer that has a width less than a width of the first SRS side; and a semiconductor die coupled the second SRS side, wherein:\n the high routing density patch comprises a denser trace line density than the SRS; \n the semiconductor die is electrically coupled to the SRS with a first conductive pillar having a first height and with a first solder distinct from and vertically shorter than the first conductive pillar; and \n the semiconductor die is electrically coupled to the SRS with a second conductive pillar having a second height substantially equal to the first height, wherein the semiconductor die is electrically coupled to the high routing density patch through the second conductive pillar and through the SRS.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 97.0
- Lexical Diversity: 2.68852
- Patent Class: 257.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14686725', '15847329', '15400041', '15854095', '14698634']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.8988892525495558
- 35 USC 102 Novelty (BERT): 0.5186592576675926
- Combined Prediction Score: 0.8608662530613596
- Mean Citation Score: 195.113448
- Max Citation Score: 315.7296
- Similarity Product: 270.0166563391685

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test