PATENT CLAIM ANALYSIS

Application Number: 16064522
Application Type: Utility
Filing Date: 2018-06
Publication Date: 2019-01
Patent Classification: ["257", "330000"]

Abstract:
A trench gate lead-out structure comprises a substrate ( 10 ), a trench formed in the surface of the substrate ( 10 ) and a first dielectric layer ( 22 ) on the substrate ( 10 ), and also comprises a polysilicon gate ( 31 ) at the inner surface of the trench. The trench is partially filled by the polysilicon gate ( 31 ), so that a recess exists in the trench above the polysilicon gate ( 31 ). A second dielectric layer ( 41 ) is filled in the recess. The trench gate lead-out structure also comprises a metal plug ( 50 ). The metal plug ( 50 ) downwards penetrates through the first dielectric layer ( 22 ) and then is inserted between the second dielectric layer ( 41 ) and the polysilicon gate ( 31 ), and accordingly is connected to the polysilicon gate ( 31 ).

Claim (Index 8):
The method according to  claim 7 , wherein the step of depositing the insulating dielectric in the trench is performed by chemical vapor deposition of a silicon dioxide layer using tetraethyl orthosilicate as a reactant.

Metadata:
- Claim Count in Document: 16.0
- Percentile: 94.0
- Lexical Diversity: 3.01887
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['16064550', '14771089', '15363138', '14902284', '12613708']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9253745270429602
- 35 USC 102 Novelty (BERT): 0.5062591028316518
- Combined Prediction Score: 0.8834629846218294
- Mean Citation Score: 230.922308
- Max Citation Score: 274.3471
- Similarity Product: 204.1010181798936

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test