PATENT CLAIM ANALYSIS

Application Number: 16411924
Application Type: Utility
Filing Date: 2019-05
Publication Date: 2019-08
Patent Classification: ["257", "192000"]

Abstract:
Method and structure of forming a vertical FET. The method includes depositing a bottom source-drain layer over a substrate; depositing a first heterostructure layer over the bottom source-drain layer; depositing a channel layer over the first heterostructure layer; depositing a second heterostructure layer over the channel layer; forming a first fin having a hard mask; recessing the first and the second heterostructure layers to narrow them; filling gaps with an inner spacer; laterally trimming the channel layer to a narrower width; depositing a bottom outer spacer over the bottom source-drain layer; depositing a high-k layer on the bottom outer spacer, the first fin, and the hard mask; and depositing a metal gate layer over the high-k and top outer spacer to produce the vertical FET. Forming another structure by recessing the metal gate layer below the second inner spacer.

Claim (Index 2):
The vertical FET structure of  claim 1 , wherein the first dielectric inner spacer comprises silicon-boron-carbon-nitride (SiBCN).

Metadata:
- Claim Count in Document: 50.0
- Percentile: 100.0
- Lexical Diversity: 2.8
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15611981', '15786047', '15163049', '15935468', '16233825']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.935627306867591
- 35 USC 102 Novelty (BERT): 0.6041638961141417
- Combined Prediction Score: 0.902480965792246
- Mean Citation Score: 376.172636
- Max Citation Score: 527.9611
- Similarity Product: 473.9333462805509

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test