PATENT CLAIM ANALYSIS

Application Number: 15956139
Application Type: Utility
Filing Date: 2018-04
Publication Date: 2019-07
Patent Classification: ["257", "324000"]

Abstract:
A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.

Claim (Index 12):
The three-dimensional memory device of  claim 11 , wherein a height of each step in the first vertical plane decreases by one unit from the first end column stair to the second end column stair, and decreases by one unit from the second end column stair to the at least one middle column stair.

Metadata:
- Claim Count in Document: 17.0
- Percentile: 91.0
- Lexical Diversity: 2.27419
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15943859', '15717102', '15834261', '15628495', '15685254']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.94192945208576
- 35 USC 102 Novelty (BERT): 0.531477073442274
- Combined Prediction Score: 0.9008842142214114
- Mean Citation Score: 356.93722599999984
- Max Citation Score: 362.49683
- Similarity Product: 243.2878564886469

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test