PATENT CLAIM ANALYSIS

Application Number: 15979557
Application Type: Utility
Filing Date: 2018-05
Publication Date: 2019-11
Patent Classification: ["257", "401000"]

Abstract:
A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Claim (Index 13):
The method of  claim 12 , wherein the lower channel layer has a thickness in a range of about 10 nm to about 50 nm.

Metadata:
- Claim Count in Document: 11.0
- Percentile: 93.0
- Lexical Diversity: 3.55556
- Patent Class: 257.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: False
- Related Applications: ['15463314', '15963566', '15960078', '15450715', '15273252']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.9253858617977818
- 35 USC 102 Novelty (BERT): 0.528677346561885
- Combined Prediction Score: 0.8857150102741922
- Mean Citation Score: 320.0325200000001
- Max Citation Score: 326.58298
- Similarity Product: 234.4604352736497

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test