PATENT CLAIM ANALYSIS

Application Number: 16224603
Application Type: Utility
Filing Date: 2018-12
Publication Date: 2019-11
Patent Classification: ["327", "158000"]

Abstract:
A synchronization circuit may include: a variable delay circuit configured to delay a first clock signal by a varied delay time according to delay control signals, and configured to output a delayed signal of the variable delay circuit as a second clock signal; a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; and a delay control circuit configured to perform a phase unstable period detection operation according to the phase detection signal, and configured to perform a delay skip operation to adjust the delay control signals such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation.

Claim (Index 9):
The synchronization circuit according to  claim 8 , wherein when any one result of the plurality of phase detections has a different value from any other result of the plurality of phase detections, the delay control circuit detects the corresponding phase detection operation set as a phase unstable period.

Metadata:
- Claim Count in Document: 41.0
- Percentile: 98.0
- Lexical Diversity: 2.58
- Patent Class: 327.0
- Transitional Phrase Type: none
- Component Type: 0
- Foreign Priority: True
- Related Applications: ['14195010', '12963133', '13219621', '13334241', '11528563']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.7886574721115263
- 35 USC 102 Novelty (BERT): 0.5027828473277206
- Combined Prediction Score: 0.7600700096331457
- Mean Citation Score: 220.294614
- Max Citation Score: 264.44843
- Similarity Product: 184.37573101309536

Labels:
- Claim Label 101: 1
- Claim Label 102: 0
- Claim Label 103: 1
- Claim Label 112: 1
- Combined Label: 0
- Label 101 Adjusted: 1

Dataset: test