PATENT CLAIM ANALYSIS

Application Number: 16266604
Application Type: Utility
Filing Date: 2019-02
Publication Date: 2019-10
Patent Classification: ["326", "038000"]

Abstract:
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Claim (Index 3):
The multi-chip system of  claim 2 , wherein:\n the routing layer of the interfacing bar comprises a plurality of metal layers including a lower wiring layer and an upper wiring layer characterized by wider wiring than the lower wiring layer; and the second chip is electrically coupled with the first chip through a first wire running a substantial distance of the longitudinal length in upper wiring layer, and further comprising a third chip electrically coupled with the first chip through a second wire in the lower wiring layer, wherein the first wire is wider than the second wire and the second chip is located further away from the first chip than the third chip is.

Metadata:
- Claim Count in Document: 29.0
- Percentile: 99.0
- Lexical Diversity: 1.52941
- Patent Class: 326.0
- Transitional Phrase Type: open
- Component Type: 1
- Foreign Priority: False
- Related Applications: ['14040223', '13646477', '14977645', '15499557', '15816360']

Analysis Scores:
- 35 USC 101 Eligibility (BERT): 0.633660494699705
- 35 USC 102 Novelty (BERT): 0.4645145322454533
- Combined Prediction Score: 0.6167458984542799
- Mean Citation Score: 122.76851000000002
- Max Citation Score: 142.67065
- Similarity Product: 102.81274059334991

Labels:
- Claim Label 101: 1
- Claim Label 102: 1
- Claim Label 103: 0
- Claim Label 112: 1
- Combined Label: 1
- Label 101 Adjusted: 1

Dataset: test